# Register now to access 7 million high quality study materials (What's Course Hero?) Course Hero is the premier provider of high quality online educational resources. With millions of study documents, online tutors, digital flashcards and free courseware, Course Hero is helping students learn more efficiently and effectively. Whether you're interested in exploring new subjects or mastering key topics for your next exam, Course Hero has the tools you need to achieve your goals.

3 Pages

### Homework4 f02

Course: EE 4720, Spring 2008
School: LSU
Rating:

Word Count: 735

#### Document Preview

EE LSU 4720 Homework 4 Solution Due: 27 November 2002 Problem 1: Consider the solution to Spring 2002 Homework 4, shown on the next page. (The solution was updated 19 November 2002, the PED is shown in dynamic order instead of the nearly-impossible-to-read static order.) (a) Show the contents of the reorder buffer in cycle 12. For each entry show the values of the fields from the illustration below, for the PC...

Register Now

#### Unformatted Document Excerpt

Coursehero >> Louisiana >> LSU >> EE 4720

Course Hero has millions of student submitted documents similar to the one
below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.

Course Hero has millions of student submitted documents similar to the one below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.
Find millions of documents on Course Hero - Study Guides, Lecture Notes, Reference Materials, Practice Exams and more. Course Hero has millions of course specific materials providing students with the best way to expand their education.

Below is a small sample set of documents:

LSU - EE - 4720
LSU EE 4720Problem 1:Homework 4Due: 22 March 2004Suppose code like the memory copy program above (from Homework 3) appears frequently enough in the execution of programs so that new instructions should be added to the ISA to allow improved exe
LSU - EE - 4720
EE 4720Problem 1:Homework 5Due: 5 December 2001An ISA has a character size of c = 9 bits (one more than most other ISA's!) and a 30-bit address space (A). An implementation has a bus width of w = 72 bits and has no cache. Show how 220 36 memo
LSU - EE - 4720
LSU EE 4720Homework 5 Solution Due: 3 December 2002To answer the questions below you need to use the PSE dataset viewer program. PSE (pronounced see) runs on Solaris and Linux; you can use the computer accounts distributed in class to run it, a L
LSU - EE - 4720
EE 4720Homework 6Due: Not CollectedIf you only have time for one of these problems, do problem three (the one on connecting memory devices to implement a cache). If you have or are hoping to get a job interview with a company that makes process
LSU - EE - 4720
LSU EE 4720Homework 1 SolutionDue: 17 September 2003Problem 1: Look at the following SPEC CINT2000 disclosures for these Dell and HP Itanium 2 systems: HP: http:/www.spec.org/osg/cpu2000/results/res2003q3/cpu2000-20030711-02389.html Dell: http:
LSU - EE - 4720
LSU EE 4720Homework 1Due: 3 October 2006Problem 1: Without looking at the solution solve Spring 2002 Homework 2 Problem 2 parts a-c. Then, look at the solution and assign yourself a grade in the range [0,1].
LSU - EE - 4720
LSU EE 4720Homework 1Due: 2 March 2007Problem 1: Without looking at the solution solve Spring 2002 Homework 2 Problem 2 parts a-c. Then, look at the solution and assign yourself a grade in the range [0,1]. Problem 2: If the value in register r2
LSU - EE - 4720
LSU EE 4720Homework 1Due: 20 February 2008Problem 1: Solve Fall 2007 Homework 2 without looking at the solution. Then look at the solution and give yourself a grade on a scale of [0, 1]. Warning: test questions are based on the assumption that
LSU - EE - 4720
LSU EE 4720Homework 1 Solution Due: 29 September 2008To answer the first question below see the MIPS32 Architecture manual linked to the course references page.Problem 1: The MIPS I bgtz and bltz instructions compare a register to zero, but can
LSU - EE - 4720
EE 4720Problem 1:Homework 1 Solution2 pts Just plug the run times into these equations AM =Assigned: Spring 1997GM =n i=1 i1XtnHM = X !,1n i=1 ti1n1vY u u t tnni=1ito obtain 42.6, 13.8, and 27.7 for the arithmetic,
LSU - EE - 4720
LSU EE 4720Homework 1 SolutionDue: 11 February 2005Problem 1: POWER is an IBM ISA developed for engineering workstations, PowerPC is an ISA developed by IBM, Apple, and Motorola for personal computers and is based on POWER. POWER and PowerPC ha
LSU - EE - 4720
LSU EE 4720Homework 1Due: 29 September 2008To answer the first question below see the MIPS32 Architecture manual linked to the course references page.Problem 1: The MIPS I bgtz and bltz instructions compare a register to zero, but can't compa
LSU - EE - 4720
LSU EE 4720Homework 2 SolutionDue: 9 March 2005For answers to the questions below refer to the PowerPC description Book I which can be found on the class references page, http:/www.ece.lsu.edu/ee4720/reference.html. Problem 1: One instruction t
LSU - EE - 4720
LSU EE 4720Homework 2 SolutionDue: 29 February 2008For the answers to these questions look at the ARM Architecture Reference Manual linked to the course references page, http:/www.ece.lsu.edu/ee4720/reference.html. Problem 1: The register field
LSU - EE - 4720
EE 4720Homework 2Due: 19 February 1999The SPARC assembly language program below is used in the problems that follow. SPARC register names are %g0-%g7, %i0-%i7, %l0-%l7, and %o0-%o7; and %g0 is a zero register (like r0 in DLX). The destination f
LSU - EE - 4720
LSU EE 4720Homework 2 SolutionDue: 1 October 2007For lecture material relevant to this assignment see http:/www.ece.lsu.edu/ee4720/2007f/lsli06.pdf. For some background and a list of similar problems see the statically scheduled study guide, ht
LSU - EE - 4720
LSU EE 4720Problem 1:Homework 3 SolutionDue: 3 November 2004Do Problems 1 and 2 From Spring 2004 Homework 3 http:/www.ece.lsu.edu/ee4720/2004/hw03.pdf. After completing the problems look at the solution and assign yourself a grade. The maximum
LSU - EE - 4720
LSU EE 4720Homework 3 SolutionDue: 15 October 2007The problems below ask about VAX instructions, which were not yet covered in class. For information on these instructions see the VAX Macro and Instruction Set manual linked to the EE 4720 refer
LSU - EE - 4720
LSU EE 4720Homework 3 SolutionDue: 29 October 2008Problem 1: Two MIPS implementations appear below, the first is the one presented in class, it will be called the mux-in-EX implementation. The second, the mux-in-ID implementation, has the ALU i
LSU - EE - 4720
LSU EE 4720Homework 3 SolutionDue: 20 March 2006Review Fall 2004 Final Exam Problem 2, which was discussed in class on Monday, 13 March 2006. Problem 1: Using the solution to Fall 2004 Final Exam problem 2 parts a, b, and d (but not c) as a sta
LSU - EE - 4720
LSU EE 4720Homework 3Due: 29 October 2008Problem 1: Two MIPS implementations appear below, the first is the one presented in class, it will be called the mux-in-EX implementation. The second, the mux-in-ID implementation, has the ALU input mult
LSU - EE - 4720
03-1Instruction Set (ISA) Design and Addressing Modes03-1Material from sections 2.1, 2.2, and 2.3.OutlineISA Design ChoicesIt's more than just picking instructions.ISA Design Choice DetailsScrew up, and you'll be cursed for decades.
LSU - EE - 4720
04-1Instruction Usage04-1Usage of DLX Instructions By SPEC92 Integer Codeand 3% 4% 5% 9% 13% 14% 16% 26% 0% compress eqntott 5% 10% 15% Total dynamic count espresso 20% gcc li 25% shift or store int compare int add intconditional branch loa
LSU - EE - 4720
08-1Interrupts and Exceptions08-1NotesMaterial in this set from Section 3.6.The book uses &quot;exception&quot; as a general term for all interrupts . . . . . . in these notes interrupt is used as the general term . . . . . . and a narrower definitio
LSU - EE - 4720
03-1Instruction Set (ISA) Design and Addressing Modes03-1 03-2ISA Design DecisionsI. OrganizationA. Data types (supported by ISA). B. Memory and register organization. C. Addressing modes.03-2Material from sections 2.1, 2.2, and 2.3.Outl
LSU - EE - 4720
12-1This Set12-1Material from Section 4.3This set under construction.Outline Branch Prediction Overview One-Level Predictor Two-Level Correlating Predictor Other topics to be added. Sample Problems12-1EE 4720 Lecture Transpare
LSU - EE - 4720
10-1Dynamic Scheduling10-1This Set Scheduling and Dynamic Execution Definitions From various parts of Chapter 4. Description of Two Dynamic Scheduling MethodsNot yet complete.(Material below may repeat material above.) Tomasulo's Algo
LSU - EE - 4720
LSU EE 4720Problem 1:# Cycle add \$t1, \$t2, \$t3 sub \$t4, \$t5, \$t1 lw \$t6, 4(\$t1) sw 0(\$t4), \$t6 0 1 IF IDHomework 3 Solution Due: 19 March 2003Consider the code below.(a) Show a pipeline execution diagram for the code running on the following
LSU - EE - 4720
09-1Multicycle Pipeline Operations09-1Material may be added to this set.Material CoveredSection 3.7.Long-Latency Operations (Topics)Typical long-latency instructions: floating pointPipelined v. non-pipelined execution unitsInitiatio
LSU - EE - 4720
03-1Instruction Set (ISA) Design and Addressing Modes03-1Material from sections 2.1, 2.2, and 2.3.OutlineISA Design ChoicesIt's more than just picking instructions.ISA Design Choice DetailsScrew up, and you'll be cursed for decades.
LSU - EE - 4720
12-1This Set12-1Material from Section 4.3This set under construction.Outline Branch Prediction Overview One-Level Predictor Two-Level Correlating Predictor Other topics to be added. Sample Problems12-1EE 4720 Lecture Transpare
LSU - EE - 4720
13-1Memory and Caches13-1See also cache study guide.ContentsSupplement to material in section 5.2.Includes notation presented in class.13-1EE 4720 Lecture Transparency. Formatted 12:18, 4 December 2006 from lsli13.13-113-2Memory
LSU - EE - 4720
13-1Memory and Caches13-1See also cache study guide.ContentsSupplement to material in section 5.2.Includes notation presented in class.13-1EE 4720 Lecture Transparency. Formatted 8:55, 30 November 2004 from lsli13.13-113-2Memory
LSU - EE - 4720
13-1Memory and Caches13-1See also cache study guide.ContentsSupplement to material in section 5.2.Includes notation presented in class.13-1EE 4720 Lecture Transparency. Formatted 13:15, 9 December 2007 from lsli13.13-113-2Memory
LSU - EE - 4720
NameSolutionComputer Architecture EE 4720 Midterm Examination, Part IMonday, 16 October 2000, 12:4013:30 CDTProblem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Alias Lets go Mets!(17 pts) Mon. (17 pts) Mon. (16 pts) Mon. (13 pts) Wed
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationFriday, 26 October 2001, 13:4014:30 CDTProblem 1 Problem 2 Problem 3 Problem 4 Alias Good Luck!(15 pts) (15 pts) (10 pts) (60 pts) (100 pts)Exam TotalProblem 1: The DLX implementation be
LSU - EE - 4720
NameSolutionComputer Architecture EE 4720 Midterm Examination22 March 2000, 13:4014:30 CSTProblem 1 Problem 2 Problem 3 Alias Good Luck!(35 pts) (20 pts) (45 pts) (100 pts)Exam TotalProblem 1: The DLX implementation below has six stages.
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationFriday, 25 October 2002, 10:4011:30 CDTProblem 1 Problem 2 Problem 3 Problem 4 Alias Good Luck!(30 pts) (13 pts) (13 pts) (44 pts) (100 pts)Exam TotalProblem 1: A new MIPS branch instruc
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationFriday, 27 October 2006, 12:4013:30 CDTProblem 1 Problem 2 Problem 3 Alias Good Luck!(50 pts) (20 pts) (30 pts) (100 pts)Exam TotalProblem 1: In the MIPS implementation below the data me
LSU - EE - 4720
NameComputer Architecture EE 4720 Midterm ExaminationWednesday, 29 March 2006, 11:4012:30 CSTProblem 1 Problem 2 Problem 3 Alias Good Luck!(10 pts) (40 pts) (50 pts) (100 pts)Exam TotalProblem 1: The MIPS code below runs on the illustrated
LSU - EE - 4720
MIPS32TM Architecture For Programmers Volume III: The MIPS32TM Privileged Resource ArchitectureDocument Number: MD00090 Revision 0.95 March 12, 2001MIPS Technologies, Inc. 1225 Charleston Road Mountain View, CA 94043-1353Copyright 2001 MIPS Te
LSU - EE - 4720
LSU EE 4720Statically Sched. MIPS Impl. Study GuideDavid M. KoppelmanSpring 20061.1 IntroductionAn important part of the course and a big chunk of midterm- and final-exam credit is on the statically scheduled MIPS implementations. Essentially
LSU - EE - 4720
09-1Multicycle Pipeline Operations09-1Material may be added to this set.Material CoveredSection 3.7.Long-Latency Operations (Topics)Typical long-latency instructions: floating pointPipelined v. non-pipelined execution unitsInitiatio
LSU - EE - 4720
NameComputer Architecture EE 4720 Practice Midterm ExaminationBefore 14 March 1997, 12:40 CSTModified 11 March 1998Problem 1 Problem 2 Problem 3 Problem 4 Alias Good Luck!(25 pts) (25 pts) (25 pts) (25 pts) (100 pts)Exam TotalProblem 1:
LSU - EE - 4720
02-1Quantitative Computer Design02-1 02-2Principles of Computer Design02-2Design guided by measured performance. Principles computer designers apply widely.Covered: Make the common case fast. Obviously. (Not covered.) Design Principles (
LSU - EE - 4720
02-1Quantitative Computer Design02-1Design guided by measured performance.Covered: Design Principles (1.6) Components of CPU Performance (Quantitative Principles) (1.6) Benchmarks (1.5)(Numbers refer to book sections.)02-1EE 4720
LSU - EE - 4720
09-1Multicycle Pipeline Operations09-1Material may be added to this set.Material CoveredSection 3.7.Long-Latency Operations (Topics)Typical long-latency instructions: floating pointPipelined v. non-pipelined execution unitsInitiatio
LSU - EE - 4720
12-1This Set12-1Material from Section 4.3This set under construction.Outline Branch Prediction Overview One-Level Predictor Two-Level Correlating Predictor Other topics to be added. Sample Problems12-1EE 4720 Lecture Transpare
LSU - EE - 4720
41.2A 1.3GHz Fifth Generation SPARC64 MicroprocessorHisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Ko
LSU - EE - 4720
fr-1Spring 2002 Final Exam Reviewfr-1When / WhereSaturday, 18 May 2002, 12:30-14:30 CDT (Here).ConditionsClosed Book, Closed NotesBring one 215 280 mm note sheet.No communication devices.FormatTwo or three or maybe four problems.
LSU - EE - 4720
mr-1Study RecommendationsSolve Old Problems Memorizing solutions is not the same as solving. Following and understanding solutions is not the same as solving. Use the solutions for brief hints and to check your own solutions.Spring 2002 Midterm E
LSU - EE - 4720
fr-1Fall 2004 Final Exam Reviewfr-1 fr-2 fr-2When / WhereStudy homework assigned this semester-test questions may be based on homework . Solve old problems, start with more recent problems. Memorizing solutions is not the same as solving. Follo
LSU - EE - 4720
05-1The DLX ISA05-1CoverageTextbook Section 2.8TopicsDLX GoalsDLX Instruction HighlightsDLX Instruction CodingSynthetic Instructions (NIB)05-1EE 4720 Lecture Transparency. Formatted 10:47, 31 August 2001 from lsli05.05-105-2
LSU - EE - 4720
11-1This Set11-1These slides do not give detailed coverage of the material. See class notes and solved problems (last page) for more information.Text covers multiple-issue machines in Chapter 4, but does not cover most of the topics presented
LSU - EE - 4720
06-1MIPS Implementation06-1 06-2Unpipelined Implementation06-2Material from Chapter 3 of H&amp;P (for DLX).Instruction fetch Instruction decode/ register fetch Memory access M u x Execute/ address calculation Write backMaterial from Chapter 6
LSU - EE - 4720
04-1Instruction Usage04-1 04-2Instruction Usage04-2Usage of DLX Instructions By SPEC92 Integer Code Usage of DLX Instructions By SPEC92 Floating-Point Codeshift 2% 2% 6% 6% 8% 8% 9% 11% 13% 23% 0% doduc ear hydro2d 5% 10% 15% Total dynamic
LSU - EE - 4720
02-1Components of CPU Performance and Performance Equation02-1Why is my computer fast (or slow)? ?Would it help to improveCPU performance equation is one way to start answering these questions.02-1EE 4720 Lecture Transparency. Formatted
Ohio State - MATH - 153
Formulas which you may use freely without reference: The Taylor series T (x) for f (x) centered at a is given byT (x) =n=0f (n) (a) (x - a)n . n! If f (x) is periodic with period b, the Fourier series F (x) for f (x) is given byF (x) = a0
Ohio State - CHEM - 121
Electron Configurations and Periodicity8.1 Electron Spin and the Pauli Exclusion Principle 8.2 Building-up Principle and the Periodic Table 8.3 Writing Electron Configurations using the Periodic TableElectron Spin In Chapter 7, we saw that electr
Ohio State - ENGL - 110.01
Syllabus, Spring Quarter 2009, English 110.01-First-Year Composition Instructor: Emilia Snyder (snyder.791@osu.edu), Denney Hall Rm. 503 by appointment Class meets: Mondays/Wednesdays, 9:30-11:18am, Denney Hall Rm. 312Rhetoric and the American Stor
Ohio State - ENGL - 110.01
A workshop critique typically takes the form of a letter addressed to the writer and signed by you. In your critique, you should address both what works and what doesn't work in the essay, offering revision strategies and examples for the author to c