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CHAP1

Course: CMPS 431, Fall 2008
School: S.E. Louisiana
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System Computer Overview Chapter 1 Operating System Exploits the hardware resources of one or more processors Provides a set of services to system users Manages secondary memory and I/O devices Basic Elements Processor Main Memory referred to as real memory or primary memory volatile I/O modules secondary memory devices communications equipment terminals System bus communication among processors,...

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System Computer Overview Chapter 1 Operating System Exploits the hardware resources of one or more processors Provides a set of services to system users Manages secondary memory and I/O devices Basic Elements Processor Main Memory referred to as real memory or primary memory volatile I/O modules secondary memory devices communications equipment terminals System bus communication among processors, memory, and I/ O modules Top-Level Components Processor Registers User-visible registers Enable programmer to minimize mainmemory references by optimizing register use Control and status registers Used by processor to control operating of the processor Used by operating-system routines to control the execution of programs User-Visible Registers May be referenced by machine language Available to all programs - application programs and system programs Types of registers Data Address Index Segment pointer Stack pointer User-Visible Registers Address Registers Index involves adding an index to a base value to get an address Segment pointer when memory is divided into segments, memory is referenced by a segment and an offset Stack pointer points to top of stack Control and Status Registers Program Counter (PC) Contains the address of an instruction to be fetched Instruction Register (IR) Contains the instruction most recently fetched Program Status Word (PSW) condition codes Interrupt enable/disable Supervisor/user mode Control and Status Registers Condition Codes or Flags Bits set by the processor hardware as a result of operations Can be accessed by a program but not altered Examples positive result negative result zero Overflow Instruction Cycle Instruction Fetch and Execute The processor fetches the instruction from memory Program counter (PC) holds address of the instruction to be fetched next Program counter is incremented after each fetch Instruction Register Fetched instruction is placed in the instruction register Types of instructions Processor-memory transfer data between processor and memory Processor-I/O data transferred to or from a peripheral device Data processing arithmetic or logic operation on data Control alter sequence of execution Example of Program Execution Direct Memory Access (DMA) I/O exchanges occur directly with memory Processor grants I/O module authority to read from or write to memory Relieves the processor responsibility for the exchange Processor is free to do other things Interrupts An interruption of the normal sequence of execution Improves processing efficiency Allows the processor to execute other instructions while an I/O operation is in progress A suspension of a process caused by an event external to that process and performed in such a way that the process can be resumed Classes of Interrupts Program arithmetic overflow division by zero execute illegal instruction reference outside user's memory space Timer I/O Hardware failure Interrupt Handler A program that determines nature of the interrupt and performs whatever actions are needed Control is transferred to this program Generally part of the operating system Interrupt Cycle Interrupt Cycle Processor checks for interrupts If no interrupts fetch next the instruction for the current program If an interrupt is pending, suspend execution of the current program, and execute the interrupt handler Multiple Interrupts Disable interrupts while an interrupt is being processed Processor ignores any new interrupt request signals Multiple Interrupts Sequential Order Disable interrupts so processor can complete task Interrupts remain pending until the processor enables interrupts After interrupt handler routine completes, the processor checks for additional interrupts Multiple Interrupts Priorities Higher priority interrupts cause lowerpriority interrupts to wait Causes a lower-priority interrupt handler to be interrupted Example when input arrives from communication line, it needs to be absorbed quickly to make room for more input Multiprogramming Processor has more than one program to execute The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt Memory Hierarchy Going Down the Hierarchy Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access of the memory by the processor locality of reference Disk Cache A portion of main memory used as a buffer to temporarily to hold data for the disk Disk writes are clustered Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk Cache Memory Invisible to operating system Increase the speed of memory Processor speed is faster than memory speed Cache Memory Cache Memory Contains a portion of main memory Processor first checks cache If not found in cache, the block of memory containing the needed information is moved to the cache Cache/Main Memory System Cache Design Cache size small caches have a significant impact on perfo...

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