Von-Neumann The Computer Model
Partitioning of the computing engine into components:
Central Processing Unit (CPU): Control Unit (instruction decode, sequencing of operations), Datapath (registers, arithmetic and logic unit, buses). Memory: Instruction and operand storage. Input/Output (I/O). The stored program concept: Instructions from an instruction set are fetched from a common memory and executed one at a time.
Control Memory (instructions, data)
Input
Datapath
registers ALU, buses
Output I/O Devices
Computer System
CPU
EECC550 - Shaaban
#1 Midterm Review Spring2001 4-18-2001
CPU Organization
Datapath Design:
Capabilities & performance characteristics of principal Functional Units (FUs): (e.g., Registers, ALU, Shifters, Logic Units, ...) Ways in which these components are interconnected (buses connections, multiplexors, etc.). How information flows between components.
Control Unit Design:
Logic and means by which such information flow is controlled. Control and coordination of FUs operation to realize the targeted Instruction Set Architecture to be implemented (can either be implemented using a finite state machine or a microprogram).
Hardware description with a suitable language, possibly using Register Transfer Notation (RTN).
EECC550 - Shaaban
#2 Midterm Review Spring2001 4-18-2001
Hierarchy of Computer Architecture
High-Level Language Programs Assembly Language Programs
Software
Machine Language Program
Application Operating System Compiler Firmware
Software/Hardware Boundary Hardware
Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design
Layout
Instruction Set Architecture
Microprogram
Logic Diagrams
Register Transfer Notation (RTN)
Circuit Diagrams
EECC550 - Shaaban
#3 Midterm Review Spring2001 4-18-2001
A Hierarchy of Computer Design
Level Name
1 2 3 Electronics Logic Organization
Modules
Gates, FF's Registers, ALU's ... Processors, Memories
Primitives
Transistors, Resistors, etc. Gates, FF's .... Registers, ALU's ...
Descriptive Media
Circuit Diagrams Logic Diagrams Register Transfer Notation (RTN)
Low Level - Hardware 4 Microprogramming Firmware 5 Assembly language programming Procedural Programming Application High Level - Software OS Routines Assembly language Instructions OS Routines High-level Languages Procedural Constructs Assembly Language Programs High-level Language Programs Problem-Oriented Programs Assembly Language Microinstructions Microprogram
6
Applications Drivers .. Systems
7
EECC550 - Shaaban
#4 Midterm Review Spring2001 4-18-2001
Instruction Set Architecture (ISA)
"... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation." Amdahl, Blaaw, and Brooks, 1964.
The instruction set architecture is concerned with:
Organization of programmable storage (memory & registers): Includes the amount of addressable memory and number of available registers. Data Types & Data Structures: Encodings & representations. Instruction Set: What operations are specified. Instruction formats and encoding. Modes of addressing and accessing data items and instructions Exceptional conditions.
EECC550 - Shaaban
#5 Midterm Review Spring2001 4-18-2001
Instruction Set Architecture (ISA) Instruction Specification Requirements
Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
Instruction Format or Encoding: How is it decoded? Location of operands and result (addressing modes): Where other than memory? How many explicit operands? How are memory operands located? Which can or cannot be in memory? Data type and Size. Operations What are supported Successor instruction: Jumps, conditions, branches. Fetch-decode-execute is implicit.
EECC550 - Shaaban
#6 Midterm Review Spring2001 4-18-2001
Types of Instruction Set Architectures
According To Operand Addressing Fields
Memory-To-Memory Machines:
Operands obtained from memory and results stored back in memory by any instruction that requires operands. No local CPU registers are used in the CPU datapath. Include: The 4 Address Machine. The 3-address Machine. The 2-address Machine.
The 1-address (Accumulator) Machine:
A single local CPU special-purpose register (accumulator) is used as the source of one operand and as the result destination.
The 0-address or Stack Machine:
A push-down stack is used in the CPU.
General Purpose Register (GPR) Machines:
The CPU datapath contains several local general-purpose registers which can be used as operand sources and as result destinations. A large number of possible addressing modes. Load-Store or Register-To-Register Machines: GPR machines where only data movement instructions (loads, stores) can obtain operands from memory and store results to memory.
EECC550 - Shaaban
#7 Midterm Review Spring2001 4-18-2001
Types of Instruction Set Architectures
Memory-To-Memory Machines: The 4-Address Machine
No program counter (PC) or other CPU registers are used. Instructions specify: Location of first operand. - Location of second operand. Place to store the result. - Location of next instruction.
Memory
CPU Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res
Instruction: add Res, Op1, Op2, Nexti Meaning: (Res Op1 + Op2)
Instruction Format
+
: :
Bits:
8 24
24
24
24
NextiAddr: Nexti
add
Opcode Which operation
ResAddr
Where to put result
Op1Addr
Op2Addr
NextiAddr
Where to find next instruction
Where to find operands
EECC550 - Shaaban
#8 Midterm Review Spring2001 4-18-2001
Types of Instruction Set Architectures
Memory-To-Memory Machines: The 3-Address Machine
A program counter is included within the CPU which points to the next instruction. No CPU storage (general-purpose registers).
Memory
CPU
Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res
Instruction:
+
add Res, Op1, Op2 Meaning: (Res Op1 + Op2)
: :
Where to find next instruction
Instruction Format
Bits:
8 24 24 24
NextiAddr: Nexti
Program 24 Counter (PC)
add
Opcode Which operation
ResAddr
Where to put result
Op1Addr
Op2Addr
Where to find operands
EECC550 - Shaaban
#9 Midterm Review Spring2001 4-18-2001
Types of Instruction Set Architectures
Memory-To-Memory Machines: The 2-Address Machine
The 2-address Machine: Result is stored in the memory address of one of the operands.
Memory
CPU
Instruction: add Op2, Op1 Meaning: (Op2 Op1 + Op2)
Instruction Format
Op1Addr: Op1
+
Op2Addr: Op2,Res
: :
Where to find next instruction
Bits:
8
24
24
add
Opcode Which operation
Op2Addr
Op1Addr
NextiAddr: Nexti
Program 24 Counter (PC)
Where to find operands
Where to put result
EECC550 - Shaaban
#10 Midterm Review Spring2001 4-18-2001
Types of Instruction Set Architectures
The 1-address (Accumulator) Machine
A single accumulator in the CPU is used as the source of one operand and result destination.
Memory
CPU
Instruction: add Op1 Meaning: (Acc Acc + Op1)
Instruction Format
Op1Addr: Op1
+
: :
NextiAddr: Nexti
Accumulator Where to find next instruction
Program 24 Counter (PC)
Where to find operand2, and where to put result
Bits:
8
24
add
Op1Addr
Opcode Where to find Which operand1 operation
EECC550 - Shaaban
#11 Midterm Review Spring2001 4-18-2001
Types of Instruction Set Architectures
The 0-address (Stack) Machine
Memory
push
A push-down stack is used in the CPU.
CPU
Stack Instruction Format Instruction: Bits: 8 24 push Op1 Meaning: push Op1Addr (TOS Op1)
Opcode Where to find operand
Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res
pop
TOS SOS etc. 8
Op2, Res Op1
add
+
: :
NextiAddr: Nexti
Instruction: Instruction Format add Bits: 8 Meaning: add (TOS TOS + SOS)
Opcode
Program 24 Counter (PC)
Instruction Format Instruction: 24 Bits: 8 pop Res pop ResAddr Meaning: (Res TOS) Opcode Memory
Destination
EECC550 - Shaaban
#12 Midterm Review Spring2001 4-18-2001
Types of Instruction Set Architectures
General Purpose Register (GPR) Machines
CPU contains several general-purpose registers which can be used as operand sources and result destination.
Memory
CPU
Registers
load
add
Op1Addr: Op1
+
: :
NextiAddr: Nexti
store
R8 R7 R6 R5 R4 R3 R2 R1
Instruction: load R8, Op1 Meaning: (R8 Op1)
Instruction Format Bits: 8
3 R8 24
load
Opcode
Op1Addr
Where to find operand1
Instruction: add R2, R4, R6 Meaning: (R2 R4 + R6)
Instruction Format 3 3 3 Bits: 8
add
R2 R4 R6
Opcode Des Operands
Program 24 Counter (PC)
Instruction: store R2, Op2 Meaning: (Op2 R2)
Instruction Format Bits: 8
3 R2 24
store
Opcode
ResAddr
Destination
EECC550 - Shaaban
#13 Midterm Review Spring2001 4-18-2001
Expression Evaluation Example with 3-, 2-, 1-, 0-Address, And GPR Machines
For the expression A = (B + C) * D - E
3-Address 2-Address
1-Address Accumulator where A-E are in memory
GPR 0-Address Register-Memory Load-Store Stack
push B push C add push D mul push E sub pop A
8 instructions Code size: 23 bytes 5 memory accesses
add A, B, C load A, B mul A, A, D add A, C sub A, A, E mul A, D sub A, E
load B add C mul D sub E store A
load R1, B add R1, C mul R1, D sub R1, E store A, R1
load R1, B load R2, C add R3, R1, R2 load R1, D mul R3, R3, R1 load R1, E sub R3, R3, R1 store A, R3
8 instructions Code size: about 29 bytes 5 memory accesses
3 instructions Code size: 30 bytes 9 memory accesses
4 instructions 5 instructions Code size: Code size:
28 bytes 12 memory accesses
20 bytes 5 memory accesses
5 instructions Code size: about 22 bytes 5 memory accesses
EECC550 - Shaaban
#14 Midterm Review Spring2001 4-18-2001
Typical ISA Addressing Modes
Addressing Mode
Register Immediate Displacement Indirect Indexed Absolute Memory indirect Autoincrement
Sample Instruction
Add R4, R3 Add R4, #3 Add R4, 10 (R1) Add R4, (R1) Add R3, (R1 + R2) Add R1, (1001) Add R1, @ (R3) Add R1, (R2) +
Meaning
R4 R4 + R3 R4 R4 + 3 R4 R4 + Mem[10+ R1] R4 R4 + Mem[R1] R3 R3 +Mem[R1 + R2] R1 R1 + Mem[1001] R1 R1 + Mem[Mem[R3]] R1 R1 + Mem[R2] R2 R2 + d R2 R2 - d R1 R1 + Mem[R2] R1 R1+ Mem[100+ R2 + R3*d]
Autodecrement
Add R1, - (R2)
Scaled
Add R1, 100 (R2) [R3]
EECC550 - Shaaban
#15 Midterm Review Spring2001 4-18-2001
Three Examples of Instruction Set Encoding
Operations & no of operands Address specifier 1 Address field 1 Address specifier n Address field n
Variable Length Encoding: VAX (1-53 bytes)
Operation Address field 1 Address field 2 Address field3
Fixed Length Encoding:
Operation Address field
DLX, MIPS, PowerPC, SPARC
Address Specifier
Operation
Address Specifier 1
Address Specifier 2
Address field
Operation
Address Specifier
Address field 1
Address field 2
Hybrid Encoding: IBM 360/370, Intel 80x86
EECC550 - Shaaban
#16 Midterm Review Spring2001 4-18-2001
Instruction Set Architecture Trade-offs
3-address machine: shortest code sequence; a large number of bits per instruction; large number of memory accesses. 0-address (stack) machine: Longest code sequence; shortest individual instructions; more complex to program. General purpose register machine (GPR): Addressing modified by specifying among a small set of registers with using a short register address (all machines since 1975). Advantages of GPR: Low number of memory accesses. Faster, since register access is currently still much faster than memory access. Registers are easier for compilers to use. Shorter, simpler instructions. Load-Store Machines: GPR machines where memory addresses are only included in data movement instructions between memory and registers (all machines after 1980).
EECC550 - Shaaban
#17 Midterm Review Spring2001 4-18-2001
Complex Instruction Set Computer (CISC)
Emphasizes doing more with each instruction. Motivated by the high cost of memory and hard disk capacity when original CISC architectures were proposed:
When M6800 was introduced: 16K RAM = $500, 40M hard disk = $ 55, 000 When MC68000 was introduced: 64K RAM = $200, 10M HD = $5,000
Original CISC architectures evolved with faster, more complex CPU designs, but backward instruction set compatibility had to be maintained. Wide variety of addressing modes:
14 in MC68000, 25 in MC68020
A number instruction modes for the location and number of operands:
The VAX has 0- through 3-address instructions.
Variable-length or hybrid instruction encoding is used.
EECC550 - Shaaban
#18 Midterm Review Spring2001 4-18-2001
Reduced Instruction Set Computer (RISC)
Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.
Goal: At least one instruction completed per clock cycle.
Designed with CPU instruction pipelining in mind. Fixed-length instruction encoding. Only load and store instructions access memory. Simplified addressing modes.
Usually limited to immediate, register indirect, register displacement, indexed.
Delayed loads and branches. Prefetch and speculative execution. Examples: MIPS, HP-PA, UltraSpark, Alpha, PowerPC.
EECC550 - Shaaban
#19 Midterm Review Spring2001 4-18-2001
RISC ISA Example:
MIPS R3000
Instruction Categories:
Load/Store. Computational. Jump and Branch. Floating Point (using coprocessor). Memory Management. Special.
4 Addressing Modes:
Base register + immediate offset (loads and stores). Register direct (arithmetic). Immedate (jumps). PC relative (branches).
Registers
R0 - R31
Operand Sizes:
Memory accesses in any multiple between 1 and 4 bytes.
PC HI LO
Instruction Encoding: 3 Instruction Formats, all 32 bits wide. R-Type I-Type: ALU
Load/Store, Branch
OP OP OP
rs rs
rt rt
rd
sa
funct
immediate
J-Type: Jumps
jump target
EECC550 - Shaaban
#20 Midterm Review Spring2001 4-18-2001
MIPS Memory Addressing & Alignment
MIPS uses Big Endian operand storage in memory where the most significant byte is in low memory (this is similar to IBM 360/370, Motorola 68k, Sparc, HP PA).
msb 0 1 2 3 0 1 2 3 lsb
MIPS requires that all words (32- bits) to start at memory addresses that are multiple of 4
Aligned
In general objects must fall on Not memory addresses that are multiple Aligned of their size.
EECC550 - Shaaban
#21 Midterm Review Spring2001 4-18-2001
MIPS Register Usage/Naming Conventions
In addition to the usual naming of registers by $ followed with register number, registers are also named according to MIPS register usage convention as follows:
Register Number Name 0 1 2-3 4-7 8-15 16-23 24-25 26-27 28 29 30 31 $zero $at $v0-$v1 $a0-$a3 $t0-$t7 $s0-$s7 $t8-$t9 $k0-$k1 $gp $sp $fp $ra
Usage
Preserved on call? n.a. no no yes no yes no yes yes yes yes yes
Constant value 0 Reserved for assembler Values for result and expression evaluation Arguments Temporaries Saved More temporaries Reserved for operating system Global pointer Stack pointer Frame pointer Return address
EECC550 - Shaaban
#22 Midterm Review Spring2001 4-18-2001
MIPS Addressing Modes/Instruction Formats
All instructions 32 bits wide
First Operand Second Operand Destination
Register (direct)
op
rs
rt
rd
register Immediate Displacement: Base+index
op op
rs rs
rt rt
immed immed + immed + Memory
Memory
register PC-relative op rs PC rt
EECC550 - Shaaban
#23 Midterm Review Spring2001 4-18-2001
MIPS Arithmetic Instructions Examples
Instruction add subtract add immediate add unsigned subtract unsigned add imm. unsign. multiply multiply unsigned divide divide unsigned Move from Hi Move from Lo Example add $1,$2,$3 sub $1,$2,$3 addi $1,$2,100 addu $1,$2,$3 subu $1,$2,$3 addiu $1,$2,100 mult $2,$3 multu$2,$3 div $2,$3 divu $2,$3 mfhi $1 mflo $1 Meaning $1 = $2 + $3 $1 = $2 $3 $1 = $2 + 100 $1 = $2 + $3 $1 = $2 $3 $1 = $2 + 100 Hi, Lo = $2 x $3 Hi, Lo = $2 x $3 Lo = $2 $3, Hi = $2 mod $3 Lo = $2 $3, Hi = $2 mod $3 $1 = Hi $1 = Lo Comments 3 operands; exception possible 3 operands; exception possible + constant; exception possible 3 operands; no exceptions 3 operands; no exceptions + constant; no exceptions 64-bit signed product 64-bit unsigned product Lo = quotient, Hi = remainder Unsigned quotient & remainder Used to get copy of Hi Used to get copy of Lo
EECC550 - Shaaban
#24 Midterm Review Spring2001 4-18-2001
MIPS Arithmetic Instructions Examples
Instruction add subtract add immediate add unsigned subtract unsigned add imm. unsign. multiply multiply unsigned divide divide unsigned Move from Hi Move from Lo Example add $1,$2,$3 sub $1,$2,$3 addi $1,$2,100 addu $1,$2,$3 subu $1,$2,$3 addiu $1,$2,100 mult $2,$3 multu$2,$3 div $2,$3 divu $2,$3 mfhi $1 mflo $1 Meaning $1 = $2 + $3 $1 = $2 $3 $1 = $2 + 100 $1 = $2 + $3 $1 = $2 $3 $1 = $2 + 100 Hi, Lo = $2 x $3 Hi, Lo = $2 x $3 Lo = $2 $3, Hi = $2 mod $3 Lo = $2 $3, Hi = $2 mod $3 $1 = Hi $1 = Lo Comments 3 operands; exception possible 3 operands; exception possible + constant; exception possible 3 operands; no exceptions 3 operands; no exceptions + constant; no exceptions 64-bit signed product 64-bit unsigned product Lo = quotient, Hi = remainder Unsigned quotient & remainder Used to get copy of Hi Used to get copy of Lo
EECC550 - Shaaban
#25 Midterm Review Spring2001 4-18-2001
MIPS data transfer instructions Examples
Instruction sw 500($4), $3 sh 502($2), $3 sb 41($3), $2 lw $1, 30($2) lh $1, 40($3) lhu $1, 40($3) lb $1, 40($3) lbu $1, 40($3) lui $1, 40 Comment Store word Store half Store byte Load word Load halfword Load halfword unsigned Load byte Load byte unsigned Load Upper Immediate (16 bits shifted left by 16) LUI R5 R5 0000 ... 0000
EECC550 - Shaaban
#26 Midterm Review Spring2001 4-18-2001
MIPS Branch, Compare, Jump Instructions Examples
Instruction branch on equal branch on not eq. set on less than set less than imm. set less than uns. set l. t. imm. uns. jump jump register jump and link Example beq $1,$2,100 bne $1,$2,100 slt $1,$2,$3 slti $1,$2,100 sltu $1,$2,$3 sltiu $1,$2,100 j 10000 jr $31 jal 10000 Meaning if ($1 == $2) go to PC+4+100 Equal test; PC relative branch if ($1!= $2) go to PC+4+100 Not equal test; PC relative branch if ($2 < $3) $1=1; else $1=0 Compare less than; 2's comp. if ($2 < 100) $1=1; else $1=0 Compare < constant; 2's comp. if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers go to 10000 Jump to target address go to $31 For switch, procedure return $31 = PC + 4; go to 10000 For procedure call
EECC550 - Shaaban
#27 Midterm Review Spring2001 4-18-2001
Example: C Assignment With Variable Index To MIPS
For the C statement with a variable array index: g = h + A[i]; Assume: g: $s1, h: $s2, i: $s4, base address of A[ ]: $s3 Steps:
Turn index i to a byte offset by multiplying by four or by addition as done here: i + i = 2i, 2i + 2i = 4i Next add 4i to base address of A Load A[i] into a temporary register. Finally add to h and put sum in g
MIPS Instructions:
add $t1,$s4,$s4 add $t1,$t1,$t1 add $t1,$t1,$s3 lw $t0,0($t1) add $s1,$s2,$t0 # $t1 = 2*i # $t1 = 4*i #$t1 = address of A[i] # $t0 = A[i] # g = h + A[i] EECC550 - Shaaban
#28 Midterm Review Spring2001 4-18-2001
Example: While C Loop to MIPS
While loop in C: while (save[i]==k) i = i + j; Assume MIPS register mapping: i: $s3, j: $s4, k: $s5, base of save[ ]: $s6 MIPS Instructions: Loop: add $t1,$s3,$s3 # $t1 = 2*i add $t1,$t1,$t1 # $t1 = 4*i add $t1,$t1,$s6 # $t1 = Address lw $t1,0($t1) # $t1 = save[i] bne $t1,$s5,Exit # goto Exit # if save[i]!=k add $s3,$s3,$s4 # i = i + j j Loop # goto Loop Exit:
EECC550 - Shaaban
#29 Midterm Review Spring2001 4-18-2001
MIPS R-Type (ALU) Instruction Fields
R-Type: All ALU instructions that use three registers
OP
6 bits
rs
5 bits
rt
5 bits
rd
5 bits
shamt
5 bits
funct
6 bits
op: Opcode, basic operation of the instruction. For R-Type op = 0 rs: The first register source operand. rt: The second register source operand. rd: The register destination operand. shamt: Shift amount used in constant shift operations. funct: Function, selects the specific variant of operation in the op field. Operand register in rs
Destination register in rd Operand register in rt
Examples:
add $1,$2,$3 sub $1,$2,$3
and $1,$2,$3 or $1,$2,$3
EECC550 - Shaaban
#30 Midterm Review Spring2001 4-18-2001
MIPS ALU I-Type Instruction Fields
I-Type ALU instructions that use two registers and an immediate value Loads/stores, conditional branches.
OP
6 bits
rs
5 bits
rt
5 bits
immediate
16 bits
op: Opcode, operation of the instruction. rs: The register source operand. rt: The result destination register. immediate: Constant second operand for ALU instruction.
Source operand register in rs Result register in rt
Examples:
add immediate: and immediate
addi $1,$2,100 andi $1,$2,10
Constant operand in immediate
EECC550 - Shaaban
#31 Midterm Review Spring2001 4-18-2001
MIPS Load/Store I-Type Instruction Fields
OP
6 bits
rs
5 bits
rt
5 bits
address
16 bits
op: Opcode, operation of the instruction. For load op = 35, for store op = 43. rs: The register containing memory base address. rt: For loads, the destination register. For stores, the source register of value to be stored. address: 16-bit memory address offset in bytes added to base register.
Offset base register in rs source register in rt
Examples:
Store word: Load word:
sw 500($4), $3 lw $1, 30($2)
base register in rs Offset
Destination register in rt
EECC550 - Shaaban
#32 Midterm Review Spring2001 4-18-2001
MIPS Branch I-Type Instruction Fields
OP
6 bits
rs
5 bits
rt
5 bits
address
16 bits
op: Opcode, operation of the instruction. rs: The first register being compared rt: The second register being compared. address: 16-bit memory address branch target offset in words added to PC to form branch address.
Register in rt Register in rs offset in bytes equal to instruction field address x 4
Examples:
Branch on equal Branch on not equal
beq $1,$2,100 bne $1,$2,100
EECC550 - Shaaban
#33 Midterm Review Spring2001 4-18-2001
MIPS J-Type Instruction Fields
J-Type: Include jump j, jump and link jal
OP
6 bits
jump target
26 bits
op: Opcode, operation of the instruction. Jump j op = 2 Jump and link jal op = 3 jump target: jump memory address in words.
Jump memory address in bytes equal to instruction field jump target x 4
Examples:
Branch on equal
j 10000
Branch on not equal jal 10000
EECC550 - Shaaban
#34 Midterm Review Spring2001 4-18-2001
Computer Performance Evaluation: Cycles Per Instruction (CPI)
Most computers run synchronously utilizing a CPU clock running at a constant clock rate:
where: Clock rate = 1 / clock cycle
A computer machine instruction is comprised of a number of elementary or micro operations which vary in number and complexity depending on the instruction and the exact CPU organization and implementation.
A micro operation is an elementary hardware operation that can be performed during one clock cycle. This corresponds to one micro-instruction in microprogrammed CPUs. Examples: register operations: shift, load, clear, increment, ALU operations: add , subtract, etc.
Thus a single machine instruction may take one or more cycles to complete termed as the Cycles Per Instruction (CPI).
EECC550 - Shaaban
#35 Midterm Review Spring2001 4-18-2001
Computer Performance Measures: Program Execution Time
For a specific program compiled to run on a specific machine "A", the following parameters are provided:
The total instruction count of the program. The average number of cycles per instruction (average CPI). Clock cycle of machine "A" How can one measure the performance of this machine running this program? Intuitively the machine is said to be faster or has better performance running this program if the total execution time is shorter. Thus the inverse of the total measured program execution time is a possible performance measure or metric: PerformanceA = 1 / Execution TimeA How to compare performance of different machines? What factors affect performance? How to improve performance?
EECC550 - Shaaban
#36 Midterm Review Spring2001 4-18-2001
Comparing Computer Performance Using Execution Time
To compare the performance of two machines "A", "B" running a given program: Performance A = 1 / Execution TimeA B Performance = 1 / Execution TimeB Machine A is n times faster than machine B means: n = PerformanceA / PerformanceB = Execution TimeB / Execution Time A Example: For a given program: Execution time on machine A: Execution A = 1 second Execution time on machine B: Execution B = 10 seconds Performance A / Performance B = Execution TimeB / Execution TimeA = 10 / 1 = 10 The performance of machine A is 10 times the performance of machine B when running this program, or: Machine A is said to be 10 times faster than machine B when running this program.
EECC550 - Shaaban
#37 Midterm Review Spring2001 4-18-2001
CPU Execution Time: The CPU Equation
A program is comprised of a number of instructions Measured in: instructions/program The average instruction takes a number of cycles per instruction (CPI) to be completed. Measured in: cycles/instruction CPU has a fixed clock cycle time = 1/clock rate Measured in: seconds/cycle
CPU execution time is the product of the above three parameters as follows:
CPU time CPU time = Seconds = Seconds Program Program = Instructions x Cycles x Seconds = Instructions x Cycles x Seconds Program Instruction Cycle Program Instruction Cycle
EECC550 - Shaaban
#38 Midterm Review Spring2001 4-18-2001
CPU Execution Time: Example
A Program is running on a specific machine with the following parameters:
Total instruction count: 10,000,000 instructions Average CPI for the program: 2.5 cycles/instruction. CPU clock rate: 200 MHz.
What is the execution time for this program:
CPU time CPU time = Seconds = Seconds Program Program = Instructions x Cycles x Seconds = Instructions x Cycles x Seconds Program Instruction Cycle Program Instruction Cycle
CPU time = Instruction count x CPI x Clock cycle = 10,000,000 x 2.5 x 1 / clock rate = 10,000,000 x 2.5 x 5x10-9 = .125 seconds
EECC550 - Shaaban
#39 Midterm Review Spring2001 4-18-2001
Factors Affecting CPU Performance
CPU time CPU time = Seconds = Seconds Program Program = Instructions x Cycles x Seconds = Instructions x Cycles x Seconds Program Instruction Cycle Program Instruction Cycle
Instruction Count Program Compiler Instruction Set Architecture (ISA) Organization Technology
CPI
Clock Rate
X X X
X X X X X X
EECC550 - Shaaban
#40 Midterm Review Spring2001 4-18-2001
Aspects of CPU Execution Time
CPU Time = Instruction count x CPI x Clock cycle
Depends on: Program Used Compiler ISA
Instruction Count
Depends on: Program Used Compiler ISA CPU Organization
CPI
Clock Cycle
Depends on: CPU Organization Technology
EECC550 - Shaaban
#41 Midterm Review Spring2001 4-18-2001
Performance Comparison: Example
From the previous example: A Program is running on a specific machine with the following parameters: Total instruction count: 10,000,000 instructions Average CPI for the program: 2.5 cycles/instruction. CPU clock rate: 200 MHz. Using the same program with these changes: A new compiler used: New instruction count 9,500,000 New CPI: 3.0 Faster CPU implementation: New clock rate = 300 MHZ What is the speedup with the changes?
Speedup Speedup = Old Execution Time = Iold xx CPIold = Old Execution Time = Iold CPIold New Execution Time Inew xx CPInew New Execution Time Inew CPInew xx Clock cycleold Clock cycleold xx Clock Cyclenew Clock Cycle
new
Speedup = (10,000,000 x 2.5 x 5x10-9) / (9,500,000 x 3 x 3.33x10-9 ) = .125 / .095 = 1.32 or 32 % faster after changes.
EECC550 - Shaaban
#42 Midterm Review Spring2001 4-18-2001
Instruction Types & CPI
Given a program with n types or classes of instructions with the following characteristics:
Ci = Count of instructions of type i CPIi = Average cycles per instruction of typei Then:
CPU clock cycles =
(CPI C )
n i =1 i i
EECC550 - Shaaban
#43 Midterm Review Spring2001 4-18-2001
Instruction Types & CPI: An Example
An instruction set has three instruction classes:
Instruction class A B C CPI 1 2 3
Two code sequences have the following instruction counts:
Code Sequence 1 2 Instruction counts for instruction class A B C 2 1 2 4 1 1
CPU cycles for sequence 1 = 2 x 1 + 1 x 2 + 2 x 3 = 10 cycles CPI for sequence 1 = clock cycles / instruction count = 10 /5 = 2 CPU cycles for sequence 2 = 4 x 1 + 1 x 2 + 1 x 3 = 9 cycles CPI for sequence 2 = 9 / 6 = 1.5 EECC550 - Shaaban
#44 Midterm Review Spring2001 4-18-2001
Instruction Frequency & CPI
Given a program with n types or classes of instructions with the following characteristics:
Ci = Count of instructions of type i CPIi = Average cycles per instruction of typei Fi = Frequency of instruction typei = Ci/ total instruction count Then:
CPI =
i =1
n
(CPI F )
i i
EECC550 - Shaaban
#45 Midterm Review Spring2001 4-18-2001
Instruction Type Frequency & CPI: A RISC Example
Base Machine (Reg / Reg) Op Freq Cycles CPI(i) ALU 50% 1 .5 Load 20% 5 1.0 Store 10% 3 .3 Branch 20% 2 .4
Typical Mix
% Time 23% 45% 14% 18%
CPI =
(CPI
n i =1
i
F )
i
CPI = .5 x 1 + .2 x 5 + .1 x 3 + .2 x 2 = 2.2 EECC550 - Shaaban
#46 Midterm Review Spring2001 4-18-2001
Metrics of Computer Performance
Application Programming Language Compiler ISA Datapath Control Function Units Transistors Wires Pins Cycles per second (clock rate). (millions) of Instructions per second MIPS (millions) of (F.P.) operations per second MFLOP/s Execution time: Target workload, SPEC95, etc.
Megabytes per second.
Each metric has a purpose, and each can be misused.
EECC550 - Shaaban
#47 Midterm Review Spring2001 4-18-2001
Types of Benchmarks
Pros
Representative Actual Target Workload
Cons
Very specific. Non-portable. Complex: Difficult to run, or measure. Less representative than actual workload.
Portable. Widely used. Measurements useful in reality.
Full Application Benchmarks
Easy to run, early in the design cycle. Identify peak performance and potential bottlenecks.
Small "Kernel" Benchmarks
Easy to "fool" by designing hardware to run them well. Peak performance results may be a long way from real application performance
Microbenchmarks
EECC550 - Shaaban
#48 Midterm Review Spring2001 4-18-2001
Computer Performance Measures : MIPS (Million Instructions Per Second)
For a specific program running on a specific computer MIPS is a measure of how many millions of instructions are executed per second:
MIPS = = = = Instruction count / (Execution Time x 10 6) Instruction count / (CPU clocks x Cycle time x 10 6) (Instruction count x Clock rate) / (Instruction count x CPI x 106) Clock rate / (CPI x 106)
Faster execution time usually means faster MIPS rating. Problems with MIPS rating:
No account for the instruction set used. Program-dependent: A single machine does not have a single MIPS rating since the MIPS rating may depend on the program used. Easy to abuse: Program used to get the MIPS rating is often omitted. Cannot be used to compare computers with different instruction sets. A higher MIPS rating in some cases may not mean higher performance or better execution time. i.e. due to compiler design variations.
EECC550 - Shaaban
#49 Midterm Review Spring2001 4-18-2001
Computer Performance Measures : MFOLPS (Million FLOating-Point Operations Per Second)
A floating-point operation is an addition, subtraction, multiplication, or division operation applied to numbers represented by a single or a double precision floating-point representation. MFLOPS, for a specific program running on a specific computer, is a measure of millions of floating point-operation (megaflops) per second:
MFLOPS = Number of floating-point operations / (Execution time x 106 )
MFLOPS is a better comparison measure between different machines than MIPS. Program-dependent: Different programs have different percentages of floating-point operations present. i.e compilers have no floatingpoint operations and yield a MFLOPS rating of zero. Dependent on the type of floating-point operations present in the program.
EECC550 - Shaaban
#50 Midterm Review Spring2001 4-18-2001
Performance Enhancement Calculations: Amdahl's Law
The performance enhancement possible due to a given design improvement is limited by the amount that the improved feature is used
Amdahl's Law: Performance improvement or speedup due to enhancement E:
Execution Time without E Speedup(E) = -------------------------------------Execution Time with E Performance with E = --------------------------------Performance without E
Suppose that enhancement E accelerates a fraction F of the execution time by a factor S and the remainder of the time is unaffected then:
Execution Time with E = ((1-F) + F/S) X Execution Time without E Hence speedup is given by: Execution Time without E 1 Speedup(E) = --------------------------------------------------------- = -------------------((1 - F) + F/S) X Execution Time without E (1 - F) + F/S
Note: All fractions here refer to original execution time.
EECC550 - Shaaban
#51 Midterm Review Spring2001 4-18-2001
Pictorial Depiction of Amdahl's Law
Enhancement E accelerates fraction F of execution time by a factor of S Before: Execution Time without enhancement E:
Unaffected, fraction: (1- F)
Affected fraction: F
Unchanged
Unaffected, fraction: (1- F)
After: Execution Time with enhancement E:
F/S
Execution Time without enhancement E 1 Speedup(E) = ------------------------------------------------------ = -----------------Execution Time with enhancement E (1 - F) + F/S
EECC550 - Shaaban
#52 Midterm Review Spring2001 4-18-2001
Performance Enhancement Example
For the RISC machine with the following instruction mix given earlier:
Op ALU Load Store Freq 50% 20% 10% Cycles 1 5 3 CPI(i) .5 1.0 .3 % Time 23% 45% 14%
CPI = 2.2
Branch 20% 2 .4 18% If a CPU design enhancement improves the CPI of load instructions from 5 to 2, what is the resulting performance improvement from this enhancement: Fraction enhanced = F = 45% or .45 Unaffected fraction = 100% - 45% = 55% or .55 Factor of enhancement = 5/2 = 2.5 Using Amdahl's Law:
1 1 Speedup(E) = ------------------ = --------------------- = (1 - F) + F/S .55 + .45/2.5 1.37
EECC550 - Shaaban
#53 Midterm Review Spring2001 4-18-2001
An Alternative Solution Using CPU Equation
Op ALU Load Store Freq 50% 20% 10% Cycles 1 5 3 CPI(i) .5 1.0 .3 % Time 23% 45% 14%
CPI = 2.2
Branch 20% 2 .4 18% If a CPU design enhancement improves the CPI of load instructions from 5 to 2, what is the resulting performance improvement from this enhancement: Old CPI = 2.2 New CPI = .5 x 1 + .2 x 2 + .1 x 3 + .2 x 2 = 1.6
Original Execution Time Speedup(E) = ----------------------------------New Execution Time Instruction count x old CPI x clock cycle = ---------------------------------------------------------------Instruction count x new CPI x clock cycle old CPI = ------------ = new CPI 2.2 --------1.6
= 1.37
Which is the same speedup obtained from Amdahl's Law in the first solution.
EECC550 - Shaaban
#54 Midterm Review Spring2001 4-18-2001
Performance Enhancement Example
A program runs in 100 seconds on a machine with multiply operations responsible for 80 seconds of this time. By how much must the speed of multiplication be improved to make the program four times faster?
Desired speedup = 4 = 100 ----------------------------------------------------Execution Time with enhancement
Execution time with enhancement = 25 seconds 25 seconds = (100 - 80 seconds) + 80 seconds / n 25 seconds = 20 seconds + 80 seconds / n
5 = 80 seconds / n n = 80/5 = 16
Hence multiplication should be 16 times faster to get a speedup of 4.
EECC550 - Shaaban
#55 Midterm Review Spring2001 4-18-2001
Extending Amdahl's Law To Multiple Enhancements
Suppose that enhancement Ei accelerates a fraction Fi of the execution time by a factor Si and the remainder of the time is unaffected then:
Speedup=
Original Execution Time
((1- F ) + F )XOriginal Execution Time
i i i i
S
i
i
Speedup=
1
((1- F ) + F )
i i i
S
i
Note: All fractions refer to original execution time.
EECC550 - Shaaban
#56 Midterm Review Spring2001 4-18-2001
Amdahl's Law With Multiple Enhancements: Example
Three CPU performance enhancements are proposed with the following speedups and percentage of the code execution time affected: Speedup1 = S1 = 10 Speedup2 = S2 = 15 Speedup3 = S3 = 30 Percentage1 = F1 = 20% Percentage1 = F2 = 15% Percentage1 = F3 = 10%
While all three enhancements are in place in the new design, each enhancement affects a different portion of the code and only one enhancement can be used at a time. What is the resulting overall speedup?
Speedup = 1
( (1 - F
i
i
)+
F S
i
i i
)
Speedup = 1 / [(1 - .2 - .15 - .1) + .2/10 + .15/15 + .1/30)] = 1/ [ .55 + .0333 ] = 1 / .5833 = 1.71
EECC550 - Shaaban
#57 Midterm Review Spring2001 4-18-2001
Pictorial Depiction of Example
Before: Execution Time with no enhancements: 1
S1 = 10 S2 = 15 S3 = 30
Unaffected, fraction: .55
F1 = .2
F2 = .15
F3 = .1 / 30
/ 10
Unchanged
/ 15
Unaffected, fraction: .55
After: Execution Time with enhancements: .55 + .02 + .01 + .00333 = .5833 Speedup = 1 / .5833 = 1.71 Note: All fractions refer to original execution time.
EECC550 - Shaaban
#58 Midterm Review Spring2001 4-18-2001
Major CPU Design Steps
1 Using independent RTN, write the microoperations required for all target ISA instructions. 2 Construct the datapath required by the microoperations identified in step 1. 3 Identify and define the function of all control signals needed by the datapath.
3 Control unit design, based on micro-operation timing and control signals identified:
- Hard-Wired: Finite-state machine implementation - Microprogrammed. EECC550 - Shaaban
#59 Midterm Review Spring2001 4-18-2001
Datapath Design Steps
Write the micro-operation sequences required for a number of representative instructions using independent RTN. From the above, create an initial datapath by determining possible destinations for each data source (i.e registers, ALU).
This establishes the connectivity requirements (data paths, or connections) for datapath components. Whenever multiple sources are connected to a single input, a multiplexer of appropriate size is added.
Find the worst-time propagation delay in the datapath to determine the datapath clock cycle. Complete the micro-operation sequences for all remaining instructions adding connections/multiplexers as needed.
EECC550 - Shaaban
#60 Midterm Review Spring2001 4-18-2001
Single Cycle MIPS Datapath
Necessary multiplexors and control lines are identified here:
EECC550 - Shaaban
#61 Midterm Review Spring2001 4-18-2001
R-Type Register-Register Timing
...