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Course: EE 525, Fall 2009School: Carnegie Mellon
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M3 Jacob Group Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis MILESTONE 13 Short Final Presentation April 20, 2005 DSP 'Swiss Army Knife' Overall Project Objective: General Purpose Digital Signal Processing Chip Project Description We aimed to implement a "general discrete-signal network that appears, in various forms, inside many digital signal processing (DSP)...
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M3
Jacob Group Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis
MILESTONE 13
Short Final Presentation
April 20, 2005
DSP 'Swiss Army Knife'
Overall Project Objective: General Purpose Digital Signal Processing Chip
Project Description
We aimed to implement a "general discrete-signal network that appears, in various forms, inside many digital signal processing (DSP) applications."[1] Specifically, the circuit is a `comb' filter followed by a second-order recursive network (referred to henceforth as a `biquad').
Project Description (Huh?)
What does that mean?
`Comb'
= selective additive delay `Biquad' = Feedback loop with multiply and adds.
Overall effect is to implement 22 distinct functions based on the input coefficients.
Marketing
Motivation
Marketing System Integration
How Does Our Circuit Fit Into the Bigger Picture? Focus on Audio/Video Applications
Audio:
Digital Radios / MP3 Players (i.e. Motorola, Lucent, Texas Instruments) Digital Music Synthesis / Sampling (i.e. Yamaha, Korg) Noise Reduction (i.e. Dolby)
Video:
Comb Filter to separate color and brightness (i.e. Sony, Toshiba)
Others:
Motor Control Functions such as RPM (i.e. Ford, GE)
Design Process
How did you get from description to actual implementation?
Behavioral/Algorithmic Description
How exactly does it work?
Dataflow
Example of function 1 of 22: The Moving Averager
Our circuit implements a simple moving average over 8 or 16 data points. An average is simply the sum of a data set divided by the number of data points. The moving average takes a set number of data points to be used and as new data comes in, old data "falls off" the end of the calculation.
For example...
Dataflow
A Moving Averager Smoothes a Signal to Reduce Noise
Dataflow
A moving average over 8 data points:
416395067218
4.625 4.125 3.625 1.375 1.125 4.25 4.75 3.0 2.25 1.0 0
Emulations C Code
Emulations - Soft-IP
Top Level Verilog Verified Complex Function
Floorplan Evolution
Road to Verification fp_mult verilog vs. schematic
VSIM 1> run # x xxxxxx xxxxx * x xxxxxx xxxxx = x xxxxxx xxxxx 0 000000 00000 * 0 000000 00000 = 0 000000 00000 0 011110 00000 * 1 011101 11000 = 1 011100 11000 0 100001 * 00100 0 100000 01000 = 0 100010 01101 0 100001 01110 * 0 100000 00001 = 0 100010 01111 100001 11100 * 0 100000 11110 = 0 100011 11010 100100 11110 * 0 100010 11000 = 0 101000 10110 100100 11110 * 1 100010 11000 = 0 101000 10110 100001 00010 * 0 100001 11110 = 0 100100 00000 Note: $finish : fp_mult_tb0.v(41) # Time: 9 ns Iteration: 0 Instance: /tester # # # # #0 #0 #1 #0 # **
Road to Verification fp_add verilog vs. schematic
VSIM 1> # x xxxxxx xxxxx + x xxxxxx xxxxx = x xxxxxx xxxxx # 0 000000 00000 + 0 000000 00000 = 0 000000 00000 # 0 011110 00000 + 1 011101 11000 = 0 011011 00000 # 0 100001 00100 + 0 100000 01000 = 0 100001 11000 # 0 100001 01110 + 0 100000 00001 = 0 100001 11110 # 0 100001 11100 + 0 100000 11110 = 0 100010 01101 # 0 100100 11110 + 0 100010 11000 = 0 100101 00110 # 1 100100 11110 + 1 100010 11000 = 1 100101 00110 # 0 100001 00010 + 0 100001 11110 = 0 100010 10000 # ** Note: $finish : fp_add_tb0.v(40) # Time: 9 ns Iteration: 0 Instance: /tester
Road to Verification Top Level Structural
Verified all of the functions for the `Swiss Army Knife' in Schematic. Plotted outputs using custom made code & MatLab. From plots it is evident that the accuracy is excellent.
Issues Encountered
Issues Encountered
Misunderstanding of DSP terms and main blocks represented in IEEE paper. Booth encoding was time consuming and problematic. Imaginary numbers proved less of a difficulty than we initially thought. Issues correctly identifying the source of errors in analog simulation.
Specs
Pin Specs
Inputs
(76 pins)
X[n] : 12 pins a1, a2, b0, b1, b2: 5 * 12 = 60 pins vdd, gnd, N, c1 : 4 * 1 = 4 pins
Outputs TOTAL:
(12 pins) 88 pins
Y[n] : 12 pins
Specs
Part Specs Fp_add:
Transistors: 2,274 Area: 103.5450m x 124.200m = 12,860.29m2 Density: 0.18
Fp_mult:
Transistors: 2,464 Area: 95.5450m x 141.750m = 13,543.50m2 Density: 0.18
Comb:
Transistors: 6,290 Area: 99.360m x 151.290m = 15,032.17m2 Density: 0.42
Specs
Chip Specs
Transistors:
34,564
Area:
434.520m x 395.460m = 171,835.28m2
Density
0.20
Layout
Layer Masks Full chip layout
Layout - Overlay
Conclusions
Jake
Layout?
Nick
Layout
/ Sims? / Matlab / C / DSP? / schematic / layout?
Darren
Verilog
Craig
Verilog
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