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CprE Name: 211 Spring 2003 Exam 2 Solution
Last Name (printed) First Name (printed) Signature ISU ID Number Lab Section _________________________ _________________________ _________________________ _________________________ _____________________
Instructions: Do not open this exam booklet until told to do so. Closed book. Closed notes. Calculator allowed. RCPU Reference Manual allowed. One-page, two-sided help sheet allowed. Be prepared to show this sheet to the instructor or submit it with your exam packet. Do all work in space provided. You must show your work to receive credit. Clearly indicate the answer you want counted. Make assumptions if necessary to work problems. Be sure to complete the five lines above. Cheating will not be tolerated by the instructor or your classmates and will result in a severe penalty. This is a 75-minute exam.
Question 1 2 3 Total
Points Possible 30 40 30 100
Points
NOTE: Unless specified otherwise, you should assume that for questions involving C or assembly code, the target is the MPC555 used in the lab.
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1. Embedded Programming using Assembly (30 points) "What is the result" means what registers/memory are affected and what are the values. a. Assume the contents of register r6 is (r6)= 0x0000FFFF, and r23 is (r23)= 0x00FFFFA3. i. What is the result of the instruction: or r23, r23, r6
r23 ! (r23) | (r6) = 0x00FFFFA3 | 0x0000FFFF = 0x00FFFFFF Changes register contents: R23 00FFFFFF 3 pts. ii. What is the result of adding the period: (be specific) or. r23, r23, r6
Changes the Condition Register, depending on whether result is less than, greater than, or equal to 0. In this case, the result is greater than 0. So the GT bit of CR0 is set to true (1). CR0 [LT GT EQ SO] ! 0100 3 pts. b. Consider the following memory dump and PowerPC registers. Assume that byte-ordering is big endian (big byte first, i.e., MSB at lower address) and memory addresses are 32 bits wide. Each question is independent.
Address Memory Contents Register Register Contents
30001FF8 30002000 30002008 30002010
25 00 AC 01
24 FE AE 23
5B 25 81 55
1A 24 83 3F
AC 5B 45 AC
57 1A 67 CB
9C EE 89 F0
8D 05 25 8D
R20 R21 R22 R23 r22, 5 (r21)
30002000 30001FFF 0000000A FFFFFFEE
i. What is the result of the instruction:
lbz
Mb[5+0x30001FFF] = Mb[0x30002004] = 0x5B, so r22 ! 0x0000005B Changes register contents: R22 0000005B 3 pts. ii. What is the result of the instruction: sthx r21, r20, r22
r21 = 0x30001FFF Mh[r20 + r22] = Mh[0x30002000+0x0000000A] = Mh[0x3000200A] ! 0x1FFF Changes memory contents: 30002008 AC AE 1F FF 45 67 89 25 3 pts. iii. Is the branch to "next" taken? YES cmpwi r22, 0x0A or NO This checks the value in r22.
0x0000000A 0x0A = 0
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beq next 3 pts.
= 0? YES
iv. Is the branch to "next" taken? YES cmpw r23, r22 blt next
or
NO
0xFFFFFFEE-0x0000000A = -18 -(+10) = -28 = 0xFFFFFFE4 < 0? YES
This treats the contents of r22 and r23 as signed numbers. Since r23 is a negative number (-18) and r22 is a positive number (+10), r23 is less than r22. 2 pts. c. Write assembly code to place the address IO_DIGITAL_INPUT_DIP_1 into register R6. Refer to the defines.h file at the end of the exam packet. lis ori --lis ori 3 pts. d. Write assembly code to store the least significant byte of register R9 into memory location 0x2000C007. lis ori stb --lis stb 4 pts. e. Given the declaration: char errorString[256]. Let (R15) = errorString. That is, register R15 contains the starting address of the array. i. Write the assembly code to store a byte from register R20 into errorString[200]. stb 4 pts.
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r6, IO_DIGITAL_INPUT_DIP_1@h r6, r6, IO_DIGITAL_INPUT_DIP_1@l
r6, 0x4000 r6, r6, 0x000B
r0, 0x2000 r0, r0, 0x0007 r9, 0(r0)
r0, 0x2000 r9, 0x0007 (r0)
r20, 200 (r15)
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ii.
TRUE or FALSE:
The assembler will report an error if the assembly program has code that stores a byte into memory location (R15)+300. 2 pts. NOTE: This does not refer to instruction syntax. It simply means that the instruction calculates an effective address using base-displacement, in which address = (R15)+300.
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2. Control Flow and Data Structures in Assembly (40 points) a. Refer to the code for function AddNibbles at the end of the exam packet for part a. i. Which lines of the assembly code correspond to the for loop? Give the range of line numbers.
A for loop in C code starts with "for" and includes the expressions in parentheses as well as the statements in braces { }. lines 4-12 4 pts.
ii.
Which lines of the assembly code correspond to the if statement? Give the range of line numbers.
An if statement in C code starts with "if" and includes the expressions in parentheses as well as the statement followed by a semicolon. lines 5-9 4 pts. iii. Consider the following memory dump and PowerPC registers. Assume that byte-ordering is big endian (big byte first, i.e., MSB at lower address) and memory addresses are 32 bits wide. Suppose that these are the contents upon entry into the function, i.e., at the start of the function before executing line 1 of the assembly code.
Address Memory Contents Register Register Contents
30001FF8 30002000 30002008 30002010
25 06 AC 01
24 FE AE 23
5B 95 81 55
1A 24 83 3F
AC 5B 45 AC
57 8A 67 CB
9C 1E 89 F0
8D 05 25 8D
R1 R3 R4 R28 R29 R30 R31
3000F800 30002000 00000006 2FFE0011 000000F0 ACAE8183 00001E05
4 pts each for a-d (a) What is the contents of register R29 after line 5 executes for the first time? byte from Mem[R3+R30], where R30=0 (line 4), R3=30002000, is 0x06 R29 ! 0x00000006
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(b) How many times is line 5 executed in this call to the function? the for loop is executed NumElements times, which is passed as a parameter in R4, where R4 = 0x00000006 6 times (c) What is the contents of register R3 when line 16 is executed? R3 has the return value sumLowNib, calculated from the bytes FE, 95, 8A, as E+5+A R3: 0x0000001D (d) What is the value of array element arr[2]? the starting address of the char array "arr" is R3 = 30002000; byte from Mem[30002000+2] is 0x95 0x95
b. Consider the following variable declarations. short S[3]; char A[3]; long T[2]; int B; struct rec { char c; int i[2]; long v; } R; Assume that this block of variables is allocated to a data space in memory beginning at address 0x30001FF8. Assume: byte-ordering is big endian (big byte first, i.e., MSB at lower address) memory addresses are 32 bits, int data type is 32 bits variables must satisfy alignment requirements Consider the following memory dump and PowerPC registers.
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Address
Memory Contents
Register
Register Contents
30001FF8 30002000 30002008 30002010 30002018 30002020 30002028 S: A: T: B: R: i.
25 06 AC 01 01 67 AC
24 FE AE 23 23 89 57
5B 95 81 55 55 25 24
1A 24 83 3F 3F 3F 5B
AC 5B 45 AC AE 06 1A
57 8A 67 CB 81 FE AC
9C 1E 89 F0 83 95 F0
8D 05 25 8D 8D 24 8D
R31
30001FF8
What is the TOTAL size in bytes used by the variable data space? 40 bytes
3 pts ii. What is the starting address of array T? 0x30002004 4 pts iii. What the is value of structure field R.v? 0xAE81838D 4 pts iv. Given R31, write a PowerPC instruction for putting the value of S[1] into R30. lhz R30, 2(R31) 5 pts
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3. Functions in Assembly (30 points) Refer to the code for function AddNibbles at the end of the exam packet. Suppose that function main calls function AddNibbles. Consider the following memory dump and PowerPC registers. Suppose that these are the contents upon entry into the function, i.e., at the start of the function before executing line 1 of the assembly code.
Address Memory Contents Register Register Contents
30001FF8 30002000 30002008 30002010
25 06 AC 01
24 FE AE 23
5B 95 81 55
1A 24 83 3F
AC 5B 45 AC
57 8A 67 CB
9C 1E 89 F0
8D 05 25 8D
R1 R3 R4 R28 R29 R30 R31 LR
3000F800 30002000 00000006 2FFE0011 000000F0 ACAE8183 00001E05 20004308
a. Draw the EABI-compliant stack frame for the function AddNibbles. The stack is shown upon entry into the function. Place actual values, where appropriate, into memory locations on the stack. Address 3000F804 3000F800
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LR Save Word Back Chain Word R31: 0x00001E05 R30: 0xACAE8183 R29: 0x000000F0 R28: 0x2FFE0011 c.i. 0x20004308 SP
header for AddNibbles
LR Save Word Back Chain Word ! SP
12 pts for values saved from R28-R31 4 pts for header words
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b. What is the total size, in bytes, of the stack frame for function AddNibbles? 6 words = 24 bytes 3 pts c. Suppose function AddNibbles is modified and calls another function. i. Where is the current Link Register saved? Place its value on the stack drawing in part a.
see stack diagram; value written at 0x3000F804, i.e., 28(SP) 3 pts ii. Re-write the prologue for the function (see lines 1-2).
add code to save LR addi stmw mflr stw 4 pts SP, SP, -24 r28, 8(SP) r0 r0, 28(SP)
iii.
Re-write the epilogue for the function (see lines 14-15).
add code to restore LR lwz r0, 28(SP) mtlr r0 lmw r28, 8(SP) addi SP, SP, 24 4 pts
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Code for Function AddNibbles C Code
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // short AddNibbles(char *arr, short numElements) // description: // Returns a short value that is the summation of the lower nibble values in the // array for array elements in which bit 7 is set to 1 // // params: // char *arr: char array used to sum lower nibbles of elements in array // short numElements: number of elements in the char array // // returns: // returns the summation of lower nibble values for elements in which bit 7 = 1 short AddNibbles(char *arr, short numElements) { //short local var to store the summation of lower nibble values short sumLowNib = 0; //walk through the array, summing lower nibble values //in the array for elements having bit 7 = 1 for (int I=0; I<numElements; I++) { //if bit 7 of arr[I] is 1, add the lower nibble of arr[I] to sumLowNib if ( (arr[I]&0x80) == 0x80) sumLowNib += arr[I]&0x0F; } //return the summed value return sumLowNib; }
Assembly Code is on the next page.
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Assembly Code
AddNibbles: // // // // // // // Register Usage r3 arr, return r4 numElements r31 sumLowNib r30 I r29 arr[I] r28 temporary
// Line number is shown on the left
1. 2. 3. 4. 5. 6. 7. 8. 9.
addi SP, SP, -24 ;create a 24-byte (6-word) stack frame stmw r28, 8(SP) li li ForLoop: r31, 0 r30, 0 lbzx r29, r3, r30 ;store bank of NV registers, R28-R31
andi. r28, r29, $80 beq SkipSum
andi r29, r29, $0F add r31, r31, r29 addi r30, r30, 1
10. SkipSum: 11. 12.
cmpw r30, r4 blt ForLoop r3, r31 ;restore bank of NV registers, R28-R31
13. Done: mr 14. 15. 16.
lmw r28, 8(SP)
addi SP, SP, 24 ;remove 24-byte (6-word) stack frame blr
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defines.h // Defines.h : Definition file for PowerPC ////////////////////////////////////////////////////////// // I/O ports // // All I/O ports are 8 bit ports // #define #define #define #define #define #define #define #define #define #define IO_DIGITAL_INPUT_1 IO_DIGITAL_INPUT_2 IO_DIGITAL_INPUT_DIP_1 IO_DIGITAL_INPUT_DIP_2 IO_DIGITAL_INPUT_KEYPAD IO_DIGITAL_OUTPUT_LED1 IO_DIGITAL_OUTPUT_LED2 IO_DIGITAL_OUTPUT_1 IO_DIGITAL_OUTPUT_2 IO_DIGITAL_OUTPUT_7SEG 0x40000003 0x40000007 0x4000000B 0x4000000F 0x40000013 0x40000023 0x40000027 0x4000002B 0x4000002F 0x40000033
EABI Register Usage
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PowerPC / MPC555 Assembly Instructions
Instruction add. rD, rA, rB addi rD, rA, value addis rD, rA, value and rA, rS, rB andi. rA, rS, value andis. rA, rS, value b target_addr ble target_addr blt target_addr beq target_addr bge target_addr bgt target_addr blr target_addr bne target_addr cmpw rA, rB cmpwi rA, value cmplw rA, rB la rD, label lbz rD, d(rA) lbzx rD, rA, rB lhz rD, d(rA) lhzx rD, rA, rB li rA, value lis rA, value lwz rD, d(rA) lwzx rD, rA, rB mr rA, rS not rA, rS ori rA, rS, value oris rA, rS, value slwi rA, rS, value srwi rA, rS, value stb rS, d(rA) stbx rS, rA, rB sth rS, d(rA) sthx rS, rA, rB stw rS, d(rA) stwx rS, rA, rB sub rD, rA, rB subi rD, rA, value subis rD, rA, value Description Add Add immediate Add imm. shifted left by 16 bits AND AND Immediate AND Imm. shifted left by 16 bits Branch Always Branch if less than or equal to 0 Branch if less than 0 Branch if equal (EQ of CR0 set) Branch if greater than or equal to Branch if greater than 0 Branch to LR (Link Register) Branch if not equal to 0 Compare Word Compare Word Immediate Compare Logical Word Load Address based upon offset Load Byte and Zero Load Byte and Zero Indexed Load Half Word and Zero Load Half Word and Zero Indexed Load immediate Load imm. shifted left by 16 bits Load Word and Zero Load Word and Zero Indexed Move Register Complement Register (invert) OR Immediate OR Imm. shifted left by 16 bits Shift Left Immediate Shift Right Immediate Store Byte Store Byte Indexed Store Half Word Store Half Word Indexed Store Word Store Word Indexed Subtract Subtract Immediate Subtract Immediate shifted left by 16 bits Other Registers Altered CR0 (LT, GT, EQ, SO) None None None CR0 (LT, GT, EQ, SO) CR0 (LT, GT, EQ, SO) None Explanation of Operation rD rA + rB rD rA + value rD rA + (value << 16) rA rS & rB rA rS & value rA rS & (value << 16) Branch to target_addr Branch to target_addr if LT = 1 or None EQ = 1 None Branch to target_addr if LT = 1 None Branch to target_addr if EQ = 1 Branch to target_addr if GT = 1 None or EQ = 1 None Branch to target_addr if GT = 1 None Branch and link to target_addr None Branch to target_addr if EQ = 0 CR0 (LT, GT, EQ, SO) rA - rB CR0 (LT, GT, EQ, SO) rA - value CR0 (LT, GT, EQ, SO) rA rB (unsigned integers) None rD label None rD m[rA + d] None rD m[rA + rB] None rD M[rA +d]15..0 None None None None None None None None None None None None None None None None None None None None rD M[rA +rB]15..0 rA value rA (value << 16) rD M[rA + d] rD M[rA + rB] rA rS rA ~rS rA rS | value rA rS | (value << 16) rA (rS << value) rA (rS >> value) m[rA + d] rS7..0 m[rA + rB] rS7..0 M[rA + d]15..0 rS15..0 M[rA + rB]15..0 rS15..0 M[rA + d] rS M[rA + rB] rS rD rA - rB rD rA - value rD rA - (value << 16)
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