Design Hardware Tips
EE 361 University of Hawaii
EE 361 Fall 2003
University of Hawaii
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Outline
Verilog: some subleties Simulators Test Benching Implementing the MIPS
Actually a simplified 16 bit version
EE 361 Fall 2003
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Monday
Overview of verilog, again Implementing combinational circuits using verilog
Rules to avoid problems
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Verilog
Basic module Combinational subcircuits Sequential subcircuits (on wed)
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Verilog: Basic Module
module circuitName(y1,y2,clock,reset,select,x1,x2,x3) output y1,y2; input clock, reset; input select, x1, x2, x3; wire h1,h2,h3; reg k1,k2;
outputs: only wire variables
// Instantiations Circuit circuit1(h1,h2,clock,h3,5,k1,k2); endmodule
inputs: wire vars, reg variables, constants
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EE 361 Fall 2003
Combinational Circuits
Continuous assign Procedural always
Rules Examples of errors More rules
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Verilog: Combinational Subcircuits
x1 x2 x3 Continuous assign assign y = x1 + x2 + 3; Formula ( no begin-end blocks, if-else, wire var case statements, or anything else)
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Combinational subcircuit
y
Verilog: Combinational Subcircuits Sensitivity List
Procedural always always @(x1 or x2 or ... or xk) A description of how to compute outputs from the inputs
Rule of thumb: List of all inputs From this description you should be able to write a truth table for the circuit Be sure the table is complete, i.e., it covers all possible inputs OR For all input values, there should be an output value
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Example: always @(x1 or x2) y = x1 + x2 + 3;
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Example: missing an input in // 2:1 multiplexer the sensitivity list module mux(y, sel, a, b)
// 2:1 multiplexer module mux(y, sel, a, b) input a, b, sel; output y; always (a or b or sel) begin if (sel == 0) y = a; else y = b; end endmodule
input a, b, sel; output y; always (a or b) begin if (sel == 0) y = a; else y = b; end endmodule
Case of missing an input ("sel") in the sensitivity list.
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Example: outputs are not defined for all inputs // 2:1 multiplexersel, a, b) module mux(y,
// 2:1 multiplexer module mux(y, sel, a, b) input a, b, sel; output y; always (a or b or sel) begin if (sel == 0) y = a; else y = b; end endmodule
input a, b, sel; output y; always (a or b or sel) begin if (sel == 0) y = a; end endmodule
Case of not updating y for all inputs
Possible hardware implementation a It's a transparent D latch 2:1 mux y sel
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Example
always @(x1 begin if (s == else h = Computation proceeds case(h) downwards 0: y (just like 1: y C language) endcase end Variables inputs: x1, x2, s output: y intermediate value: h or x2 or s) 1) h = 0; 1; = x1|x2; // AND the inputs = x1&x2; // OR the inputs
Truth table for circuit
Next, we'll present some rules to use procedural always to model combinational circuits
EE 361 Fall 2003 University of Hawaii
Input s x1 x2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Output y 0 1 1 1 0 0 0 1 11
Rules for procedural-always to model combinational circuits
Assignments y = x1 + x2 + 3; Blocking assignment (we'll discuss blocking and nonblocking assignments shortly) reg variable Note that the left hand side is always an output or intermediate variable
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Rules for procedural-always to model combinational circuits
Update variables at most once
always @(x1 or x2) begin y = x1 + x2; if (y > 4) y = x1; else y = x2; end y could be updated more than once BUT outputs shouldn't change twice when inputs change
EE 361 Fall 2003 University of Hawaii
always @(x1 or x2) begin r = x1 + x2; if (r > 4) y = x1; else y = x2; end We introduced a new reg variable r. Now "r" and "y" are updated at most once.
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Rules for procedural-always to model combinational circuits
always @(x1 or x2) begin blocking assigments (e.g., y = x1+x2;) if-else case statements end module .... always @(x1 or x2) begin Circuit circ1(y,x1,x2); end This won't work. A module is not endmodule a C function. module Circuit(h,g1,g2) output h; input g1, g2 assign h=g1+g2; endmodule
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Some rules to design combinational circuits with "always"
Sensitivity list should have all inputs Outputs should have values for all possible inputs Variables that are updated (left side of blocking assignments) should be a register variable Update each variable at most once per change in input. Module instantiations are not C function calls
Use blocking assignments, case, if-else, maybe others such as "for" but be careful.
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Wednesday
Sequential circuits with verilog Electronic Design Automation (EDA)
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Sequential Circuits
Procedural always Examples Nonblocking and blocking assignments
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Rules for procedural-always to model sequential circuits
x1 x2 x3
state
clock
y1 y2
= state
Example: D flip flop always @(posedge clock) q <= d;
we'll assume this
Example: T flip flop always @(posedge clock) if (t == 1) q <= ~q;
always @(posedge clock) Update the state
state vars are reg vars.
EE 361 Fall 2003
nonblocking assignments
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Nonblocking Assignments
A 0 D Q D B Q D C Q clock clock clock clock
All flip flops get updated together on a positive clock edge.
always @(posedge clock) begin A <= 0; B <= A; C <= B; end
All nonblocking assignments are updated together on the positive edge of the clock.
Example
A 0 D Q 1
B D Q 0
C D Q 1 0
A D Q 0
B D Q 1
C D Q 0
clock clock
clock
clock clock
clock
clock
clock
Before clock edge
After clock edge
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Nonblocking Assignments
A 0 D Q D B Q D C Q clock clock clock clock
Suppose initially (A,B,C) = (1,1,1)
begin A <= 0; B <= A; C <= B; end begin A = 0; B = A; C = B; end
(A,B,C) = (0,1,1)
EE 361 Fall 2003
(A,B,C) = (0,0,0)
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Example: 2-bit counter
module counter2(q,clock,s,d) out [1:0] q; // 2-bit output in clock; s [1:0] s; // Select input in [1:0] d; // Parallel load input reg [1:0] q;
d[1] d[0]
q[1] q[0]
s[1] s[0] clock
s = 0: s = 1: s = 2: s = 3:
reset q = 0 count up count down load
// This is our state variable
always @(posedge clock) begin case (s) 0: q<=0; 1: q<=q+1; // Counting up. Note that the count wraps around // when it goes past the value 3 2: q<=q-1; // Counting down. Also has wrap around 3: q<=d; // Parallel load endcase // Actually, the begin-end is unnecessary end endmodule EE 361 Fall 2003 University of Hawaii 21
Example: Lights
module Lights(y,clock,s,d) out [3:0] y; // 4-bit output in clock; s [1:0] s; // Select input in [1:0] d; // Parallel load input reg [1:0] q;
s[1] s[0]
clock s = 0: s = 1: s = 2: s = 3:
y[3] y[2] y[1] y[0] reset y=1000 rotate right rotate left hold
// This is our state variable
always @(posedge clock) begin case (s) 0: q<=0; 1: q<=q+1; // Counting up. Note that the count wraps around // when it goes past the value 3 2: q<=q-1; // Counting down. Also has wrap around 3: q<=q; // Hold endcase // Actually, the begin-end is unnecessary end // Continued EE 361 Fall 2003 University of Hawaii 22
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Example: Lights
// Continued always @(q) case (q) 0: y=4'b1000; 1: y=4'b0100; 2: y=4'b0010; 3: y=4'b0001; endcase endmodule
s[1] s[0]
clock s = 0: s = 1: s = 2: s = 3:
y[3] y[2] y[1] y[0] reset y=1000 rotate right rotate left hold
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Electronic Design Automation
Simulator EDA process Test bench
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Simulators, e.g., veriwell and Modelsim
Simulator will simulate what a circuit will do over time.
Time is divided into time units (fictitious) but you can think of them as some small time duration, e.g., 0.1ns A variable keeps track of the "current time" (e.g., $time) Initially, "current time" = 0 (or 1) Update variable values at time 1 based upon values at time 0 Update variable values at time 2 based upon values at time 1 and so on.
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Example
$time = 0
0 0 1 0 0 1
1 $time = 1
1 0 1
new value based on
$time = 2
1
EE 361 Fall 2003
0 0
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Simulator
verilog circuit module verilog testbench module
project
synthesizer simulator hardware verify that your circuit works (debugging)
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EE 361 Fall 2003
Test Bench
Protoboard 5V Gnd IC Chip Clock Generator
LEDs (probes)
inputs to excite the circuit
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outputs to observe behavior
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module testbench; reg clock; reg [1:0] A; reg [2:0] B; wire [2:0] C; icChip // Clock signal // Inputs A and B to excite // Output C to observe
c1(A,B,C,clock); // Instantiation of the circuit to test
init clock = 0; // Clock generation, with clock period = 2 time units always #1 clock = ~clock; init begin: Input A = 0; B = 0; #2 A = 1; // #1 B = 3; // #2 $stop; // end // Changing inputs to excite icChip c1 values for testing
After 2 time units, A is changed to 1. After another time unit, B changes to 3. After 2 more time units, the simulation stops
init begin: Display $display("A B C $monitor("%d %d %d %d // Note that $monitor // while $display can end endmodule
// Display of outputs clock time"); // Displayed once at $time = 0 %d",A,B,C,clock,$time); // Displayed whenever variable changes can occur at most once in verilog code occur many times.
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Friday
Building single cycle MIPS naive way MIPS-L: 16 bit version of MIPS Build it in stages
MIPS-L0: executes only R-type instructions
Tips on testing and debugging
MIPS-L1, L2, L3
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Building Single Cycle MIPS
How NOT to build a single cycle MIPS in verilog. Build all the components in verilog. Test/debug each component Put everything together into the single cycle MIPS Simulate --> syntax errors Fix syntax errors, and then simulate --> `xxx' Hmmm. Maybe I'm unlucky. Simulate again. Hmmm. Must be the simulator. Reset PC. Simulate again. 8. Problem too hard -- it's a complicated computer after all First three steps are okay. But need improvement after that.
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1. 2. 3. 4. 5. 6. 7.
MIPS-L
To experience building a moderately large circuit, you will build a MIPS computer
Homework 10A and 10B
MIPS-L: 16 bit version of MIPS
Description Simplified version MIPS-L0
Only R-type arithmetic instructions Modified register file: RegFileL0
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MIPS-L Description
Instructions (and integer data) are 16 bits long Word = 16 bits Addresses are 16 bits Eight general purpose registers $0-$7 $0 is always equal to 0 Memory is byte-addressable and big Endian Addresses of words are divisible by 2
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MIPS-L Register Convention
Name $zero $v0-$v1 $t0-$t2 $sp $ra Register Number 0 1-2 3-5 6 7 Usage the constant 0 values for results and expression evaluation temporaries stack pointer return address Preserved on call? n.a. No No Yes No
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MIPS-L Instruction Formats
Name Field Size Fields 3 bits 3 bits 3 bits rs rs rt rt 3 bits rd rd 4 bits funct Comments ALL MIPS-L instructions 16 bits Arithmetic instruction format
Rop format Iop format Jop format
Address/ Transfer, branch, immediate immediate format Jump instruction format
target address
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MIPS-L Machine Instructions
Name add sub and or slt jr lw sw beq addi j jal Format 3 bits 3 bits R R R R R R I I I I J J 0 0 0 0 0 0 4 5 6 7 2 3 2 2 2 2 2 7 2 2 1 2 5000 5000 Example 3 bits 3 3 3 3 3 0 1 1 2 1 3 bits 1 1 1 1 1 0 100 100 (offset to 100)/2 100 0 1 2 3 4 8 4 bits add $1,$2,$3 sub $1,$2,$3 and $1,$2,$3 or $1,$2,$3 slt $1,$2,$3 jr $7 lw $1,100($2) sw $1,100($2) beq $1,$1,100 addi $1,$2,100 j 10000 jal 10000 Comments
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Single Cycle MIPS-L
Instruction [25 0] 26 Shift left 2 Jump address [31 0] 28 0 M u x ALU Add result Add 4 Instruction [31 26] Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Read register 1 Shift left 2 1 1 M u x 0 PC+4 [31 28]
Instruction [25 21] PC Read address Instruction [31 0] Instruction memory Instruction [15 11] Instruction [20 16] 0 M u x 1
Read data 1 Read register 2 Registers Read Write data 2 register Write data
0 M u x 1
Zero ALU ALU result
Address
Read data Data memory
This thing's got a cycle in it. Not good. Build 361 in stages it Fall 2003 EE
Write data 16 Sign extend 32 ALU control
1 M u x 0
Instruction [15 0]
Instruction [5 0]
TheUniversity of Hawaii JUST A SUGGESTION following is 37
MIPS-L0
Something even simpler: MIPS-L0 Only executes R format arithmetic instructions Register File RegFileL0
Register $5 = 1 always Register $4 = 2 always
ALUControl: Same as MIPS-L
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MIPS-L0
iaddr
Instruction Memory (ROM)
aluout aluina MIPS-L0 aluinb Used to verify correctness
idata
reset clock
Everything is 16 bits except reset and clock
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MIPS-L0
Describe MIPS-L0 Example Program Memory
Example testbench General testbench of simple combination circuits
Building Single Cycle MIPS-L0
Pre MIPS-L0, yet even simpler Debugging tips
Building Single Cycle MIPS-L
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MIPS-L0
reset clock
iaddr
PC +
idata
(instruction)
RegWrite=1
aluina
r2
ALU
4
r3 r1 RegFileL0 ALU Control ALUOp=2
aluout aluinb
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Example Instruction Memory
// Instruction memory // Program has only 8 instructions module IM(addr, dout) input [15:0] addr; dout [15:0] dout; reg [15:0] dout; always @(addr[3:1]) case (addr[3:1]) 0: dout = {3'd0,3'd4,3'd5,3'd3,4'd0} 1: dout = 2: dout = 3: dout = 4: dout = 5: dout = 6: dout = 7: dout = endcase endmodule
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// add $3,$4,$5 // sub $2,$4,$5 // slt $1,$4,$5 // and $1,$3,$5 // slt $1,$4,$3 // sub $1,$3,$5 // add $3,$0,$2 // add $3,$5,$1
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// Testbench for program memory module testbench_memory reg [15:0] addr; wire [15:0] dout;
Example Testbench
IM pmem(addr, dout); // Instantiation of memory initial begin // Drive the memory addr = 0; #2 addr = 2; #2 addr = 4; ...... #2 addr = 14; #2 $stop; end initial begin // Display the outputs $monitor("time = %d, addr=%d, instr=(%d,%d,%d,%d,%d)",$time,addr,dout[15:13],... end endmodule
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Simple Testbenches
Declare reg variables to drive inputs Declare wire variables to tap into outputs and connect circuits Clock generator signal (if necessary) Set up circuit with instantiations and possible connections Initial procedure to change input signals over time (use delays # and $stop) Initial procedure to output results
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Building MIPS-L0
Build the components and test
Instruction memory ALU ALU Control Register file RegFileL0
Build and test a Pre-MIPS-L0 (see next slide) Build and test a MIPS-L0 (finally!)
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Pre MIPS-L0
reset clock
iaddr
PC +
idata
(instruction)
RegWrite=1
aluina
r2
ALU
4
9 is an 9 arbitrary number
r3 r1 RegFileL0 ALU Control ALUOp=2
aluout aluinb
We got rid of the cycle
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Pre MIPS-L0
What do we gain by removing the cycle?
If there's a bug, we can find it by tracing backwards
Testbench
Has an instantiation of MIPS-LO and program memory Try different programs for testing
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Pre MIPS-L0
Rules of thumb for debugging
Determine a set of input signals to test whether the circuit works or not Input signals will vary over time Determine where to probe signals
At outputs At intermediate points
Determine by hand what signals to expect
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Pre MIPS-L0
Rules of thumb for debugging
Create test bench that
generates the appropriate input signals over time outputs the signals you want
Run the test bench and see if the circuit works If not, put probe signals upstream to determine where the problem is
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Probing Upstream
probe 0
This is supposed to be "1".
Check upstream until you find a device that isn't working, e.g., outputs don't match inputs
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Pre MIPS-L0
Rules of thumb for debugging
Change input signals to REALLY verify that the circuit will work under all conditions
Example: change program
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MIPS-L0
After verifying correctness of Pre MIPSLO, build and test MIPS-L0 This is Homework 10A
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MIPS-L
Build the MIPS-L in stages Stage 1 MIPS-L1
Include addi and j Use ordinary register file Include Control circuit
Stage 2 MIPS-L2:
include beq Modify ALU for zero output
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MIPS-L
Stage 3 MIPS-L3 (final)
Include lw and sw Have the RAM store 128 words. RAM is implemented like a register file
Have the program read and write to RAM and check if it does so properly Verification can be done by checking inputs and outputs
This is Homework 10B
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Testbenching
Your testbench should include
Your MIPS-Lx Program memory
Don't be afraid to try different programs for testing
Last slide unless there'...