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### lab2_002

Course: EE 2381, Fall 2009
School: Cox School of Business
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Word Count: 1325

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2 Master-Slave Laboratory J-K Flip-Flops INTRODUCTION: The J-K flip-flop is one of the most commonly used flip-flops in digital designs as it usually requires fewer additional logic gates to implement a sequential circuit than other flip-flop families. There are three main varieties: pulse mode, edge-triggered and masterslave. In this lab, we will study the master-slave J-K flip-flop is detail. The SN74107...

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2 Master-Slave Laboratory J-K Flip-Flops INTRODUCTION: The J-K flip-flop is one of the most commonly used flip-flops in digital designs as it usually requires fewer additional logic gates to implement a sequential circuit than other flip-flop families. There are three main varieties: pulse mode, edge-triggered and masterslave. In this lab, we will study the master-slave J-K flip-flop is detail. The SN74107 contains two independent, master-slave J-K flip-flops with individual J-K, clock and direct clear lines. The function table that describes the operation of the flipflop is shown in Table 1. As soon as CL' (an asynchronous, active low clear) is brought low, the flip-flop will reset, regardless of the values of J, K and CK. When CL' is high, the J-K input data is loaded into the master while the clock is high and is transferred to the slave on the high-to-low clock transition. The J and K inputs must be stable while the clock is high to insure proper operation. Table 1. SN74107 Function Table. Inputs Outputs CK J K Q Q' X X X L H -_| |_ L L Q0 Q0' _|--|_ H L H L -_| |_ L H L H _|--|_ H H Toggle CL' L H H H H The logic diagram of the SN74107 is show in Fig. 1. Since it contains two transistors as well as logic gates, it is beyond the scope of this class to either simulate it or study its behavior analytically. Instead, we will use the logic diagram show in Fig. 2 that is functionally equivalent in the sense that it realizes the function table shown in Table 1. We will be concerned with three aspects of operation. First, we want to verify that the master-slave J-K flip-flop operates according to the function table shown in Table 1 and so a truth-table will be determined. Second, we want to study the relationship between the clear and clock to determine which function has precedence over the other. Finally, we want to study the "pulse catching" behavior of this type of master-slave flip-flop. Both simulation of the functionally equivalent circuit given in Fig. 2 and the testing of an actual SN74107 will study these three aspects of operation. Figure 1. Logic diagram of a SN74107 [1]. U1A U2 U3A U4 J 7411 U1B S Master Q 7408 U3B S Slave Q Q CL' 7411 U5A 7408 CK 7404 Figure 2. Logic diagram of a functionally equivalent master-slave J-K flip-flop. 2 CL' CL' K R Q' R Q' Q' SIMULATIONS: In this part of the experiment, you will simulate the behavior of the master-slave J-K flipflop shown in Fig. 2 using Verilog. Develop a Verilog model of the master-slave J-K flip-flop using the nominal rise time and fall time delays shown in Table 2 below for the 7400 TTL logic family of Texas Instruments. Be sure to provide a copy of your Verilog program and relevant simulation outputs, including timing diagrams. Table 2. Nominal Rise Time and Fall Time Delays for 7400 TTL Logic Family. Gate NOT AND NAND OR NOR Rise Time Delay (ns) 12 17.5 11 10 12 Fall Time Delay (ns) 8 12 7 14 8 First, develop a stimulus pattern for the J, K, CL' and CK inputs that will allow you to construct a truth table for Q+, the next-state of Q. Note that the CL' will be used only to reset the J-K flip-flop to a known state at the beginning of the simulation. The Boolean variables of interest will be J, K and Q coupled with a positive pulse on CK that generates the next-state Q+. Since there are eight possible combinations of these three Boolean variables, you will need a minimum of eight clock pulses with appropriate values for J, K and Q. Also, be sure that you operate the flip-flop correctly by insuring that J and K are stable while the clock is high. Second, we want to study the interaction of the CL' input with the other Boolean variables J, K, Q and CK. In the first simulation, the CL' was "off" (logic level 1) while the truth-table for Q+ was being determined. Now, repeat the first simulation with the CL' being "on" level (logic 0) for the entire simulation and determine the resulting truthtable for Q+. Note: By combining this truth-table with the previous truth-table, you essentially have derived a truth-table for Q+ using the five Boolean variables J, K, Q, CK and CL'. Third, we want to study what happens if the J and K inputs change while the clock CK is high. You will need to derive a new stimulus pattern for this simulation. First, reset Q to a 0 with J, K and CK being low. Then change the inputs in the following sequence: (1) CK goes high; (2) J goes high; (3) J goes low; (4), K goes high; (5), K goes low; (6) CK goes low. This effective pulses the J input and then the K input while the clock is high and Q is low. Second, set Q to a 1 with J, K and CK being low. Then change the inputs in the following sequence: (1) CK goes high; (2) K goes high; (3) K goes low; (4), J goes high; (5), J goes low; (6) CK goes low. . This effective pulses the K input and then the J input while the clock is high and Q is high. Be sure to space these input changes sufficiently far apart in time. 3 SN74107: In this part of the experiment, you will use a Digi Design box to aid in studying a SN74107. The pin-out is shown in Table 3. Using the switches to control the J, K, CL' and CK inputs, repeat the input patterns you used in the above three different simulations. Table 3. SN74107 N Package Pin-Out. 1J 1 14 VCC 1Q' 2 13 1CL' 1Q 3 12 1CK 1K 4 11 2K 2Q 5 10 2CL' 2Q' 6 9 2CK GND 7 8 2J QUESTIONS: I. Simulations: 1. Derive the truth-table for the master-slave J-K flip-flop shown in Fig. 2 under the assumptions that J, K and Q are the inputs of the truth-table, Q+ is the desired output of the truth-table, the clock CK has a single positive pulse, the J-K inputs are stable while the clock CK is high and the clear CL' is "off". 2. Rederive the truth-table in question 1 above under the assumption that the clear is CL' "on". 3. Based upon the above two truth-tables, does the circuit in Fig. 2 correctly realize the function table shown in Table 1? 4. What is the relationship between the clear and clock? Which has precedence over the other? 5. Does the flip-flop shown in Fig. 1 show any evidence of "catching a pulse" on the J-K inputs when the clock is high? If so, please state explicitly the conditi...

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