Generate VHDL-1
VHDL Functionality
Using VHDL Generate Statements to Replicate Logic
Tired of writing N copies of your components? Write short, easy-to-read code that does the work for you!
Learn to GENERATE!
2003 David M. Zar
VHDL-2
VHDL Generate Functionality
What's the Problem
You have a VHDL component that you want to use in an array or other regular structure. You can describe the hook-up of these components algorithmically. You have a lot of these components.
N-bit array of memory, J-bit wide register, K-register register file, etc.
2003 David M. Zar
VHDL-3
VHDL Generate Functionality
Using Generate
In this example, we will build a 32-bit wide shift register using a DFF with clear as discussed in class/homework:
2003 David M. Zar
VHDL-4
VHDL Generate Functionality
Using Generate Cont.
Using this DFF, we want to place 32 of them in a row and wire the ith input to the (i-1)st output. The first input should be wired to shift-in and last the output should be wired to shift-out. We could do this with 32 component instantiation statements of the form:
dff1: component edge_triggered_Dff port map (Sin, clk, clr, en, parallel_data(1) ); dff2: component edge_triggered_Dff port map (parallel_data(1), clk, clr, en, parallel_data(2) );
dff3: ...
2003 David M. Zar
VHDL-5
VHDL Generate Functionality
Using Generate Cont.
Or... we could use generate to do the work for us.
shift_reg: for i in 1 to 32 generate begin dffx: generate begin dff: component edge_triggered_Dff port map (parallel_data(i-1), clk, clr, en, ...