ID: Student ____________
CS 151
Quiz 4
Name : _________________ , _________________ (Last Name) (First Name) : _______________ : ________________
Student ID Signature
Instructions:
1. Please verify that your paper contains 9 pages including this cover. 2. Write down your Student-Id on the top of each page of this quiz. 3. This exam is closed book. No notes or other materials are permitted. 4. Total credits of this quiz are 50 points. 5. To receive credit you must show your work clearly. 6. Calculators are NOT allowed.
CS 151 Digital Logic Design, Spring Quarter'2007, QUIZ 4
Page 1
Student ID: ____________
Q1 [Memory Design]
Design a 16K*64-bit RAM using 8K*32-bit RAM modules shown below.
[10 points]
8K*16-bit RAM Module Use a minimum number of the following logic components in your design (no other components may be used for this design): 1) Priority Encoder 2) Decoder 3) Multiplexer
CS 151 Digital Logic Design, Spring Quarter'2007, QUIZ 4
Page 2
Student ID: ____________ <This page is intentionally left blank>
CS 151 Digital Logic Design, Spring Quarter'2007, QUIZ 4
Page 3
Student ID: ____________
Q2 [Critical Path Delay Calculation]
[15 points]
Assume that you can use only 2-input gates with a gate delay of 2ns and inverters with negligible delay. a. Determine the critical path delay of a 4-to-1 MUX built using only 2-input gates and inverters. [6 points]
CS 151 Digital Logic Design, Spring Quarter'2007, QUIZ 4
Page 4
Student ID: ____________ b. Determine critical the path delay of a 4-to-1 MUX built using 2-to-1 MUX components that are in turn built using 2-input gates and inverters [9 points] (HINT: You should first implement a 4-to-1 MUX using 2-to-1 MUXes and then determine the critical path delay of the circuit)
CS 151 Digital Logic Design, Spring Quarter'2007, QUIZ 4
Page 5
Student ID: ____________
Q3 [RTL Design-Queue Operation]
[25 points]
Design a circuit which takes as an input an integer number n (in the form of a 4 bit unsigned binary number) and computes the nth number in the Fibonacci sequence as the output FIBN. A START signal begins the operation and a DONE signal is asserted when the Fibonacci number is outputted on FIBN, as shown below:
n DONE Fibonacci Generator START FIBN
The computation of FIBN should use a queue as shown below. Assume that the first two numbers of Fibonacci sequence are already inserted in...