Update SPRZ122C
Manual Sheet
Document Being Updated: TMS320C6000 Peripherals Reference Guide Literature Number Being Updated: SPRU190D
DATE: January 31, 2003
This Manual Update Sheet (SPRZ122C) describes changes for the TMS320C6000 Peripherals Reference Guide (SPRU190D). Updates within paragraphs, figures, and tables appear in a bold typeface.
Page:
19
Change or Add:
Add a C6416 column and a VCP/TCP coprocessors row, change the footnote in Table 12:
Table 12.
TMS320C6000 Peripherals
C6201 C6202(B) C6203(B) Y Y C6204 C6205 C621x C6414 C6415 C6416 C6701 C671x Y Y N N N N Y N
Peripheral Direct memory access (DMA) controller Enhanced direct memory access (EDMA) controller Host-port interface (HPI) Expansion bus (XBUS) PCI External memory interface (EMIF) Boot configuration Multichannel buffered serial ports (McBSPs) UTOPIA Interrupt selector 32-bit timers Power-down logic
N
N
N
N
Y
Y
Y
Y
N
Y
Y N N 1
N Y N 1
N Y N 1
N N Y 1
Y N N 1
Y N N 2
Y{ N Y{ 2
Y{ N Y{ 2
Y N N 1
Y N N 1
Y 2
Y 3
Y 2
Y 2
Y 2
Y 3
Y 3{
Y 3{
Y 2
Y 2
N Y 2 Y
N Y 2 Y
N Y 2 Y
N Y 2 Y
N Y 2 Y
N Y 3 Y
Y{ Y 3 Y
Y{ Y 3 Y
N Y 2 Y
N Y 2 Y
1
Page:
Peripheral GPIO peripheral
Change or Add:
C6201 C6202(B) C6203(B) N N N N C6204 N N C6205 C621x C6414 C6415 N N N N Y N Y{ N C6416 C6701 C671x Y{ Y N N N N
VCP/TCP coprocessors
The C6415/C6416 peripheral set is selected at device reset. For details, see Chapter 11, Boot Modes and Configuration, and the specific device datasheet.
23
Change the last paragraph in section 2.2: Table 21 and Table 22 compare the internal memory and cache configurations available on the current TMS320C6x0x devices. Figure 22 shows a block diagram of the connections between the C6201/C6204/C6205/C6701 CPU, PMEMC, and memory blocks. Figure 23 shows a block diagram of the connections between the CPU, PMEMC, and memory blocks in the C6202/ C6202B/C6203(B). For C6202(B)/C6203(B), there are two program memory controllers, PMEM1 and PMEM0. The PMEM1 controller handles all accesses to program memory block 1 (SRAM and cache), as well as all cache operations and external accesses. The PMEM0 controller always accesses program memory block 0 (SRAM only). The addresses shown in Figure 22 and Figure 23 are for operation in memory map mode 1.
212
Add to the end of the paragraph in section 2.2.6: While the CPU is executing from external memory, IPRAM block 1 can not be accessed using the DMA. The PMEM1 memory controller is used by the CPU to fetch instructions from the EMIF, therefore while performing a fetch from external memory, DMA access to PMEM1 is limited.
212
Add a new section 2.2.7:
2.2.7
Illegal Access to Program Memory
An access to a section of memory that does not return a ready indication is not allowed. Possible requestors are: CPU program fetches, CPU loads and stores, programmed DMA channels or HPI/PCI/XBUS host mastering of the DMA through the auxiliary DMA. This type of access can create a stall indefinitely. When a requestor has created a program memory stall, other requestors are unable to access this program memory space. For C6202/C6203, if an access generates a program memory block 0 stall, other requestors may still access program memory block 1 and vice versa.
2
Page:
224
Change or Add:
Add a new section 2.4.8. The subsequent sections are renumbered accordingly:
2.4.8
Illegal Access to Data Memory
An access to a section of memory that does not return a ready indication is not allowed. Possible requestors are: CPU program fetches, CPU loads and stores, programmed DMA channels or HPI/PCI/XBUS host mastering of the DMA through the auxiliary DMA. This type of access can create a stall indefinitely. When a requestor has created a data memory stall, other requestors are unable to access this data memory space.
3all
Chapter 3: TMS320C621x/C671x/C64x Two-Level Internal Memory. This chapter has been revised and divided into two new documents: TMS320C621x/C671x Two-Level Internal Memory (SPRU609) and TMS320C64x Two-Level Internal Memory (SPRU610). Updates to Chapter 3 that are not yet applied in those two new documents are documented in this manual update sheet. Change the first paragraph in section 3.3.3: The L2 operates in four operation modes, depending on the state of the CCFG register. CPU may only perform read/write access to L2 addresses which are mapped as SRAM. Undefined operation may occur if CPU reads/writes from/to L2 addresses acting as cache. Figure 36 shows the division of the L2 SRAM into mapped memory space and cache for each TMS320C621x/C671x L2 Mode. It also shows how the memory configuration for the L2 affects the proportion of cache and SRAM.
311
318
Change the title in section 3.4.4:
3.4.4
333
L1D Memory Banking Structure
Delete the last sentence of section 3.6.1: Since the L1D and L2 could be incoherent due to write hits in the L1D, the user should perform an L1D invalidation to force any dirty L1D data into the L2. Change the paragraph in section 3.6.3: Figure 326 shows four L1D misses when the L2 segment is configured as cache. The pipeline signals are explained in Figure 327. In this scenario, the CPU requests data in clock cycle 0 for read1 and read 2. In clock cycle 1 the data is looked for in L1D. The data is not present in L1D so in cycle 2 a miss is recorded for both read1 and read2. Also in cycle 1 the CPU requests the data for read3 and read4. In cycle 3, there is an L2 request for the data for read1 and a miss is recorded for both read3 and read4. In cycles 4, 7, and 9 there are L2 requests for the data for read2, read3, and read4, respectively. In cycles 9 and 10, the data for read1 is found in L2 and placed in L1. In cycles 11 and 12, the data for read2 is found in L2 and placed in L1. In cycle 13, the data from read1 and read2 is placed in the register file. Also in cycle 13 and in cycle 14 the data from read3 is found in L2 and placed in L1. In cycles 15 and 16 the data from read4 is found in L2 and placed in L1. In cycle 17, the data from read3 and read4 is placed in the register file. For these four misses, the CPU was stalled for a total of 14 clock cycles. This averages 4.67 cycles instead of 8 cycles for a single miss.
335
3
Page:
339
Change or Add:
Change the paragraph below Table 310: The reset value of the L2MODE field is 000b, thus the L2 RAM is configured as mapped SRAM at reset to support data boot-loading. Any L2 RAM that is configured as cache is no longer in the memory map. For example, in L2 mode 010b the address range from 000F 0000h to 000F FFFFh is no longer available in the TMS320C64x memory map. The associativity of the L2 cache RAM is a function of the L2 Mode on the C671x and C621x but stays at four-way for the C64x architecture. On C621x/C671x each of SRAM added in the cache increases the associativity by one line per set. To ensure coherency and data integrity on an L2 mode switch, the user must perform a series of operations.
340
Change the second paragraph in section 3.7.2: The L2 SRAM is made up of four 64-bit-wide memory banks on the C621x/C671x, and eight 64-bit-wide memory banks on the C64x. Since the L1P data bus is 256-bits wide, any L1P request that occurs at the same time as an L1D or EDMA request will cause a bank collision and, therefore, a stall.
341
Add section 3.7.2.1, Figure 329, and Table 312. The subsequent figures and tables are renumbered accordingly:
3.7.2.1
L2 Write Hits vs. EDMA Priority (C64x only)
C64x devices (revision 1.1 and later) incorporate a register to give EDMA accesses a temporary boost in priority so that they can meet real-time needs. This priority boost only applies when competing with write data from the CPU that misses in L1D, but hits in L2 cache or L2 SRAM. The EDMA weight register (EDMAWEIGHT) lets you control how often this priority boost is given. When EDMA priority is raised, it is allowed to complete one access before priority is returned to the CPU data. The EDMAWEIGHT is shown in Figure 329 and summarized in Table 312.
Figure 329. TMS320C64x EDMA Weight Register (EDMAWEIGHT)
31 Reserved R,+0 2 1 0 EDMAWEIGHT RW,+01
Table 312.
Field
TMS320C64x EDMA Weight Register (EDMAWEIGHT) Field Description
Description Allows EDMA priority raised over L1DL2 writes once every N CPU cycles. EDMAWEIGHT=00: L1D 100%, EDMA 0%, EDMA never gets priority over L1D. EDMAWEIGHT=01: L1D 94%, EDMA 6%, EDMA gets priority every 16 cycles (default). EDMAWEIGHT=10: L1D 80%, EDMA 20%, EDMA gets priority every 4 cycles. EDMAWEIGHT=11: L1D 50%, EDMA 50%, EDMA gets priority every other cycle.
EDMAWEIGHT
341
Add section 3.7.3. The subsequent sections are renumbered accordingly.
3.7.3
Data Endianness
The data endianness of C621x/C671x/C64x is the same as C620x/C670x. See section 2.4.8, Data Endianness, for details.
4
Page:
341
Change or Add:
Change the paragraph in section 3.7.3: When an L2 location is enabled as a cache, the operation is similar to the L1D cache. On a read request to the L2 the data is sent to the requestor if a hit occurs. If the data is not in the L2 the requestor is stalled and the Least Recently Used(LRU) line is allocated for the new data. If the allocated line contains valid data the L1D is snooped. The L1D must be snooped even if an L1P miss supplied the L2 miss address because the evicted L2 line could be cached in the L1D. If the L1D returns data both the matching L1D line and evicted L2 line are invalidated, otherwise only the evicted L2 line is invalidated. Both the L2 and L1D caches must be invalidated on an L1D match to maintain coherency between the caches. If the L1D returns dirty data or if the evicted L2 line contains dirty data that data is evicted to the external memory and the required data is requested from the Enhanced DMA. The L2 is a load through cache, thus when servicing L1/L2 misses, data is stored in both L1 and L2 simultaneously. To minimize the CPU stall time, the L2 will fetch misses so that the data needed by L1 is returned first, followed by the rest of the L2 line. When the requested L1 data is available from the EDMA, the L2 will immediately forward it to L1 and unstall the CPU, and then wait for the remainder of the L2 line from the EDMA.
44
Change the paragraph before Figure 41: Figure 41 shows the TMS320C6000 block diagram with the DMA-related components shaded. Table 41 summarizes the differences between the DMAs in different C6000 devices.
411
Change the bit name of bits 1816 in Figure 43:
Figure 43.
31
DMA Channel Secondary Control Register (SECCTL)
22 Reserved R, +0 21 WSPOL* RW, +0 20 RSPOL* RW, +0 19 FSIG* RW, +0 18 DMAC EN RW, +000 16
15 WSYNC CLR RW, +0
14 WSYNC STAT RW, +0
13 RSYNC CLR RW, +0
12 RSYNC STAT RW, +0
11 WDROP IE RW, +0
10 WDROP COND RW, +0
9 RDROP IE RW, +0
8 RDROP COND RW, +0
7 BLOCK IE RW, +1
6 BLOCK COND RW, +0
5 LAST IE RW,+0
4 LAST COND RW,+0
3 FRAME IE RW, +0
2 FRAME COND RW, +0
1 SX IE RW,+0
0 SX COND RW,+0
Note:
* WSPOL, RSPOL, and FSIG bit fields are not available to the C6201 and C6701 devices. These bitfields are R+0 on the C6201 and C6701 devices.
412
Change the bit numbers (No.) of WSYNC CLR and DMAC EN in Table 45:
Table 45.
No.
15
DMA Channel Secondary Control Register (SECCTL) Field Descriptions (Continued)
Field
WSYNC CLR
Description Write synchronization status clear: Read as 0 write 1 to clear write synchronization status.
Section 4.6.1
18 to 16
DMAC EN
DMA action complete pins reflect status and condition.
4.12
5
Page:
420
Change or Add:
Add a paragraph after the introduction paragraph in section 4.6.1: Care must be taken if software is used to poll and clear the status/conditions in the SECCTL register during a synchronized DMA transfer. To avoid inadvertently setting an extra RSYNC/WSYNC event during a synchronized DMA transfer, users should only write zeros to the STAT and CLR fields.
430
Change the last paragraph in section 4.8.1: When a DMA channel is operating in split mode, only one element count and one frame count are used for both the transmit and receive transfers. The end of frame or end of block is set following the last transfer. When the channel operating in split mode is servicing a McBSP, this will normally be the last receive transfer because the transmit transfers will normally run ahead of the receive transfers. The transfer counters will be modified after the transmit transfer, so that if autoinitialization is enabled, the transfer counters may indicate that another transfer has begun before the receive portion of the split-mode transfer has completed. For split-channel operation to work properly, both the RSYNC and WSYNC fields must be set to non-zero synchronization events. Also, frame synchronization must be disabled in split-channel operation.
431
Change the last paragraph in section 4.8.1: The above sequence is maintained for all transfers. However, the transmit transfers do not have to wait for all previous receive element transfers to finish before proceeding. Therefore, it is possible for the transmit stream to get ahead of the receive stream. The DMA channel transfer counter decrements (or reinitialize) after the associated transmit transfer finishes. However, reinitialization of the source address register occurs after all transmit element transfers finish. This configuration works as long as transmit transfers do not exceed eight or more transfers ahead of the receive transfers. If the transmit transfers do get ahead of the receive transfers, transmit element transfers are stopped, possibly causing synchronization events to be missed. For cases in which receive or transmit element transfers are within seven or less transfers of the other, the DMA channel maintains this information as internal status.
433
Change the Description of CH PRI (bits 3 to 0) in Table 49:
Table 49.
No. 4
DMA Auxiliary Control Register (AUXCTL) Field Descriptions
Field AUXPRI Description Auxiliary channel priority mode AUXPRI = 0: CPU priority AUXPRI = 1: DMA priority
3 to 0
CH PRI
DMA channel priority CH PRI = 0000b: fixed channel priority mode auxiliary channel highest priority CH PRI = 0001b: fixed channel priority mode auxiliary channel 2nd-highest priority CH PRI = 0010b: fixed channel priority mode auxiliary channel 3rd-highest priority CH PRI = 0011b: fixed channel priority mode auxiliary channel 4th-highest priority CH PRI = 0100b: fixed channel priority mode auxiliary channel lowest priority CH PRI = other, reserved
6
Page:
434
Change or Add:
Change the paragraph in section 4.9.2: A higher priority channel gains control of the DMA controller from a lower priority channel once it has received the necessary read synchronization. In switching channels, the current channel allows all data from requested reads to be completed. The DMA controller determines which higher priority channel gains control of the DMA controller read operation. That channel then starts its read operation. Simultaneously, write transfers from the previous channel are allowed to finish. The write transfer must complete before the higher priority channel will be able to start its transfer. Arbitration of the higher priority channel will occur as soon as the write from the lower priority channel completes. For example, if the lower priority channel's write is blocked by the CPU, the higher priority channel will not be able to start until the CPU releases the contending resource and the write is able to complete. This occurs even if the higher priority channel is accessing a different resource. See Chapter 5, DMA and CPU Data Access Performance, for more detail.
442
Add before the last paragraph in section 4.11.2.2: As with the shared FIFO DMA, a higher priority DMA channel can still be stalled by a lower priority channel if the lower priority channel is unable to complete its write to a resource. Arbitration of the higher priority channel will occur as soon as the write from the DMA completes.
513
Add a new section 5.2.7:
5.2.7
DMA Port Crossing
The DMA has 46 master ports, all of which are listed below:
- Data Memory - Program Memory Block 0 - Program Memory Block 1 (on C6202/C6203 only) - XBUS I/O (on C6202/C6203/C6204 only) - EMIF - Internal Peripheral Bus (peripheral control registers including McBSP data
registers) The DMA auxiliary port is a slave port and should be considered a requestor much like a programmed DMA channel. DMA accesses/bursts are not permitted to cross a port boundary. See section 11.3, Memory Map, for a listing of C620x/C670x memory map and port boundaries.
7
Page:
64
Change or Add:
Add a row to Table 61:
Table 61.
Differences in TMS320C6000 EDMAs
Features EDMA rate Supported on Device Runs at CPU rate on C621x/C671x; runs at half of CPU rate on C64x Described in Section 6.1
613
Change the second paragraph in section 6.5: The contents of the 2K byte PaRAM, shown in Table 63 comprises:
- For C621x/C671x, there are 16 transfer parameter entries for the
16 EDMA events. For C64x, there are 64 transfer parameter entries for the 64 EDMA events. Each entry is six words or 24 bytes. These areas can also serve as reload/link parameters.
- Remaining parameter entries (69 entries for C621x/C671x, and 21
entries for C64x) serve as additional parameter sets used for linking transfers. Each set or entry is 24 bytes.
- 8 bytes of unused RAM that can be used as scratch pad area. Note that
a part or entire EDMA RAM can be used as a scratch pad RAM provided this area corresponding to an event(s) is disabled. It is the user's responsibility to provide the transfer parameters when the event is eventually enabled.
8
Page:
614
Change or Add:
Change Table 63:
Table 63.
Address
EDMA Parameter RAM Contents
C621x/C671x Parameters for event 0 (6 words) Parameter for event 1 (6 words) Parameters for event 2 (6 words) Parameters for event 3 (6 words) Parameters for event 4 (6 words) Parameters for event 5 (6 words) Parameters for event 6 (6 words) Parameters for event 7 (6 words) Parameters for event 8 (6 words) Parameters for event 9 (6 words) Parameters for event 10 (6 words) Parameters for event 11 (6 words) Parameters for event 12 (6 words) Parameters for event 13 (6 words) Parameters for event 14 (6 words) Parameters for event 15 (6 words) Additional reload/link entry (6 words) Additional reload/link entry (6 words) Additional reload/link entry (6 words) Additional reload/link entry (6 words) Additional reload/link entry (6 words) Additional reload/link entry (6 words) Parameters for event 16 (6 words) Parameters for event 17 (6 words) ... ... Parameters for event 62 (6 words) Parameters for event 63 (6 words) C64x
01A0 0000h to 01A0 0017h 01A0 0018h to 01A0 002Fh 01A0 0030h to 01A0 0047h 01A0 0048h to 01A0 005Fh 01A0 0060h to 01A0 0077h 01A0 0078h to 01A0 008Fh 01A0 0090h to 01A0 00A7h 01A0 00A8h to 01A0 00BFh 01A0 00C0h to 01A0 00D7h 01A0 00D8h to 01A0 00EFh 01A0 00F0h to 01A0 0107h 01A0 0108h to 01A0 011Fh 01A0 0120h to 01A0 0137h 01A0 0138h to 01A0 014Fh 01A0 0150h to 01A0 0167h 01A0 0168h to 01A0 017Fh 01A0 0180h to 01A0 0197h 01A0 0198h to 01A0 01AFh ... ... 01A0 05D0h to 01A0 05E7h 01A0 05E8h to 01A0 05FFh 01A0 0600h to 01A0 0617h 01A0 0618h to 01A0 062Fh ... 01A0 07E0h to 01A0 07F7h 01A0 07F8h to 01A0 07FFh
Additional reload/link entry (6 words) Additional reload/link entry (6words) ... Additional reload/link entry (6 words) Scratch pad area (2 words)
9
Page:
616
Change or Add:
Change all read/write fields and the footnote, add a footnote in Figure 69:
Figure 69.
31 PRI
Options (OPT) BitFields
29 28 ESIZE RW,+x 27 26 2DS RW,+x 25 SUM RW,+x 24 23 2DD RW,+x 22 DUM RW,+x 21 20 TCINT RW,+x 19 TCC RW,+x 16
RW,+x
15 rsvd RW,+x
14
13 TCCM{ RW,+x
12 ATCINT{ RW,+x
11 rsvd RW,+x
10 ATCC{ RW,+x
5
4 rsvd RW,+x
3 PDTS{ RW,+x
2 PDTD{ RW,+x
1 LINK RW,+x
0 FS RW,+x
Applies to C64x only. On C621x/C671x, you should always write 0 to these reserved fields. You should always write 0 to the reserved fields.
617
Change the Description of ESIZE (bits 2827) in Table 65:
Table 65.
Bit No. 2827
EDMA Channel Options Parameter (OPT) Description (C621x/C671x/C64x)
Field ESIZE Description Element size ESIZE=00b; 32-bit word, or 64-bit doubleword (on certain C64x transfers only. See section 6.9.1) ESIZE=01b; 16-bit half-word ESIZE=10b; 8-bit byte ESIZE=11b; reserved Section 6.9
620
Change the second paragraph in section 6.6.5: Element index provides an address offset (in bytes) to the next element in a frame. Element index is used only for 1D transfers. This is because 2D transfers do not allow spacing between elements, and hence the term `array' is used to define a group of contiguous elements. Frame/array index provides an offset (in bytes) to the next frame/array in a block.
620
Change the title and the first paragraph in section 6.6.7:
6.6.7
EDMA Performance Considerations on the C621x/C671x
The EDMA controller provides a mechanism to link EDMA transfers. This is analogous to the autoinitialization feature in the DMA. When LINK=1 in the EDMA options parameter, the 16-bit link address specified in the EDMA parameter RAM specifies the lower 16-bit address in the parameter RAM from which the EDMA loads/reloads the parameters of the next event in the chain. Since the entire EDMA parameter RAM is located in the 01A0 xxxxh area, only the lower 16-bit address matters.
10
Page:
624, 25
Change or Add:
Change events on EDMA channel numbers 28, 29, 30, 31, and 53 in Table 68:
Table 68.
EDMA Channel Number 28 29 30 31 53
EDMA Channel Synchronization Events TMS320C64x
Event Acronym VCPREVT VCPXEVT TCPREVT TCPXEVT GPINT13
Event Description VCP receive interrupt VCP transmit interrupt TCP receive interrupt TCP transmit interrupt GPIO event 13
632
Delete the last paragraph in section 6.9: When transferring a burst of elements to or from a 64 bit wide peripheral (e.g. L2 or EMIFA), 64-bit elements are transferred regardless of the ESIZE programmed. This allows the EDMA to maximize the available bandwidth. Change the second paragraph in section 6.9.1: When transferring a burst of elements to or from a 64-bit-wide peripheral (for example, L2 SRAM or EMIFA), 64-bit elements are transferred to maximize the available bandwidth if the element size is 32-bit word (ESIZE = 00b). Care must be taken when performing a fixed-mode access (SUM or DUM = fixed) to peripherals that have 64-bit data paths to/from the EDMA. These include L2 SRAM, EMIFA (C64x only), and TCP/VCP (C64x only). If the EDMA is setup with the following parameters:
- Element size is 32-bit word (ESIZE = 00b) - Fixed address mode (SUM or DUM = 00b in the options parameter) - Transfer/synchronization type is array-/frame-/block-synchronized (not
632
element-synchronized, see section 6.10)
- Element count is greater than 1 (ELECNT > 1). - Either the source or destination bus width is 64 bits.
Then the programmer must ensure that the following conditions are true:
- Element count (ELECNT) must be a multiple of 2. - Frame/Array index field must be a multiple of 2.
Operation is undefined if the above conditions are not met. 632 Change the last paragraph in section 6.9.1: For a write to a 64-bit-wide data bus with the above conditions, both word 0 and word 1 of the fixed doubleword address are updated. For example, under the above conditions a write to the L2 SRAM address 0x00000000 updates both word 0 (at address 0x00000000) and word 1 (at address 0x00000004) with the new data.
11
Page:
634
Change or Add:
Change the paragraph in section 6.10.1: There is a special condition for reloading the element count for element synchronized (FS = 0) 1D transfers. In this case the address is updated by element size or element/frame index depending on SUM/DUM fields. See the first row in Table 611. Therefore, the EDMA controller keeps track of the element count to update the address. When an element sync event occurs at the end of a frame (ELECNT = 1), the EDMA controller sends off the transfer request, and reloads the ELECNT from the element count reload field in the parameter RAM. This element count reload occurs when element count is 1 and the frame count is nonzero. When configuring transfers where ELERLD will be used, ELERLD must be set to a nonzero value, or the transfer will hang. For all other types of transfers, the 16-bit element count reload field is not used because the address generation hardware (transparent to users) tracks the address directly.
639
Change "Elementary count reload" to "Element count reload" in Figure 616:
Figure 616. Linked EDMA Transfer
Reload Event N parameters with Event N parameters Options (LINK=1) Source (SRC) address Array/Frame count Element count parameters located at address 01A0 0180h Options (LINK=1) Source (SRC) address Array/Frame count Element count
Destination (DST) address Array/Frame index Element count reload Element index Link address = 0180h
Destination (DST) address Array/Frame index Element count reload Element index Link address = 01B0h
Reload Event N parameters with null parameters located at address 01A0 01B0h{ 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h { See section 6.13 for details on null parameters
12
Page:
640
Change or Add:
Change the paragraph in section 6.12: The link address is evaluated only if LINK is equal to 1 and only after the event parameters have been exhausted. An event's parameters are exhausted when the EDMA controller has completed the transfer associated with the request. Table 613 shows the channel completion conditions when the linking of parameters is performed. There is virtually no limit to the length of linked transfers. The last transfer parameter entry should have its LINK = 1 to link to a NULL parameter set so that the linked transfer stops after the last transfer. See section 6.13 for details.
641
Change "Elementary count reload" to "Element count reload" in Figure 617:
Figure 617. Terminating EDMA Transfers
Event N parameters Options (LINK=1) Source (SRC) address Array/Frame count Element count Null parameters located at 01A0 07E0h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
Destination (DST) address Array/Frame index Element count reload Element index Link address = 07E0h
645
Change the TCC in Options column in Table 614:
Table 614.
Transfer Complete Code (TCC) to EDMA Interrupt Mapping
TCC in Options (TCINT=1) 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b CIPR Bits Set CIP0 CIP1 CIP2 CIP3 CIP4 CIP5 CIP6 CIP7 TCC in Options (TCINT=1) 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b CIPR Bits Set CIP8 CIP9 CIP10 CIP11 CIP12 CIP13 CIP14 CIP15
13
Page:
645
Change or Add:
Change the TCC in Options column in Table 615:
Table 615.
C64x Transfer Complete Code (TCC) to EDMA Interrupt Mapping
TCC in Options (TCINT=1) 00 0000b 00 0001b 00 0010b 00 0011b 00 0100b ... ... ... 01 1110b 01 1111b CIPRL Bits Set{ CIP0 CIP1 CIP2 CIP3 CIP4 ... ... ... CIP30 CIP31 TCC in Options (TCINT=1) 10 0000b 10 0001b 10 0010b 10 0011b 10 0100b ... ... ... 11 1110b 11 1111b CIPRH Bits Set{ CIP32 CIP33 CIP34 CIP35 CIP36 ... ... ... CIP62 CIP63
648
Change the second paragraph in section 6.15.1: To enable the EDMA controller to chain channels by way of a single event, the TCINT bit must be set to `1'. Additionally, the relevant bit in the channel chain enable register (CCER) in Figure 620 should be set to trigger off the next channel transfer specified by TCC. Since events 8 to 11 are the only EDMA channels that support chaining, only these bits are implemented in CCER. Reading unused bits returns the corresponding bits in the EER and writing to them has no effect. Therefore, one can still specify a TCC value between 8 and 11, and need not necessarily initiate the transfer on channels 8-11. However, the event is still captured in the ER[11:8] even if the corresponding bit in CCER is disabled. This allows selective enabling and disabling of these four specific events.
648
Change the paragraph in section 6.15.2: The C64x EDMA transfer chaining is an expansion of the C621x/C671x transfer chaining. Any of the 64 transfer completion codes of the C64x EDMA can be used to trigger another channel transfer. The user-specified transfer complete code is expanded to a 6-bit value TCCM:TCC. The 4 bits in the TCC field (bits 19 to 16) of the options parameter are the least significant bits of the transfer complete code, while the new TCCM bit fields are the most significant bits of the transfer complete code. For example, if the transfer complete code (TCCM:TCC) is 010001b (i.e. TCCM = 01, TCC = 0001b) and CCERL[17] = 1 is specified for EDMA channel 4, the completion of the channel 4 transfer will initiate the next transfer specified by EDMA channel 17, provided that the channel 4 TCINT = 1. Unlike the C621x/C671x, the event bits on the C64x are captured in the ER only if the corresponding bits in CCER are enabled.
14
Page:
655
Change or Add:
Change the C64x Requesters column in Table 616:
Table 6-16.
Programmable Priority Levels for Data Requests
C621x/C671x Priority Level Level0; urgent priority Level1; high priority Level2; low priority Reserved C621x/C671x Requestors L2 controller EDMA, QDMA and/or HPI EDMA, QDMA Reserved Reserved C64x Priority Level Level0; urgent priority Level1; high priority Level 2; medium priority Level 3, low priority Reserved C64x Requesters L2 controller, EDMA, QDMA, HPI, and PCI L2 controller, EDMA, QDMA, HPI, and PCI L2 controller, EDMA, QDMA, HPI, and PCI L2 controller, EDMA, QDMA, HPI, and PCI Reserved
PRI(31:29) 000b 001b 010b 011b
100b 111b Reserved
655
Change the paragraph in section 6.17.1: The priority queue status register (PQSR) shown in Figure 624 (C621x/C671x) and Figure 625 (C64x) indicates whether the transfer request queue is empty on the priority level queues. Status bits PQ in the PQSR provide the status of the queues. A `1' in the PQ bit indicates that there are no requests pending in the respective priority level queue. For C621x/C671x, if PQSR[0] is `1', this means all L2 requests for data movement have been completed and there are no requests pending in the priority level 0 queue. For C64x, if PQSR[0] is `1', this means all requests for data movement from requestors programmed for priority level 0 have been completed.
656
Add a paragraph after the section header in section 6.17.2:
6.17.2 Transfer Request Queue Length
Care should be taken to not overload any priority queue, as overloading any one queue can adversely affect all queues. When a transfer is submitted to a queue that is full, the EDMA controller stalls until room in the queue is available. While stalled, the EDMA controller does not process any other events, including those events that submit requests on a different priority queue. Events are still captured in the ER and processed when the EDMA controller is released.
15
Page:
657
Change or Add:
Change Table 618:
Table 618.
Transfer Request Queues (C64x)
Total Queue Length (fixed) 16 Default Queue Length 6 2 0 2 6 0 2 2 4 2 6 0
Queue Q0
Priority Level (PRI) 0; urgent priority
Requester L2 controller and QDMA EDMA HPI/PCI
Register to Program Queue Length L2ALLOC0 PQAR0 TRCTL/TRCTL L2ALLOC1 PQAR1 TRCTL/TRCTL L2ALLOC2 PQAR2 TRCTL/TRCTL L2ALLOC3 PQAR3 TRCTL/TRCTL
Q1
1; high priority
16
L2 controller and QDMA EDMA HPI/PCI
Q2
2; medium priority
16
L2 controller and QDMA EDMA HPI/PCI
Q3
3; low priority
16
L2 controller and QDMA EDMA HPI/PCI
L2 controller and QDMA share one queue allocation. L2ALLOCx register controls this queue allocation length. HPI and PCI share one queue allocation. TRCTL register in the HPI module controls the queue allocation length of HPI requests. TRCTL register in the PCI module controls the queue allocation length of PCI requests.
658
Change Figures 6-26, 6-27, 6-28, and 6-29:
Figure 626. Priority Queue Allocation Register 0 (PQAR0) (C64x only)
31 rsvd R,+0 4 3 rsvd RW,+0 2 PQA2 RW,+0 1 PQA1 RW,+1 0 PQA0 RW,+0
Figure 627. Priority Queue Allocation Register 1 (PQAR1) (C64x only)
31 rsvd R,+0 4 3 rsvd RW,+0 2 PQA2 RW,+1 1 PQA1 RW,+1 0 PQA0 RW,+0
Figure 628. Priority Queue Allocation Register 2 (PQAR2) (C64x only)
31 rsvd R,+0 4 3 rsvd RW,+0 2 PQA2 RW,+0 1 PQA1 RW,+1 0 PQA0 RW,+0
16
Page:
Change or Add:
Figure 629. Priority Queue Allocation Register 3 (PQAR3) (C64x only)
31 rsvd R,+0 4 3 rsvd RW,+0 2 PQA2 RW,+1 1 PQA1 RW,+1 0 PQA0 RW,+0
659
Change the first bullet in section 6.18:
- EDMA stalls occur when the EDMA submits another request to a priority
level queue that is already full. 659 Add the following text after the bullets in section 6.18: EDMA bandwidth is fully utilized when performing burst transfer, which is obtained if and only if the EDMA transfer is configured as:
- Transfer/synchronization type is array-/frame-/block-synchronized trans-
fer (not element-synchronized, see section 6.10).
- Element size is 32-bit (ESIZE = 00b) - Addressing
mode is increment, decrement, or fixed (SUM or DUM = 00/01/10b in the options parameter)
The EDMA will perform single element transfers for all transfers not meeting all of the above conditions, which will utilize only a portion of the bandwidth available. For burst transfer types described above, the burst length is dictated by the 1D component of the transfer, which is specified by the ELECNT field. For arrayor frame-synchronized transfer, the 1D component of the transfer is the amount of data that gets transferred per synchronization event. For block-synchronized transfers, the complete 2D transfer is transferred per synchronization event; however, burst transfers are only performed for the 1D component. If the 1D length (ELECNT) is programmed to a small value, the performance will reduce accordingly and in the worst case (ELECNT = 1), the performance will be identical to the performance described for single element transfers. 661 Change Figure 632:
Figure 632. QDMA Options Register (QDMA_OPT, QDMA_S_OPT)
31 29 PRI W, +0 Notes: 28 27 ESIZE W, +0 26 2DS W, +0 25 24 SUM W, +0 23 2DD W, +0 22 21 DUM
W, +0
20 TCINT W, +0
19 16 TCC W, +0
15 Rsvd W,+0
14 TCCM W,+0
13
12
1
0 FS W,+0
Rsvd W,+0
1) TCCM applies to C64x only. For C621x/C671x, this bit is Reserved W,+0. 2) Register QDMA_OPT is read/writable. Pseudo-register QDMA_S_OPT is write only.
17
Page:
662
Change or Add:
Change the first paragraph in section 6.19.5: The QDMA has several stalling conditions. Once a write has been performed to one of the pseudo-registers (resulting in a pending QDMA transfer request), future writes to the QDMA registers are stalled until the transfer request is sent. Normally this will occur for 23 EDMA cycles, as this is how long it takes to submit a transfer. Stalls are not generally seen by the CPU, because writes to QDMA registers occur via the L1D write buffer. Future writes to the buffer may eventually fill it up and stall the CPU from subsequent reads/ writes.
662
Change the third paragraph in section 6.19.5: Similar to the EDMA channels, QDMA can have programmable priority in the lower levels as described in section 6.17. The PRI bit-field in the QDMA_OPT register specifies the priority level of the QDMA. On the C621x/C671x, level 0 (urgent priority) is reserved for L2 cache accesses; thus, QDMA requests with level 0 or reserved values will be discarded.
666
Change the first paragraph in section 6.21.1.1: For TMS320C64x, cache servicing requests can be made on any priority levels as specified in the P bits in the CCFG register. For read requests, the cache controller always requests an L2 line in two bursts of 64 bytes each, requesting the "missed" portion of the line first. For write requests, as a result of flush/clean operations or eviction, the cache controller transfers one complete L2 line in two bursts of 64 bytes each.
666
Change the paragraph in section 6.21.1.2: The HPI/PCI automatically generates transfer requests to service host activity. For C621x/C671x, these transfer request submissions are submitted only with a high priority and are invisible to the user. For C64x, by default HPI/PCI transfer requests are submitted with medium priority, but request priority can be programmed to any of the four priority levels by setting the PRI field in the TRCTL register to the appropriate value. The HPI/PCI submits a transfer request for a single element read or write for fixed mode host accesses and a transfer request for a short data burst for autoincrement transfers. The burst size is always for eight or fewer elements. See section 6.17 for available HPI transfer request priority.
666
Change the paragraph in section 6.21.1.3: The EDMA channel transfers can be submitted with urgent (C64x only), high, medium (C64x only), or low priority; with the recommendation that high priority be reserved for short bursts and single element transfers and low priority be used for longer (background) block moves. It is also recommended that transfers be divided between the priority levels when applicable, as this helps to maximize the device performance.
673
Change the fourth paragraph in section 6.22.3: For this example it is assumed that the 16-bit data is located in external RAM, beginning at address 0xA0000000 (CE2). The QDMA is used to bring four frames of 1k half-words from their locations in RAM to internal data memory beginning at 0x00002000. The index value required is ELEIDX = F x S = 4 x 2 = 8.
18
Page:
73
Change or Add:
Add a paragraph below Figure 72 in section 7.1: Through the HPI, an external host is capable of accessing the entire DSP memory map except the following:
- L2 control registers (C6x1x only) - Interrupt selector registers - Emulation logic
721
Add a paragraph at the end of section 7.4.3: When performing reads with autoincrement, the C64x differs slightly from the C621x/C671x in that the C64x will not indicate ready (HRDY low) until the internal read buffer has filled with the 16-word prefetch. Thus, accesses to slow regions of memory, such as internal peripheral registers or slow external memory, might take a significant amount of time. For best performance, accesses to these regions should be done in fixed mode unless multiple words are desired.
722
Change Figure 711 (delete HRDY case 2 waveform):
Figures 711. HPI32 Read Timing (HAS Not Used, Tied High) for C64x only
HAS HCNTL[1:0] HR/W HSTROBE HCS HD[31:0] (output)
HRDY
19
Page:
722
Change or Add:
Change Figure 712 (delete HRDY case 2 waveform):
Figures 712. HPI32 Read Timing (HAS Used) for C64x only
HAS{ HCNTL[1:0] HR/W HSTROBE HCS HD[31:0] (output) HRDY For correct operation, strobe the HAS signal only once per HSTROBE cycle.
723
Change the HR/W and HRDY waveforms in Figure 713:
Figure 713. HPI Write Timing (HAS Not Used, Tied High) for C64x only
HAS HCNTL[1:0] HR/W HSTROBE HCS HD[31:0] (input) HRDY
20
Page:
723
Change or Add:
Change the HR/W and HRDY waveforms in Figure 714:
Figure 714. HPI Write Timing (HAS Used) for C64x only
HAS{ HCNTL[1:0] HR/W HSTROBE HCS HD[31:0] (input) HRDY For correct operation, strobe the HAS signal only once per HSTROBE cycle.
724
Add a row to Table 77:
Table 77.
HPI Registers for C64x
Register Register Abbreviation Name TRCTL TR control Host Read/Write Access CPU Read/Write Access RW CPU Read/Write (Hex Byte Address) 018A 0000h
725
Change the first paragraph in section 7.5.1: The HPIA contains the address of the memory accessed by the HPI at which the current access occurs. This address is a 32-bit word address with all 32-bits readable/writable. The two LSBs always function as 0, regardless of the value read from their location. The C62x/C67x HPIA register is only accessible by the host. It is not mapped to the DSP memory.
725
Change the second paragraph in section 7.5.1: The C64x HPIA register is accessible by both the host and the CPU. Furthermore, the HPIA register is separated into two registers internally: the HPI address write register (HPIAW), and the HPI address read register (HPIAR). By separating the HPIA into HPIAW and HPIAR internally, the CPU can update the read and write memory address independently to allow the host to perform read and write to different address ranges. When reading HPIA from the CPU, the value returned corresponds to the address currently being used by the HPI and DMA to transfer data inside the DSP. It is not the address for the current transfer at the external pins. Thus, reading HPIA does not indicate the status of a transfer, and should not be relied upon to do so.
21
Page:
Change or Add:
725
Change the paragraph in section 7.5.2: The HPIC register, shown in Figure 715 and Figure 716 and summarized in Table 78, is normally the first register accessed to set configuration bits and initialize the interface. From the host's view, the HPIC is organized as a 32-bit register with two identical halves, meaning the high halfword and low halfword contents are the same. On a host write, both halfwords must be identical, except when writing the DSPINT bits in HPI16 mode (see section 7.5.4). In HPI16 mode when setting DSPINT = 1, the host must only write `1' to the lower 16-bit halfword or upper 16-bit halfword, but not both. In HPI32 mode, the upper and lower halfwords must always be identical. From the C6000 (CPU) view, the HPIC is a 32-bit register with only 16-bits of useful data. Only CPU writes to the lower halfword affect HPIC value and HPI operation.
725
Add a second paragraph in section 7.5.2: On C64x, the HWOB bit is writable by the CPU. Therefore, care must be taken when writing to the HPIC, in order not to write an undesired value to HWOB.
726
Change the title, all read/write fields, and the footnote in Figure 715:
Figure 715. HPIC Register--Host Reference View
31 rsvd{
HRW,+0
30
24
23 rsvd
HRW,+0
22 21 rsvd
HR,+0
20 FETCH
HRW,+0
19 HRDY
HR,+1
18 HINT
HRW,+0
17 DSPINT
HRW,+0
16 HWOB
HRW,+0 (C62x/C67x) HRW,+0 (C64x)
rsvd
HR,+0
15 rsvd
HRW,+0
14 rsvd
HR,+0
8
7 rsvd
HRW,+0
6
5
4 FETCH
HRW,+0
3 HRDY
HR,+1
2 HINT
HR,+0
1 DSPINT
HRW,+0
0 HWOB
HRW,+0 (C62x/C67x) HRW,+0 (C64x)
rsvd
HR,+0
For C62x/C67x, bits 7, 15, 23, 31 are read-only; HR,+0. For C64x, bits 7, 15, 23, and 31 are writable fields and must be written with 0. Otherwise, operation is undefined.
726
Add a new Figure 716. The subsequent figures are renumbered accordingly:
Figure 716. HPIC Register--C6000 Reference View
31 reserved
CR,+0
16
15 rsvd
CRW,+0
14 rsvd
CR,+0
8
7 rsvd
CRW,+0
6
5
4 FETCH
CR,+0
3 HRDY
CR,+1
2 HINT
CRW,+0
1 DSPINT
CRW,+0
0 HWOB
CR,+0
rsvd
CR,+0
22
Page:
726
Change or Add:
Add a new section 7.5.3, Figure 717, and Table 79. The subsequent sections, figures, and tables are renumbered accordingly:
7.5.3
TR Control Register (TRCTL) (C64x only)
The TR control register (TRCTL) controls how the HPI submits its requests to the EDMA subsystem. The TRCTL is shown in Figure 717 and summarized in Table 79.
Figure 717. TR Control Register (TRCTL)
31 Reserved RW,+0 9 8 TRSTALL RW,+0 7 6 5 PRI RW,+10 4 3 0 Reserved RW,+x PALLOC RW,+0100
Table 79.
Bit PALLOC PRI TRSTALL
TR Control Register (TRCTL) Bit Descriptions
Description Controls the total number of outstanding requests that can be submitted by the HPI to the EDMA Controls the priority queue level that HPI requests are submitted to. Forces the HPI to stall all HPI requests to EDMA This bit allows safe changing of the PALLOC and PRI fields. TRSTALL=0: Allows HPI requests to be submitted to EDMA TRSTALL=1: Halts the creation of new HPI requests to EDMA Section 7.5.3 7.5.3 7.5.3
To safely change the PALLOC or PRI bits in TRCTL, the TRSTALL bit needs to be used to ensure a proper transition. The following procedure must be followed to change the PALLOC or PRI bits: 1) Set the TRSTALL bit to 1 to stop the HPI from submitting TR requests on the current PRI level. In the same write, the desired new PALLOC and PRI fields may be specified. 2) Clear all EDMA event enables (EER) corresponding to both old and new PRI levels to stop EDMA from submitting TR requests on both PRI levels. Do not manually submit additional events via the EDMA. 3) Do not submit new QDMA requests on either old or new PRI level. 4) Stop L2 cache misses on either old or new PRI level. This can be done by forcing program execution or data accesses in internal memory. Another way is to have the CPU executing a tight loop that does not cause additional cache misses. 5) Poll the appropriate PQ bits in PQSR until both queues are empty (see section 6.17.1). 6) Clear the TRSTALL bit to 0 to allow the HPI to continue normal operation. Requestors are halted on the old HPI PRI level so that memory ordering can be preserved. In this case, all pending requests corresponding to the old PRI level must be let to complete before HPI is released from stall state.
23
Page:
Change or Add:
Requestors are halted on the new PRI level to ensure that at no time can the sum of all requestor allocations exceed the queue length. By halting all requestors at a given level, the user can be free to modify the queue allocation counters of each requestor.
727
Change the paragraph in section 7.5.4: The host can interrupt the CPU by writing to one of the DSPINT bits in the HPIC. In order for the CPU to receive DSPINT correctly, the host must only write one but not both of the DSPINT bits in HPIC register. The DSPINT bit is tied directly to the internal DSPINT signal. By writing DSPINT = 1 when DSPINT = 0, the host causes a low-tohigh transition on the DSPINT signal. If the user programs the selection of the DSPINT interrupt with interrupt selector, the CPU detects the transition of DSPINT as an interrupt condition. Unlike a host write, a CPU write of DSPINT = 1 when DSPINT = 0 has no effect. The CPU can clear the DSPINT bits by writing a 1 to DSPINT when DSPINT = 1. Writing DSPINT = 0 (in HPIC) via the host or the CPU does not affect either the DSPINT bit or signal in any case.
727
Change the first paragraph in section 7.5.5: The CPU can send an active interrupt condition on the HINT signal by writing to the HINT bit in the HPIC. The HINT bit is inverted and tied directly to the HINT pin. The CPU can set HINT active by writing HINT = 1. The host can clear the HINT to inactive by writing a 1 to HINT. Writing HINT = 0 (in HPIC) via the host or the CPU does not affect either the HINT bit or the HINT signal.
732
Change the Value During Access column in Table 714:
Table 714.
Data Read Access in Fixed Address Mode for HPI32
Value During Access Value After Access HRDY 1 HPIC HPIA HPID ????????
Event Host reads HPIC Data not ready Host writes HPID Data ready
Note:
HD ????????
HR/W 1
HCNTL[1:0] 00
00000000 80001234
789ABCDE
0
11
0
00080008 80001234 789ABCDE
The "?" in this table indicate the value is unknown.
735
Change the title of Tables 718 and 719:
Table 718 Table 719.
16-Bit Data Write Access to HPI in Fixed Address Mode: HWOB = 1 16-Bit Data Write Access to HPI in Fixed Address Mode: HWOB = 0
24
Page:
735
Change or Add:
Add a new table after Table 719. The subsequent tables are renumbered accordingly:
Table 720.
32-Bit Data Write Access to HPI in Fixed Address Mode: HWOB = 1
Value During Access Value After Access HRDY 1 HHWIL 0 HPIC 00010001 HPIA 80001234 HPID ???????? Location 80001234 00000000
Event Host writes HPID 1st halfword Waiting for previous access to complete Host writes HPID 1st halfword Host writes HPID 2nd halfword Waiting for access to complete
HD 5566
HBE[1:0] 00
HR/W 0
HCNTL[1:0] 11
5566
00
0
11
0
0
00090009
80001234
????5566
00000000
wxyz
00
0
11
0
1
00090009
80001234
wxyz5566
00000000
????
??
?
??
1
?
00010001
80001234
wxyz5566
wxyz5566
For C620x/C670x HPI, wxyz represents a "don't care" value on the HD pins. The HBE[1:0] value indicates that only 16-bit is transferred. For C621x/C671x and C64x HPI, however, wxyz should be 0000 on the HD pins. The entire 32-bit word is transferred. Note: The "?" in this table indicate the value is unknown.
741
Change the paragraph in section 7.7: All C621x/C671x HPI transfers are placed in the high priority transfer queue, Q1. All C64x HPI transfers can be programmed to any of the four priority levels, with the medium priority level set as default. Refer to section 6.17, Resource Arbitration and Priority Processing, for details on transfer priority.
86
Add a footnote in Table 82 at the XHOLD and XHOLDA signals:
Table 82.
Signal State for Disabled Host Port
XBUS Signal XHOLD XHOLDA I/O Port Mode (I/O/Z) I/O/Z I/O/Z External Connection Pull down Pull down
Internal arbitration should be enabled, such that the DSP is the master of the bus when not using the host port. See section 8.6 for more details.
25
Page:
89
Change or Add:
Change the Description of XFRAT in Table 85:
Table 85.
Field XFRAT
Expansion Bus Global Control Register (XBGC) Field Description
Description FIFO clock rate XFRAT = 00: XFCLK = 1/8 CPU clock rate XFRAT = 01: XFCLK = 1/6 CPU clock rate XFRAT = 10: XFCLK = 1/4 CPU clock rate XFRAT = 11: XFCLK = 1/2 CPU clock rate The FIFO clock setting cannot be changed while a DMA request to XCE space is active. The XFCLK should be disabled before changing XFRAT field. There is no delay required between enabling/disabling XFCLK and changing the XFRAT field. Section 8.4.2
812
Add a paragraph in section 8.4: Figure 85 illustrates how to interface four 8-bit FIFOs to the I/O port (memory map for this case is described in Table 88). Figure 86 is an example of an interface between two 16-bit FIFOs and the I/O port. The XOE, XRE, XWE, and XCEn signals are not tri-stated while the DSP releases control of the XBUS.
814
Add a paragraph below the Notes in section 8.4.1: An access to a section of memory that does not return a ready indication is not allowed. This includes accesses to XBUS I/O asynchronous spaces with XRDY pulled inactive or left floating on the device. Possible requestors are: programmed DMA channels or HPI/PCI/XBUS host mastering via the auxiliary DMA. This type of access can create a stall indefinitely.
814
Delete the third paragraph in section 8.4.2: The XOE, XRE, XWE, and XCEn signals are not tri-stated while the DSP releases control of the XBUS. Change the last paragraph in section 8.5.1.2: This register is used when the host port operates either in synchronous or asynchronous mode. The DSP does not have access to the XBISA register content. Burst transfers in the synchronous host-port mode are always expected to occur with autoincrement (AINC bit should be cleared to 0). In autoincrement mode (AINC = 0), operation is undefined if an external host attempts to access the last 2 word locations in the internal program/data RAM. This is because the DSP tries to prefetch data from reserved locations. Operation is also undefined if an external host attempts to cross a block boundary in a single DMA transfer. See Chapter 2 for details.
824
26
Page:
826
Change or Add:
Change the Descriptions of DSPINT and INTSRC in Table 816:
Table 816.
Expansion Bus Host Port Interface Control Register (XBHC) Description
Field DSPINT Description The expansion bus to DSP interrupt (set either by the external host or the completion of a master transfer) is cleared when this bit is set. The DSPINT bit must be manually cleared before another one can be set. The XBUS host port interrupt can be caused either by DSPINT bit or by XFRCT counter. The INTSRC selects interrupt source between DSPINT and XFRCT counter. INTSRC=0: interrupt source is DSPINT bit of the XBISA. When a zero is written to INTSRC, the DSPINT of the XBISA is copied to the DSPINT bit of the XBHC. INTSRC=1: interrupt is generated at the completion of the master transfer initiated by writing to the START bit-field.
INTSRC
836
Add a paragraph before the third paragraph in section 8.5.2.2: Initial access made to the expansion bus in host slave mode should be done in the order indicated above. After reset, the first access from the host should be an XBISA write followed by an XBD read/write. Undefined operation may occur if an XBISA read or an XBD read/write occurs before an XBISA write. To read/write from the DSP memory space, the host must follow the following sequence:
27
Page:
838
Change or Add:
Change Figure 822 to show the XRDY signal in high impedance (not high) in clock cycle four and five. The DSP should start driving the XRDY signal during the sixth clock cycle.
Figure 822. Expansion Bus Master Writes a Burst of Data to the DSP
1 2 3 Wait DSP latches CNTL XCLKIN XCS (input) 1 = XBISA XCNTL (input) XW/R (input) XBE[3:0] (input) XBLAST (input) XAS (input) XD[31:0] XRDY (output) Write 0000 = Word Write 0 = XBD 4 Ready 5 6 7 8 Ready Ready 9 10 11
Internal src/dst addr D1 D2 D3 D4
28
Page:
840
Change or Add:
Change Figure 823 to show the XRDY signal in high impedance (not high) in clock cycle four and five. The DSP should start driving the XRDY signal during the sixth clock cycle.
Figure 823. The Bus Master Reads a Burst of Data From the DSP
1 2 3 Wait DSP latches CNTL XCLKIN XCS (input) 1 = XBISA XCNTL (input) XW/R (input) XBE[3:0] (input) XBLAST (input) XAS (input) Internal src/dst addr XD[31:0] XRDY (output) D1 D2 D3 D4 Write Read 0 = XBD 4 Ready Wait 5 6 7 8 9 10 11
0000 = Word
843
Add a paragraph before the third paragraph in section 8.5.3: Initial access made to the expansion bus in host slave mode should be done in the order indicated above. After reset, the first access from the host should be an XBISA write followed by an XBD read/write. Undefined operation may occur if an XBISA read or an XBD read/write occurs before an XBISA write. If the XBUS host port is configured to operate in asynchronous mode, the XCS signal is used for four purposes:
843
Change the fourth paragraph in section 8.5.3: The XRDY signal of the DSP functions differently than the C6201 HPI READY signal. The XRDY signal indicates normally not ready condition (active low READY signal is internally OR-ed with XCS signal in order to obtain XRDY). XRDY should be polled during reads/ writes to/from the XBISA or XBD.
29
Page:
844
Change or Add:
Add a new section 8.5.4:
8.5.4
Special Circumstance of XBUS Host Memory Accesses
When the XBUS host port executes a read from the DSPs memory space, it does so by performing burst prefetches of 3 words. This results in the DMA auxiliary channel reading 3 higher-word addresses that you may not have explicitly requested. This occurs only under the following situations:
- An external master performs an autoincremented read from the XBUS
configured for host slave mode (both synchronous or asynchronous).
- The XBUS configured as the master in synchronous host port mode writes
from the DSP to the external space via the XBUS. The accesses described above can cause the following undesired operations: 1) Accesses to undesired CE spaces:
J
When reading the top 3 words of EMIF CE0, the resulting prefetches can cause an inadvertent access to CE1 that may cause an undesired read to a device or a stall if the inadvertent access is to an asynchronous memory space with ARDY left floating or pulled inactive (notready). The above example also applies to CE2 with the resulting prefetches possibly causing an inadvertent access to CE3 (see section 11.3, Memory Map).
J
Associated design tip: If not using ARDY or XRDY, always pull to the ready state to avoid stalls. If you always want to detect bad software setups, always pull to the not-ready state to detect system stalls. 2) Unintended port crossings or illegal accesses to a reserved location:
J
When reading the top 3 words of EMIF CE1, the access can cross into either program memory (PMEM) block 0 when in Map 0 or to the internal peripheral bus (PBus) region storing EMIF control registers when in Map 1. This is an illegal port crossing. When reading the top 3 words of EMIF CE3, the access can cross into reserved address space. This is an illegal access. When reading the top 3 words of PMEM block 0, the access can cross into PMEM block 1. This is an illegal port crossing. When reading the top 3 words of PMEM block 1, the access can cross into reserved address space. This is an illegal access. When reading the top 3 words of data memory (DMEM) block 1, the access can cross into reserved address space. This is an illegal access. When reading anywhere in the PBus space, you may prefetch ahead to three undesired control registers. This can cause an illegal access when accessing a reserved register address. If the register access has side effects (like reading the McBSP DRR, clearing RRDY), then you may inadvertently cause these side effects.
J J J J J
30
Page:
Change or Add:
Note: A restriction does NOT exist when crossing between DMEM block 0 and block 1 because they both use the same DMA port. Associated design tips:
J
When reading internal peripheral registers: H For reads from an external master, use fixed-mode addressing. As a broader statement, it is good practice to use fixed mode also when writing to peripheral registers as sometimes there are gaps between them. Do not use the XBUS host port configured in synchronous master mode to directly copy peripheral register values to external slaves. This is an atypical operation. If you must do so, copy the register data to an internal space with the CPU and then copy those internal locations to external space.
H
J
When reading the top 3 locations of an EMIF CEx, internal program block or DMEM block 1, use fixed-mode addressing. Note this procedure does not have to be followed when accessing the top 3 words of DMEM block 0, this is because DMEM block 0 and block 1 are in the same DMA port.
31
Page:
92
Change or Add:
Change the following PCI features in section 9.1:
Conforms to power management interface specification revision1.1 (C6205 only) DSP power control via software (C6205 only) Peripheral power control via software (C6205 only) Software-controlled assertion of PME from D0, D1, D2, D3hot (C6205 only) Hardware-controlled assertion of PME on power wakeup active from D3cold. Optional hardware-controlled assertion of PME from D0, D1, D2, D3hot. (C6205 only) - Supports D0, D1, D2, D3hot, D3cold power management modes (C6205 only) - Implements PCI power management control status register "sticky" bits from logic powered by 3.3Vaux (C6205 only)
92
Delete the following PCI feature in section 9.1:
- 5-V or 3.3-V input signaling, 3.3-V output signaling
95
Add a row to Table 91:
Table 91.
Features
Differences Between the C62x/C67x and C64x PCI
C62x/C67x PCI 8 words C64x PCI 16 words Section N/A
FIFO depth
912
Change the Description of INTSRC in Table 95:
Table 95
Bits 0
Host Status Register (HSR) Bit Field Description
Name INTSRC Reset Source PRST Description PCI IRQ source active since last HSR clear. This bit, when 1, indicates that the DSP asserted the PINTA interrupt by writing the INTREQ bit in the RSTSRC register, and the INTAM bit in the HSR was a 0. This bit can be cleared by the PCI Host by writing a 1 to this bit. This will also negate the PINTA signal. Reads INTSRC = 0: PINTA was not asserted after last clear INTSRC = 1: PINTA was asserted after last clear Writes INTSRC = 0: no affect INTSRC = 1: deassert PINTA. Note that this does not enable future interrupts. INTRST in RSTSRC must also be set to allow future interrupts. See section 9.10.3.
32
Page:
914
Change or Add:
Add a new section 9.3.3, Figure 97, and Table 98. The subsequent sections, figures, and tables are renumbered accordingly:
9.3.3
TR Control Register (TRCTL) (C64x only)
The TR control register (TRCTL) controls how the PCI submits its requests to the EDMA subsystem. The TRCTL is shown in Figure 97 and summarized in Table 98.
Figure 97.
31
TR Control Register (TRCTL)
9 Reserved RW,+0 8 TRSTALL RW,+0 7 6 5 PRI RW,+10 4 3 0 Reserved RW,+x PALLOC RW,+0100
Table 98.
Bit PALLOC PRI TRSTALL
TR Control Register (TRCTL) Bit Descriptions
Description Controls the total number of outstanding requests that can be submitted by the PCI to the EDMA Controls the priority queue level that PCI requests are submitted to. Forces the PCI to stall all PCI requests to EDMA This bit allows safe changing of the PALLOC and PRI fields. TRSTALL=0: Allows PCI requests to be submitted to EDMA TRSTALL=1: Halts the creation of new PCI requests to EDMA Section 9.3.3 9.3.3 9.3.3
To safely change the PALLOC or PRI bits in TRCTL, the TRSTALL bit needs to be used to ensure a proper transition. The following procedure must be followed to change the PALLOC or PRI bits: 1) Set the TRSTALL bit to 1 to stop the PCI from submitting TR requests on the current PRI level. In the same write, the desired new PALLOC and PRI fields may be specified. 2) Clear all EDMA event enables (EER) corresponding to both old and new PRI levels to stop EDMA from submitting TR requests on both PRI levels. Do not manually submit additional events via the EDMA. 3) Do not submit new QDMA requests on either old or new PRI level. 4) Stop L2 cache misses on either old or new PRI level. This can be done by forcing program execution or data accesses in internal memory. Another way is to have the CPU executing a tight loop that does not cause additional cache misses. 5) Poll the appropriate PQ bits in PQSR until both queues are empty (see section 6.17.1). 6) Clear the TRSTALL bit to 0 to allow the PCI to continue normal operation. Requestors are halted on the old PCI PRI level so that memory ordering can be preserved. In this case, all pending requests corresponding to the old PRI level must be let to complete before PCI is released from stall state.
33
Page:
Change or Add:
Requestors are halted on the new PRI level to ensure that at no time can the sum of all requestor allocations exceed the queue length. By halting all requestors at a given level, the user can be free to modify the queue allocation counters of each requestor.
915
Add a TRCTL row and footnote to Table 98:
Table 98.
PCI Memory-Mapped Peripheral Registers
Register Accessed Reads EECTL TRCTL Writes EECTL TRCTL Section 9.13.4 9.3.3
DSP Data Space Address C62x/C67x 01A8 0008h -- C64x 01C2 0008h 01C3 0000h
HALT register applies to C62x/C67x only. TRCTL register applies to C64x only.
923
Change the paragraph in section 9.9.1: The DSP master address register (DSPMA) contains the DSP's address for the location of destination data for DSP master reads, or the address location of source data for DSP master writes. The register also contains bits to control the address modification. DSPMA is doubleword aligned on C64x and word aligned on C6205. The DSPMA is shown in Figure 99 and summarized in Table 99.
923
Change the Description of AINC (bit 1) in Table 99:
Table 99.
Bits 1
DSP Master Address Register (DSPMA) Bit Field Description
Name AINC Reset Source RESET WARM Description Autoincrement mode of DSP master address AINC = 0: Autoincrement of ADDRMA enabled AINC = 1: ADDRMA will not autoincrement Autoincrement only affects the lower 24 bits of DSPMA. As a result, autoincrement does not cross 16MB boundaries and will wrap around if incrementing past the boundary. DSP's word address for PCI master transactions
31:2
ADDRMA
RESET WARM
924
Change the paragraph in section 9.9.2: The PCI master address register (PCIMA) contains the PCI word address. For DSP master reads, PCIMA contains the source address. For DSP master writes, the PCIMA contains the destination address. The PCIMA is shown in Figure 910 and summarized in Table 910.
34
Page:
924
Change or Add:
Change the Description of ADDRMA in Table 910:
Table 910.
Bits 31:2
PCI Master Address Register (PCIMA) Bit Field Description
Reset Source RESET WARM Description PCI word address for PCI master transactions.
Name ADDRMA
925
Change Figure 911. Add a footnote.
Figure 911. PCI Master Control Register (PCIMC)
31 16 15 4 3 2 0
CNT RW, +0000h
Reserved R, +0
Rsvd RW, +0
START RW, +000
This reserved bit must always be written with zero. Writing 1 to this bit results in undefined operation.
925
Change the Bits and the Description of START in Table 911:
Table 911.
Bits 2:0
PCI Master Control Register (PCIMC) Bit Field Description
Name START Reset Source RESET WARM PRST Description Start the read or write master transaction START = 000b: Transaction not started/flush current transaction START = 001b: Start a master write transaction START = 010b: Start a master read transaction to prefetchable memory START = 011b: Start a master read transaction to nonprefetchable memory START = 100b: Start a configuration write START = 101b: Start a configuration read START = 110b: Start an I/O write START = 111b: Start an I/O read START will return to 000b when the transaction is complete. The START field must not be written/changed during active master transfer. If the PCI bus is reset during a transfer, the transfer will stop and the FIFOs will be flushed. (A CPU interrupt can be generated on a PRST transition.) START will only get set if bits 31:16 0000h
31:16
CNT
RESET WARM
Transfer Count . It specifies the number of bytes to transfer
35
Page:
928
Change or Add:
Change the third paragraph in section 9.9.8: For DSP master writes, the ADDRMA field in the DSPMA contains the word-aligned (C62x/C67x) or doubleword-aligned (C64x) source (DSP) address. If AINC = 0 in the DSPMA, the source address is autoincremented by 4 bytes after each internal data transfer. The PCIMA contains the word-aligned destination address (PCI address). An internal register keeps track of the PCI master address.
929
Change the third through sixth paragraphs in section 9.9.9: For DSP master reads, the PCIMA contains the external PCI slave source address. The ADDRMA field in the DSPMA contains the word-aligned (C62x/C67x) or doublewordaligned (C64x) destination address (DSP address). If AINC = 0 in the DSPMA, the destination address is autoincremented by 4 bytes after each internal data transfer. A master memory read is initiated by enabling the START bits in the PCIMC. The PCI port performs a PCI bus request. Once a PCI bus request is granted, a PCI bus cycle is initiated. The type of cycle initiated depends on the number of bytes to be transferred and the cache line size. The following master memory read commands are supported:
- Memory read - Memory read multiple - Memory read line
The user can initiate two types of memory reads, based on the START bits in the PCIMC. Prefetchable reads (START = 010b) use the memory read multiple and memory read line commands for transfers greater than one word. A memory read command is used for transfers of one word. Nonprefetchable memory reads (START = 011b) always use a memory read command. A transfer size of N words is broken up into N one-word read cycles on the PCI bus. Users should read from prefetchable memory whenever possible. 930 Add a new section 9.9.10:
9.9.10 DSP As System Host
In systems where the DSP is the host for the PCI bus, an external mechanism is required to enable the DSP's master bit (bit 2 of PCI command register). This bit is not accessible by the CPU, and the DSP cannot generate any cycles until the master bit is set. A CPLD or FPGA can be programmed to do the configuration write necessary to set the bit. Once this bit is set, the DSP is capable of generating the configuration cycles necessary to configure a PCI bus. However, the DSP is not capable of configuring itself. If this is necessary and there is no other device on the bus capable of performing the configuration (such as another DSP), then the external mechanism used to set the master bit must also configure the rest of the PCI configuration registers.
36
Page:
934
Change or Add:
Change Figure 917. Add a footnote.
Figure 917. PCI interrupt Enable Register (PCIIEN)
31 13 12 Rsvd RW,+0 11 PRST RW, +0 10 Rsvd RW, +0 9 EERDY RW, +0 8 CFG ERR RW, +0 7 CFG DONE RW, +0 6 MASTER OK RW, +0 5 PWRHL RW, +0 4 PWRLH RW, +0 3 HOSTSW RW, +1 2 PCI MASTER RW, +0 1 PCI TARGET RW, +0 0 PWR MGMT RW, +0 Rsvd R, +0
These reserved bits must always be written with zeros. Writing 1 to these bits result in undefined operation.
936
Change the Description of INTREQ (bit 3) and INTRST (bit 4) in Table 918:
Table 918.
DSP Reset Source/Status Register (RSTSRC) Bit Field Description
Reset Source RESET WARM RESET WARM Description Request a DSP-to-PCI interrupt when written with a 1. Causes assertion of PINTA if the INTAM bit in HSR is 0. Writes of 0 have no effect. Always reads as 0. When a 1 is written to this bit, PINTA is deasserted and the interrupt logic is reset to enable future interrupts. This bit must be asserted before another host interrupt can be generated. Writes of 0 have no effect. Always reads as 0.
Bits Name 3 INTREQ
4
INTRST
941
Change the third paragraph in section 9.13: For C62x/C67x, the state of the boot configuration pins EESZ[2:0] at power-on reset determines if a serial EEPROM is present, and if so, what size. See Chapter 11, Boot Modes and Configuration, for details on EESZ[2:0]. Table 920 summarizes the EEPROM sizes supported by the C62x/C67x. The C64x only supports 4K bits EERPOM, and EESZ[2:0] does not exist.
941
Change the column header in Table 920:
Table 920.
TMS320C62x/C67x EEPROM Size Support
EESZ[2:0] EEPROM Size Supported on C62x/C67x (bits)
945
Change the Description of EESZ (bits 5:3) in Table 925:
Table 925.
Bits 5:3
EEPROM Control Register (EECTL) Bit Field Description
Reset Source RESET Description Indicates the state of the EESZ[2:0] pins at power-on reset EESZ = 000b: No EEPROM EESZ = 001b: 1K bits (C6205 only) EESZ = 010b: 2K bits (C6205 only) EESZ = 011b: 4K bits EESZ = 100b: 16K bits (C6205 only)
Name EESZ
37
Page:
960
Change or Add:
Change the first paragraph in section 9.16: This section discusses the PCI configuration registers in detail. These registers are only accessible from the external host PCI. Table 928 to Table 950 summarize the bit fields in the PCI configuration registers. Table 951 lists the power management states in the PWRDATA register. See section 9.3.1.
961
Add a note to Table 934:
Table 934.
Cache Line Size Register Bit Field Description
Bits 7:0
Note:
Access R/W
Default 00h
Description Cache Line Size
This field only accepts power-of-2 cache line sizes. If a cache line size other than a power of 2 is written, 0 will be written to this field.
962
Change Table 937:
Table 937
Base 0 Address Register Bit Field Description
Bits 31:0 Access R/W Default 0000 0008 Host Read FFC0 0008 Description Mask for 4 Mbytes, prefetchable memory
The host reads this value after writing FFFF FFFFh, used as mask bits to determine the size of the base address region during register initialization.
962
Change Table 938:
Table 938
Base 2 Address Register Bit Field Description
Bits 31:0 Access R/W Default 0000 0000 Host Read FF80 0000 Description Mask for 8 Mbytes, nonprefetchable memory
The host reads this value after writing FFFF FFFFh, used as mask bits to determine the size of the base address region during register initialization.
962
Change Table 939:
Table 939
Base 1 Address Register Bit Field Description
Bits 31:0 Access R/W Default 0000 0001 Host Read FFFF FFF1 Description Mask for 16 Bytes, I/O space
The host reads this value after writing FFFF FFFFh, used as mask bits to determine the size of the base address region during register initialization.
38
Page:
968
Change or Add:
Add a new section 9.17:
9.17
C620x/C670x Special Circumstance of PCI-to-Memory Accesses
When the PCI executes a read from the DSPs memory space, it does so by performing burst prefetches of 3 words. This results in the DMA auxiliary channel reading 3 higher-word addresses that you may not have explicitly requested. This occurs only under the following situations:
- The PCI master performs prefetchable reads from an external PCI master. - The C6205 PCI acts as the PCI master performing a prefetchable read
from the DSPs address space to the PCI address. These prefetchable reads can generate the following undesired operations: 1) Accesses to undesired CE spaces:
J
When reading the top 3 words of EMIF CE0, the resulting prefetches can cause an inadvertent access to CE1 that may cause an undesired read to a device or a stall if the inadvertent access is to an asynchronous memory space with ARDY left floating or pulled inactive (notready). The above example also applies to CE2 with the resulting prefetches possibly causing an inadvertent access to CE3 (see section 11.3, Memory Map).
J
Associated design tip: If not using ARDY, always pull to the ready state to avoid stalls. If you always want to detect bad software setups, always pull to the not-ready state to detect system stalls. 2) Unintended port crossings or illegal accesses to a reserved location:
J
When reading the top 3 words of EMIF CE1, the access can cross into either program memory (PMEM) block 0 when in Map 0 or to the internal peripheral bus (PBus) region storing EMIF control registers when in Map 1. This is an illegal port crossing. When reading the top 3 words of EMIF CE3, the access can cross into reserved address space. This is an illegal access. When reading the top 3 words of PMEM block 0 the access can cross into PMEM block 1. This is an illegal port crossing. When reading the top 3 words of PMEM block 1, the access can cross into reserved address space. This is an illegal access. When reading the top 3 words of data memory (DMEM) block 1, the access can cross into reserved address space. This is an illegal access. When reading anywhere in the PBus space, you may prefetch ahead to three undesired control registers. This can cause an illegal access when accessing a reserved register address. If the register access has side effects (like reading the McBSP DRR, clearing RRDY), then you may inadvertently cause these side effects.
J J J J J
39
Page:
Change or Add:
Note: A restriction does NOT exist when crossing between DMEM block 0 and block 1 because they both use the same DMA port. Associated design tips:
J
When reading internal peripheral registers: H For reads from an external master, use fixed-mode addressing. As a broader statement, it is good practice to use fixed mode also when writing to peripheral registers as sometimes there are gaps between them. On PCI, always use non-prefetchable reads of peripheral registers.
H
J
When reading the top 3 locations of an EMIF CEx, internal program block or DMEM block 1, use fixed-mode addressing. Note this procedure does not have to be followed when accessing the top 3 words of DMEM block 0, this is because DMEM block 0 and block 1 are in the same DMA port.
40
Page:
10all
Change or Add:
Chapter 10: change all occurrences of CExCTL, CE0CTL, CE1CTL, CE2CTL, CE3CTL, CExSEC, CE0SEC, CE1SEC, CE2SEC, and CE3SEC:
From CExCTL CE0CTL CE1CTL CE2CTL CE3CTL CExSEC CE0SEC CE1SEC CE2SEC CE3SEC To CECTLx CECTL0 CECTL1 CECTL2 CECTL3 CESECx CESEC0 CESEC1 CESEC2 CESEC3
1010
Change the footnote in Figure 107:
See Table 102 for ED, EA, CE, and BE pins on EMIFA and EMIFB.
1014
Change the paragraph in section 10.2: Control of the EMIF and the memory interfaces it supports is maintained through memorymapped registers within the EMIF. The EMIF clock is needed to access these registers. The memory-mapped registers are listed in Table 103.
41
Page:
1015
Change or Add:
Change the C621x/C671x bits 6 and 5 read/write fields and the footnotes in Figure 108:
Figure 108. EMIF Global Control Register (GBLCTL)
C621x/C671x:
31 Rsv R, +0
15 14 13 12 11 10 9 8 7 NO HOLD RW, +0 6 5 4 3 2 1 0
16
Rsv
Rsv
Rsv
Rsv
BUSREQ
ARDY
HOLD
HOLDA
Rsv
EKEN
CLK1EN
CLK2EN
Rsv
Rsv
Rsv
R,+0
RW,+0
RW,+1
RW,+1
R, +0
R, +x
R, +x
R, +x
RW, +1
RW, +1
RW, +1
RW, +1
R, +0
R, +0
R, The +0
reserved bit fields should always be written with their default values when modifying the GBLCTL. Writing other values to these fields may cause improper operation. For all C621x/C671x devices, except C6713, C6711C, and C6712C, this bit field is reserved, RW, +1.
1016
Change the Device Group of CLK4EN and CLK6EN in Table 104:
Table 104.
EMIF Global Control Register (GBLCTL) Field Descriptions
Apply to Device Group 4
Field CLK4EN
Description CLKOUT4 enable CLK4EN = 0, CLKOUT4 held high CLK4EN = 1, CLKOUT4 enabled to clock For C64x, CLKOUT4 pin is muxed with GP1 pin. Upon exiting reset, CLKOUT4 is enabled and clocking. After reset, CLKOUT4 maybe be configured as GP1 via the GPIO enable register GPEN. CLKOUT6 enable CLK6EN = 0, CLKOUT6 held high CLK6EN = 1, CLKOUT6 enabled to clock For C64x, CLKOUT6 pin is muxed with GP2 pin. Upon exiting reset, CLKOUT6 is enabled and clocking. After reset, CLKOUT6 maybe be configured as GP2 via the GPIO enable register GPEN.
CLK6EN
4
42
Page:
Change or Add:
1017
Add EKEN, a Group 6 to the footnote, and two new footnotes. Change the Group 3 footnote and the Description of EK1EN, EK2EN, EK1HZ, EK2HZ, EK2RATE, NOHOLD, and ARDY in Table 104:
Table 104.
EMIF Global Control Register (GBLCTL) Field Descriptions
Apply to Device Group 6
Field EKEN
Description ECLKOUT enable EKEN = 0, ECLKOUT held low EKEN = 1, ECLKOUT enabled to clock (default) ECLKOUT1 enable EK1EN = 0, ECLKOUT1 held low EK1EN = 1, ECLKOUT1 enabled to clock ECLKOUT2 enable EK2EN = 0, ECLKOUT2 held low EK2EN = 1, ECLKOUT2 enabled to clock ECLKOUT1 High-Z control EK1HZ = 0, ECLKOUT1 continues clocking during Hold (if EK1EN = 1) EK1HZ = 1, ECLKOUT1 High-Z during Hold ECLKOUT2 High-Z control EK2HZ = 0, ECLKOUT2 continues clocking during Hold (if EK2EN = 1) EK2HZ = 1, ECLKOUT2 High-Z during Hold
EK1EN
4,5
EK2EN
4,5
EK1HZ
4,5
EK2HZ
4,5
EK2RATE ECLKOUT2 Rate. ECLKOUT2 runs at: EK2RATE = 00, 1x EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) rate EK2RATE = 01, 1/2x EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) rate EK2RATE = 10, 1/4x EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) rate NOHOLD External NOHOLD enable NOHOLD = 0: no hold disabled. Hold requests via the HOLD input are acknowledged via the HOLDA output at the earliest possible time. NOHOLD = 1: no hold enabled. Hold requests via the HOLD input are ignored. ARDY = 0: ARDY input is low. External device not ready. ARDY = 1: ARDY input is high. External device ready. For C64x only, valid ARDY bit reflects the true value of the ARDY input pin only during an asynchronous memory access, indicated by asynchronous CEx active.
4,5
1,2,3,4,5
ARDY
1,2,3,4,5
Group1 devices include: C6201/C6701. Group 2 devices include: all C620x/C670x except C6201/C6701. Group 3 devices include: C621x/C671x (including C6713, C6711C, and C6712C). Group 4 devices include: C64x EMIFA. Group 5 devices include: C64x EMIFB. Group 6 devices include: C6713, C6711C, and C6712C. ECLKOUTx does not turn off/on glitch free via EKxEN or via EKxHZ. See section 10.14. ECLKOUT2 rate should only be changed once during EMIF initialization from the default (1/4x) to either 1/2x or 1x.
43
Page:
1019
Change or Add:
Change the footnote and the TA (bits1514) read/write field in Figure 109:
Figure 109. TMS320C62x/C67x/C64x EMIF CE Space Control Register (CExCTL)
C621x/C671x/C64x:
31 Write setup RW, +1111 15 TA RW, +11 14 13 Read strobe RW, [phone] Write strobe RW, [phone] MTYPE RW, +0010 22 21 20 19 Read setup RW, +1111 3 Write hold MSB} RW, +0 2 0 16 Write hold RW, +11 4
Read hold RW, +011
For C64x, MTYPE default value is RW,+0000. For C621x/C671x, this field is reserved. R,+0.
1020
Change Table 105:
Table 105.
Field
EMIF CE Space Control Registers (CExCTL) Field Descriptions
Description Setup width. Number of clock cycles of setup time for address (EA), chip enable (CE), and byte enables (BE) before read strobe or write strobe falls. For asynchronous read accesses, this is also the setup time of AOE before ARE falls. Hold width. Number of clock cycles that address (EA) and byte strobes (BE) are held after read strobe or write strobe rises. For asynchronous read accesses, this is also the hold time of AOE after ARE rising. Write hold MSB is the most-significant bit of write hold (C64x only). Minimum Turn-Around time (C621x/C671x/C64x only). Turn-around time controls the minimum number of ECLKOUT cycles between a read followed by a write (same or different CE spaces), or between reads from different CE spaces. Applies only to asynchronous memory types.
Read setup Write setup
Read hold Write hold MSB Write hold TA
44
Page:
Change or Add:
1023
Change the SDCSZ (bits 2726) and INIT (bit 24) read/write fields in Figure 1011:
Figure 1011. EMIF SDRAM Control Register (SDCTL)
C621x/C671x:
31 Rsv R,+0 15 TRC RW, +1111 30 SDBSZ RW, +0 29 28 27 26 25 RFEN RW, +1 24 INIT W, +0 23 TRCD RW, +0100 20 19 TRP RW, +1000 0 Reserved R, +0000 0000 0000 16 SDRSZ RW, +00 12 11 SDCSZ RW, +00
C64x:
31 Rsv R,+0 15 TRC RW, +1111 30 SDBSZ RW, +0 29 28 27 26 25 RFEN RW, +1 24 INIT W, +0 23 TRCD RW, +0100 20 19 TRP RW, +1000 1 Reserved R, +000 0000 0000 0 SLFRFR RW, +0 16 SDRSZ RW, +00 12 11 SDCSZ RW, +00
1024
Change the Description of INIT and RFEN in Table 107:
Table 107.
Field INIT
EMIF-to-SDRAM Control Register (SDCTL) Field Descriptions
Description Forces initialization of all SDRAM present INIT = 0: no effect INIT = 1: initialize SDRAM in each CE space configured for SDRAM. The CPU should initialize all of the CE space control registers and SDRAM extension register before setting INIT = 1. Reading this bit returns an undefined value.
RFEN
Refresh enable RFEN = 0: SDRAM refresh disabled RFEN = 1: SDRAM refresh enabled If SDRAM is not used, be sure RFEN = 0; otherwise, BUSREQ may become asserted when SDRAM timer counts down to 0.
45
Page:
Change or Add:
1025
Delete the first paragraph below Table 107 that begins: The EMIF automatically clears the INIT field to zero... Change the PERIOD (bits 110) read/write field in Figure 1012:
1026
Figure 1012. EMIF SDRAM Timing Register (SDTIM)
31 Reserved
R, +0000 00
26
25
24 XRFR
23
COUNTER R, +0000 1000 0000 R, +0101 1101 1100
12
11
PERIOD RW, +0000 1000 0000 RW, +0101 1101 1100
0
R, +00 RW,+00
Applies to C620x/C670x Applies to C621x/C671x/C64x
1027
Change the paragraph in section 10.2.5: The SDRAM extension register of the C621x/C671x/C64x allows programming of many parameters of SDRAM. The programmability offers two distinct advantages. First, it allows an interface to a wide variety of SDRAMs and is not limited to a few configurations or speed characteristics. Second, the EMIF can maintain seamless data transfer from external SDRAM due to features like hidden precharge and multiple open banks. It should be noted that the SDCTL register must be set after configuring the SDEXT register. Figure 1013 shows the SDRAM extension register and Table 109 discusses these parameters.
1027
Change the WR2DEAC (bits 1918) read/write field in Figure 1013:
Figure 1013. TMS320C621x/C671x/C64x SDRAM Extension Register (SDEXT)
31 21 20 WR2RD RW,+1 19 18 17 WR2WR RW,[phone] RD2RD RW,+1 8 7 6 TWR RW,+01 5 4 TRRD RW,+1 3 TRAS RW,+111 1 0 TCL RW,+1
Rsvd R, +0
WR2DEAC RW,+10 RW,+01
R2WDQM RW,+11 RW,+10
RD2WR RW,+101
RD2DEAC RW,+11
THZP RW,+10
Applies to C621x/C671x. Applies to C64x.
1032
Change the last paragraph in section 10.3.3: Figure 1015 shows the byte lane used on C64x. The external memory is always right aligned to the ED[7:0] side of the bus. The endianness mode determines whether byte lane 0 (ED[7:0]) is accessed as byte address 0 (little endian) or as byte address N (big endian), where 2N is memory width in bytes. Similarly, byte lane N is addressed as either byte address 0 (big endian) or as byte address N (little endian).
46
Page:
1033
Change or Add:
Change the label in Figure 1015:
Figure 1015. TMS320C64x Byte Alignment by Endianness
EMIFB (16-bit bus):
TMS320C64x EMIF B ED[15:8] ED[7:0]
16-bit device
8-bit device
1034
Change the third paragraph in section 10.5: The C621x/C671x/C64x EMIF allows programming of the addressing characteristics of the SDRAM, including the number of column address bits (page size), the row address bits (pages per bank), and banks (maximum number of pages that can be opened). The maximum number of open pages is limited by the number of EMIF address registers. Using this information, the C621x/C671x/C64x is able to open up to four pages of SDRAM simultaneously. The pages can all be in different banks of a single CE space, or distributed across multiple CE spaces. Only one page can be open per bank at a time. The C621x/C671x/C64x can interface to any SDRAM that has 8 to 10 column address pins, 11 to 13 row address pins, and two or four banks.
47
Page:
1038
Change or Add:
Change Table 1015:
Table 1015. TMS320C620x/C670x Compatible SDRAM
Max Devices/ CE 4 Addressable Space (MBytes) 8M SDRAM EMIF
SDRAM Size 16M bit
B 2
W 8
D 1M
Column Address A8A0 EA10EA2
Row Address A10A0 SDA10, EA11EA2 A10A0 SDA10, EA11EA2 A11A0 EA13, SDA10, EA11EA2 A10A0 SDA10, EA11EA2 A11A0
Bank Select BA0 EA13
Precharge A10 SDA10
2
16
512K
2
4M
SDRAM EMIF
A7A0 EA9EA2
BA0 EA13
A10 SDA10
64M bit
4
16
1M
2
16M
SDRAM EMIF
A7A0 EA9EA2
BA1BA0 EA15EA14
A10 SDA10
4
32
512K
1
8M
SDRAM EMIF
A7A0 EA9EA2
BA1BA0 EA14EA13
A10 SDA10
128M bit (1)
4
32
1M
1
16M
SDRAM
A7A0
BA1BA0
A10
EMIF
EA9EA2
EA13, SDA10, EA11EA2 A11A0 SDA10, EA11EA2 A12A0 (3)
EA15EA14
SDA10
4
16
2M
2
8M
SDRAM EMIF
A8A0 EA10EA2
BA1BA0 EA14EA13
A10 SDA10
256M bit (1)
4
16
4M
2
16M
SDRAM
A8A0
BA1BA0
A10
EMIF
EA10EA2
SDA10, EA11EA2 A12A0 (3)
EA14EA13
SDA10
512M bit (1)
4
16
8M
2
16M
SDRAM
A9A0 (2)
BA1BA0
A10
EMIF
EA10EA2
SDA10, EA11EA2
EA14EA13
SDA10
Legend: B = Banks; W = Width; D = Depth Notes: 1) Not all of the memory space will be used in larger memories. This is due to column and row address size limitations of the 620x/670x EMIF architecture. 2) SDRAM address A9 reflects EA11 during a RAS command. See Table 1020 for more details. 3) SDRAM address A12 should follow the SDRAM datasheet guidelines (Typically this signal should be tied low).
48
Page:
1043
Change or Add:
Change the paragraph in section 10.5.1:
10.5.1
SDRAM Initialization
After reset, none of the CE spaces are configured as SDRAM. The CPU should initialize all of the CE space control registers and the SDRAM extension register before performing SDRAM initialization by setting the INIT bit to 1. You should not write a 1 to the INIT bit, if SDRAM does not exist in the system. The EMIF performs the following steps when INIT is set to 1: 1) Sends a DCAB command to all CE spaces configured as SDRAM. 2) Sends eight refresh commands. 3) Sends an MRS command to all CE spaces configured as SDRAM.
1043
Delete the last paragraph in section 10.5.1: The DCAB cycle is performed immediately after reset, provided the HOLD input is not active (a host request). If HOLD is active, the DCAB command is not performed until the hold condition is removed. In this case the external requester should not attempt to access any SDRAM banks, unless it performs SDRAM initialization and control itself. Add a new section 10.5.2. The subsequent sections are renumbered accordingly:
1043
10.5.2
C620x/C670x Bootmode
If BOOTMODE[4:0] bits are set such that CE0 is configured for SDRAM, SDRAM initialization proceeds according to the steps listed in section 10.5.1 under the control of hardware, prior to the boot process. However, if HOLD is active, the DCAB command is not performed until the hold condition is removed. In this case, the external requester should not attempt to access any SDRAM banks, unless it performs SDRAM initialization and control itself. If other CE spaces besides CE0 are configured for SDRAM, and since CE0 is initialized with slower default timings following reset, SDRAM initialization should be performed by software.
1059
Change the paragraph in section 10.5.6: The C621x/C671x/C64x uses a mode register value of either 0032h or 0022h. The register value and description are shown in Figure 1026 and summarized in Table 1024. Both values program a default burst length of four words for both reads and writes. The value programmed depends on the CAS latency parameter defined by the TCL field in the SDRAM extension register (SDEXT). If the CAS latency is three (TCL = 1), 0032h is written during the MRS cycle. If the CAS latency is two (TCL = 0), 0022h is written during the MRS cycle. Figure 1027 shows the timing diagram during execution of the MRS command.
1064
Change the title of Figure 1029:
Figure 1029. TMS320C621x/C671x/C64x SDRAM DEAC -- Deactivate Single Bank
49
Page:
1072
Change or Add:
Change the first paragraph in section 10.6: The C6000 EMIF interfaces directly to industry-standard synchronous burst SRAMs (SBSRAMs). This memory interface allows a high-speed memory interface without some of the limitations of SDRAM. Most notably, since SBSRAMs are SRAM devices, random accesses in the same direction can occur in a single cycle. Besides supporting the SBSRAM interface, the programmable synchronous interface on the C64x supports additional synchronous device interfaces. See section 10.7 for details on the C64x interface with the other synchronous devices. This section discusses the SBSRAM interface on all the C6000 devices.
1075
Change the input on ADV and the footnote in Figure 1039:
Figure 1039 TMS320C64x SBSRAM Interface
External clock
ECLKIN ECLKOUT CEx ARE/SDCAS/SADS/SRE VCC AOE/SDRAS/SOE AWE/SDWE/SWE External memory interface (EMIF) BE[3:0] EA[all] ED[31:0] CLK CS ADSC ADV OE WE BE[3:0] A[N:0] D[31:0] SBSRAM
ECLKOUTx used is selected by the SNCCLK bit in the CExSEC register. For interface to a 64-bit data bus, BE[7:0], EA[all], and ED[63:0] are used. For interface to a 16-bit data bus, BE[1:0], EA[all], and ED[15:0] are used.
50
Page:
1079
Change or Add:
Delete the PDT signal and change the footnotes in Figure 1042:
Figure 1042. TMS320C64x SBSRAM Six-Element Read
Read ECLKOUTx Read Read/D1 latched Read/D2 latched Read/D3 latched Read/D4 latched D5 latched D6 latched/ deselect
CEx
BE[7:0]
BE1
BE2
BE3
BE4
BE5
BE6
EA[22:3]
A1
A2 RL = 2
A3
A4
A5
A6
ED[63:0]
D1
D2
D3
D4
D5
D6
SADS
SOE
SWE For EMIFB, BE[1:0], EA[20:1], and ED[15:0], respectively, are used instead.
51
Page:
1082
Change or Add:
Delete the PDT signal and change the footnotes in Figure 1045:
Figure 1045. TMS320C64x SBSRAM Six-Element Write
Write ECLKOUTx Write Write Write Write Write Deselect
CEx
BE[7:0]
BE1
BE2
BE3
BE4
BE5
BE6
EA[22:3]
A1
A2 WL = 0
A3
A4
A5
A6
ED[63:0]
D1
D2
D3
D4
D5
D6
SADS
SOE
SWE For EMIFB, BE[1:0], EA[20:1], and ED[15:0], respectively, are used instead.
52
Page:
1084
Change or Add:
Change the signal names and footnote in Figure 1046:
Figure 1046. TMS320C64x ZBT SRAM Interface
External clock
ECLKIN ECLKOUTx{ CEx External memory interface (EMIF) SADS/SRE SOE SWE BE[7:0]} EA[all]} ED[63:0]} CLK CE ADV/LD OE R/W BE[7:0] A[N:0] D[63:0] ZBT SRAM
ECLKOUTx used is selected by the SNCCLK bit in the CExSEC register. The MTYPE field selects the interface to be 8-, 16-, 32-, or 64-bits wide. For 32-bit interface, BE[3:0], EA[all], and ED[31:0] are used For 16-bit interface, BE[1:0], EA[all], and ED[15:0] are used
53
Page:
1085
Change or Add:
Delete the PDT signal and change the signal names and footnotes in Figure 1047:
Figure 1047. TMS320C64x ZBT SRAM Six-Element Write
Write ECLKOUTx Write Write Write Write Write Deselect
CEx
BE[7:0]
BE1
BE2
BE3
BE4
BE5
BE6
EA[all]
A1
A2 WL = 2
A3
A4
A5
A6
ED[63:0]
D1
D2
D3
D4
D5
D6
SADS
SOE
SWE Figure shows 64-bit interface. The MTYPE field selects the interface type to be 8-, 16-, 32-, or 64-bits wide. For 32-bit interface, BE[3:0], EA[all], and ED[31:0] are used For 16-bit interface, BE[1:0], EA[all], and ED[15:0] are used
1087
Change the figure title, signal name, and footnote in Figure 1050:
Figure 1050. TMS320C64x Glueless Synchronous FIFO Write Interface
ECLKOUTx{ CEx EMIF SWE SADS/SRE EXT_INTx ED[63:0]}
n
WCLK WEN
RCLK REN OE Synchronous FIFO EF FF HF D[n:0}]
Q[31:0]
ECLKOUTx used is selected by the SNCCLK bit in the CExSEC register. The MTYPE field selects the interface to be 8-, 16-, 32-, or 64-bits wide. For EMIFB, only 8- and 16-bit interfaces are available. Therefore only ED[15:0] is used. Reads to CEx must not be performed in this interface, since reads cause CEx to go active, causing FIFO data contention.
54
Page:
1087
Change or Add:
Add text below Figure 1050 at the end of section 10.7.2: Care must be taken when implementing glueless synchronous FIFO interface:
- For glueless synchronous FIFO read interface in CE3 space
(Figure 1049), writes to CE3 must not be performed. Internally, SOE3 = CE3 OR SOE. Performing a write causes CE3 and SOE3 to go active, hence REN and OE will be active. Data contention will occur on the ED bus since both DSP and FIFO will be driving data at the same time.
- For glueless synchronous FIFO write interface in any CE space
(Figure 1050), reads must not be performed. Reads cause CEx signal to go active; therefore, FIFO data corruption will occur since FIFO expects data from DSP. 1088 Change Figure 1051 into two figures. The subsequent figures are renumbered accordingly:
Figure 1051. TMS320C64x Standard Synchronous FIFO Read for CE0, CE1, or CE2
Read ECLKOUTx CEx (CEEXT = 0){ CEx (CEEXT = 1){ BE[7:0]} EA[all]} BE1 BE2 BE3 BE4 BE5 BE6 Read Read Read Read Read
A1
A2 RL = 1
A3
A4
A5
A6
ED[63:0]} SRE (RENEN = 1) SOE
D1
D2
D3
D4
D5
D6
SOE3 SWE CEEXT = 0 for glueless synchronous FIFO interface. CEEXT = 1 for interface with glue. Figure shows 64-bit interface. The MTYPE field selects the interface type to be 8-, 16-, 32-, or 64-bits wide. For 32-bit interface, BE[3:0], EA[all], and ED[31:0] are used For 16-bit interface, BE[1:0], EA[all], and ED[15:0] are used
55
Page:
Change or Add:
Figure 1052. TMS320C64x Standard Synchronous FIFO Read for CE3 only
Read ECLKOUTx CE3 (CEEXT = 0){ CE3 (CEEXT = 1){ BE[7:0]} EA[all]} BE1 BE2 BE3 BE4 BE5 BE6 Read Read Read Read Read
A1
A2 RL = 1
A3
A4
A5
A6
ED[63:0]} SRE (RENEN = 1) SOE SOE3
D1
D2
D3
D4
D5
D6
SWE CEEXT = 0 for glueless synchronous FIFO interface. CEEXT = 1 for interface with glue. Figure shows 64-bit interface. The MTYPE field selects the interface type to be 8-, 16-, 32-, or 64-bits wide. For 32-bit interface, BE[3:0], EA[all], and ED[31:0] are used For 16-bit interface, BE[1:0], EA[all], and ED[15:0] are used
56
Page:
Change or Add:
1090
Change the signal names and footnote in Figure 1053:
Figure 1053. TMS320C64x FWFT Synchronous FIFO Read
Read/D1 latched ECLKOUTx Read/D2 latched Read/D3 latched Read/D4 latched Read/D5 latched Read/D6 latched
CEx (CEEXT = 0)
CEx (CEEXT = 1)
BE[7:0]{
BE1
BE2
BE3
BE4
BE5
BE6
EA[all]{
A1
A2
A3
A4
A5
A6
ED[63:0]{
D1
D2 RL = 0
D3
D4
D5
D6
SRE (RENEN = 1)
SOE or SOE3
SWE Figure shows 64-bit interface. The MTYPE field selects the interface type to be 8-, 16-, 32-, or 64-bits wide. For 32-bit interface, BE[3:0], EA[all], and ED[31:0] are used For 16-bit interface, BE[1:0], EA[all], and ED[15:0] are used
1091
Change the third paragraph in section 10.8: ... It has also been enhanced to allow for longer read hold time, and the 8- and 16-bit interface modes have been extended to include writable asynchronous memories, instead of ROM devices. To avoid bus contention, a programmable turnaround time (TA) also allows the user to control the minimum number of cycles between between a read followed by a write (same or different CE spaces), or between reads from different CE spaces.
1097
Add a sub-bullet to the 4th bullet in section 10.8.3:
- At the end of the hold period: AOE becomes inactive as long as another
read access to the same CE space is not scheduled for the next cycle.
J
CE becomes inactive only if another read or write access to the same CE space is not pending.
57
Page:
Change or Add:
1099
Change the second sub-bullet of the 4th bullet in section 10.8.4:
- At the end of the hold period: J J
ED goes into the high-impedance state only if another write access to the same CE space is not scheduled for the next cycle. CE becomes inactive only if another read or write access to the same CE space is not pending.
10102
Change the paragraph in section 10.8.5:
- TMS320C621x/C671x/C64x Operation: For C621x/C671x, ARDY is
sampled for the first time on the ECLKOUT cycle at the end of the programmed strobe period (Figure 1062). For C64x, ARDY is sampled two clock cycles before the last cycle of the programmed strobe period (Figure 1063). If sampled low, the strobe period is extended and ARDY is sampled again on the next ECLKOUT cycle. Read data is latched by the C621x on the cycle that ARDY is sampled high. The ARE signal goes high on the the following cycle. Therefore, the strobe period is visibly extended by three cycles in Figure 1062 and Figure 1063, although data is latched after the second cycle. 10102 Add a new Figure 1063. The subsequent figures are renumbered accordingly:
Figure 1063. TMS320C64x Ready Operation
Setup 2 Programmed strobe 4 Ready sampled Strobe extended 3 Hold 1 Data latched
ECLKOUT CE BE[3:0] EA[21:2] ED[31:0] AOE ARE AWE ARDY BE Address
58
D
Page:
10102
Change or Add:
Add a new section 10.8.6:
10.8.6
C620x/C670x Illegal Access to Asynchronous Memory
An access to a section of memory that does not return a ready indication is not allowed. This includes accesses to EMIF asynchronous spaces with ARDY pulled inactive externally or left floating on the device. Possible requestors are: CPU program fetches, CPU loads and stores, programmed DMA channels or HPI/PCI/XBUS host mastering of the DMA through the auxiliary DMA. This type of access can create a stall indefinitely.
59
Page:
Change or Add:
10103
Change section 10.9. The subsequent figures and tables are renumbered accordingly:
10.9
Peripheral Device Transfers (PDT) (TMS320C64x)
To perform a peripheral device transfer (PDT), the PDTS or PDTD bits in the EDMA options parameter must be appropriately set. Refer to Chapter 6, EDMA Controller, for details. A PDT allows you to directly transfer data from an external peripheral (such as a FIFO) to another external memory (such as SDRAM), and vice versa. Normally, this type of transfer would require an EMIF read of a peripheral followed by an EMIF write to memory, or an EMIF read of a memory followed by an EMIF write to a peripheral. In a typical system, however, both the peripheral and memory are connected to the same physical data pins, and thus an optimization can be made. In a PDT write transfer, data is driven by the peripheral directly, and written to the memory in the same bus transaction. In a PDT read transfer, data is driven by the memory directly, and written to the peripheral in the same bus transaction. Typically, the memory device will be mapped to an addressable location via a CEx signal. Normally, the peripheral device is not memory mapped (it does not use a CEx signal). It is activated with the PDT signal and optionally a combination of other control signals (via external logic). PDT transfers are classified in terms of the memory on the EMIF. A PDT write is a transfer from a peripheral to memory (memory is physically written). A PDT read is a transfer from memory to a peripheral (memory is physically read). For a PDT read, the EMIF ignores the read data on the external bus. For a PDT write, the EMIF data bus is placed in a high-impedance state during the transaction to allow the external peripheral or memory to drive the data bus. A PDT transfer is only supported when the external memory is SDRAM (specified by the MTYPE field in the CE space control register). PDT transfers should not be performed to non-SDRAM CE spaces. In a PDT transaction, the EMIF: 1) Generates normal SDRAM read bus cycles for a PDT read, or generates normal SDRAM write bus cycles for a PDT write. For example, for a PDT read from CE0 configured as SDRAM, the EMIF asserts CE0 and generates the SDRAM read control signals. The EMIF does not explicitly generate the control signals to the destination peripheral in a PDT read. For a PDT write to CE0 with an SDRAM, the EMIF asserts CE0 and generates the SDRAM write control signals. The EMIF does not explicitly generate the control signals to the source in a PDT write. 2) Generates PDT control signal (PDT) and the PDT address pins. PDT is asserted low 0, 1, 2, or 3 cycles prior to the data phase of the transaction. The PDTWL and PDTRL fields in the PDT control register (PDTCTL) control the latency of the PDT signal for write and read transfers, respectively (see section 10.9.1).
60
Page:
Change or Add:
3) In addition to the direct control provided by the PDT signal, the EMIF uses two upper-address pins (PDTA and PDTDIR) during a PDT transfer. Table 1035 describes each of these signals, listing their appropriate EMIF and SDRAM pin and their function. 4) Drives EMIF data outputs (ED pins) to a high-impedance state.
Table 1035. PDT Signal Description
Pin Name PDTA PDTDIR PDT 64-bit EMIF EA19 EA20 PDT 32-bit EMIF EA18 EA19 PDT 16-bit EMIF EA17 EA18 PDT SDRAM A16 A17 Function PDT access PDT read, not write PDT data
During a PDT transfer, the EMIF drives PDTA active and PDTDIR to its appropriate state. Activation of PDTA signals that a PDT transfer is controlling the bus while the state of the PDTDIR denotes the type of transfer, either a read (high) or write (low) to memory. For a non-PDT transfer to SDRAM:
- PDT is inactive - PDTA is high - PDTDIR is not used
For a non-PDT transfer to asynchronous or programmable synchronous memory:
- PDT is inactive - PDTA functions as an address bit - PDTDIR functions as an address bit
61
Page:
Change or Add:
10.9.1
PDT Control Register (PDTCTL)
The PDT control register, shown in Figure 1063 and defined in Table 1036, configures the latency of the PDT signal with respect to the data phase of the transaction.
Figure 1063. EMIF PDT Control Register (PDTCTL)
31 Reserved R, +0 4 3 PDTWL RW, +00 2 1 PDTRL RW, +00 0
Table 1036. EMIF PDT Control Register (PDTCTL) Field Descriptions
Field PDTRL Description PDT Read Latency PDTRL=00: PDT asserted 0 cycles prior to the data phase of a read transaction PDTRL=01: PDT asserted 1 cycle prior to the data phase of a read transaction PDTRL=10: PDT asserted 2 cycles prior to the data phase of a read transaction PDTRL=11: PDT asserted 3 cycles prior to the data phase of a read transaction PDTWL PDT Write Latency PDTRL=00: PDT asserted 0 cycles prior to the data phase of a write transaction PDTRL=01: PDT asserted 1 cycle prior to the data phase of a write transaction PDTRL=10: PDT asserted 2 cycles prior to the data phase of a write transaction PDTRL=11: PDT asserted 3 cycles prior to the data phase of a write transaction
62
Page:
Change or Add:
10.9.2
PDT Write
A PDT write transfer refers to a transfer from a peripheral to memory, in which the memory is physically written. To enable a PDT write transfer, the PDTD bit in the EDMA options field must be set to 1. The assertion/deassertion of the PDT address pins (PDTA and PDTDIR) and the PDT pin are timed according to the destination memory clock. Since the destination memory is SDRAM, ECLKOUT1 is used. A PDT write transfer procedure is as follows: 1) The destination address is to a CE space set as SDRAM:
J
The PDT access bit (PDTA) and the PDT direction (PDTDIR) are used to give the system advance warning that a PDT transaction is pending. This may be useful to activate bus switches or other external logic that will control the actual PDT transfer. If the access is to a closed page, then during the ACTV cycle, PDTA is low, and PDTDIR is low to indicate a write access. If the access is to an open page previously accessed without a PDT operation, then the page will be closed and reopened, with the PDT address pins asserted low during the ACTV cycle. If the access is to an open page previously accessed with a PDT operation, then the access goes directly to the data phase.
J J
J
2) Normal write control signals are generated to the appropriate CE space. 3) The write transaction proceeds as normal except:
J
EMIF data outputs remain in a high-impedance state. Therefore, the memory latches data from the peripheral device, instead of data from the EMIF. PDT is asserted low PDTWL cycles prior to the data being latched by the destination device. This implies that the peripheral must drive valid data PDTWL cycles after PDT is active.
J
Figure 1064 displays the timing diagram for a PDT write transaction.
63
Page:
Change or Add:
Figure 1064. PDT Write Transaction Timing Diagram
ACTV/PDT_OPEN ECLKOUT1 CEx BE[7:0] ED[64:0] EA[18:14] EA13 EA[12:3] SDRAS SDCAS SDWE PDTA PDTDIR PDT (PDTWL=0) PDT (PDTWL=1) PDT (PDTWL=2) PDT (PDTWL=3) For EMIFB, BE[1:0], EA[16:12], EA[10:1], EA11, and ED[15:0], respectively, are used instead. Prev Prev Prev Bank/Row Row Row Column BE1 D1 BE2 D2 BE3 D3 Bank BE4 D4 WRITE
10.9.2.1
PDT Write Examples PDT write transactions are supported from both a standard synchronous (STD) FIFO interface and a first word fall through (FWFT) FIFO interface. Table 1037 gives an overview of the supported systems. Figure 1065 through Figure 1070 describe the various systems where PDT write transfers are supported. These examples can be extended to other external peripherals.
Table 1037. Supported Set Ups for PDT Write Transfers
Case A System Description Glueless PDT write transfer to either FWFT FIFO or standard FIFO. PDTWL should be programmed accordingly with respect to the FIFO interface selected. Limited to SDRAM only in the system. PDT write transfer from a FWFT FIFO with glue. PDTWL programmed to 1 cycle latency. PDT write transfer from a standard FIFO with glue. PDTWL programmed to 1 cycle latency.
B C
64
Page:
Change or Add:
Figure 1065 shows the glueless synchronous FIFO interface for a PDT write transaction. When the glueless interface is implemented, SDRAM must be the only memory type present in the system. This is because the glueless interface uses PDTA to generate the output enable (OE) to the FIFO. If a memory type other than SDRAM is included in the system, the upper EMIF address bit used to generate PDTA (EA17, EA18, or EA19 depending on the EMIF data bus interface), will be used (see Table 1012). In this setup, PDT generates the read enable (REN) to the FIFO. PDT latency should be programmed as follows:
- FWFT FIFO: PDTWL = 0 - Standard FIFO: PDTWL = 1
Figure 1066 shows the timing diagram for a glueless PDT write transaction to a synchronous FIFO. Note, the PDT and REN waveforms differ between the standard FIFO interface and the FWFT FIFO interface. Figure 1067 and Figure 1068 show a PDT write interface with glue to a FWFT FIFO. Figure 1069 and Figure 1070 show a PDT write interface with glue to a standard FIFO. In each of these systems, external logic is used to shape the PDT signal to generate the appropriate control inputs to the FIFOs. For both systems, PDTWL should be programmed to 1. These systems are not restricted to SDRAM only, any combination of memory types is allowed.
Figure 1065. Case A: Glueless PDT Write Interface From Synchronous FIFO
ECLKIN CEx ECLKOUT1 SDRAS SDCAS SDWE EMIFA SDCKE BE[7:0] EA[18:3] PDTA (EA19) ED[63:0] PDTD
SDRAM CS CLK RAS CAS WE CKE DQM[7:0] A[15:0] D[63:0]
RCLK REN Synchronous FIFO OEN Q[63:0]
SDRAM must be the only memory type present in the system.
65
Page:
Change or Add:
Figure 1066. Case A: Glueless PDT Write Transfer From Synchronous FIFO Timing Diagram
ACTV/PDT_OPEN ECLKOUT1 CEx BE[7:0] ED[64:0] EA[18:14] EA13 DSP outputs EA[12:3] SDRAS SDCAS SDWE PDTA PDT (PDTWL=0 FWFT FIFO) PDT (PDTWL=1, STD FIFO) OE FIFO inputs REN (PDTWL=0, FWFT FIFO) REN (PDTWL=1, STD FIFO) Prev Prev Prev Bank/Row Row Row Column BE1 D1 BE2 D2 BE3 D3 Bank BE4 D4 WRITE
For EMIFB, BE[1:0], EA[16:12], EA[10:1], EA11, and ED[15:0], respectively, are used instead.
66
Page:
Change or Add:
Figure 1067. Case B: PDT Write Interface From FWFT FIFO With Glue
SDRAM or non-SDRAM CS ECLKIN CEy CEx ECLKOUT1 SDRAS SDCAS SDWE EMIFA SDCKE BE[7:0] EA[18:3] ED[63:0] PDT
CS CLK RAS CAS SDRAM WE CKE DQM[7:0] A[15:0] D[63:0]
Q D DFLOP
RCLK FWFT REN FIFO OE Q[63:0]
67
Page:
Change or Add:
Figure 1068. Case B: PDT Write Transfer From FWFT FIFO With Glue Timing Diagram
ACTV/PDT_OPEN ECLKOUT CEx BE[7:0] ED[64:0] EA[18:14] DSP outputs EA13 EA[12:3] SDRAS SDCAS SDWE PDT OE FIFO inputs REN Prev Prev Prev Bank/Row Row Row Column BE1 D1 BE2 D2 BE3 D3 Bank BE4 D4 WRITE
For EMIFB, BE[1:0], EA[16:12], EA[10:1], EA11, and ED[15:0], respectively, are used instead.
68
Page:
Change or Add:
Figure 1069. Case C: PDT Write Interface From Standard FIFO With Glue
SDRAM or non-SDRAM CS ECLKIN CEy CEx ECLKOUT1 SDRAS SDCAS EMIFA SDWE SDCKE BE[7:0] EA[18:3] ED[63:0] PDT Q D RCLK REN Standard FIFO OE Q[63:0]
CS CLK RAS CAS SDRAM WE CKE DQM[7:0] A[15:0] D[63:0]
DFLOP
69
Page:
Change or Add:
Figure 1070. Case C: PDT Write Transfer From Standard FIFO With Glue Timing Diagram
ACTV/PDT_OPEN ECLKOUT CEx BE[7:0] ED[64:0] EA[18:14] DSP inputs EA13 EA[12:3] SDRAS SDCAS SDWE PDT OE FIFO inputs REN Prev Prev Prev Row Row Column BE1 D1 Bank/Row BE2 D2 BE3 D3 BE4 D4 WRITE
For EMIFB, BE[1:0], EA[16:12], EA[10:1], EA11, and ED[15:0], respectively, are used instead.
70
Page:
Change or Add:
10.9.3
PDT Read
A PDT read transfer refers to a transfer from memory to a peripheral, in which the memory is physically read. To enable a PDT read transfer, the PDTS bit in the EDMA options field must be set to 1. The assertion/deassertion of the PDT address pins (PDTA and PDTDIR) and the PDT pin are timed according to the source memory clock. Since the source memory is SDRAM, ECLKOUT1 is used. A PDT read transfer procedure is as follows: 1) The source address is to a CE space set as SDRAM:
J
The PDT access bit (PDTA) is used to give the system advance warning that a PDT transaction is pending. This may be useful to activate bus switches or other external logic that will control the actual PDT transfer. If the access is to a closed page, then during the ACTV cycle, PDTA is asserted low. If the access is to an open page previously accessed without a PDT operation, then the page will be closed and reopened, with PDTA asserted low during the ACTV cycle. If the access is to an open page previously accessed with a PDT operation, then the access goes directly to the data phase. PDTDIR remains inactive (high) throughout the course of the transaction.
J J
J J
2) Normal read control signals are generated to the appropriate CE space. 3) The read transaction proceeds as normal except:
J J
EMIF ignores data at the ED pins PDT is asserted low PDTRL cycles before the data is to be returned by the source SDRAM.
Figure 1071 displays the timing diagram for a PDT read transaction.
71
Page:
Change or Add:
Figure 1071. PDT Read Transaction (CAS Latency is 3) Timing Diagram
Read data latched Read data latched Read data latched Read data latched
ACTV/PDT_OPEN ECLKOUT CEx BE[7:0] ED[64:0] EA[18:14] EA13 EA[12:3] SDRAS SDCAS SDWE PDTA PDTDIR PDT (PDTRL=0) PDT (PDTRL=1) PDT (PDTRL=2) PDT (PDTRL=3) Prev Prev Prev Row Row
Read
BE1
BE2
BE3 D1
BE4 D2 D3 D4
Bank/Row
Column
For EMIFB, BE[1:0], EA[16:12], EA[10:1], EA11, and ED[15:0], respectively, are used instead.
10.9.3.1
PDT Read Examples PDT read transactions are supported from both a standard synchronous FIFO interface and a first word fall through (FWFT) FIFO interface. Figure 1072 shows an example of a PDT read transaction from SDRAM to a synchronous FIFO. The PDT signal is used to generate the write enable (WEN) input to the FIFO. PDT latency should be programmed to 0. This system is not restricted to SDRAM only, any combination of memory types is allowed. This example can be extended to other external peripherals. Note in this example that no glue is required. However, if both read and write PDT transactions are required on the same bus, glue is required to properly create the OE, REN, and WEN signals for the FIFO (see section 10.9.4.1). Figure 1073 shows the timing diagram for a PDT read transfer to a synchronous FIFO.
72
Page:
Change or Add:
Figure 1072. Case D: Glueless PDT Read Interface to Synchronous FIFO
ECLKIN CEx ECLKOUT1 SDRAS SDCAS SDWE EMIFA SDCKE BE[7:0] EA[18:3] ED[63:0] PDT
CS CLK RAS CAS SDRAM WE CKE DQM[7:0] A[15:0] D[63:0]
WCLK WEN Synchronous FIFO Q[63:0]
Figure 1073. Case D: Glueless PDT Read Transfer to Synchronous FIFO Timing Diagram
Read data latched Read data latched Read data latched Read data latched
ACTV/PDT_OPEN ECLKOUT CEx BE[7:0] ED[64:0] EA[18:14] DSP inputs EA13 EA[12:3] SDRAS SDCAS SDWE PDT FIFO input WEN Prev Prev Prev Row Row
Read
BE1
BE2
BE3 D1
BE4 D2 D3 D4
Bank/Row
Column
For EMIFB, BE[1:0], EA[16:12], EA[10:1], EA11, and ED[15:0], respectively, are used instead.
73
Page:
Change or Add:
10.9.4
PDT Transfers with Multiple FIFOs on the Same Bus
The following sections describe PDT transfers with multiple FIFOs connected to a single CE space via the same data bus.
10.9.4.1
PDT Read and Write Transactions on the Same Bus If both PDT read and write transactions are required on the same bus, glue is required to properly create the OE, REN, and WEN signals for the FIFO. Figure 1074 shows a system that can perform both a PDT read and write transaction to a CE space configured as SDRAM. The discrete logic needed to generate the appropriate input signals to the FIFOs has two main stages: Direction Detect and Demux and Signal Generation. The direction detect stage latches the state of the PDTDIR (EA20, E19, or E18, depending on the EMIF data bus interface) signal, if CEx is active and outputs the signal DIR. The demux stage receives the DIR signal and the PDT signal as inputs. Based on these inputs, the demux stage generates the appropriate input signals to drive the selected read or write FIFO. Figure 1075 and Figure 1076 show the timing diagrams when write and read transactions are performed in a system with FWFT FIFOs, respectively. During a PDT write transaction, PDTDIR is active (low) denoting data is read from the synchronous FIFO and written to SDRAM. Therefore, during a PDT write transaction the appropriate OE and REN signals should be generated by the demux stage (see Figure 1075). During a PDT read transaction, PDTDIR is inactive (high) denoting data is read from SDRAM and written to the synchronous FIFO. Therefore, during a PDT read transaction the appropriate WEN signal should be generated by the demux stage (see Figure 1076). The OE and REN signals generated during the PDT write transaction, shown in Figure 1075, are identical to those described for case B. The WEN signal generated during the PDT read transaction, shown in Figure 1076, is identical to that described for case D. Therefore, for PDT write and PDT read timing diagrams when standard FIFOs are in the system, see Figure 1070 and Figure 1073, respectively.
74
Page:
Change or Add:
Figure 1074. Case E: PDT Read and Write Interface With Multiple FIFOs
SDRAM or non-SDRAM CS ECLKIN CEy CEx ECLKOUT1 SDRAS SDCAS SDWE EMIFA SDCKE BE[7:0] EA[18:3] PDTDIR (EA20) ED[63:0] PDT
CS CLK RAS CAS SDRAM WE CKE DQM[7:0] A[15:0] D[63:0]
Direction detect Dir Demux and signal generation
RCLK REN Synchronous FIFO OEN Q[63:0]
WCLK WEN Synchronous FIFO Q[63:0]
75
Page:
Change or Add:
Figure 1075. Case E: PDT Write Transfer with Read and Write FIFOs in the System (FWFT FIFO)
ACTV/PDT_OPEN ECLKOUT CEx ED[64:0] PDT PDTDIR OE REN WEN For EMIFB, ED[15:0] is used instead. D1 D2 D3 D4 WRITE
Figure 1076. Case E: PDT Read Transfer with Read and Write FIFOs in the System (FWFT FIFO)
Read data latched Read data latched Read data latched Read data latched
ACTV/PDT_OPEN ECLKOUT CEx ED[64:0] PDT PDTDIR WEN OE REN For EMIFB, ED[15:0] is used instead.
Read
D1
D2
D3
D4
76
Page:
10.9.4.2
Change or Add:
Multiple PDT Read and Write Transactions on the Same Bus Each of the previous systems can be extended to include additional read and or write FIFOs. In a system where more than two synchronous FIFOs are interfaced to a single CE space, additional unused upper row address bits of the SDRAM can be used to select the appropriate FIFO for the current transaction. In this case, the required glue receives PDTDIR, PDT, EAxx (upper address bits), and CEx as inputs. Based on the state of these inputs, the control signals are generated for the selected FIFO. The addition of multiple read and or write FIFOs is limited by the size of the SDRAM in a given CE space. This is because the size of the SDRAM dictates the number of column and row address bits required per transaction. Therefore, in some systems, it is possible to have zero unused valid address bits (see Figure 1022 and Figure 1023). For example, a 64-bit SDRAM that requires 11 row address bits, 8 column address bits, and 1 bank bit leaves 4 unused valid address bits for EMIFA (see the first row in Figure 1022). This means an additional 16 FIFOs per direction can be added to the data bus. However, a 64-bit SDRAM that requires 13 row address bits, 10 column address bits, and 2 bank bits leaves zero unused valid address bits for EMIFA (see the last row in Figure 1022). This means no additional FIFOs can be added to the data bus. Table 1038 shows the relationship between unused valid address bits and the number of additional peripherals that can be added to the same data bus.
Table 1038. Limitations on the Number of Additional Peripherals for a PDT Transfer
Number of Unused Valid Address Bits 0 1 2 3 4 Number of Additional Peripherals that can be Added 0 2 4 8 16
77
Page:
Change or Add:
10.9.5
PDT Transfers: Bus Width and DMA Considerations
When performing a PDT transfer, the bus width and DMA configuration must be considered. The following describes the proper system configurations for a PDT transfer:
- The FIFO (or external peripheral) bus width must equal the SDRAM bus
width.
- DMA must be configured such that: J J J J
The SRC and DST addresses are set to the same address, which matches the SDRAM address. The SRC and DST addresses must be aligned to the memory (MTYPE) bus width. Element size (ESIZE) is set to a 32-bit word. This is a preferred setting, see section 6.18, EDMA Performance. Element count (ELECNT) is set to a multiple of the bus width size (in elements).
Table 1039 summarizes the DMA configurations for supported SDRAM bus widths (MTYPE). SUM/DUM bits are set to increment.
Table 1039. DMA Configuration for a PDT Transfer
MTYPE (SDRAM width in bits) 8 16 32 64 Element size (ESIZE) 32, 16, 8 32, 16 32 32 Element count (ELECNT) No restrictions No restrictions No restrictions Even number
78
Page:
Change or Add:
10107
Add a new section 10.11. The subsequent sections are renumbered accordingly:
10.11
EMIF and CLKOUTx Usage Condition
There is a usage condition associated with the EMIF (EMIFA on C64x) that can affect the functionality of CLKOUTx. The EMIF global control register (GBLCTL) controls the logic that outputs the internal CPU/x clocks to the CLKOUTx pins. The bits in GBLCTL that enable CLKOUTx are clocked with the boot-time selected EMIF clock. Without a valid EMIF clock selected, ECLKIN (AECLKIN on C64x) or an internal clock, it is possible to have unknown values in GLBCTL and, therefore, a non-functional CLKOUTx. This happens only when ECLKIN is selected at boot time, but no external clock is provided. Furthermore, without a valid EMIF clock, the EMIF registers are not accessible or assured to have their default values. To avoid a non-functional CLKOUTx, a valid clock must be provided to the EMIF during the entire RESET active pulse.
10108
Change the bullets in section 10.11:
- HOLD: hold request input. HOLD is synchronized internally to the CPU
clock. This synchronization allows an asynchronous input while avoiding metastability. The external device drives this pin low to request bus access. HOLD is the highest priority request that the EMIF can receive during active operation. When the hold is requested, the EMIF stops driving the bus at the earliest possible moment, which may entail completion of the current accesses, device deactivation, and SDRAM bank deactivation. The external device must continue to drive HOLD low for as long as it wants to drive the bus. The external device may deassert HOLD after HOLDA is asserted and the bus is no longer needed. If any memory spaces are configured for SDRAM, these memory spaces are deactivated and refreshed after HOLD is released by the external master.
- HOLDA: Hold acknowledge output. The EMIF asserts this signal active
after it has placed its signal outputs in the high-impedance state. The external device can then drive the bus as required. The EMIF places all outputs in the high-impedance state with the exception of BUSREQ, HOLDA, and the clock outputs (CLKOUT1, CLKOUT2, ECLKOUT, SDCLK, and/or SSCLK, depending on the device). For the C64x, the EKxHZ bits in the GBLCTL register determine the state of the ECLKOUTx signals while HOLDA is asserted. There may be glitches on the ECLKOUTx signals when they transition from being driven to being place...