Files Register and Memories
ECE 554 Digital Engineering Laboratory C. R. Kime and M.J. Schulte and M. Lipasti Modified: Kewal K. Saluja
10/2/2007
Register Files and Memories
Register Files
Issues and Objectives Register File Concepts Implementation of Register Files Workarounds For Xilinx FPGAs Bottom Line
Memories
Timing Issues Width Expansion
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Issues and Objectives
Issues
ECE 554 projects require a broad range of register file and memory configurations ECE 554 lab boards provide very limited structures for implementing register files and memories.
Objectives:
To develop techniques for implementing a broad range of register file and memory configurations by using available lab board structures
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Register File Concepts
Register file environments
Non-Pipelined Pipelined
Register File Ports
Address Ports Data Ports Control Ports
Register File Implementations
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Register File Ports
Address
Read Write Shared
Data
Input Output Bidirectional
Control
Write Enable, Read/Write, Enable, Read, Write, CLK
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Environment - Non-Pipelined
RAddr B CLK Rdata B WEn WAddr C Wdata C Rdata A RAddr A ALU
Input Wdata C not registered outside of Register File
Clock controls when Wdata C is written
Inputs WEN and Waddr C may or may not be registered
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Environment - Pipelined 1
... ...
CLK RAddr B CLK Rdata B WEn WAddr C Wdata C Rdata A RAddr A
ALU
...
CLK
Register File is part of the pipeline platform Inputs may or may not be registered
Clock controls when Wdata C is written
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Environment - Pipelined 2
... ...
CLK Raddr B Rdata B WEn Waddr C Wdata C Rdata A Raddr A
... ...
CLK
...
Register File
is between pipe stages is not clocked - WEN controls latches => SRAM
Inputs
may or may not be registered, but register must be between Rdata A, Rdata B, and Wdata C
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Latch/bit of file Latch control can be Write Enable and addresses or some combination of other signals and addresses
WEn
Latch-Based
... ...
Waddr Wdata
Write Logic
Read Logic
Raddr
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... ...
...
Rdata
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Latched-Based
Level-sensitive write (assume positive level) Setup time on write address relative to leading edge of Wen Hold time on write address relative to trailing edge of Wen Setup and hold time on write data relative to trailing edge of Wen Latches cannot be in closed loop without:
Additional latch on different clock in loop, or Flip-flop in loop
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Flip-flop (Latch Pair)-Based
Flip-flop/bit of file Flip-flop is clocked by CLK or some combination of CLK and other signal and enabled by addressing logic and combination of other signals
WEn
... ...
Waddr Wdata
CLK
Write Logic
Read Logic
Raddr
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... ...
...
Rdata
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Flip-flop (Latch Pair)-Based
Write Logic adds setup-time to that for flipflops Read Logic adds propagation delay to that for flip-flops Acts as edge triggered flip-flop register file with above delays added
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Flip-flop (Shared-Slave)-Based
Latch/bit of file plus latch/bit of output Master latches are clocked by CLK or some combination of CLK and other signal and enabled by addressing logic and combination of other signals; slave latches clocks by CLK
WEn
... ...
Waddr Wdata
CLK
Write Logic
Read Logic
Raddr
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... ...
...
CLK
...
Rdata
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Flip-flop (Shared-Master)-Based
Latch/bit of file plus latch/bit of input Master latches are clocked by CLK some combination of CLK and other signal and enabled by addressing logic and combination of other signals; slave latches clocks by CLK
WEn Waddr Wdata Raddr
CLK
... ... ...
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... ...
Write Logic
Read Logic
...
...
...
Rdata
CLK
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Implementation of Register Files
Custom VLSI SRAM Classic SRAM Xilinx Virtex SRAM
Specifications Shortcomings
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Is the most flexible of all implementation techniques Can be used to implement any combination of variants discussed
Latch-based straightforward; needs additional rank of latches to do flip-flopbased Short of performance issues due to capacitance, can implement any port configuration in a singe storage element array.
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Custom VLSI SRAM
Classic SRAM
Has single RWaddr port, single Wdata port, and single Rdata port and is latch-based.
Due to single address port, can handle only one R or W access per clock cycle
Expansion to n R address/data ports
Place n SRAMs in parallel with the write accomplished by:
Applying same address to all RWaddr, and Wiring together all Wdata ports
Expansion to m W address/data ports
Add an m-way multiplexer to address port Use a clock that is m times CLK and multiplex the writes over m clocks
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Classic SRAM (Continued)
Addresses must be switched on positive clock edge WEn must be generated from negative clock edge and positive clock edge
Expansion to m W address/data ports and n R address/data ports
Doing both expansions above
Using (m +1)-way multiplexer, and A clock that is (m + 1) times CLK
Virtex Distributed SelectRAM
The SRAM capability provided in CLBs Can be used with expansion methods here in classic asynchronous SRAM mode or some synchronous modes Getting reliable timing is tricky - may require more complex clocking!
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Virtex Block SRAM Specifications
Symbol - Single Port
RAMB4_S#
WE EN RST CLK ADDR[#:0] DI[#:0]
DO[#:0]
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Virtex Block SRAM Specifications
Symbol - Dual Port
RAMB4_S#_S#
WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0]
DOA[#:0]
DOB[#:0]
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Virtex Block SRAM Specifications
Functionality
A WRITE operation of data DI to address ADDR occurs for WE = 1, EN = 1, RST = 0 and a positive edge on CLK. DI can also be read on DO after a delay. A READ operation from address ADDR occurs for WE = 0, EN = 1, RST = 0 and a positive edge on CLK. A RESET operation occurs on the DO latches only for EN = 1, RST = 1, and a positive edge on CLK
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Virtex Block SRAM Specifications
Functionality
CLK, EN, WE, and RST can also be programmed to be active low Conflicts for Dual Port SRAM
Simultaneous WRITEs to same location give invalid data A simultaneous READ on the alternate port of a location being written gives invalid READ data A READ on the alternate port of a location being written may not be performed until after a clock-to-clock setup window
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Virtex Block SRAM Specifications
Functionality - Timing
EN, WE, RST, ADDR, DI are captured on the positive edge of CLK in registers WRITEs into the SRAM latch array occur later due to internal timing logic READs (including those associated with writes) occur later due to internal timing logic
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Virtex Block SRAM Shortcomings
Positive edge-triggered storage of inputs to SRAM places an implicit register in front of the SRAM
Combinational READs with address changing, for example, on both the leading and trailing edge of clock, impossible (i.e. dual-porting with single clock) Feeding the SRAM array directly from combinational logic impossible
Latching of outputs
Combinational READs impossible
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I can only guess - perhaps you have better ideas. Guess 1: Excessive obsession with potential timing problems
Why Did Xilinx Produce Such a Design?
In terms of critical timing on signals into SRAM, with the interconnect delay uncertainty in the FPGA, these concerns are realistic
Must guarantee timing for Wen with async SRAM
Based on their past experience with customers based on Distributed SRAM use, although we made it work with some conservative clocking methods
Guess 2: The designers didn't understand the range of applications well, e.g., expectations for register files
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Workarounds for Virtex FPGAs
Absorbing input registers READ-after-alternate port-WRITE READ port expansion Inter-operation address dependency removal WRITE port expansion Absorbing output latches
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Absorbing Input Registers
Non-Pipelined - looks like flip-flopbased file - no absorbing needed!
RAMB4_S#_S#
WEA RSTA ENA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0]
CLK
DOA[#:0] ALU
CLK
DOB[#:0]
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Pipelined 1 - Register file part of pipeline platform - looks like flip-flop-based file - no absorbing needed!
RAMB4_S#_S#
WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0]
Absorbing Input Registers
CLK
DOA[#:0] ALU Pj DOB[#:0] CLK
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Pi
... ...
CLK
...
CLK
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Absorbing Input Registers
Pipelined 2 - Register file as SRAM between pipeline platforms - input registers give unwanted platform - must absorb into Pi and Pj platforms Combinational logic between Pi and SRAM now placed before Pi
Pi
... ...
...
RAMB4_S#_S#
WEA ENA Pi RSTA CLKA Pi ADDRA[#:0] DIA[#:0] P
j
CLK
DOA[#:0]
...
DOB[#:0]
CLK
WEB ENB Pi RSTB CLKB ADDRB[#:0] DIB[#:0] Pi
Pj
...
...
CLK
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Absorbing Input Registers
Summary Non-pipelined - No problem Pipelined 1 - No problem Pipelined 2 - Problem
Handle by moving pipeline platform pieces Handle by converting to Pipeline 1 form Affects combinational delay distribution between stages and hence may affect pipeline performance
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Virtex Block SRAM Shortcomings
Additional implication of conditions on prior page:
Since the Virtex Block SRAM has two addresses, it should support operands for a binary operation: R[ADDRA] <= R[ADDRA] op R[ADDRB] for arbitrary ADDRA and ADDRB on each clock cycle. But, it does not!
Since it is READ-after-WRITE, the right hand side operands are read in clock cycle i and the left hand side result is written in clock cycle i+1. One of the two addresses on the right hand side for cycle i must be the same as the write address on the left hand side for cycle i. Hazard logic would have to enforce this or insert a stall cycle (would almost always stall). Further, the READ-after-alternate port-WRITE problem causes the transfer R[ADDRy] <= R[ADDRx] op R[ADDRx] to be impossible to execute after a write to ADDRx. Would cause frequent stalls, once again.
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Virtex Block SRAM Shortcomings
Using Dual Port Virtex Block SRAM with custom VLSI SRAM used as the standard for comparison On a single clock cycle:
Maximum of two independent READ or WRITE operations Maximum of two READbacks of written value from WRITE operation on same port possible READback of written value from WRITE on alternate port not possible
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Add bypass logic outside of Virtex Block SRAM:
Select CLK P
READ-after-alternate port-WRITE
RAMB4_S#_S#
WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] P 1 0
CLK
DOA[#:0]
=
CLK
DOB[#:0]
0 1
Select
CLK
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Read Port Expansion
Expansion to n R address/data ports
Place ceiling(n/2) SRAMs in parallel with the two writes accomplished by:
Applying same address to all ADDRA and the same address to all ADDRB, and Wiring together all DIA ports and all DIB ports
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Read Port Expansion
Example for n = 4 ENA
ENA1 WADDRA CLK ENB RADDRA1 ENB1 WADDRB RADDRB1 DIA DIB ENA2 CLK RADDRA2 Select for all A mux's is WEA and all B mux's ENB2 is WEB All other like-named signals RADDRB2 connected together CLK
RAMB4_S#_S#
WEA ENA RSTA CLKA DOA[#:0] ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0]
RAMB4_S#_S#
WEA ENA RSTA CLKA DOA[#:0] ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0]
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CLK
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Inter-operation Address Dependency
READ-after-WRITE - Can be done for one WRITE two READs with two parallel Dual Port Block SRAMs with READ-after-alternate port-WRITE logic added to READ side of both.
Parallel WRITE on A ports Independent parallel READs on B-ports
Each additional parallel Dual Port Block SRAM adds one more READ port Cannot accomplish WRITE-after-READ Cannot be done for more than one active WRITE port without using WRITE Port Expansion
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Write Port Expansion
Requires "super-clocking," in which a clock having a multiple of the frequency of the fundamental operational clock is used to serialize Block SRAM operations. Requires additional registers to locally enter into and return from serialized operations Muxes required that are switched by the a flip-flop driven by the faster clock
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Example - Non-Pipelined - 4 WRITE Max Pi1 2CLK Pj Pi -1 ports
RAMB4_S#_S#
2CLK WEA ENA 2CLK RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB 2CLK CLKB ADDRB[#:0] DIB[#:0]
Write Port Expansion
DOA[#:0]
2CLK
2CLK
DOB[#:0]
CLK
Pi2
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CLK
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Absorbing Output Latches
The output latch is a part of the attempt at a "flip-flop" appearance for the SRAM operation. As such, there appears to be no way to explicitly work around it Other workarounds handle its effects
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The Bottom Line
Overall, it appears that the best approach is to:
Use a Non-Pipelined or Pipeline 1 structure Use the Interoperation Dependency solution to achieve ...