to Intro High Level Design with SystemC
Aim
To introduce SystemC, and its associated Design Methodology
Date
26th March 2001
Presented By
Alan Fitch
Designer Challenges
Design complexity
High level Behavioral Synthesis Cycle-Based Simulation Design Reuse Deep Submicron Logic Synthesis Transistors ASICs Place & Route Logic Simulation Polygons SPICE Pattern Generation IC CAD 1975 1980 1985 1990 1995 2000 System on Chip
Gates
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Silicon Complexity vs. Software Complexity
Silicon complexity is growing 10x every 6 years
Log scale 1G 64M 100 M 16M P7 10 M P6 IBM gate array Pentium Mitsubishi 1M gate array 256K 80486TMS320C80 80386 68040 64K 68020 LSI Logic gate array 80286 TMS320C240 Memory (DRAM) 16K 68000 Microprocessor/ TMS320C30 8086 Logic 8085 TMS320C15 DSP 8080 4M 78 82 86 90 94 98 256M Growth in software complexity in consumer products
Software in systems is growing faster than 10x every 6 years
40 35 30 25 20 15 10 5 0
1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998
Microprocessors Microcontrollers
1M
100 K 4K
10 K 1K 1K 70
4044 74
year
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Attacking Complexity
Work at a higher level of abstraction blocks RTL gates
Reuse existing designs
Cut n paste Virtual components (VCs) Capture Intellectual Property inhouse
Platform based design uP core ROM RAM DSP ATM MPEG INTERFACE
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Levels of Abstraction
System analysis System analysis
System level modeling System level modeling
H/W S/W partitioning H/W S/W partitioning
Many of these steps are presently manual!
Architectural exploration Architectural exploration
H/W spec H/W spec
S/W spec S/W spec
Gates
Analog spec Analog spec Digital spec Digital spec
Integration and verification Integration and verification
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Crossing the Gap
Different sorts of engineers have different areas of expertise
They think differently They use a different design language
Each area of design (analogue, digital, physical, software) requires a different (but overlapping) set of skills
Within an area of design there is a series of steps from high levels of abstraction to low levels of abstraction. Each level
May use different languages May require a different mindset May be capable of automatic translation to the next lower level
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Main requirements of hardware systems
Concurrency: hardware systems are parallel. Almost all hardware systems include concurrency
Reactivity: hardware systems react at transition on signals in the system
Distributiveness: hardware systems are made of a set of basic computation units that may
process data at different speeds use different clock rates
Timing: specification of hardware systems includes timing concepts for the synchronisation of parallel and distributed behaviour
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Language Comparison
SystemC SystemC C/C++-based C/C++-based Cynlib Cynlib SoC++ SoC++ VHDL/Verilog Replacements VHDL/Verilog Replacements System-Level Languages System-Level Languages Higher-Level Languages Higher-Level Languages A|RT A|RT VHDL+ VHDL+ SDL SDL SLDL SLDL Entirely New Languages Entirely New Languages SUPERLOG SUPERLOG Java-based Java-based
Java Java
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C/C++ Based Languages
Hardware engineer
Software/System engineer
Hand over specification doc Hand over specification doc Executable spec Executable spec Testbench Testbench
Conceptualize Conceptualize C/C++ simulation C/C++ simulation Write specification doc Write specification doc
Understand Understand Refine in C++, SystemC Refine in C++, SystemC Verify reusing testbench Verify reusing testbench Synthesize from C++, SystemC Synthesize from C++, SystemC
Faster simulation speed
Tools already on the market
C/C++ familiar to system and S/W engineers
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Development SystemC
Synopsys Scenic Synopsys Fridge SystemC Version 0.9 Frontier Design A|RT Library
IMEC
CoWare N2C Abstract Modelling
SystemC Version 1.0
Fixed Point Types
SystemC Version 1.1
SystemC Version 1.0.1
Onward to Version 2!
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SystemC Methodology
Version 1 Version 2 Version 3 refinement
Abstract (UTF)
S O F T W A R E
Generic RTOS
BCA
refinement
H A R D W A R E
RTOS
RTL
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Levels of Abstraction
Untimed Functional (UTF)
separates communication from behaviour uses Remote Procedure Call (RPC) paradigm
Timed Functional (TF)
allows allocation of time to behavioural blocks
Bus Cycle Accurate
models interfaces accurately using three handshaking methods
Cycle Accurate (CA)
essentially Register Transfer Level (RTL)
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RTL Example
EXOR gate built hierarchically from 4 NAND gates Each design created using
header file (contains C++ constructor) source code file (contains algorithm)
// nand2.cc // nand2.cc #include "nand2.h" #include "nand2.h" void nand2::do_nand2() void nand2::do_nand2() { { F = !(A & B); F = !(A & B); } } C++ Function
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NAND Gate Constructor
// nand2.h // nand2.h #include "systemc.h" #include "systemc.h" Module SC_MODULE(nand2) SC_MODULE(nand2) { { // ports // ports sc_in<sc_bit> A; sc_in<sc_bit> A; sc_in<sc_bit> B; sc_in<sc_bit> B; sc_out<sc_bit> F; sc_out<sc_bit> F; void do_nand2(); void do_nand2(); Constructor SC_CTOR(nand2) SC_CTOR(nand2) { { SC_METHOD(do_nand2); SC_METHOD(do_nand2); sensitive << A << B; sensitive << A << B; } } }; };
Copyright 2001 Doulos Ltd. All Rights Reserved
Header
Ports
Register do_nand2 with kernel
EXOR Gate
// exor2.h // exor2.h #include "systemc.h" #include "systemc.h" #include "nand2.h" #include "nand2.h" SC_MODULE(exor2) SC_MODULE(exor2) { { sc_in<sc_bit> A; sc_in<sc_bit> A; sc_in<sc_bit> B; sc_in<sc_bit> B; sc_out<sc_bit> F; sc_out<sc_bit> F; // 4 nand2 instances // 4 nand2 instances nand2 n1; nand2 n1; nand2 n2; nand2 n2; nand2 n3; nand2 n3; nand2 n4; nand2 n4; sc_signal<sc_bit> sc_signal<sc_bit> sc_signal&...