330 EE Lecture 42
Other Logic Styles Digital Building Blocks
Logic Styles
Static CMOS Complex Logic Gates Pass Transistor Logic (PTL) Pseudo NMOS Dynamic Logic
Domino Zipper
Static CMOS
Widely used Attractive static power dissipation and signal swing Dynamic Power Dissipation can become large Device count can get large
Static CMOS
Example:
F=A B
F=AB+AB
Straightforward Static CMOS implementation
22 transistors, 5 levels of logic
Example:
F=A B
Static CMOS
F=AB+AB
Static CMOS implementation
Recall "Bubble Pushing"
Example:
F=A B
Static CMOS
F=AB+AB
Static CMOS implementation
18 transistors, 4 levels of logic
Example:
F=A B
Static CMOS
F=AB+AB
Static CMOS implementation
Example:
F=A B
Static CMOS
F=AB+AB
16 transistors, 3 levels of logic Number of devices is unacceptably large in some applications
Logic Styles
Static CMOS Complex Logic Gates Pass Transistor Logic (PTL) Pseudo NMOS Dynamic Logic
Domino Zipper
Complex Logic Gates
DD
VDD
PUN
PUN
PDN
PDN
Recall: Basic gates can be decomposed into n-channel PD network and p-channel PU network Concept can be extended to more general PD and PU networks and signal swing and static power properties will be retained if PD of n-channel and PU of p-channel
Complex Logic Gates
p-channel n-channel Implement B in PDN Implement B in PUN with complimented input variables Zero static power dissipation VH=VDD, VL=0V (or VSS) Complimented input variables often required
Complex Logic Gates
Example:
F=A B
VDD
F=AB+AB
F= ( A+B ) ( A+B )
A
A
A and B need to be generated
B B
Y
12 transistors, 2 levels of logic Sizing can be: Minimum Size Equal worst-case rise/fall Equal worst-case rise/fall with OD Arbitrary
A
B
A
B
Complex Logic Gates
p-channel n-channel
Complex Logic Gates were discussed at the beginning of the course
Logic Styles
Static CMOS Complex Logic Gates Pass Transistor Logic (PTL) Pseudo NMOS Dynamic Logic
Domino Zipper
Pass Transistor Logic
Consider:
F=A
Requires only two components Implements noninverting function !
Pass Transistor Logic
Consider:
F=A
Inverter
Pass Transistor Logic
F=AB
AND Gate
Requires only 3 components
Even simpler AND gate, requires only 2 components
Pass Transistor Logic
F =A B
F =A B
If complimented input variables available, may be useful
Pass Transistor Logic
F =A B
F =A B C
VDD can be replaced with a Boolean variable
Pass Transistor Logic Gates
Pass Transistor Logic Gates
Pass Transistor Logic Gates
Pass Transistor Logic Gates
Pass Transistor Logic Gates
Pass Transistor Logic
F=AB
Observations about PTL
Low device count implementation of non inverting function (can be dramatic) Logic Swing not rail to rail Static power dissipation not 0 when F high RLG may be unacceptably large Slow tLH Signal degradation can occur when multiple levels of logic are used
Pass Transistor Logic
Methods of implementing RLG
SMALL
Physical Size of RLG too large
k
RLG
RLG
RLG
Pass Transistor Logic
A B RLG
D F RLG
Signal degradation
No inherent signal degradation
(if A, B and D to VDD)
Signal degradation may occur with PTL
Can intermix n-channel and p-channel devices to reduce/eliminate the signal degradation problem Can add static CMOS buffers to restore signals provided too much signal degradation has not occurred
Pass Transistor Logic
- signal restoration
A
VDD
VDD
B RLG
F D RLG
Pass Transistor Logic
- signal restoration Implement F in PTL and use single Static CMOS inverter
Alternate Notation
Pass Transistor Logic Gates
DD
PU Network
IN LG
Observe all PTL gates discussed so far were of this form PU network can contain a mixture of n-channel and p-channel devices Any of the PU networks used for complex logic gates could also be used in PTL
Pass Transistor Logic Gates
PTL gates could also be designed with logic in PD network PD network can contain a mixture of n-channel and p-channel devices Any of the PD networks used in complex logic gates could be used in PTL
Pass Transistor Logic Gates
As an example:
Pseudo NMOS Logic
May be viewed as a special case of PTL Ratioed Logic Static power dissipation not 0 (in PD state) Often used for really large number of inputs e.g. NOR Would be particularly useful for identifying one (or more) of many events that occur very infrequently
Pseudo NMOS Logic
DD
1
2
n
n could be several hundred or even several thousand
Dynamic Logic
PTL reduced complexity of either PUN or PDN to single "resistor" PTL relaxed requirement of all n-channel or all p-channel devices in PUN/PDN
What is the biggest contributor to area?
PUN (3X active area for inverter, more for NOR gates, and Well)
What is biggest contributor to dynamic power dissipation ? PUN and is responsible for approximately 75% of the dynamic power dissipation in inverter, more in NOR gates !
Can the PUN be eliminated W/O compromising signal levels and power dissipation?
Dynamic Logic
Can the PUN be eliminated W/O compromising signal levels and power dissipation?
Benefits could be most significant !
Dynamic Logic
Consider:
F=A
Precharges F to "1" when is low F either stays high if output is to be high or changes to low on evaluation
Dynamic Logic
Consider:
F=A
F=A B
F=A + B
Termed Dynamic Logic Gates Parasitic capacitors actually replace CD If Logic Block is n-channel, will have rail to rail swings Logic Block is simply a PDN that implements F
Dynamic Logic
Basic Dynamic Logic Gate
Any of the PDNs used in complex logic gates would work ! here Have eliminate the PUN ! Ideally will have a factor of 4 or more reduction in CIN Ideally will have a factor of 4 or more reduction in dynamic power dissipation relative to that of equal rise/fall ! Ideally will have a factor of 2 reduction in dynamic power dissipation relative to that of minimum size!
Dynamic Logic
F=A
Basic Dynamic Logic Gate What about the speed? Consider the inverter Recall
tREF =2RPDREFCREF
C CIN =COX WMINLMIN = REF 4 RPD =RPDREF
Assume is nominally a 50% duty cycle
TCLK C =RPDREF REF 2 4 C t TCLK =RPDREF REF = REF 2 4
Dynamic Logic
F=A
Basic Dynamic Logic Gate What about the speed?
C t TCLK =RPDREF REF = REF 2 4
tHL=tREF/4 tLH=0 Ideally, dynamic logic is 4 times as fast as equal rise/fall CMOS
Dynamic Logic
VDD
A
A
B
B
Y
A
B
A
B
Dynamic XOR Gate
From Wikipedia:
Dynamic logic (properly designed) is over twice as fast as normal logic. It uses only fast N transistors, and is amenable to transistor sizing optimizations. Static logic is slower because it has twice the loading, higher thresholds, and actually uses slow P transistors to compute things. Domino logic may be harder to work with, but if you need the speed, there is no other choice. Anything you buy that runs over 2GHz in 2007 uses dynamic logic. Another advantage is low power. A dynamic logic circuit running at 1/2 voltage will consume 1/4 the power of normal logic. Also each rail can convey an arbitrary number of bits, and there are no powerwasting glitches. Also power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.
Dynamic Logic
Basic Dynamic Logic Gate
Advantages: Lower dynamic power dissipation (Ideally 4X) Improved speed (ideally 4X) Limitations: Output only valid during evaluate state Need to route a clock (and this dissipates some power) Premature Discharge ! More complicated Charge storage on internal nodes of PDN No Static hold if output H
Dynamic Logic
Premature Discharge Problem If A is high, then F may go low at the start of the evaluate cycle and there is no way to recover a high output later in the evaluate phase - i.e. there may be a boolean error!. Can not reliably cascade dynamic logic gates !
Dynamic Logic
Premature Discharge Problem This problem occurs when any inputs to an arbitrary dynamic logic gate create an RPD path in the PDN during at the start of the evaluate phase that is not to pull down later in that evaluate phase How can this problem be fixed? Precharging to the low level all inputs to a PDN that may change to the high state later in the evaluate cycle (called domino) Alternating gates with n-channel and p-channel pull networks (Zipper Logic)
Dynamic Logic
Premature Discharge Problem Adding an inverter at the output will cause F to precharge low so it can serve as input to subsequent gate w/o causing premature discharge Implement F instead of F in the PDN Termed Domino Logic Some additional dynamic power dissipation in the inverter Some additional delay during the evaluate state in inverter
Domino Logic
Dynamic Logic
p-channel logic gate will pre-charge low Phasing of PUN and PDN networks is reversed Some performance loss with p-channel logic devices Direct coupling between alternate type dynamic gates is possible without causing a premature discharge problem
Dynamic Logic
D...