Instructor
Table Name: number: Solution
ECE 327: Electronic Devices and Circuits Laboratory I
Lab 6: Digital-to-Analog Conversion Quiz A (10 points)
Description. This quiz tests your understanding of digital-to-analog conversion (DAC) and demodulation of a pulse-width modulated (PWM) signal. Complete this quiz with closed book and closed notes.
Problem Q6-1: Obligatory DAC Question
The following questions refer to the 2-bit parallel-input current-summing DAC in Figure Q6-1.1. Answer the questions correctly to receive full credit for this problem. Assume that the OA is ideal with 20 V power supply rails. Ra iF 4 k
ia 1 V or 0 V
ib 1 V or 0 V
1 k
+
vout
0V Figure Q6-1.1: Current-summing DAC. Assume that each of 0 V, 4 V, 8 V, and 12 V is a possible output of this circuit that corresponds to one of its four possible input combinations. What must be the value of Ra ? (4 points)
Solution
The operational amplier is ideal and is connected with negative feedback. So: (i) There is no current owing into either inverting (i.e., ) or non-inverting (i.e., +) input, and so iF = ia + ib . (ii) There is no potential dierence between the two inputs, and so V = V+ = 0 V. Consequently, ia 0 A, 1 V Ra Hence, iF 0 A, 1 mA, 1 V , 1 mA + Ra Moreover, because vout = iF 4 k, vout 0 V, 4 V,
4 k Ra (1 V), 1V Ra V and ib 0 A, 11k = 1 mA .
.
4V+
4 k Ra (1 V)
.
So it must be that (4 k)/Ra 1 V = 8 V. That is, Ra = (4 k)/8 = 500 .
Copyright c 20072009 by Theodore P. Pavlic All rights reserved.
Page 1 of 3
ECE 327 [Lab 6: Digital-to-Analog Conversion Quiz A (10 points)]
Problem Q6-2: Sample-and-Hold Circuits (Ideal and Otherwise)
Consider the circuit in Figure Q6-2.2. The signal vC (t) represents the potential dierence across the capacitor at time t. Likewise, the signal vout (t) is the circuit output at time t. Assume that the switch has been closed for a VERY LONG TIME and is OPENED at the instant just before time t = 0.
t = 0 2.5 VDC + vC (t)
+
i
vout (t)
1 nF
1.25 k
0V
0V
Figure Q6-2.1: Op. amp. circuit. Switch OPENS at instant just BEFORE time t = 0. 1. Assuming that the OA is ideal and has 18 V power supply rails, what is vout (0)? That is, what is the value of the output at the instant AFTER the switch has OPENED? (2 points)
Solution
The OA is congured as a unity-gain zero-oset follower. Therefore, vout (0) = vC (0) = 2.5 V.
2. Assume that the OA is ideal. What is the current i through the 1.25 k resistor at time t = 2 s? (2 points)
Solution
An ideal OA has zero leakage current, and so no current will go into the OA, and so vC will hold a constant voltage indenitely. Because the OA is a follower, vout will also hold this constant voltage. Therefore, vout (t) = 2.5 V for all time t, and i = (2.5 V)/(1.25 k) = 2 mA. Imagine if the operational amplier was removed and the 1 nF capacitor was connected directly to the 1.25 k load. The current sourced to the resistor would cause the voltage across the capacitor to sharply drop. In fact, without the follower attached, the current i 0 just a few microseconds after the switch opens. Hence, this circuit can sample an input onto the capacitor (i.e., by opening and closing the switch) and then hold the sample while still allowing it to be used (i.e., by using the operational amplier).
3. The CA3160 internally connects each of its two inputs to the gate of a MOSFET. With this in mind, why is the CA3160 an excellent choice for use in a sample-and-hold circuit like this one? (2 points)
Solution
In its active mode, a bipolar transistor draws a fraction of its collector current (e.g., 0.01) from its base. As a consequence, the LM741 will readily pull current away from its inputs. In a sample-and-hold circuit, this biasing current will cause the sampling capacitor to drain through operational the amplier over time. In the case of an LM741, the typical input current is 80 nA. Assuming that this 80 nA can be modeled as a constant current source pointing into the operational amplier, the voltage vC will decay linearly at an 80 nA/1 nF = 80 V/s rate. Hence, the 1 nF capacitor will discharge quickly.
Copyright c 20072009 by Theodore P. Pavlic All rights reserved.
Page 2 of 3
Name: Instructor
ECE 327 [Lab 6: Digital-to-Analog Conversion Quiz A (10 points)]
Problem Q6-2 (continued)
One solution to this problem is to use a very large capacitor to reduce the decay rate. However, because the switches we use have some nite impedance (e.g., 20120 ), a large capacitor may not charge instantaneously when the switch closes (i.e., the switchcapacitor combination will act like an RC low-pass lter with a step input). Hence, a large capacitor may require a very slow sampling rate. A better solution is to use a CA3160 operational amplier. This amplier ties each of its inputs to the gate of a MOSFET. Field-eect transistors (FETs) do not require input current for operation; however, they do suer from leakage. Fortunately, typical MOSFET leakage is 5 pA, which would cause a 1 nF capacitor to decay at a 1 mV/s rate. In this laboratory, we will be sampling the signal at 30, 000 S/s, and so the decay due to input leakage will be negligible. Note that the 10 oscilloscope probe looks like 10 M to our circuit at DC and much less at high frequencies. Hence, the oscilloscope probe itself will cause a noticeable decay when connected directly to the sampling capacitor. Active oscilloscope probes use their own buers internally to greatly increase their input impedance.
4. There is a digital circuit known as a gated latch. It has inputs D and E. When digital input E is assserted (i.e., true), the output Q tracks all changes in input D (i.e., the device is transparent). However, when digital input E is not asserted, the output Q holds whatever value it was at the time when E was previously asserted, and the D input is ignored (i.e., the device is opaque or nontransparent). The ideal implementation of a positive-edge-triggered D ipop uses a transparent-low latch (i.e., transparent when E is low) followed by a transparent-high latch (i.e., transp...