5473: 3/3/2010
EL Introduction to CMOS VLSI Design VLSI Design Midterm Review
Hai (Helen) Li Spring 2010
Slides adapted from Harris' slides from Harvey Mudd. Copyright 2005 Addison-Wesley and Rabaey's Digital Integrated Circuits, Copyright 2002, J. Rabaey et al.]
MOORE'S LAW IN MICROPROCESSOR
1000 100 10 1 0.1 0.01 386 286 8086 8085 8080 8008 4004 1980 1990 2000 2010
2X growth in 1.96 years!
P6 Pentium proc 486
Transistors (MT T)
0.001 1970
Year
Transistors on lead microprocessors double every 2 years
Hai (Helen) Li, March 3, 2010 2
1
3/3/2010
THE IDEAL DIODE
The ideal diode equation (for both forward and reverse / bias conditions) is ID = IS(e VD/ T 1) I +
VD a forwardbias lowers the potential barrier allowing carriers to flow across the 2.5 diode junction a reversebias raises the 1.5 potential barrier and the diode becomes nonconducting 0.5
-0.5 T = kT/q = 26mV at 300K -1 -0.75 IS is the saturation current of the diode
Hai (Helen) Li, March 3, 2010
-0.5 -0.25
0
0.25 0.5 0.75
1
3
SWITCH MODEL OF NMOS
| VGS |
Gate
Source (of carriers)
Drain (of carriers)
Open (off) (Gate = `0')
Closed (on) (Gate = `1')
Ron
| VGS | < | VT |
| VGS | > | VT |
Hai (Helen) Li, March 3, 2010
4
2
3/3/2010
CMOS PROCESS AT A GLANCE
Define active areas Etch and fill trenches
One full photolithography sequence per layer (mask) Built (roughly) from the bottom up
5 4 2 3 1 metal 2 metal 1 polysilicon exception! ti ! source and drain diffusions tubs (aka wells, active areas)
Implant well regions
Deposit and pattern polysilicon layer
Implant source and drain regions and substrate contacts
Create contact and via windows Deposit and pattern metal layers
Hai (Helen) Li, March 3, 2010
5
LAYOUT VS. CROSS SECTION
cut line
n well
Hai (Helen) Li, March 3, 2010
6
3
3/3/2010
WELL AND SUBSTRATE TAPS
Substrate must be tied to GND and nwell to VDD Metal to lightlydoped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps
A GND Y VDD
p+
n+
n+ p substrate
p+ n well
p+
n+
substrate tap
well tap
Hai (Helen) Li, March 3, 2010
7
NMOS IV SUMMARY
Shockley 1st order transistor models
0 V I ds Vgs Vt ds 2 2 Vgs Vt 2
Vgs Vt V V V ds ds dsat Vds Vdsat
cutoff linear saturation
Hai (Helen) Li, March 3, 2010
8
4
3/3/2010
LONGCHANNEL IV PLOT (NMOS)
6 5 4
X 10-4
VDS = VGS - VT
VGS = 2.5V
VGS = 2.0V
3
Linear
2 1 0
Saturation VGS = 1.5V VGS = 1 0V 1.0V
cut-off
0
0.5
1
1.5
2
2.5
VDS (V)
Hai (Helen) Li, March 3, 2010 9
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
DC VOLTAGE TRANSFER CURVE (VTC)
NMOS off PMOS lin
2.5
NMOS sat PMOS lin
Transcribe points onto Vin vs. Vout plot
2
Vout (V)
1.5
NMOS sat PMOS sat
1
VM
NMOS lin NMOS lin PMOS sat PMOS 0 off
0.5
0 0.5 1 1.5 2 2.5
Vin (V)
Hai (Helen) Li, March 3, 2010 10
5
3/3/2010
NOISE MARGINS
How much noise can a gate input see before it does not recognize the input?
Output Characteristics Logical High Output Range
VDD
Input Characteristics Logical High Input Range Indeterminate Region Logical Low Input Range
VOH NMH VIH VIL NML VOL GND
Logical Low Output Range
Hai (Helen) Li, March 3, 2010
11
OAI22 LAYOUT
A VDD B D C
X
GND
Hai (Helen) Li, March 3, 2010
12
6
3/3/2010
RC DELAY MODEL
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width Resistance inversely proportional to width
d R/k g kC s kC kC d k s kC g kC d
Hai (Helen) Li, March 3, 2010 13
s
kC 2R/k
g
d k s
g
ELMORE DELAY
ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t pd Ri to sourceCi
R1C1 R1 R2 C2 ... R1 R2 ... RN C N
R1 R2 C1 R3 C2 C3 RN CN
nodes i
Hai (Helen) Li, March 3, 2010
14
7
3/3/2010
THRESHOLD DROPS
PUN VDD
S
VDD
D
VDD
D
0 VDD CL
VGS
S
0 VDD - VTn CL VDD |VTp|
PDN
D
VDD 0 VDD
S
VGS
CL
S
CL
D
Hai (Helen) Li, March 3, 2010
15
LUMPED ELEMENT MODELS
Wires are a distributed system
Approximate with lumped element models
N segments R C R C L-model L d l R/N C/N R C/2 C/2 R/N C/N R/N C/N R/2 R/2 C T-model T d l R/N C/N
-model d l
3segment model is accurate to 3% in simulation Lmodel needs 100 segments for same accuracy! Use single segment model for Elmore delay
Hai (Helen) Li, March 3, 2010 16
8
3/3/2010
CROSSTALK NOISE
Crosstalk causes noise on nonswitching wires If victim is floating:
model as capacitive voltage divider
Vvictim
Cadj Cgnd v Cadj
Aggressor
Vaggressor
Vaggressor Victim
Cadj Cgnd-v Vvictim
Hai (Helen) Li, March 3, 2010
17
DELAY IN LOGIC GATE
Express delays in processindependent unit d abs Delay has two components 3RC 3RC
d
d=f+p
Effort delay f = gh (a.k.a. stage effort) f
12 ps in 180nm 40 ps in 0.6m
g: logical effort relative ability of gate to deliver current g 1 for inverter h: electrical effort fanout
h = Cout / Cin
Parasitic delay p delay of gate driving no load p
Set by internal parasitic capacitance
Hai (Helen) Li, March 3, 2010 18
9
3/3/2010
REVIEW OF DEFINITIONS
Term number of stages logical effort electrical effort branching effort effort effort delay y Stage Path
1
g h b
Cout Cin
Con-path Coff-path Con-path
N
G gi H
Cout-path Cin-path
B bi F GBH DF f i
f gh f p d f p
parasitic delay delay
P pi
D d i DF P
Hai (Helen) Li, March 3, 2010
19
METHOD OF LOGIC EFFORT
Compute path effort Estimate best number of stages Sketch path with N stages Estimate least delay Determine best stage effort g Find gate sizes
F GBH N log 4 F
D NF N P
1 ^ f FN gi Couti Cini ^ f
1
Hai (Helen) Li, March 3, 2010
20
10