Dig log chapter 7
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Dig log chapter 7

Course Number: EE 2730, Spring 2009

College/University: Lakeland Community College

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Classification of Digital Circuits Combinational. Output depends only on current input values. Sequential. Output depends on current input values and present state of the circuit, where the present state of the circuit is the current value of the devices memory. Also called finite state machines. State of a Circuit The contents of storage elements. A collection of know internal signal values that contain...

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of Classification Digital Circuits Combinational. Output depends only on current input values. Sequential. Output depends on current input values and present state of the circuit, where the present state of the circuit is the current value of the devices memory. Also called finite state machines. State of a Circuit The contents of storage elements. A collection of know internal signal values that contain information about the past necessary to account the future behavior of the circuit. Bi-stable Element (Simple Memory) The simplest sequential circuit. It consist of a pair of inverters connected as shown below. Notice the feedback loop. A B Digital Analysis Two stable states. If A is HIGH then the lower inverter has a HIGH at its input and a LOW at its output. This in turn forces the upper inverters input to be LOW and its output to be HIGH. If A is LOW then the lower inverter has a LOW at its input and a HIGH at its output. This in turn forces the upper inverters input to be HIGH and its output to be LOW. Analog Analysis Considering the steady state behavior of the bistable element. Vin1 Vin1 Vin1 Vin1 = = = = Vout2 T(Vin2) T(Vout1) T(T(Vin1)) Vout1 = Vin2 metastable Transfer function: Vout1 = T(Vin1) Vout2 = T(Vin2) stable Vin1 = Vout2 stable Vin1 Vout1 Q Vin2 Vout2 Q_L Copyright 2000 by Prentice Hall, Inc. Analog Analysis Metastable behavior: Consider the middle intersecting point in the diagram shown below. What would happen if a small amount of noise varies either input voltage. Vout1 = Vin2 metastable stable stable Vin1 = Vout2 Analog Analysis The drawing on this slide shows a very good analogy to the stable and metastable behavior of a bistable element. metastable stable stable Clock Signal that determines the change of state in most sequential circuits. (a) CLK tH tper tL period = tper frequency = 1 / tper duty cycle = tH / tper state changes occur here (b) CLK_L state changes occur here tL tper tH duty cycle = tL / tper Latches and Flip-Flops Binary cells capable of storing 1 bit of information. Generates one of two possible stable states. Two outputs labeled Q and Q. One or more inputs. Latches and Flip-Flops These sequential devices differ in the way their outputs are changed: The output of a latch changes independent of a clocking signal. The output of a flipflop changes at specific times determined by a clocking signal. Basic Latch Set Memory element On Off Alarm Sensor Reset Reset Set Q S-R Latch R Qa S 0 0 1 1 R 0 1 0 1 Qa Qb 0/1 0 1 0 1/0 (no change) 1 0 0 Qb (a) Circuit t1 1 R 0 1 S 0 1 ? 0 1 ? 0 Time (c) Timing diagram t2 t3 t4 t5 t6 S (b) Truth table t7 t8 t9 t 10 Qa Qb S-R Latch R Q S 0 0 1 1 (b) R 0 1 0 1 Q QN last Q last QN 0 1 0 1 0 0 (a) S QN SR latch based on NOR gates. The S input sets the Q output to 1 while R reset it to 0. When R=S=0 then the output keeps the previous value. When R=S=1 then Q=Q=0, and the latch may go to an unpredictable next state. S-R Latch S (1) R (2) Q tpLH(SQ) tpHL(RQ) tpw(min) S-R Latch S R Q QN S R Q Q S R Q QN (a) (b) (c) Double negation is not a good idea. It is confusing and it creates problems. S-R Latch (a) S_L or S Q (b) S_L R_L 0 0 1 1 0 1 0 1 Q 1 QN 1 (c) S R Q Q R_L or R QN 1 0 0 1 last Q last QN SR latch based on NAND gates. The S input sets the Q output to 1 while R reset it to 0. When R=S=1 then the output keeps the previous value. When R=S=0 then Q=Q=1, and the latch may go to an unpredictable next state. Gated S-R Latch Gated S-R Latch With NAND Gates The outputs change only when the enable input C is asserted. (a) S Q C QN R 001 011 101 111 x x0 last Q last QN 0 1 0 1 1 1 last Q last QN (b) SRC Q QN (c) S C R Q Q Ignored since C is 0. S R C Q QN Ignored until C is 1. Gated D Latch This latch eliminates the problem that occurs in the SR latch when R=S=1 and in the SR latch when R=S=0. Clk is an enable input. D Latch D C (1) Q (2) (3) (4) (5) tpHL(DQ) tpLH(CQ) tpHL(CQ) tpLH(DQ) tpLH(DQ) thold tsetup For proper operation the D input must not change during a time interval around the falling edge of C. This time interval is defined by the setup time tsetup and the hold time thold . Master-Slave D Flip-Flop This flip-flop is made out of two D latches. The first latch is the master, and the second the slave. Master-Slave D Flip-Flop When CLK_L = 1 the master is on and the slave is off. Qm and (a) Ds follow Dm . D When CLK_L = 0 the master is closed, the slave is open and Qm is transferred to Qs . Note that Qs does not change if Dm changes because the master latch is closed leaving Qm fixed. CLK Positive edge-triggered D flipflop. Q* = D D CLK QM Q QN ( D C Q QM D C Q Q Q QN Master-Slave D Flip-Flop D CLK Q thold tpLH(CQ) tpHL(CQ) tsetup If the set-up and hold times are not met the flip-flops output will go to a stable, though unpredictable, state. Preset and Clear (b) PR_L D (a) PR D Q CLK Q CLR Q QN CLK CLR_L Asynchronous inputs are used to force the output of the flip-flop to a particular state. PR (preset) Q = 1. CLR (clear) Q = 0. Edge Triggered D Flip-Flop (b) PR_L D (a) PR D Q CLK Q CLR Q QN CLK CLR_L PR_L CLR_L Q CLK QN D Edge Triggered D Flip-Flop Edge triggered D flip-flop with enable. (a) D EN D CLK Q Q (b) D EN CLK 0 Q QN 1 x x x 1 1 0 x x 0 1 Q 0 1 QN 1 0 (c) D EN CLK Q Q last Q last QN last Q last QN last Q last QN CLK T Flip-Flop T Flip-Flop Flip-flop changes state every tick of the clock. Q* = Q (a) D Q Q (b) Q T T CLK 1 J CLK K Q Q Q QN QN Q T Q T Q (b) (a) T Flip-Flop With Enable Flip-flop changes state every tick of the clock when enable is asserted. Q* = ENQ+ENQ Scan Flip-Flop This flip-flop allows its inputs to be driven from alternate sources, which can be very useful during device testing. D TE D Q Q TE TI 0 Q QN 0 1 1 x (b) x x x 0 1 x x D CLK 0 1 x x x x 0 1 Q 0 1 0 1 QN 1 0 1 0 D Q TE TI Q CLK TI CLK (a) CLK last Q last QN last Q last QN (c) ASIC external pins D Q TE TE TI Q CLK CLK Q CLK D Q TE TI Q CLK D Q TE TI Q D Q TI TI TO CLK TE Master/Slave S-R Flip-Flop The postponed output indicator shows that the output signal does not change until the enable C input is negated. Flip-flops with this kind of behavior are called pulse-triggered flip-flops. Q* = S+RQ SR = 0 (a) S R C S C R Q Q (b) S QM QM_L S C R Q Q (c) R x 0 1 0 1 C 0 Q QN S C R Q Q Q QN x 0 0 1 1 last Q last QN last Q last QN 0 1 1 0 undef. undef. Master/Slave S-R Flip-Flop Ignored since C is 0. S R C QM QM_L Q QN Ignored until C is 1. Ignored until C is 1. Master/Slave J-K Flip-Flop The J and the K inputs of the J-K flipflop are analogous to the S and R inputs of the S-R flip-flop, except in the case where J=K=1. In this case the outputs of the J-K flip-flop will toggle to the opposite state. (a) (b) J J K C S C R Q Q (c) K x 0 1 0 1 C 0 Q QN J C K Q Q QM QM_L S C R Q Q Q QN x 0 0 1 1 last Q last QN last Q last QN 0 1 1 0 last QN last Q Master/Slave J-K Flip-Flop Q* = JQ+KQ (a) (b) J J K C S C R Q Q (c) K x 0 1 0 1 C 0 Q QN J C K Q Q QM QM_L S C R Q Q Q QN x 0 0 1 1 last Q last QN last Q last QN 0 1 1 0 last QN last Q Ignored since C is 0. J K C QM QM_L Q QN Ignored since QN is 0. Ignored since C is now 0. Ignored since Q is 0. Ignored since QN is 0. Edge Triggered J-K Flip-Flop Q* = JQ+KQ (a) (b) J J D Q Q (c) K x x 0 1 0 1 CLK 0 1 Q QN J CLK K Q Q x Q QN x 0 0 last Q last QN last Q last QN last Q last QN 0 1 1 0 K CLK CLK 1 1 last QN last Q J K CLK Q Edge Triggered J-K Flip-Flop 74LS109 PR_L CLR_L Q CLK QN J K_L Registers Collection of two or more D flip-flops with a common clock input. Often used to store a collection of related bits, such as a byte of data. May also be used to store unrelated bits of data. 74x175 shown in figure (a) 1D (4) D CLK CLR Q (3) Q (2) 1Q 1Q_L (a) 2D (5) D CLK CLR Q Q (7) (6) 2Q 2Q_L 3D (12) D CLK CLR Q Q (10) (11) 3Q 3Q_L 4D CLK CLR_L (13) D (9) CLK CLR (1) Q Q (15) (14) 4Q 4Q_L Registers OE_L (a) 1D (1) (3) D (2) CLK Q 1Q 2D (4) D (5) CLK Q 2Q 3D (7) D (6) CLK Q 3Q 4D (b) 74x374 11 1 3 4 (8) D (9) CLK Q 4Q CLK OE 1D 1Q 2 5 5D (13) D (12) CLK Q 5Q 2D 7 3D 8 4D 13 14 17 18 2Q 6 3Q 9 4Q 5Q 15 6Q 7Q 8Q 16 19 12 6D (14) D (15) CLK Q 6Q 5D 6D 7D 8D 7D (17) D (16) CLK Q 7Q 8D CLK (18) D CLK (19) Q (11) 8Q Registers (a) 74x377 11 1 3 4 7 8 13 14 17 18 (b) CLK EN 1D 2D 3D 4D 5D 6D 7D 8D 1Q 5 2Q 3Q 4Q 6 9 12 2 D Q CK (19) 8Q 8D (18) 5Q 15 6Q 7Q 8Q 16 19 EN_L (1) CLK (11) Shift Register In Clock D Q Q Q1 D Q Q Q2 D Q Q Q3 D Q Q Q4 Out (a) Circuit t0 t1 t2 t3 t4 t5 t6 t7 In 1 0 1 1 1 0 0 0 Q1 0 1 0 1 1 1 0 0 Q2 0 0 1 0 1 1 1 0 Q3 0 0 0 1 0 1 1 1 Q4 = Out 0 0 0 0 1 0 1 1 (b) A sample sequence Figure 7.18. A simple shift register. Shift Registers N-bit register with the provision for shifting its stored data by a bit position each tick of the clock. Serial input specifies a new bit to shifted into the register. Serial output specifies the bits being shifted out of the register SERIN CLOCK D CK Q D CK Q D CK Q SEROUT Copyright 2000 by Prentice Hall, Inc. Digital Principles Design and Practices, 3/e Shift Registers CLOCK LOAD/SHIFT SERIN D Q CK 1Q 1D D Q CK 2Q 2D D Q CK NQ ND Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Parallel input specifies a new set of bits to be entered into the register, all at once during a single clock tick. Parallel output specifies the bits at the output of every flip-flop in the register. Shift Registers Serial-in, parallelout shift register. SERIN CLOCK D CK Q 1Q D CK Q 2Q D CK Q NQ Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Shift Registers Parallel-in, serialout shift register. CLOCK LOAD/SHIFT SERIN D Q CK 1D D Q CK 2D D Q CK SEROUT ND Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Shift Register Parallel output Q3 D Q Q D Q2 Q Q D Q1 Q Q D Q0 Q Q Serial input Shift/Load Parallel input Clock Figure 7.19. Parallel-access shift register. Shift Registers MSI Shift Registers. 74x164 serial-in, parallel-out with asynchronous clear input. 74x166 parallel-in, serial-out with asynchronous clear input. 74x194 universal shift register. Inputs Next state QA QB QC QD al Function S1 S0 Hold Shift right Shift left Load 0 0 1 1 0 1 0 1 QA RIN QB A QB QA QC B QC QB QD C QD QC LIN D Shift Registers CLK (11) CLR_L (1) LIN (7) 10 S1 S0 00 (12) D 11 CLK CLR Q D (6) QD 01 RIGHT 10 00 (13) D 11 CLK CLR Q C (5) QC 01 10 00 (14) D 11 CLK CLR Q B (4) QB S1 (10) 01 LEFT S0 (9) 10 00 (15) D 11 CLK CLR Q A (3) QA RIN (2) 01 Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e Counters S1 S2 S3 Sm S4 S5 Clocked sequential circuit whose state diagram contains a single cycle. Modulus number of states in the cycle. Counters with nonpower of 2 modulus has unused states Asynchronous Counters Ripple counter. Requires fewer components than other counters. Slowest one. Q Q0 CLK T Q Q T Q Q1 Q T Q Q2 Q T Q Q3 Up-Counter 1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2 (a) Circuit Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 6 7 0 (b) Timing diagram Figure 7.20. A three-bit up-counter. Down-Counter 1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2 (a) Circuit Clock Q0 Q1 Q2 Count 0 7 6 5 4 3 2 1 0 (b) Timing diagram Figure 7.21. A three-bit down-counter. Synchronous Counter Synchronous counters. The clock inputs of all flip-flops in the counter circuit are connected to a common clock signal. Synchronous Counter Clock cycle 0 1 2 3 4 5 6 7 8 Q2 Q1 Q0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Q1 changes Q2 changes Table 7.1. Derivation of the synchronous up-counter. Synchronous Serial Counter 1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2 T Q Q Q3 (a) Circuit Clock Q0 Q1 Q2 Q3 Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 (b) Timing diagram Figure 7.22. A four-bit synchronous up-counter. Synchronous Serial Counter CNTEN CLK EN T Q Q0 EN T Q Q1 EN T Q Q2 EN T Q Q3 Synchronous Serial Counter Enable Clock T Q Q T Q Q T Q Q T Q Q Clear Figure 7.23. Inclusion of Enable and Clear capability. Synchronous Parallel Counter Synchronous parallel counter. CNTEN CLK EN T Q Q0 EN T Q Q1 EN T Q Q2 EN T Q Q3 Synchronous Counter With Parallel Load capability MSI Counter 74x163 MSI Counter 74x163 CLK LD_L (2) (9) CLR_L A (1) (3) (14) D CK Q Q QA B (4) (13) D CK Q Q QB C (5) (12) D CK Q Q QC D (6) (11) D CK Q Q QD (15) RCO ENP ENT (7) (10) 74x163 Free Running Mode 74x163 CLOCK 1 9 2 CLK CLR +5 V R 7 RPU LD ENP 10 ENT 3 4 5 A B C 6 D QA QB QC QD RCO 14 13 12 11 15 QA QB QC QD RCO U1 CLK QA QB QC QD RCO COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Modulo 11 Counter 74x163 CLOCK 1 2 CLK CLR LD ENP ENT A QA 13 QB QC 11 QD RCO U1 12 14 RPU 9 +5 V R 7 10 3 4 5 Q0 Q1 Q2 Q3 74x00 1 2 3 B C 6 D 15 CNT10_L U2 Modulo 11 Counter 74x163 CLOCK RPU 1 9 7 2 CLK CLR +5 V LD ENP 10 ENT 3 A 4 5 QA 14 13 Q0 Q1 Q2 Q3 74x04 CNT15 CNT15_L 1 2 R B C 6 D QB 12 QC 11 QD RCO U1 15 U2 BCD Counter 1 0 0 0 0 Enable D0 D1 D2 D3 Load Clock Clock Clear 0 0 0 0 Enable D0 D1 D2 D3 Load Clock Q0 Q1 Q2 Q3 BCD 0 Q0 Q1 Q2 Q3 BCD 1 Figure 7.28. A two-digit BCD counter. 74x163 Excess-3 Counter 74x163 CLOCK 1 9 7 10 2 CLK CLR LD ENP ENT A B C D +5 V R 3 RPU 4 5 6 QA 13 QB 12 QC 11 QD RCO U1 15 1 2 14 Q0 Q1 Q2 Q3 74x00 3 S11XX_L U2 Reset Synchronization 1 0 0 0 Enable D0 D1 D2 Load Clock Q0 Q1 Q2 Clock (a) Circuit Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1 (b) Timing diagram Figure 7.26. A modulo-6 counter with synchronous reset. Reset Synchronization 1 Clock T Q Q Q0 T Q Q Q1 T Q Q Q2 (a) Circuit Clock Q0 Q1 Q2 Count 0 1 2 3 4 5 0 1 2 (b) Timing diagram Figure 7.27. A modulo-6 counter with asynchronous reset. 74x163 Cascading Counters 74x163 CLOCK RESET_L LOAD_L CNTEN D0 D1 D2 D3 2 1 9 7 74x163 2 1 9 7 10 CLK CLR LD CLK CLR LD ENP ENT QA QB 14 13 12 ENP 10 ENT 3 A 4 B 5 QA QB 14 13 12 Q0 Q1 Q2 Q3 RCO4 D4 D5 D6 D7 3 A 4 B 5 Q4 Q5 Q6 Q7 RCO8 C 6 D QC 11 QD RCO U1 15 C 6 D QC 11 QD 15 RCO U2 74x163 Modulo 193 Counter +5 V 1 74x163 2 CLK CLR LD ENP ENT A B C D R RPU 9 7 10 3 4 5 6 CLOCK RESET_L 74x00 GO_L 1 2 3 QA QB QC QD RCO U2 14 13 12 11 15 Q0 Q1 Q2 Q3 RCO4 CNTEN 2 74x163 CLK CLR LD ENP ENT A B C D 1 6 U1 74x00 4 5 RELOAD_L 9 7 U1 10 3 4 5 6 QA QB QC QD RCO U3 14 13 12 11 15 Q4 Q5 Q6 Q7 MAXCNT 74x163 Modulo 8 Counter With Decoder RPU 74x163 CLOCK 1 9 7 10 3 4 5 6 2 +5 V R 6 4 5 74x138 G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7 CLK CLR LD ENP ENT A B C D QA QB QC QD RCO 14 13 12 11 15 Q1 Q2 Q3 1 A 2 B 3 C S0_L S1_L S2_L S3_L S4_L S5_L S6_L S7_L U2 U1 CLOCK_L S0_L S1_L S2_L S3_L S4_L S5_L S6_L S7_L COUNT 0 1 2 3 4 5 6 7 0 1 2 74x163 Modulo 8 Counter With Decoder Modulo 8 counter with decoder and glitch-free outputs. RPU 74x163 CLOCK 1 9 7 10 3 4 5 6 2 +5 V 11 74x374 1 15 14 13 12 11 10 9 7 R 6 4 5 74x138 G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 S0_L S1_L S2_L S3_L S4_L S5_L S6_L S7_L CLK OE 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2 5 6 9 12 15 16 19 CLK CLR LD ENP ENT A B C D 3 4 7 8 13 14 17 18 QA QB QC QD RCO 14 13 12 11 15 Q1 Q2 Q3 1 A 2 B 3 C RS1_L RS2_L RS3_L RS4_L RS5_L RS6_L RS7_L RS0_L U2 U1 U3 Copyright 2000 by Prentice Hall, Inc. Shift Registers Counters Shift register counter a circuit formed by a shift registers and combinational logic. The state diagram for this state machine is cyclic. This circuit does not necessarily count in ascending or descending order. Ring Counter the simplest shift register counter. This circuit uses a nbit shift register to obtain a counter with n states. Shift Registers +5 V R CLOCK 11 1 10 74x194 CLK CLR RESET (load) S1 9 S0 7 wired as a shift-left shift register CLOCK RESET Q0 LIN D 5 C 6 4 3 2 B A RIN QD 13 QC 14 QB 15 QA 12 Q0 Q1 Q2 Q3 Q1 Q2 Q3 STATE S1 S2 S3 S4 S1 S2 Copyright 2000 by Prentice Hall, Inc. U1 Shift Registers 0001 0000 0010 0101 0011 0100 0110 1001 1110 1011 1000 0111 1010 Copyright 2000 by Prentice Hall, Inc. 1100 1111 1101 Self Correcting Counter A self correcting counter is designed so that all abnormal states have transitions leading to normal states. 0001 0000 +5 V R CLOCK 11 1 10 74x194 CLK CLR S1 9 S0 7 wired as a shift-left shift register LIN D 5 C 4 B 6 3 2 QD 13 QC 14 QB QA 15 1 2 12 A RIN Q0 Q1 Q2 Q3 74x27 12 0010 1000 U1 1001 0100 1100 13 ABC0 1110 U2 1010 0110 0101 1101 0011 1011 0111 1111 Johnson Counter Twisted-ring, Moebius or Johnson counter is a n-bit shift register whose serial input receives the complement of serial output. This counter has 2n states. CLOCK RESET_L Q0 Q1 Q2 Q3 STATE S1 S2 S3 S4 S5 S6 S7 S8 S1 S2 S3 +5 V R CLOCK RESET_L 11 74x194 CLK CLR 10 S1 9 S0 1 7 6 5 wired as a shift-left shift register LIN D QD QC QB QA 12 13 14 15 C 4 B 3 2 Q0 Q1 Q2 Q3 74x04 1 2 A RIN U1 U2 Q3_L Gated D Latch module D_latch (D, Clk, Q); input D, Clk; output reg Q; always @(D, Clk) if (Clk) Q = D; endmodule D Flip-flop module flipflop (D, Clock, Q); input D, Clock; output reg Q; always @(posedge Clock) Q = D; endmodule Posedge, Negedge Verilog keywords that allow for the specification of which edge are used to clock the flip-flop. Blocking and Non-blocking Assignments Blocking: Verilog compilers evaluate the statements in an always block in the order they are written. The value given a variable by an assignment is used in evaluating the next statement, for example: C = A + B; D = C + A; Non-blocking: Denoted with <=; Statements are evaluated using the values that the variable had when it entered the always block. C = A + B; D <= C + A; Incorrect Version of Cascading Two Flip-flops module example7_3 (D, Clock, Q1, Q2); input D, Clock; output reg Q1, Q2; always @(posedge Clock) begin Q1 = D; Q2 = Q1; end endmodule D Clock D Q Q Q1 D Q Q Q2 Cascading Flip-flops module example7_4 (D, Clock, Q1, Q2); input D, Clock; output reg Q1, Q2; always @(posedge Clock) begin Q1 <= D; Q2 <= Q1; end endmodule D Clock D Q Q Q1 D Q Q Q2

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SOCIAL PSYCHOLOGY, PRACTICE MIDTERM 2This practice exam covers the following topics: Prejudice; Social Facilitation &amp; Group Influences; Conformity, Compliance, and Obedience; Attraction and Relationships; and Aggression. The actual midterm will only cove
San Diego State - PSY - 340
Social Psychology Socialby David G. Myers, 6/eChapter Ten Aggression: Hurting OthersWhat is aggression? Hostile aggression Instrumental aggressionCopyright 2002 by The McGraw-Hill Companies, Inc.2 of 8Theories of aggression Is aggression inborn?
San Diego State - PSY - 340
Social Psychology SocialAltruism: Helping Others (Chapter Twelve in Myers)Why do we help? Social exchange Helping as disguised self-interest Empathy as a source of genuine altruism Social Norms The reciprocity norm The social-responsibility norm2 o
San Diego State - PSY - 340
Social Psychology SocialLegal Psychology (Module B in Myers)Is Justice Blind? Pride of U.S. legal system: Justice for all. - objective set of laws &amp; rules, w/o bias. Major Sources of Bias: The Players Eyewitnesses, Attorneys, Judges, Defendants, Juror
San Diego State - PSY - 340
Social PsychologyDeviant Behavior1Introduction Introduction DefiningDeviance Social Psychology &amp; Deviant Behavior, 2 Reasons to Study it: Social Norms, Social Order Reducing, Eliminating2Four Basic Questions: Causes:Four Theories to be Discussed
San Diego State - PSY - 340
SOCIAL PSYCHOLOGY STUDY GUIDE FINAL EXAM, DR. ASHLYN Note: Although most of the following concepts are either in class lecture outlines or in your text, a few may have only be discussed in lecture and may not be in the outlines or your text. If you missed
UCLA - ENVIRON - M155
Coda automotive: 10am Monday Dec 7th Big names vouching for quality of product o Signaling to investors Company hopes to sell 10,000 units for $45k o $45,000 + 10,000 miles * X Kwh/miles * PKwh o PDV calculation against Camry at $28,000 $28,000 + Pgas*400
UCLA - ENVIRON - M155
Physics M155 November 10, 2009 Mobile device charging station Zenware Electric Utilities: Regional Science and Urban Economics SO2 Emissions Coal fired power plants E-Grid database 5000 power plants o Microdata Age Input Capacity Pollution Coal power pl
UCLA - ENVIRON - M155
When information is the missing link, nerds can change the world. Kahn Final Exam: Review 10 topics what are the Big Ideas from each topic. Re-read pages he assigns NYT: Homeowners purchase green certificates to draw energy from wind, offset CO2 If only 2
UCLA - A&O SCI - 145
dlnSdDp=0 In order to rest assured that activation will occur, Sc &lt; SenvIf incomplete dissociation, Sc increases because not all of the ions are acting as solutes. Lazy Larger fraction of insolubles, reduces effective diameter, reduces Sc (supersaturatio
UCLA - A&O SCI - 145
Brownian D decreases. rrection which increases asmotion: random movement of particles in air p Difficulties in accurately modeling the billions of individual molecules results in using diffusion to describe the macroscopic scale movements Mean velocity of
UCLA - A&O SCI - 145
NgvJan 19 A&amp;O Sciradius Rp containing n water molecules (via random collision) in the box homogeneous nucleation.Ideal Gas Law pV=nRT p[Pa] V[m3] n[moles] R=8.314Jmol K T[K]Clausius-Clapeyron Equation relationship between water vapor pressure and temp
UCLA - A&O SCI - 145
Jan 26 Growth velocity of droplets Use the Khler equation to find a psat for the edge of the particle, plug pressure into ideal gas law to obtain concentration cs Then use cr=c-Rpr(c-cs) with cequal to ambient concentration to find concentration at surfac
UCLA - ENVIRON - M161
I.IDs 1) The Malthusian argument of population and scarcity chiefly implies an obligate limit to human consumption. The human population grows exponentially, requiring similar exponential growths in resources and space to satisfy the consumption habits o
SUNY Buffalo - MFC - 141
AntioxidantAntioxidantsBackground Oxidation of biomolecules is the basis of many diseases; such as cancer, heart disease, cataracts, inflammatory joint disease. The process of oxidation involves the production of free radicals and reactive oxygen speci
SUNY Buffalo - MFC - 141
Bitter OrangeBitter OrangeBackgroundBitter Orange is an herbal product which comes the Bitter Orange tree (Citrus aurantium, Seville Orange ). It is found naturally in tropical Asia , but is cultivated in Africa, Arabia, Syria, Spain, Italy, and North
SUNY Buffalo - MFC - 141
Calcium &amp; OsteoporosisBackground Osteoporosis, which means porous bones, is a reduction in bone density, which increases the risk for fractures resulting in mild or moderate trauma. For example, a fall that would not cause a fracture in healthy bone may
SUNY Buffalo - MFC - 141
ChromiumChromiumBackground Chromium is an essential nutrient, that has become a popular weight loss supplement. It is said to reduce fat and increase lean body mass. When used as a supplement, chromium is combined with picolinic acid to make Chromium (I
SUNY Buffalo - MFC - 141
Coenzyme Q10Background Structure Coenzyme Q10 (also known as CoQ10, Q10, vitamin Q10, ubiquinone, or ubidecarenone) is made in the human body. The term &quot;coenzyme&quot; denotes it as an organic, nonprotein molecule necessary for the proper functioning of its p
SUNY Buffalo - MFC - 141
CreatineBackground Creatine, a compound endogenously synthesized by the liver, pancreas, and kidneys, comprises three amino acids: Arginine, Glycine and Methionine. Creatine is also found abundantly in red meats, fish and other animal products and typica
SUNY Buffalo - MFC - 141
Dietary Supplements - SoyBackgroundSoy ProteinIn Asian countries there is a much lower incidence of of cardiovascular disease, menopausal symptoms, as well as some cancers than in the United States. Some of these reduced rates can be attributable to di
SUNY Buffalo - MFC - 141
Ma HuangMa Huang (Ephedra sinica)Background Ephedra sinica, or Ma Huang, is a potentially very dangerous herb and represents the other side of the herbal dietary supplements covered so far. Ephedra sinica is native to Mongolia and the related species Ep
SUNY Buffalo - MFC - 141
GarlicBackground Garlic, Allium sativum, has been cultivated and used for thousands of years both as a spice to flavor foods and as a medicine for its reported health benefits in treating infectious and cardiovascular diseases. From Egyptian pharaohs to
SUNY Buffalo - MFC - 141
GinkgoGinkgoA. Background The leaves (both dried and fresh) and the seeds of Ginkgo biloba have been used as a treatment for &quot;brain dysfunction, vertigo, tinnitus, and intermittent claudication. This tree, called the Maidenhair-Tree (30 to 40 m tall), i
SUNY Buffalo - MFC - 141
GinsengBackground Ginseng has been used for thousands of years in Asian cultures and in Eastern Russia. Most times it is used in combination with other herbs, but this is one herb that can be used fairly safely as a single herb. According to the FDA gins
SUNY Buffalo - MFC - 141
GLUCOSAMINEGlucosamine is a dietary supplement typically used to treat joint conditions associated with arthritis. Although it is not approved by the FDA and some speculate about its efficacy, many studies have supported a positive effect of glucosamine
SUNY Buffalo - MFC - 141
Kava-KavaBackground Kava-kava (Piper methysticum) has been used in the South Pacific for hundreds of years for its therapeutic effects as a &quot;social lubricant&quot;. The active components are most likely Kava lactones (pyrones, such as kavain, methysticin, and
SUNY Buffalo - MFC - 141
Dietary SupplementsOmega 3 and 6 Fatty AcidsBackground The essential fatty acids (PolyUnsaturated Fatty Acids, PUFA, omega 3 and omega 6) are required for the production of eicosanoids. Essential fatty acids are not made in the human body, but can be co
SUNY Buffalo - MFC - 141
Dietary SupplementsSt. Johns WortBackground St. Johns Wort (Hypericum perforatum) has been getting a great deal of attention lately due to its use in Europe to treat depression. It is licensed in Germany for the treatment of anxiety, depression, and sle
SUNY Buffalo - MFC - 141
Performance EnhancersAnabolic Androgenic Steroids (AAS)Background From adolescents to adults, student to major league athletes, the need to become bigger, better, and faster is the reason for the ever-increasing use of anabolic steroids. Anabolic androg
SUNY Buffalo - MFC - 141
ValerianValerianA. Background The malodorous root of valerian, has a musty old-gym-sock aroma. Valerian is a pink-flowered perennial herb, native to North America, Asia, and Europe, has been a popular calming and sleep-promoting agent that dates back to
SUNY Buffalo - MFC - 141
!&quot;#$%&quot;&amp;'()$*+,-./&amp;0 !&quot;#$%&amp;#'!(!#)!%!*%$! !)+,-.,/!0#$%&amp;#'!$1%$!#)!%0%#,%.,/!#'!$2+!*+3&amp;)! !&quot;#$%&amp;#'!(4! 5/36+7%,7#*/3+,8!%'9!&quot;#$%&amp;#'(:!571+,/7%,7#*/3+,8;!&lt;$!#)!%!1+3&amp;+'/=,#&gt;/!0#$%&amp;#'!$1%$!#)! /)/'$#%,!*+3!?3+?/3!7%,7#-&amp;!-$#,#@%$#+'!#'!$1/!.+9A;!&lt;$!7%'!./!
UCSC - AMS - 02
Prestatistics - AMS002 Practice nal test - Spring Quarter 2010Name1. How much is 21 + 22 ? 3 27x7 2. Simplify . 3 9 x43. Solve the following equation:2u1 2+1 2u3 = 1 46u.4. After a 40% reduction and 10% sales tax, your computer costs $630. What wa
UCSC - AMS - 02
AMS 2: Pre-statistics.Instructor: Bruno Mendes mendes@ams.ucsc.edu, Oce 141 Baskin Engineering Teaching Assistants: Luis Acevedo-Arreguin arreguin@soe.ucsc.edu, Oce 142 Baskin Engineering March 30, 2010IntroductionThis courses main goal is to help stud
UCSC - ANTH - 02
UCSC Anthropology 02 MWF 9:30 10:40 A.M. Professor Triloki N. Pandey pandey@ucsc.edu, Tel: 459-4674, messages x9-3366 Office Hours: MW 1:30-3:00pm Office: 319 Social Sciences 1Spring 2010 Classroom Unit 2Teaching Assistants: Ted Biggs (tbiggs@ucsc.edu),
UC Davis - BIS - BIS 104
Page 1Name _1. The cell on the left (N) is a respiratory epithelial cell from a normal individual. The cell on the right (CF) is from a patient with cystic fibrosis. Information on the proteins shown in these cells is provided below the diagrams. Obviou
UCSD - ECON - 120B
Spring 2010 April 7th. list +-+ | no hw1 hw2 hw3 exam1 exam2 exam3 | |-| 1. | 1 15 . 70 79 73 60 | 2. | 2 62 95 50 71 89 64 | 3. | 3 66 80 . 43 16 .| . sum Variable | Obs Mean Std. Dev. Min Max -+-no | 206 103.5 59.61124 1 206 hw1 | 206 96.47573 8.029026
UCSD - ECON - 120B
Economics 120B Professor Yongil Jeon Summer 2006Name: _ Student ID#: _Answer to Exam #1 Summer 2006: Econometrics 120B 1-a. (5 points) Analyzing the behavior of unemployment rates across 150 different countries in July of 2006 is an example of using a.
UCSD - ECON - 120B
Economics 120B Professor Yongil Jeon Winter 2008 (February 11)Name: _ Student ID#: _Answer to Exam #1 Winter 2008: Econometrics 120B1-a. (4 points) To provide quantitative answers to policy questions a. b. c. d. it is typically sufficient to use common