Design
Chapter Digital 8: Programmable Processors
Slides to accompany the textbook Digital Design, First Edition, by Frank Vahid, John Wiley and Sons Publishers, 2007. http://www.ddvahid.com
Copyright 2007 Frank Vahid
Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf Digital Design with animations) may not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Copyright 2006 1 Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors Frank Vahid may obtain PowerPoint source or obtain special use permissions from Wiley see http://www.ddvahid.com for information.
Introduction
Programmable (general-purpose) processor
Well-known common programmable processors: Pentium, Sparc, PowerPC Lesser-known but still common: ARM, MIPS, 8051, PIC
Low-cost embedded processors found in cell phones, blinking shoes, etc.
8.1
Mass-produced, then programmed to implement different processing tasks
Instructive to design a very simple programmable processor
Real processors can be much more complex
e Seatbelt 3-tap FIR filter warning light program program
a p a t a i s
a
Other programs
1 0 2x4
3 2
Instruction memo I ry
r t
Data memo D ry
n
x(t)
xt0
x(t-1) c0
xt1
x(t-2) c1
xt2
o
c
o
c2
t
PC
0
IR
g
n-bit 2x 1
R egister file RF
Seatbelt warning light single-purpose processor
Digital Design Copyright 2006 Frank Vahid
+
+
reg
Controller
AL U
Control unit Datapat h
3-tap FIR filter single-purpose processor
General-purpose processor
2
Note: Slides with animation are denoted with a small red "a" near the animated items
1
Basic Architecture
Processing generally consists of:
Loading some data Transforming that data Storing that data
Data memo D ry
8.2
someh ow connected to the outside world
Basic datapath: Useful circuit in a programmable processor
Can read/write data memory, where main data exists Has register file to hold data locally Has ALU to transform local data
i s
n-bit 2x1
a p a t a
R egister file RF
r t n o c
o
t
ALU
g
Datapath
Digital Design Copyright 2006 Frank Vahid
3
Basic Datapath Operations
Load operation: Load data from data memory to RF ALU operation: Transforms data by passing one or two RF register values through
ALU, performing operation (ADD, SUB, AND, OR, etc.), and writing back into RF.
Store operation: Stores RF register value back into data memory Each operation can be done in one clock cycle
Data memory D Data memory D Data memory D
n-bit 2x1
n-bit 2x1
n-bit 2x1
a
Register file RF
Register file RF
Register file RF
ALU
Digital Design Copyright 2006 Frank Vahid
ALU
ALU
Load operation
ALU operation
Store operation
4
2
Basic Datapath Operations
Q: Which are valid single-cycle operations for given datapath?
Move D[1] to RF[1] (i.e., RF[1] = D[1])
A: YES That's a load operation
Store RF[1] to D[9] and store RF[2] to D[10]
A: NO Requires two separate store operations
a
Add D[0] plus D[1], store result in D[9]
A: NO ALU operation (ADD) only works with RF. Requires two load operations (e.g., RF[0]=D[0]; RF[1]=D[1], an ALU operation (e.g., RF[2]=RF[0]+RF[1]), and a store operation (e.g., D[9]=RF[2])
Data memory D Data memory D Data memory D
n-bit 2x1 Register file RF
n-bit 2x1 Register file RF
n-bit 2x1 Register file RF
ALU
Digital Design Copyright 2006 Frank Vahid
ALU
ALU
Load operation
ALU operation
Store operation
5
Basic Architecture Control Unit
D[9] = D[0] + D[1] requires a sequence of four datapath operations:
0: RF[0] = D[0] 1: RF[1] = D[1] 2: RF[2] = RF[0] + RF[1] 3: D[9] = RF[2]
a
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
Data memory D
Each operation is an instruction
Sequence of instructions program Looks cumbersome, but that's the world of programmable processors Decomposing desired computations into processor-supported operations Store program in Instruction memory Control unit reads each instruction and executes it on the datapath
PC: Program counter address of current instruction IR: Instruction register current instruction
PC IR
n-bit 2x1
Register file RF
Controller ALU
sgnas i l to cont r ol t he dat apat h
Control unit
Datapath
Digital Design Copyright 2006 Frank Vahid
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3
Basic Architecture Control Unit
To carry out each instruction, the control unit must:
Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
PC 0>1
IR RF[0]=D[0] PC 1 IR RF[0]=D[0]
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
Data memory D D[0]: 99
PC Controller
sgnas i l to cont r ol t he dat apat h
1 Controller "load"
sgnas i l to cont r ol t he dat apat h
IR RF[0]=D[0]
sgnas i l to cont r ol t he dat apat h
n-bit 2x1
Register file RF R[0]: ?? 99
a
Control unit (a )
Controller ALU
sgnas i l to cont r ol t he dat apat h
Fetch
Digital Design Copyright 2006 Frank Vahid
Control unit (b)
Decode
Control unit
Datapath (c )
Execute
7
Basic Architecture Control Unit
To carry out each instruction, the control unit must:
Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
PC 1>2
IR RF[1]=D[1} PC 2 IR RF[1]=D[1]
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
Data memory D D[1]: 102
PC Controller
sgnas i l to cont r ol t he dat apat h
2 Controller "load"
sgnas i l to cont r ol t he dat apat h
IR RF[1]=D[1]
sgnas i l to cont r ol t he dat apat h
n-bit 2x1
Register file RF R[1]: ?? 102
a
Control unit (a )
Controller ALU
sgnas i l to cont r ol t he dat apat h
Fetch
Digital Design Copyright 2006 Frank Vahid
Control unit (b)
Decode
Control unit
Datapath (c )
Execute
8
4
Basic Architecture Control Unit
To carry out each instruction, the control unit must:
Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
PC 2>3
IR RF[2]=RF[0]+RF[1] PC 3
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
Data memory D
IR RF[2]=RF[0]+RF[1] PC 3 IR RF[2]=RF[0]+RF[1]
sgnas i l to cont r ol t he dat apat h
n-bit 2x1
Controller
sgnas i l to cont r ol t he dat apat h
Controller "ALU (add)"
sgnas i l to cont r ol t he dat apat h
Register file RF R[2]: ?? 201 99 Controller ALU
sgnas i l to cont r ol t he dat apat h
a
Control unit (a )
102 201
Fetch
Digital Design Copyright 2006 Frank Vahid
Control unit (b)
Decode
Control unit
Datapath (c )
Execute
9
Basic Architecture Control Unit
To carry out each instruction, the control unit must:
Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
PC 3>4
IR D[9]=RF[2] PC 4 IR D[9]=RF[2]
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
Data memory D D[9]=?? 201
PC Controller
sgnas i l to cont r ol t he dat apat h
4 Controller "store"
sgnas i l to cont r ol t he dat apat h
IR D[9]=RF[2]
sgnas i l to cont r ol t he dat apat h
n-bit 2x1
Register file RF R[2]: 201
a
Control unit (a )
Controller ALU
sgnas i l to cont r ol t he dat apat h
Fetch
Digital Design Copyright 2006 Frank Vahid
Control unit (b)
Decode
Control unit
Datapath (c )
Execute
10
5
Basic Architecture Control Unit
Init PC=0 Fetch
IR=I[PC] PC=PC+1
Decode
Execute Controller
sgnas i l to cont r ol t he dat apat h
Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
Data memory D
sgnas i l
to
cont r ol t he
dat apat h
n-bit 2x1 PC IR
sgnas i l to cont r ol t he dat apat h
Register file RF
sgnas i l to cont r ol t he dat apat h
Controller
Digital Design Copyright 2006 Frank Vahid
ALU Control unit Datapath
11
Creating a Sequence of Instructions
Q: Create sequence of instructions to compute D[3] = D[0]+D[1]+D[2] on earlier-introduced processor A1: One possible sequence A2: Alternative sequence First load data memory First load D[0] and D[1] and locations into register file add them
R[3] = D[0] R[4] = D[1] R[2] = D[2] (Note arbitrary register locations) R[1] = D[0] R[2] = D[1] R[1] = R[1] + R[2]
a
a
Next, perform the additions
R[1] = R[3] + R[4] R[1] = R[1] + R[2]
Next, load D[2] and add
R[2] = D[2] R[1] = R[1] + R[2]
Finally, store result
D[3] = R[1]
Digital Design Copyright 2006 Frank Vahid
Finally, store result
D[3] = R[1]
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6
Number of Cycles
Q: How many cycles are needed to execute six instructions using the earlier-described processor? A: Each instruction requires 3 cycles 1 to fetch, 1 to decode, and 1 to execute Thus, 6 instr * 3 cycles/instr = 18 cycles
a
Digital Design Copyright 2006 Frank Vahid
13
Three-Instruction Programmable Processor
Instruction Set List of allowable instructions and their representation in memory, e.g.,
Load instruction0000 r3r2r1r0 d7d6d5d4d3d2d1d0 Store instruction0001 r3r2r1r0 Add d7d6d5d4d3d2d1d0 instruction0010 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2}
a
8.3
a
Instruction memory 0: 0000 0000 00000000 1: 0000 0001 00000001 2: 0010 0010 0000 0001 3: 0001 0010 00001001 Digital Design Copyright 2006 Frank Vahid
I
Instructions in 0s and 1s machine code
14
opcode operands
7
Program for Three-Instruction Processor
Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2} Instruction memoryI 0: 0000 0000 00000000 1: 0000 0001 00000001 2: 0010 0010 0000 0001 3: 0001 0010 00001001 Computes D[9]=D[0]+D[1] Data memory D
n-bit 2 1 PC IR Register file RF
Controller ALU
sgnas i l to cont r ol t he dat apat h
Control unit Digital Design Copyright 2006 Frank Vahid
Datapath
15
Program for Three-Instruction Processor
Another example program in machine code
Compute D[5] = D[5] + D[6] + D[7]
0: 0000 0000 00000101 // RF[0] = D[5] 1: 0000 0001 00000110 // RF[1] = D[6] 2: 0000 0010 00000111 // RF[2] = D[7] 3: 0010 0000 0000 0001 // RF[0] = RF[0] + RF[1] // which is D[5]+D[6] 4: 0010 0000 0000 0010 // RF[0] = RF[0] + RF[2] // now D[5]+D[6]+D[7] 5: 0001 0000 00000101 // D[5] = RF[0]
Digital Design Copyright 2006 Frank Vahid
Load instruction0000 r3r2r1r0 d7d6d5d4d3d2d1d0 Store instruction0001 r3r2r1r0 d7d6d5d4d3d2d1d0 Add instruction0010 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
sgnas i l to cont r ol t he
dat apat h
16
8
Assembly Code
Machine code (0s and 1s) hard to work with Assembly code Uses mnemonics
Load instructionMOV Ra, d
specifies the operation RF[a]=D[d]. a must be 0,1, ..., or 15so R0 means RF[0], R1 means RF[1], etc. d must be 0, 1, ..., 255
Store instructionMOV d, Ra
specifies the operation D[d]=RF[a]
Add instructionADD Ra, Rb, Rc
specifies the operation RF[a]=RF[b]+RF[c]
Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2]
Digital Design Copyright 2006 Frank Vahid
0: 0000 0000 00000000 1: 0000 0001 00000001 2: 0010 0010 0000 0001 3: 0001 0010 00001001
0: MOV R0, 0 1: MOV R1, 1 2: ADD R2, R0, R1 3: MOV 9, R2
assembly code
17
machine code
Control-Unit and Datapath for Three-Instruction Processor
To design the processor, we can begin with a high-level state machine description of the processor's behavior
Init PC=0 Fetch IR=I[PC] PC=PC+1
Decode op=0000 op=0001 op=0010
Load RF[ra]=D[d]
Store D[d]=RF[ra]
Add RF[ra] = RF[rb]+ RF[rc]
18
Digital Design Copyright 2006 Frank Vahid
9
Control-Unit and Datapath for Three-Instruction Processor
Create detailed connections among components
D_addr 8 addr 16 PC clr up
Init PC=0 Fetch IR=I[PC] PC=PC+1
_r d PC_ c r l PC_ n c i
rd
data 16 IR Id 16
R_ d l
I
D_rd D_wr
addr rd 256x16 wr W_data R_data 16
D
I
I
RF_s
s
Decode op=0000 op=0001 op=0010
1 0 16-bit 2x1 16
Load RF[ra]=D[d]
Store D[d]=RF[ra]
Add RF[ra] = RF[rb]+ RF[rc]
Controller
RF_W_addr RF_W_wr RF_Rp_addr RF_Rp_rd RF_Rq_addr RF_Rq_rd
4 4 4
W_data W_addr W_wr Rp_addr 16x16 Rp_rd RF Rq_addr Rq_rd 16 Rp_data Rq_data 16 B 16
alu_s0 s0 A
16 ALU
Digital Design Copyright 2006 Frank Vahid
Control unit
Datapath
19
Control-Unit and Datapath for Three-Instruction Processor
Convert high-level state machine description of entire processor to FSM description of controller that uses datapath and other components to achieve same behavior
Init Init
a
addr 16 PC clr up
rd data 16 IR Id 16
I
D_addr 8 addr D_rd rd x16 256 D_wr wr W_data R_data 16 RF_s s 1 0 16-bit 2x1 16
D
PC=0 PC_ clr=1
Fetch Fetch
IR=I[PC] IR= I[PC] PC=PC+1 PC=PC+1 I_rd=1 PC_inc=1 IR_ld=1
PC_ c r l _r d R_ d l PC_ n c i
I
I
Decode Decode
op=0000 op=0001 op=0010 op=0000 op=0001 op=0010
Controller Load Load
st at es Ex ec ut e
Store Store
D[d]=RF[ra] D[d]=RF[ra] D_addr=d
Add Add
RF[ra] = RF[ra] = RF[rb]+
RF[rc] RF[rb]+ RF_Rp_addr=rb RF[rc] RF_Rp_rd=1
RF_W_addr 4 RF_W_wr RF_Rp_addr 4 RF_Rp_rd RF_Rq_addr 4 RF_Rq_rd
W_data W_addr W_wr Rp_addr 16x16 Rp_rd RF Rq_addr Rq_rd 16 Rp_data Rq_data
RF[ra]=D[d] RF[ra]=D[d] D_addr=d
D_rd=1 RF_s=1
RF_W_addr=ra RF_W_wr=1
D_wr=1 RF_s=X
RF_Rp_addr=ra RF_Rp_rd=1
alu_s0 s0 Control unit Datapath
16 A
16
RF_s=0 RF_Rq_addr=rc RF_Rq _rd=1
RF_W_addr=ra RF_W_wr=1 alu_s0=1
B ALU 16
Digital Design Copyright 2006 Frank Vahid
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10
A Six-Instruction Programmable Processor
Let's add three more instructions:
Load-constant instruction0011 r3r2r1r0 c7c6c5c4c3c2c1c0
MOV Ra, #cspecifies the operation RF[a]=c
8.4
Subtract instruction0100 ra3ra2ra1ra0 rb3rb2rb1rb0 rc3rc2rc1rc0
SUB Ra, Rb, Rcspecifies the operation RF[a]=RF[b] RF[c]
Jump-if-zero instruction0101 ra3ra2ra1ra0 o7o6o5o4o3o2o1o0
JMPZ Ra, offsetspecifies the operation PC = PC + offset if RF[a] is 0
Digital Design Copyright 2006 Frank Vahid
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Extending the Control-Unit and Datapath
1: The load constant instruction requires that the register file be able to load data from IR[7..0], in addition to data from data memory or the ALU output. Thus, we widen the register files multiplexer from 2x1 to 3x1, add another mux control signal, and also create a new signal coming from the controller labeled RF_W_data, which will connect with IR[7..0].
PC_ d l PC_ c r l
addr 16 PC ld clr up
PC_inc PC_clr PC_ld
rd data 16 IR Id
IR_ld
D_addr 8 addr D_rd rd 256x16 D_wr wr W_data R_data 1 8 RF_W_data 1 RF_s1 RF_s0 16 2 1 0 s1 16-bit s0 3x1 16 RF_W_addr 4 4 4
D
_r d
I
16
+
PC_ n c i
3b
a+b-1
I R_ d l
IR[7..0]
2: The subtract instruction requires that we use an ALU capable of subtraction, so we add another ALU control signal. 3: The jump-if-zero instruction requires that we be able to detect if a register is zero, and that we be able to add IR[7..0] to the PC. 3a: We insert a datapath component to detect if the register files Rp read port is all zeros (that component would just be a NOR gate). 3b: We also upgrade the PC register so it can be loaded with PC plus IR[7..0]. The adder used for this also subtracts 1 from Digital Design the sum, to compensate for the fact that the Copyright 2006 Fetch state already added 1 to the PC. Frank Vahid
Controller
RF_Rp_addr RF_Rq_addr
W_data W_addr W_wr Rp_addr 16x16 Rp_rd RF Rq_addr Rq_rd 16 Rp_data 16 A ALU B 16 Rq_data 16
RF_Rp_zero alu_s1 alu_s0 2 s1 0 0 1 s0 0 1 0
3a =0
Control unit
s1 s0 Datapath
ALU operation pass A through A+B A-B
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11
Controller FSM for the Six-Instruction Processor
Init PC_clr=1 Fetch I_rd=1 PC_inc=1 IR_ld=1
Decode op=0000
Load Store
op=0001
op=0010
Add
op=0011 Loadconstant
op=0100
op=0101
Subtract Jump-if-zero
D_addr=d D_rd=1 RF_s1=0 RF_s0=1 RF_W_addr=ra RF_W_wr=1
D_addr=d D_wr=1 RF_s1=X RF_s0=X RF_Rp_addr=ra RF_Rp_rd=1
PC_ld=1
Digital Design Copyright 2006 Frank Vahid
RF_Rp_zero'
RF_ Rp _ z e r o
RF_Rp_addr=rb RF_Rp_rd=1 RF_s1=0 RF_s0=0 RF_Rq_add=rc RF_Rq_rd=1 RF_W_addr_ra RF_W_wr=1 alu_s1=0 alu_s0=1
RF_s1=1 RF_s0=0 RF_W_addr=ra RF_W_wr=1
RF_Rp_addr=rb RF_Rp_rd=1 RF_s1=0 RF_s0=0 RF_Rq_addr=rc RF_Rq_rd=1 RF_W_addr=ra RF_W_wr=1 alu_s1=1 alu_s0=0
RF_Rp_zero
RF_ Rp _ z e r o
RF_Rp_addr=ra RF_Rp_rd=1
Jump-ifzero-jmp
?
23
Program for the Six-Instruction Processor
Example program Count number of non-zero words in D[4] and D[5]
Result will be either 0, 1, or 2 Put result in D[9]
_r d
I
MOV R0, #0; // initialize result to 0 MOV R1, #1; // constant 1 for incrementing result MOV R2, 4; // get data memory location 4 JMPZ R2, lab1; // if zero, skip next instruction
PC_ d l PC_ c r l PC_ n c i I R_ d l
0011 0000 00000000 0011 0001 00000001 0000 0010 00000100 0101 0010 00000010 0010 0000 0000 0001 0000 0010 00000101 0101 0010 00000010 0010 0000 0000 0001 0001 0000 00001001 (b)
ADD R0, R0, R1; // not zero, so increment result lab1:MOV R2, 5; // get data memory location 5 JMPZ R2, lab2; // if zero, skip next instruction ADD R0, R0, R1; //not zero, so increment result lab2:MOV 9, R0; // store result in data memory location 9 (a)
Digital Design Copyright 2006 Frank Vahid
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12
Further Extensions to the Programmable Processor
Typical processor instruction set will contain dozens of data movement (e.g., loads, stores), ALU (e.g., add, sub), and flow-of-control (e.g., jump) instructions
Extending the control-unit/datapath follows similarly to previously-shown extensions
256x16 D addr rd wr 0: 1: 2: 239: 240: 241: 248: 255: 00..0 00..0 I0 I1
8.5
Input/output extensions
Certain memory locations may actually be external pins
e.g, D[240] may represent 8-bit input I0, D[255] may represent 8-bit output P7
P0 P7
Digital Design Copyright 2006 Frank Vahid
W_data R_data
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Program using I/O Extensions Recall Chpt 1 C-Program Example
Programmed Custom designed Desired motion-at-night detector microprocessor digital circuit Microprocessors a common choice to implement a digital system
Easy to program Cheap (as low as $1) Available now
M
r
p o
r
o
c
I0 I1 I2 I3 I4 I5 I6 I7
P0 P1 P2 P3 P4 P5 P6 P7
void main() 1 a { 0 while (1) { 1 b P0 = I0 && !I1; 0 // F = a and !b, 1 F } 0 }
6:00 7:057:06 9:009:01 time
Digital Design Copyright 2006 Frank Vahid
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13
Program Using Input/Output Extensions
Underlying assembly code for C expression I0 && !I1.
0: MOV R0, 240 // move D[240], which is the value at pin I0, into R0 1: MOV R1, 241 // move D[241], which is that value at pin I1, into R1 2: NOT R1, R1 // compute !I1, assuming existence of a complement instruction 3: AND R0, R0, R1 // compute I0 && !I1, assuming an AND instruction 4: MOV 248, R0 // move result to D[248], which is pin P0
256x16 D addr rd wr 0: 1: 2: 239: 240: 241: 248: 255: 00..0 00..0 I0 I1 P0 P7
void main() { while (1) { P0 = I0 && !I1; // F = a and !b, } }
Digital Design Copyright 2006 Frank Vahid
W_data R_data
27
Chapter Summary
Programmable processors are widely used
Easy availability, short design time
Basic architecture
Datapath with register file and ALU Control unit with PC, IR, and controller Memories for instructions and data Control unit fetches, decodes, and executes Extended to six instructions Real processors have dozens or hundreds of instructions Extended to access external pins Modern processors are far more sophisticated
Three-instruction processor with machine-level programs
Instructive to see how one general circuit (programmable processor) can execute variety of behaviors just by programming 0s and 1s into an instruction memory
Digital Design Copyright 2006 Frank Vahid
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14