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### lesson20

Course: MAE 140, Spring 2010
School: UCSD
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Word Count: 838

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20 Lesson Op-Amps #5 (Section 4-5) (CLO 4-3) This lesson is dedicated to Op-Amp application, in particular, D/A and Comparator circuits. The next two lessons are reserved for Instrumentation applications. Digital-to-Analog Converters (DACs or D/As) We will look at two different types of D/A circuits the weighted summer and the R-2R ladder circuit. The first is very easy for students to grasp since it is simply...

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20 Lesson Op-Amps #5 (Section 4-5) (CLO 4-3) This lesson is dedicated to Op-Amp application, in particular, D/A and Comparator circuits. The next two lessons are reserved for Instrumentation applications. Digital-to-Analog Converters (DACs or D/As) We will look at two different types of D/A circuits the weighted summer and the R-2R ladder circuit. The first is very easy for students to grasp since it is simply an inverting summer. The figure below is for a 4-bit DAC, but generally, DACs are eight or more bits in length. RF b b b VREF b1 + 2 + 3 + 4 VREF The output is given by vO = R 2 4 8 v1 R Where each bit drives an electronic switch that switches b1 between ground (0V) and VREF, whatever the designer v2 2R RF wants it to be. The simplicity of this design is offset by the accuracy that each resistor must have to make all the b2 vO bits weighing proportional. In general, this is not the v3 4R way DACs are designed. b3 Consider instead the R-2R realization shown in the following circuit. Here the importance is that all resistors b4 be the same R or 2R. An easy task especially if laid-out on a PC board or thick- or thin-film construction. It is worthwhile to let the students derive the output for a simple 4-bit DAC and they can then readily expand it to an n-bit device. The analysis is best done by finding the Thvenin equivalent circuit using superposition. A RF vO Using the look-back method we can R R R readily see that RT = R. To find vT we 2R 2R 2R 2R 2R start by setting all of the sources v4 v3 v2 v1 except v1, the MSB (most significant bit) to zero. The resistors to the left LSB MSB (a) collapse thusly, the furthermost 2R is in parallel with the 2R that was in RT =R A RF vO series with v yielding simply R. This 4 equivalent R then is in series with the fist R between the v4 and v3 branch. vT This then produces 2R. This new 2R equivalent resistor is in parallel with (b) the 2R that is in series with the v3shorted source yielding R. Following this process to node A produces a single 2R connected between node A and ground. Then using a voltage divider, the contribution of the MSB is v1/2 at node A. Have the students RF v v v v1 + 2 + 3 + 4 . The do the remaining three sources. The result then is vO = 2R 2 4 8 realization in the text allows one to set the input voltage VREF to regardless of the values of the four bits. v4 8R Comparators Comparators are not linear devices, so one might argue that they do not belong in this lecture. We usually involve Op-Amps in their linear mode between VCC. However, comparators purposely let the output to saturate the Op-Amp resulting in just two output values, namely VCC. The comparator shown below is simply an Op-Amp without feedback. Hence, even the smallest input will drive the Op-Amp towards saturation since the open-loop gain is generally very large, >105. If we input the vP vO signal shown, the output will go positive to +VCC whenever the vN signal is positive and towards VCC whenever the signal goes vS negative. The output is also shown in the figure. This configuration is called a zero-crossing detector because the OpAmps output switches whenever the signal crosses zero volts. Ask the students how the output would change if the signal went to the terminal and the + terminal was grounded. Likewise, one can add a DC source VDC between vN and 5 ground. This would in effect cause the output to switch between +VCC and VCC whenever the signal exceeded 0 t VDC. Another useful application is to compare two signals (a) one connected to vN and the other to vP and to switch -5 whenever one signal exceeds the other. Such an V cc application could be used to monitor the temperature rise in an engine versus an ideal maximum temperature t 0 rise and to issue a warning whenever the actual signal (b) exceeds the ideal maximum rise. -Vcc The last application would be as a flash Analog-to-Digital Converter (A/D or ADC). The figure below shows how a 3-bit device would be connected. The voltage divider sets the switching values for the input. Whenever the input + 8V exceeds 1 V vO1 goes high. When it exceeds 3 V both vO1 and vO2 go high and when the input exceeds 5 V all three 3R outputs are high. You might compare this design with the vO3 one in the text. Since the output occurs instantaneously 2R vN3 with the input changing, it is called a Flash converter. v O2 These are the fastest of all A/D converters. However, most A/Ds today are not Flash converters but rather sample-hold 2R vN2 devices. We will talk about these after we have studied vO1 capacitors and RC step response. vS R vN1 VOH = 5 V VOL = 0 V
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UCSD - MAE - 140
Lesson 21 Op-Amps #6 (Section 4-6) (CLO 4-3) The sixth lesson on Op-Amps focuses on designing Instrumentation Systems. After this and the next lesson, the students should be able to design simple instrumentation systems.KInput Transducer Gain+ +Bias,
UCSD - MAE - 140
Lesson 22 Op-Amps #7 (Section 4-6) (CLO 4-3) This last lesson on Op-Amps focuses on designing Instrumentation Systems with passive transducers.KInput Transducer Gain+ +Bias, b Output TransducerAs mentioned previously, passive transducers require an e
UCSD - MAE - 140
Lesson 23 Signals I (Section 5-1 through 5-3, and 5-7) (CLO 5-1) We will now have a change of pace; away from design to developing a repertoire of signals that we will use to excite circuits and use to represent solutions of circuit behavior. This is the
UCSD - MAE - 140
Lesson 24 Signals II (Section 5-4, 5-6 and 5-7) (CLOs 5-1 and 5-3) This is the second lesson of a three-lesson block on signals. The first lesson was on Singularity functions and exponentials. This one is on sinusoids and partial descriptors (VP, VPP, VMA
UCSD - MAE - 140
Lesson 25 Signals III (Section 5-5 and 5-7) (CLO 5-1 through 5-3) This is the last lesson of a three-lesson block on signals. This section focuses on composite signals and how to construct them using OrCAD and MATLAB. We start by discussing the various co
UCSD - MAE - 140
Lesson 26 Capacitors and Inductors I (Sections 6-1 and 6-2) (CLO 6-1) This is the first of two lessons on Capacitors and Inductors. The first lesson introduces the i-v characteristics of the devices and includes power and energy considerations. The second
UCSD - MAE - 140
Lesson 27 Capacitors and Inductors II (Sections 5-5 and 5-7) (CLOs 6-2 and 6-3) This is the second of two lessons on Capacitors and Inductors. This lesson discusses combining multiple devices and introduces two new operational modules, the integrator and
UCSD - MAE - 140
Lesson 28 RL and RC Circuits (Natural Response) (Section 7-1) (CLO 7-1) The next three lessons on First-Order Circuits can be a bit challenging for the students because they involve calculus. The first looks at deriving the equations that describe first-o
UCSD - MAE - 140
Lesson 29 RL and RC Circuits (Step Response) (Sections 7-2 and 7-3) (CLO 7-1) This lesson starts out challenging but fortunately becomes easy for the students to use once the derivations are done and they can apply solutions to a template. That this analy
UCSD - MAE - 140
Lesson 30 RL and RC Circuits (Exponential and Sinusoidal Transient Responses) (Section 7-4) (CLO 7-2) This lesson is somewhat mathematically challenging since we will be differentiating exponentials and sinusoids. However, the concepts are easy to underst
UCSD - MAE - 140
Lesson 31 RLC Series and Parallel Circuits (Sections 7-5 and 7-6) (CLOs 7-3 and 7-4) This is the first lesson on the behavior of RLC circuit. There are several key points that we want the cadets to learn in this and the next lesson (step response of RLC c
UCSD - MAE - 140
Lesson #32 RLC Step Response (Section 7-7) (CLOs 7-3 and 7-4) This is the second lesson on the behavior of RLC circuits. In this lesson, we look at the response of RLC circuits to a step input. In many ways, this is repetitious of the natural response exc
UCSD - MAE - 140
Lesson 33 AC Circuit Analysis I (Sections 8-1 and 8-2) (CLOs 8-1 and 8-2) This is the beginning of a four-lecture block on doing all those things we did with dc (KVL, KCL, Node Voltage, Mesh Current, Thvenin Equivalent, Voltage and Current dividers, Super
UCSD - MAE - 140
Lesson 34 AC Circuit Analysis II (Sections 8-2 and 8-3) (CLO 8-3) This lesson begins to apply all of the theorems learned back in Chapters 2 and 3 to ac circuits. But, before we start we bring in one very important concept involving impedance. It is very
UCSD - MAE - 140
Lesson 35 AC Circuit Analysis III (Sections 8-5 and 8-6) (CLOs 8-4 and 8-5) We did the circuit theorems last lecture and will do Node Voltage and Mesh Currents in this one. It is important to solve several Op-Amp circuits since they will need them later t
UCSD - MAE - 140
Lesson 36 Transfer Functions and Cascade Connections (Variant of Sections 11-1 and 11-2) (Variant of CLOs 11-1) This is the first lecture of a three-lecture block on learning how filters work and designing first-order filters. The end result is for the st
UCSD - MAE - 140
Lesson 37 Filters II (Variant of Sections 12-1 thru 12-3) (Variant of CLO 12-1) This is the first of two lessons on filter analysis and design. The first focuses on first-order LP and HP both passive and active. The second focuses on BP and BR. Begin by w
UCSD - MAE - 140
Lesson 38 Filters III (Variant of Section 12-4) (Variant of CLO 12-2) This is the last of two lessons on filter analysis and design. The first focused on first-order LP and HP. The second focuses on BP and BR. In discussing BP and BR filters start by usin
UCSD - MAE - 140
Lesson 39 Intro to L aplace Transforms and the Complex Frequency Domain. (Sections 9-1and 9-2) (CLO 9-1) We are now entering a major new part of the course. Remind the students of the basic tools they will use in all circuits analysis. Remind them of what
UCSD - MAE - 140
Lesson 40 Laplace II: Pole-Zero Diagrams and the Inverse Laplace. (Sections 9-3, 9-4 and 9-5) (CLOs 9-1 and 9-2) There is a lot to cover in this lesson and depending on how much emphasis you want to place on classical expansion of transforms it may take p
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