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Course: ECE EEL 5225, Fall 2010School: University of Florida
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Technology, Fabrication Part I #! Agenda $! $! $! $! $! $! $! Microfabrication Overview Layer Deposition Lithography Pattern Transfer (etching) Impurity Doping Heat Treatment Example process flows !! Senturia, Ch. 3, pp. 29-47, 50-77; Ch. 4 pp. 79-98 "! HW2 1 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold Basic Semiconductor Devices %! P/N diode %! Bipolar junction transistor (BJT) %! N/P/N %! P/N/P...
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Technology, Fabrication Part I
#! Agenda
$! $! $! $! $! $! $! Microfabrication Overview Layer Deposition Lithography Pattern Transfer (etching) Impurity Doping Heat Treatment Example process flows
!! Senturia, Ch. 3, pp. 29-47, 50-77; Ch. 4 pp. 79-98 "! HW2
1 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Basic Semiconductor Devices
%! P/N diode %! Bipolar junction transistor (BJT) %! N/P/N %! P/N/P %! Metal-oxide-semiconductor field-effect transistor (MOSFET) %! n-channel (NMOS) %! p-channel (PMOS) %! complementary MOS (CMOS)
Idealized pictures P Metal (Al) N P N N
SiO2 N
Poly Si N P
2
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Basic Semiconductor Devices
%! Diode
Planar Process P+ N+ N Metal (Al) P N
%! CMOS
Johns and Martin, Analog Integrated Circuit Design
3
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EEL 5225, Fall 2010, David Arnold
Materials Classification
%! By Class: %! Metals %! Ceramics %! Polymers %! Semiconductors %! Composites %! By Property: %! Mechanical %! Electrical %! Magnetic %! Optical %! Chemical
4 Lecture 3 Fab 1
Cu, Al, Ta, alloys oxides, nitrides, carbides, glass photoresist, plastics, liquid crystals Si, Ge, GaAs, InSb particulate composites, laminates, etc.
modulus, ductile, brittle, fatigue, conductors, dielectrics, semiconductor ferromag., paramag., magnetostrictive refractive index, absorption oxidation states,
EEL 5225, Fall 2010, David Arnold
Crystallinity
Crystalline
Polycrystalline
Domains Domain walls
Amorphous
5
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Crystallinity
%! MOS Gate
Poly-Crystalline Si Gate Electrode
Amorphous SiO2 Dielectric
Crystalline Si Channel
High-resolution transmission electron microscope image
Ref: Jaeger, Intro to Microelectronic Fabrication, p.39.
6
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EEL 5225, Fall 2010, David Arnold
Crystallography
Unit Cell Lattice
Group IV Materials (Si)
Ref: S. A. Campbell, The Science and Engineering of Microelectronic Fabrication, 2001, pp. 15, 16.
Diamond structure
7
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EEL 5225, Fall 2010, David Arnold
Miller Indices
To find the miller index of a plane: Step 1: Find points where plane crosses x,y,z coordinate axes Step 2: Take inverse Step 3: Multiply by smallest factor to make indexes integers
Notation for Miller indices (ijk): a specific crystal plane or face {ijk}: a family of equivalent planes
Ref: Senturia, Microsystem Design, pg. 31
[ijk]: a specific direction which is normal to the (ijk) plane <ijk>: a family of equivalent directions
8
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EEL 5225, Fall 2010, David Arnold
Substrate Materials: Silicon
%! Defined by plane crystal orientation and wafer flat direction
(100) n-type
(100) p-type
<110>
<110>
(111) n-type
(111) p-type
<110>
<110>
Primary (largest) flat is always perpendicular to <110> direction 9 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Substrate Materials
%! Group IV Elemental Semiconductors %! e.g. Si %! 4 valence electrons %! Tetrahedral covalent bonding %! Diamond crystal lattice
III IV V VI VII
%! Silicon bonded to 4 nearest neighbors %! 2 (Si) FCC lattices that are offset by a/4, a/4, a/4
%! Group III-V Compound Semiconductors %! e.g. GaAs, InSb %! Ga bonded to 4 nearest neighbor As %! Zinc blende lattice
%! 1 FCC consists of Ga %! 1 FCC consists of As
Fab 1
10
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EEL 5225, Fall 2010, David Arnold
Semiconductor Structure
%! Visualization %! http://cst-www.nrl.navy.mil/lattice/struk/a4.html
11
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Donor Doping
%! Group V Impurities %! 5 valence electrons %! Impurity donates extra electron to its nearest neighbors %! Extra electron donated %! N-type semiconductor %! Semiconductor with intentionally added concentration of group V impurities, ND %! Electron-rich n ! ND >> p
III IV V VI VII
Si Si Si
Si P Si
Si Si Si
%! where n=electron concentration and n=hole concentration (units: #/cm3)
12
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EEL 5225, Fall 2010, David Arnold
Acceptor Doping
%! Group III Impurities %! 3 valence electrons %! Impurity accepts extra electron from its nearest neighbors %! Results in hole %! P-type semiconductor %! Semiconductor with intentionally added concentration of group III impurities, NA %! Hole-rich
%! where n=electron concentration and p=hole concentration (units: #/cm3)
III IV V VI VII
Si Si Si
Si B Si
Si Si Si
p ! NA >> n
13
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EEL 5225, Fall 2010, David Arnold
Microfabrication Overview
%! Microfabrication %! Silicon integrated circuit fabrication %! > 40 years of collective equipment and process experience %! Primarily planar process %! Key processes:
Layer Deposition
Photolithography
Pattern Transfer (Etching)
Impurity Doping
Heat Treatment
14
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EEL 5225, Fall 2010, David Arnold
Layer Deposition Overview
%! %! %! %! Oxidation (for silicon wafers only) Physical Vapor Deposition (PVD) Chemical Vapor Deposition (CVD) Other
Layer Deposition
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Layer Deposition Oxidation
%! Thermal Oxidation %! Dry: Si(s) + O2(g) & SiO2(s) %! Wet: Si(s) + 2H2O(g) & SiO2(s) + 2H2(g) %! Principal Uses %! Insulating layer in device and between metal lines %! Passivation layer to seal silicon surface %! Blocking layer to stop or mask impurity atoms
16
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EEL 5225, Fall 2010, David Arnold
Oxidation Kinetics
%! Reaction %! Gas phase transport of oxidation species to silicon surface
%! Diffusion through existing oxide %! Reaction at silicon surface
%! Silicon is consumed to make SiO2
%! Deal-Grove Model B/A = linear rate coefficient (um/hr) B = parabolic rate constant (um2/hr) xi = initial oxide thickness
NOTE: Eq. 3.1 is incorrect in Senturia. Also Tables 3.1 and 3.2 should units as um2/hr for column B
17
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EEL 5225, Fall 2010, David Arnold
Oxidation Kinetics
Oxide thickness, xox -! 0
Time, t Diffusion limited C0
Reaction rate limited C0
Ci
18 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Ci
Oxidation Coefficients
%! Standard oxidation rates for (100) Silicon
Ref: Campbell, p. 72.
19
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EEL 5225, Fall 2010, David Arnold
Oxidation Kinetics
%! Standard oxidation rates for (100) Silicon
Ref: Campbell, p. 72.
20
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EEL 5225, Fall 2010, David Arnold
Oxidation Example
%! Ex: Determine how long it takes to grow 1 um of oxide on a bare silicon wafer at 1000C under both wet and dry conditions. How much silicon was consumed for each case?
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EEL 5225, Fall 2010, David Arnold
Oxidation Details
%! Thermal oxides are amorphous and have compressive stress %! Dry Oxide %! Denser oxide %! Higher dielectric strength %! Ex: Gate oxide for MOSFET %! Wet Oxide %! Faster growth %! Ex: Field oxide %! Dry/Wet/Dry process %! High quality Si/SiO2 interfacial oxide %! Faster growth %! Cleanliness essential %! Oxide charge very detrimental %! Need RCA clean before oxidation
22 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Layer Deposition PVD
%! Physical Vapor Deposition (PVD) %! Physical transport of material onto substrate surface %! Typically used for metals, but also dielectrics %! Two primary types:
Evaporation Sputtering
Poor step coverage Lower temp Higher purity Metals only
Good step coverage Higher temp Lower purity Metals and dielectrics
23
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Evaporation
%! Thermal Evaporation %! Sublimation of heated material in vacuum
%! Resistive Filament or W boat %! Inductive %! E-beam %! Metals only
Typical Evaporator
%! Limitations
Ref: S. A. Campbell, Science and Eng. of Micro. Fab., 2001.
24
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Sputtering
%! Sputtering %! Momentum transfer induces release of material via energetic Ar+ ion impact %! Metals (DC) and dielectrics (RF) %! Limitations
%! Higher Cost %! Ion bombardment damage
Typical Sputterer
Typical Sputterer
Ref: S. A. Campbell, Science and Eng. of Micro. Fab., 2001.
25
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EEL 5225, Fall 2010, David Arnold
Layer Deposition CVD
%! Chemical Vapor Deposition (CVD) %! Chemical species in vapor phase react at a surface to deposit a solid film %! Typically used for SiO2, SixNy, Si, poly Si, some metals %! Process:
1. Mass transport of reactants 2. Adsorption 6. Mass transport of products 5. Desorption
4. Reaction
3. Diffusion
Ref: http://groups.physics.umn.edu/stmlab/dmah/dmah.html
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EEL 5225, Fall 2010, David Arnold
CVD Techniques
%! Atmospheric pressure (APCVD) %! Not very common %! Low pressure (LPCVD) %! Cleaner than APCVD %! Plasma-enhanced (PECVD) %! Lower temperature and faster than LPCVD, but plasma damage %! Molecular Beam Epitaxy (MBE) %! Crystalline materials (e.g. Si, III-V materials), ultra high vacuum
27
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CVD Reactions
Material SiO2
Reaction SiH4 + O2 ! SiO2+2H2 SiCl2H2+2N2O ! SiO2+2N2+2HCl Si(OC2H5)4+12O2 ! SiO2+8CO2+10H2O SiH4+4N2O ! SiO2+4N2+2H2O 3SiH4+4NH3 ! Si3N4 + 12H2 3SiCl2H2 + 4NH3 ! Si3N4+6HCl+6H2 SiH4+NH3 ! SiNH+3H2 SiH4 ! Si + 2H2 WF6 + H2 ! W + by-products
Temperature (C) 400-450 (AP) 850-900 (LP) 650-750 (LP) 200-350 (PE) 700-900 (AP) 650-750 (LP) 200-350 (PE) 600-650 (LP) 580 (LP)
SixNy
Poly-Si W
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CVD Equipment
Typical LPCVD System Typical PECVD System
Ref: S. A. Campbell, Science and Eng. of Micro. Fab., 2001.
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CVD Details
%! Deposition Variables %! Substrate temperature %! Pressure %! Gas composition %! RF energy (PECVD) %! CVD layers are prone to pinhole defects %! Oxides not as dense %! Residual film stresses %! Compressive or tensile %! Can lead to cracking, delamination, and wafer bow
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Layer Deposition Other
%! Other Deposition Techniques %! Electroplating
%! %! %! %! %! Electrochemical process Cu, Au, Cr, Ni, Alloys Low temperature Rough surface Wet process
%! Spin casting
Ref: http://www.aesf.org/
%! Photoresist %! Polyimide %! Spin-on glass
%! Lamination %! Direct write (ink-jet)
31 Lecture 3 Fab 1
Ref: http://ssg.epfl.ch
EEL 5225, Fall 2010, David Arnold
Lithography
%! %! %! %! Overview Components Process Photoresists
Lithography
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Lithography Overview
%! Photolithography %! Process of transferring geometric patterns from a photomask to the substrate via a photoresist (a photosensitive layer)
%! %! %! Light Source Optics Photomask Photoresist Substrate
33 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
h!
Patterned Photoresist Layer
Lithography Exposure Methods
%! Shadow Printing %! Contact lithography
%! %! %!
%! Proximity lithography
Contact/Proximity
%! Projection Printing
%! %! %!
Projection
34 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Lithography Details
%! For contact/proximity:
!: wavelength g: gap between mask and wafer
(including photoresist thickness)
%! For projection:
NA: numerical aperture, usually 0.2 - 0.8 n: index of refraction for lens
"
35
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EEL 5225, Fall 2010, David Arnold
Light Sources
%! UV light from Hg lamp %! g-line ("= 436 nm) %! h-line ("= 405 nm) %! i-line ("= 365 nm) & 0.3!m
%! Excimer lasers (DUV) %! KrF ("= 248 nm) & 0.18 !m %! ArF ("= 193 nm) & 0.10 !m %! F2 ("= 157 nm) & 0.07 !m
Ref: May & Sze, Fund. Semiconductor Fabrication, pp.66
36
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Lithography Example Systems
Karl Suss MA6 Nikon NSR-S207D
%! %! %! %!
37
Contact 1:1 aligner Mask size: 100 or 125 mm Resolution: ~1m Wafer size: 75 or 100 mm
Lecture 3 Fab 1
%! Wafer Size: 200/300 mm
EEL 5225, Fall 2010, David Arnold
%! %! %! %! %!
Wavelength: 248 nm Lens-NA: 0.82 Exposure Area: 26 mm x 33 mm Reduction Ratio: 4x Resolution: < 110 nm
Lithography Photomask
%! Photomask (1:1 transfer) %! Reticle (up to 10x reduction)
Plate (transparent) Ex: Quartz, borosilicate glass, soda-lime glass
Clear Field
Pattern (opaque) Ex: Cr Anti-reflection coating
Dark Field
%! Requirements %! Flat %! High transmission %! Low coefficient of thermal expansion
38 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Masks
~15 cm x 15 cm
~6 mm thick
Ref: May & Sze, Fund. Semiconductor Fabrication, p .67
39
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EEL 5225, Fall 2010, David Arnold
Photoresist Types
%! Positive %! Photoresist image is a positive representation of mask %! %! %! %! Negative %! Photoresist image is a negative representation of mask %! %!
Positive Negative
Ref: Jaeger, Intro. Microelectronic Fabrication, p. 19.
40
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Lithography Process
START Clean wafer Dehydration bake Adhesion promoter Spin photoresist Prebake (soft-bake) Align and Expose Develop Inspect OK Post-bake (hard-bake)
41 Lecture 3 Fab 1
NOT OK
Strip resist
END
Pattern transfer
EEL 5225, Fall 2010, David Arnold
Cleanroom
%! Cleanroom Environment %! Class X: the maximum number of particles (>0.5 m) per ft3 of air
%! Typically Class 1000 or 100 %! Photolithography usually Class 10 or better %! Mask making usually Class 1 or better
%! Temperature: 70 F (21 C) %! Humidity: 45% RH
42
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EEL 5225, Fall 2010, David Arnold
Cleaning
%! Necessary for high yield %! Minimize organic and metallic contamination %! Types of contamination %! Particulates %! Organic residues %! Inorganic residues %! Metallic contamination %! Unwanted native oxide %! Sources: %! Personnel!! %! Equipment %! Process chemicals
43 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Particles
Solvent Cleans
%! Solvents are often used throughout a process to remove organic contamination, dust, etc. %! Trichloroethylene (TCE) %! Acetone %! Methanol %! Isopropyl Alcohol (IPA) %! Often used in conjunction with ultrasonic agitation
44
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Piranha Clean
%! Piranha etches almost everything except Si, SiO2, and SiN %! Purpose: remove residual organic and metallic contaminants
%! H2SO4 : H2O2 %! Typically 3:1 @ 90C, 10 min
%! VERY AGGRESSIVE %! Vigorous H2 bubbling during reaction gives name piranha
45
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
RCA RCA Clean
%! commonly used before high temperature steps %! Standard Clean 1 (SC1)
%! Oxide Etch
%! Purpose: remove residual organic and metallic contaminants %! NH4OH : H2O2 : H2O %! Typically 1:1:5 @ 75-85C, 10 m %! Purpose: remove thin oxide layer %! HF : H2O %! Typically 1:50 @ R.T., 30 s %! Purpose: remove remaining atomic and ionic contaminants %! HCl : H2O2 : H2O %! Typically 1:1:5 @ 75-85C, 10 m
%! Standard Clean 2 (SC2)
Ref.: W. Kern and D. A. Puotinen, Cleaning solutions based on hydrogen peroxide for use in silicon semiconductor technology, RCA Rev. 31, pp. 187-206 (1970).
46
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer
%! %! %! %! %! Overview Wet Etching Dry Etching Liftoff Electrodeposition
Pattern Transfer (etching)
47
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Overview
Lithography
Etching Electrodep.
Liftoff
Wet (liquid)
Dry (gas)
ADDITIVE
SUBTRACTIVE
48
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Etching
%! %! %! %! Etch rate Uniformity Selectivity Undercut/Anisotropy %! %!
Isotropic
Anisotropic
49
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Wet Etching
%! Uses %! Oxide, nitride, Si, poly Si, metals, III-V %! Cleaning %! Mechanism 1.! 1 3 2.! 3.! 2 %! Advantages Silicon substrate %! %! %! Disadvantages %! Usually only isotropic %! Fluid issues (mixing, bubbles, safety hazards, waste, etc.)
50 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Pattern Transfer Wet Etching
%! Examples %! Silicon etch
%! SiO2 etch
%! Isotropic etch: HF : HNO3 : CH3COOH HNA etch %! Anisotropic etch: KOH %! Buffered oxide etch BOE %! NH4 : HF (5:1) %! 100 nm/min etch rate at R.T. (thermal SiO2) %! Hot Phosphoric %! H3PO4 (83%) @ 180C %! ~10 nm/min etch rate at R.T. %! H3PO4 : CH3COOH : HNO3 : H2O (16:1:1:2) %! 100 nm/min at R.T.
Fab 1
%! SixNy etch
%! Al etch
PAN etch
51
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Dry Etching
%! Uses %! Oxide, nitride, Si, poly Si, metals, III-V %! Cleaning %! Mechanism 1 3 1.! Reactant transport Gas In Gas Out 2.! Chemical reaction 2 3.! Product removal %! Advantages Silicon substrate %! %! %! Disadvantages %! Often not batch process Usually vacuum chamber (0.1 100 mT) %! Gas issues (mixing, toxicity, waste, etc.) %! Cost (requires vacuum and plasma system)
52 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Dry Etching
%! Examples
Ref: Campbell, p. 266.
53
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Pattern Transfer Dry Etching
%! Plasma Basics %! Plasma fully or partially ionized gas composed of equal numbers of positive and negative particles and a different number of unionized molecules %! 4th State of Matter (99% of the universe) %! Ex: Hydrogen (1 atm)
~14K
H H H H H H H H H2
20K
H2 H2
~105
H+ e H+
H
H H
e
Solid
Liquid
Gas
Plasma
54
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Dry Etching
%! Plasma %! Mechanism: %! Selectivity: %! Directionality: %! Reactive Ion Etch (RIE) %! Mechanism: %! Selectivity: %! Directionality: %! Ion milling %! Mechanism: %! Selectivity: %! Directionality:
55 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Silicon substrate
Silicon substrate
Silicon substrate
Pattern Transfer Dry Etching
Typical Plasma Etcher Typical RIE System
Ref:http://eserver.bell.ac.uk/semicd/semi_p/topics/etch/e_eq2.htm Ref: S. A. Campbell, Science and Eng. of Micro. Fab., 2001.
56
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Conventional
%! Process %! Deposit film %! PR lithography %! Etch film %! Resist (mask layer) removed %! Advantages %! General purpose %! Disadvantages %! Need etch that is selective to film without etching PR mask or Substrate
Deposit film
PR Mask
Etch Film
Lift-off
57
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Lift Off
%! Lift Off Process (*usually only for metals) %! PR lithography %! Evaporate metal on top of resist pattern %! Remove resist, undercutting the metal %! Advantages %! No need for etching film %! Disadvantages %! Requires thicker resist (3-5x thicker than film) %! Substrate PR residues from lithography
PR mask
Deposit Film (metal)
Lift-off
58
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Pattern Transfer Electrodeposition
%! Electroplating Process %! Deposit conductive seed layer %! Lithography for PR mold %! Electroplate metal %! Remove mold %! Remove seed layer %! Advantages %! Inexpensive %! Thick layers (Solder bumps, etc.) %! Disadvantages %! Limited material selection
Seed layer
PR mold
Plate
Strip mold & seed
59
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EEL 5225, Fall 2010, David Arnold
Impurity Doping
%! Overview %! Ion Implantation %! Example
Impurity Doping
60
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EEL 5225, Fall 2010, David Arnold
Impurity Doping Overview
%! Typical Process %! Predeposition
%! Introduction of impurities via ion implantation %! Redistribution of impurities via heat treatment
%! Drive-in (optional)
N-type impurity
%! Applications %! Doping of p- and n- semiconductors %! **Ion implant used almost exclusively compared to solid- gas-source diffusion %! Precise dose/depth control
N-type impurity P-type impurity
diffusion
N-type impurity
61
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Ion Implantation
%! Kinetic bombardment of impurities into semiconductor.
Energy, E (keV) +n +n
Projected range, RP
A Ion current, I
Typical Implanter
Ref: S. A. Campbell, Science and Eng. of Micro. Fab., 2001.
62
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Ion Implantation Distribution
%! The total implant is the superposition of many of these individual stopping events
Wafer Surface
Projected Range Vertical Straggle
Ref: A. Doolittle Notes, Georgia Tech.
Lateral Straggle
63 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Ion Implantation Distribution
%! Key parameters %! Dose, Q (#/cm2), sets: %! Ion energy, E (keV), sets:
%! %! %!
%! Model for impurity distribution
Np: peak concentration (#/cm3) Gaussian distribution: = Rp , # = "Rp
64 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Ion Implantation Depth
%! Projected range (Rp) and straggle (sigma) ("Rp) for Si
Ref. Campbell, p. 108.
65
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Junction Formation
%! Junction depth, xj %! Defined as depth into silicon surface where impurity concentration (NA or ND) equals background concentration (NB) For Implant:
N
NB
0
66 Lecture 3 Fab 1
xj1
xj2
x
EEL 5225, Fall 2010, David Arnold
Ion-Implant Example
%! Ex: What is the range and straggle for phosphorous implanted at 50 keV? If a peak concentration of 1019/cm3 is desired, what is the required dose? Compute the surface concentration and the junction depth (background of 1015/cm3). Sketch the doping profile.
67
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Ion-Implant Example
%! Ex (cont.):
Rp = 62.5 nm, "Rp= 20 nm
68
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EEL 5225, Fall 2010, David Arnold
Implant Masks
%! SiO2 %! Ion implant characteristics similar to Si %! Si3N4 %! Better mask than SiO2 %! Requires only of the thickness of SiO2 %! Photoresist %! Worse mask than SiO2 %! Requires the thickness of SiO2
B+
Rp
SiO2 Q (dose)
69
Lecture 3
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EEL 5225, Fall 2010, David Arnold
Ion Implantation Details
%! Channeling %! Deep penetration of ions %! 7 beam offset %! Thin oxide protection layer (screen mask) %! Implant Damage %! Disrupts the crystalline silicon lattice %! Heat treatment (anneal) required to repair implant damage and drive-in impurities (usually > 900C)
Ref: S. A. Campbell, Science and Eng. of Micro. Fab., 2001, p.111.
Ref. Wolf and Tauber, Silicon Processing for VLSI Era I, p. 299.
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Heat Treatment
%! Overview %! Methods %! Applications %! Diffusion/Drive-In
Heat Treatment
71
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Heat Treatment Overview
%! Process by which temperature of wafer is varied to achieve specific results %! Methods: %! Furnace (resistive coil)
%! Long to medium anneal time %! Large Batch (dozens of wafers) %! Short anneal time %! Small Batch (few wafers) %! Ultra-short anneal time %! Serial (single wafer)
%! Rapid Thermal Anneal (halogen lamp)
%! Laser
%! Other
72
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EEL 5225, Fall 2010, David Arnold
Heat Treatment Applications
%! Key Applications %! Thermal Oxidation %! Diffusion/Drive-in steps %! Repair damage after ion implantation (around 900-1000C) %! Metallization contact anneal
%! Ambient depends on need for simultaneous oxidation %! Impurity redistribution occurs at Si/SiO2 interface
%! Oxide trap reduction
%! To improve metal-to-semiconductor contact resistance (around 450 C for 30 minutes) %! Usually nonoxidizing ambient (N2 or Forming Gas N2/H2 mixture) %! To reduce interface trap density in Metal-Oxide-Semiconductor Field-effect Transistors by hydrogen passivation %! Ambient is forming gas N2/H2 mixture %! Polysilicon to single-crystal silicon on silicon dioxide
Fab 1 EEL 5225, Fall 2010, David Arnold
%! Silicon-on-insulator (SOI) wafer bonding
73
Lecture 3
Heat Treatment Diffusion
%! Diffusion %! Tendency for a material that is free to move to redistribute itself to reduce a concentration gradient
Homogenous distribution Non-homogenous distribution
74
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diffusion Kinetics
%! Physics 1.! Flux proportional to concentration gradient
J(x,t): particle flux (#/cm2s) N(x,t): particle concentration (#/cm3) D: diffusion coefficient (diffusivity) (cm2/s)
2.! Gradient of flux is proportional to time rate of change of concentration (continuity equation for particle flux)
%! Ficks Diffusion Equation (or Ficks 2nd Law): %! Combining 1 and 2 yields 1-D diffusion equation:
75
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diffusivity Coefficients
%! First-order approximation
D0: constant (cm2/s) EA: activation energy (eV) k: Boltzman constant = 8.617 x 10-5 eV/K T: temperature (K)
Boron: D0 = 0.72 cm2/s EA=3.46 eV Phosphorus: D0 = 3.85 cm2/s EA=3.66 eV Arsenic: D0 = 0.066 cm2/s EA=3.44 eV %! Characteristic diffusion length Characteristic Diff. Length = (cm)
76
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diffusion Equations
%! Special Case: Drive-in %!
B.C.s: Initial condition (delta func.) Surface conc. slope Infinite conc.
x diffusion
Qi: initial dose (#/cm2) Gaussian distribution
77
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diffusion Profiles
Homogenous distribution of impurity atoms, NB=substrate bulk conc.,#/cm3
N-type impurity
Impurity incorporation of dose Q via ion implantation P-type impurity
N-type impurity
Drive-in diffusion
diffusion
N-type impurity
Ref. R. C. Jaeger, Intro. To Microelectronic Fabrication, p. 79.
78
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diffusion Profiles
With Drive-In Diffusion: %! Junction depth increases
Pre Dep Implant
Drive-in
%! Surface concentration decreases
Ref. R. C. Jaeger, Intro. To Microelectronic Fabrication, p. 79.
79
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Heat Treatment Misc
%! All heat treatments lead to further diffusion
%! Key parameters are temperature and annealing time. %! D is highly temperature-dependent & numerical simulations %! Excessive heating of Al may lead to interdiffusion of Al and Si %! Al-coated wafers limited to ~450C
80
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Drive-In Example
%! Ex: The phosphorous-implanted wafer from the previous example is subjected to a 1100C anneal for 3 hr. Compute the new surface concentration and junction depth (background of 1015/cm3). Sketch the doping profile.
81
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Drive-In Example
%! Ex (cont.):
82
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Process Flow Examples
%! Diode Process Flow %! NMOS Process Flow %! CMOS Process Flow
83
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diode Process Flow
1.! Starting material: n-type (100) silicon
n
2.!
Grow thermal oxide
n
3.!
Apply photoresist
n
4.!
Lithography (mask1)
n
84
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diode Process Flow
5.!
Ion implantation of boron
p+ n
6.!
Strip off photoresist
n
7.!
Apply photoresist
n
8.!
Lithography (mask2)
n
85
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
Diode Process Flow
9.! Ion implantation of phosphorus
n
p+
n+
10.! Strip off photoresist
n
11.! Drive-in diffusion
n
12.! Apply photoresist
n 86 Lecture 3 Fab 1 EEL 5225, Fall 2010, David Arnold
Diode Process Flow
13.! Lithography (mask3)
n
14.! Oxide etch
n
15.! Strip off photoresist
n
16.! Al deposition (e-beam or thermal evaporation)
87 Lecture 3 Fab 1
n EEL 5225, Fall 2010, David Arnold
Diode Process Flow
17.! Apply photoresist
n
18.! Lithography (mask3)
n
19.! Aluminum etch
n
20.! Strip off photoresist
n
p+
n+
Idealized pictures P
88 Lecture 3 Fab 1
Metal (Al)
N
EEL 5225, Fall 2010, David Arnold
NMOS Process Flow
a)! Grow oxide and deposit nitride
b)
Pattern nitride and implant boron for device isolation
c)
Grow oxide using nitride as oxidation mask (LOCOS).
Ref. R. C. Jaeger, Intro. To Microelectronic Fabrication, p. 7.
89
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
NMOS Process Flow
d) Grow gate oxide and deposit polysilicon gate material.
e)! Deposit oxide and pattern contact holes.
f)
Deposit and pattern metal. Sinter metal for ohmic contacts.
Ref. R. C. Jaeger, Intro. To Microelectronic Fabrication, p. 7.
90
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
CMOS Process Flow
a)! Implant and diffuse p-well.
b)
LOCOS isolation
c)
Grow gate oxide, deposit and dope polysilicon, and pattern polysilicon.
Ref. R. C. Jaeger, Intro. To Microelectronic Fabrication, p. 9.
91
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
CMOS Process Flow
d)! Implant boron for source and drain of p-channel MOSFET
e)
Implant arsenic for source and drain of n-channel MOSFET
f)
Deposit oxide, pattern contact holes, deposit aluminum, pattern metal, and sinter contacts.
Ref. R. C. Jaeger, Intro. To Microelectronic Fabrication, p. 9.
92
Lecture 3
Fab 1
EEL 5225, Fall 2010, David Arnold
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University of Florida - ECE - EEL 5225
Fabrication Technology, Part II#! Agenda $! Micromachining - Overview $! Surface Micromachining $! LIGA $! Bulk Micromachining $! Wafer Bonding $! MEMS Process Examples $! Packaging! Senturia, Ch. 3, pp. 42-50, 57-77, Ch. 4 pp. 79-98; Overview Surface M
University of Florida - ECE - EEL 5225
Lumped-Element Modeling#! Agenda $! Intro to LEM $! Lumped Assumption $! Conjugate Power Variables $! Single-Port Elements $! Circuit Connections $! Two-Port Elements ! Senturia, Ch. 5, Supplement: Tilmans papers "! HW51 Lecture 5 LEM EEL 5225, Fall 201
University of Florida - ECE - EEL 5225
Transducers#! Agenda $! Linear, Energy-Conserving Transducers $! Ex: Electrodynamic Transduction $! General Transducer Theory $! Ex: Piezoelectric Transduction $! Ex: Electrostatic Transduction $! Non-Energy Conserving Transducers ! Senturia, Ch. 6, Appe
University of Florida - ECE - EEL 5225
#! Agenda $! Stress & Strain $! Thermal Expansion $! Residual Stress $! Simple Structures $! Beams $! Plates ! Senturia, Ch. 8, Ch. 9 "! HW91 Lecture 8 MechanicsMechanicsEEL 5225, Fall 2010, David ArnoldMotivation%! Microsystems are comprised of diff
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Thermodynamics#! Agenda $! Dissipation $! Thermal Energy Domain $! Heat Transfer and Thermodynamic Concepts $! Lumped Element Modeling $! Ex: Self-Heating Resistor $! Other Dissipation Mechanisms ! Senturia, Ch. 11 "!1 Lecture 9 Thermodynamics EEL 5225,
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS Transducers Exam 2 Fall 2010 Semester Wednesday, 11/17Name: _ Honor Code: We, the members of the University of Florida community, pledge to hold ourselves and our peers to the highest standards of honesty and integrity. _ Signa
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS Transducers Exam 3 Fall 2010 Semester Tuesday, 12/14Name: _ Honor Code: We, the members of the University of Florida community, pledge to hold ourselves and our peers to the highest standards of honesty and integrity. _ Signatu
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS Transducers Exam 1 Fall 2010 Semester Monday, 10/11Name: _ Honor Code: We, the members of the University of Florida community, pledge to hold ourselves and our peers to the highest standards of honesty and integrity. _ Signatur
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW1 Fall 2010 Semester Assigned: Friday, 8/28 Due: Friday, 9/3 1. From the specification sheet for the Kulite XCS-190 (15 psi model) pressure transducer (see attached), determine the following a. Rated voltage input
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW2 Fall 2010 Semester Assigned: Friday, 9/3 Due: Monday, 9/13 1. A 0.5 m oxide is required as a dielectric layer for a MEMS device, and the furnace in your cleanroom is limited to 1000C. Using the Deal-Grove model,
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW3 Fall 2010 Semester Assigned: Monday, 9/13 Due: Wednesday, 9/22 1. You want to etch circular holes into an SiO2 layer on a silicon wafer to achieve the structure shown below. For the etch (using hydrofluoric acid)
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW4 Fall 2010 Semester Assigned: Monday, 9/27 Due: Friday, 10/1 1. A 4:1:1 HNO3 : HF : HC2H3O2 solution is used to etch silicon. How long would it take to etch a hole all the way through a 500 m-thick wafer?For 4:1:
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW5 Fall 2010 Semester Assigned: Wednesday, 10/13 Due: Monday, 10/25 1. The deflection curve for a clamped-clamped beam is given by, w ( x ) =pl 4 x 2 x 3 x 4 2 2 3 + 4 . 2 Eh 3 l l l Using the center deflection, w
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW6 Fall 2010 Semester Assigned: Monday, 10/25 Due: Monday, 11/1 1. Consider the gear system shown below, with input angular velocity, 1. Draw and completely label an appropriate equivalent circuit model for the syst
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW7 Fall 2010 Semester Assigned: Thursday, 11/4 Due: Wednesday, 11/10 1. Some details on general two-port theory a. Prove that the units of TEM and TME in the linear transducer model are the same. b. Derive the follo
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW8 Fall 2010 Semester Assigned: Friday, 11/12 Due: Friday, 11/19 1. A sensor design calls for a piezoresistor rotated 30 from the <100> direction on a (100) wafer. a.) Sketch the piezoresistor on a wafer, indicating
University of Florida - ECE - EEL 5225
EEL5225 Principles of MEMS TransducersHW9 Fall 2010 Semester Assigned: Monday, 12/6 Due: Monday, 12/13 1. The following two questions relate to residual stress. a.) Explain why thermally grown oxide is compressive, and estimate the stress (at room temp.)
University of Florida - ECE - Biomedical
Lecture 0: Introduction EEL 6935 Analog and Mixed-Signal Electronics for Biomedical ApplicationsFall 2010 Section: 7812 Course Outline In vivo biomedical devicesPractical Information Instructor Rizwan Bashirullah Office: 527 NEB, E-mail: rizwan@ufl.ed
University of Florida - ECE - Biomedical
Lecture 2: Simple Amplifier Review Amplifier Gain and DC bias Amplifier Models STC circuits Amplifier frequency responseAmplifier Amplifier Circuit SymbolTo amplify means to multiply by constantVo=Av x Vi Av is the gain Vo cannot increase indefinitel
University of Florida - ECE - Biomedical
Lecture 3: Opamp Review Inverting amplifier Generalized impedances Inverting integrator Inverting differentiator Weighted summer Non-inverting amplifier Voltage buffer Non-linear amplifiersFirst, assume ideal op amp.Basic Opamp Op amp is a circuit
University of Florida - ECE - Biomedical
Lecture 4: Opamp Review Effect of finite open-loop gain, A Frequency dependence of open-loop gain Frequency dependence of closed-loop gain Output voltage and current saturation Output slew rate Offset voltage Input bias and offset current Non-zero output
University of Florida - ECE - EEL6323
Lecture 5: Logical Effort Logical Effort (g, h, p) ExamplesIntroductionChip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be?
University of Florida - ECE - EEL6323
Lecture 6: Multistage Logic Networks Multistage Logic NetworksMultistage Logic Networks Path Logical Effort Reading: Ch. 410 g1 = h1 = x g2 = h2 = y g3 = h3 = z g4 = h4 =20Multistage Logic Networks Path Electrical EffortMultistage Logic Networks
University of Florida - ECE - EEL6323
Lecture 7: Multistage Logic Networks Multistage Logic Networks (cont. from Lec 06) Examplesx x A 8 xExample: 3-stage pathy 45 y BSelect gate sizes x and y for least delay from A to B45 Reading: Ch. 4Logical Effort Electrical Effort Branching Effor
University of Florida - ECE - EEL6323
Hierarchy of design abstractionsOverview of Digital IC Design FlowState Charts/UML/ SystemC/SystemVerilog C,C+/VHDL/Verilog Matlab/SystemCSpecification Behavior (Algorithm)System designVHDL/Verilog Register-Transfer (Arch.)VHDL/Verilog/EDIFFront-en
University of Florida - ECE - EEL6323
3. Logic Synthesis Use a HDL (VHDL or Verilog) and a synthesis tool to produce a gate-level netlist a description of the logic cells and their connections.Synthesis is Constraint-DrivenTechnology IndependentLogic Synthesis Overview1Logic Synthesis I
University of Florida - ECE - EEL6323
Todays Lecture Part I: Digital IC Design Tools Tutorials(1) RTL Simulation Cadence NCSim (2) Logic Synthesis Synopsys Design Compiler (3) Physical Implementation Cadence SOC EncounterNCLaunch Tutorial (1/12) Log in to your ECEL account. Create a desig
University of Florida - ECE - EEL6323
Lecture 11: Circuit Simulations Circuit Characterization (Brief)IV curves: Basic Shapes IDS vs VDS (two regions) Linear (Low VDS) Effective Resistance Saturated (High VDS) Current, gm, gds Reading: Ch. 5 IDS vs VGS Linear IDS (above threshold) Log
University of Florida - ECE - EEL6323
Lecture 12: Power Dissipation Power and Energy Dynamic Power Static Power LeakagePower and EnergyPower is drawn from a voltage source attached to the VDD pin(s) of a chip.Instantaneous Power: Energy: Average Power:P(t ) iDD (t )VDDE P (t )dt iDD (t
University of Florida - ECE - EEL6323
Lecture 13: Low Power Design Notes: J. Rabaey, A. Chandrakasan, B. Nikolik, Digital Integrated Circuits: A Design Perspective, 2nd ed. Printice Hall 2003. Shekhar Borkar, Intel Corporation, Digital Design for Low Power SystemsThe Importance of Power Aw
University of Florida - ECE - EEL6323
Lecture 14: Power Dissipation Low Power Design Throughput oriented design Clock gating Leakage reduction techniques Multi-processing trendsTypes of Processing Fixed-rate Processing (i.e. Signal processing for multimedia or communications) Stream base
University of Florida - ECE - EEL6323
Lecture 15: Circuit Families Static CMOS and Compound Gates Asymmetric Gates Pseudo-nMOS Logic CVSL, PTL, LEAP, CPLBubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic Remember DeM
University of Florida - ECE - EEL6323
Lecture 16: Circuit Families Dynamic Logic Dynamic Noise Dynamic KeepersDynamic Logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate2 A 1 Static Y2/3 Y A 4/3 Y A1 Y 1Pseudo-nMOSPrechargeDynamicEvaluate PrechargeFoo
University of Florida - ECE - EEL6323
Lecture 17: Adders Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Select Adder Carry-Lookahead Adder Tree Adder Half AdderS =AB Cout = ABCout ASingle-Bit AdditionBFull AdderS= Cout =CoutAB C SSA 0 0 1 1B 0 1 0 1Cout SA 0 0 0
University of Florida - ECE - EEL6323
Lecture 18: Adders Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Select Adder Carry-Lookahead Adder Tree AdderCarry Generation and PropagationDefine 3 new variables that depend only on A and B Generate: Cout = 1 independent of C G=AB S
University of Florida - ECE - EEL6323
Lecture 19: Datapaths Multipliers Shifters Comparators Counters LFSRs Example:Multiplication1100 : 1210 0101 : 510 1100 0000 1100 0000 00111100 : 6010 multiplicand multiplier partial products product M x N-bit multiplication Produce N M-bit partial p
University of Florida - ECE - EEL6323
Lecture 20: Clock Distribution Clock distribution trends Distribution networks Clock Power Clock Skew Timing DefinitionsClocking Synchronous systems use a clock to keep operations in sequence Distinguish this from previous or next Determine speed at w
University of Florida - ECE - EEL6323
Lecture 21: Sequential Circuits Sequencing Elements Simple Latch/FF Timing Definitions SequencingUse flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Sequencing overhead
University of Florida - ECE - EEL6323
Lecture 22: Sequential Circuits Setup and Hold time MS FF Power PC Pulsed FF HLFF, SDFF, SAFFReview: Timing Definitions TCQ: Propagation Delay from Ck to Q, assuming D has been set early enough relative to Ck Tsetup (U): minimum time between D change a
University of Florida - ECE - EEL6323
Lecture 23: Process variations Process Variations Process Independent TechniquesProcess Corners Process corners describe worst case variations If a design works in all corners, it will probably work for any variation. Transistors have uncertainty in
University of Florida - ECE - EEL6323
Lecture 24: Input/Output (IOs) Input/Output System functions Communicate between chip and external world Drive large capacitance off chip Operate at compatible voltage levels Provide adequate bandwidth Limit slew rates to control di/dt noise Protect chi
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IUPUI - ME - 200
Excerpts from this work may be reproduced by instructors for distribution on a not-for-profit basis for testing or instructional purposes only to students enrolled in courses for which the textbook has been adopted. Any other reproduction or translation o
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