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EEL6935-F10-HLec02-opamps-2spp

Course: ECE Biomedical, Fall 2010
School: University of Florida
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2: Lecture Simple Amplifier Review Amplifier Gain and DC bias Amplifier Models STC circuits Amplifier frequency response Amplifier Amplifier Circuit Symbol To amplify means to multiply by constant Vo=Av x Vi Av is the gain Vo cannot increase indefinitely 1 Amplifier with supply rails To explicitly show the supply voltages, VCC and VEE are shown. In some cases, VEE is zero. Linear and non-linear...

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2: Lecture Simple Amplifier Review Amplifier Gain and DC bias Amplifier Models STC circuits Amplifier frequency response Amplifier Amplifier Circuit Symbol To amplify means to multiply by constant Vo=Av x Vi Av is the gain Vo cannot increase indefinitely 1 Amplifier with supply rails To explicitly show the supply voltages, VCC and VEE are shown. In some cases, VEE is zero. Linear and non-linear regions of operation Amplifier Gain and DC Bias Vi(t)=VI+vi(t) Total instantaneous signal DC bias 2 Amplifier Gain Voltage Gain: Av = Vo VI (dB) 20log Av dB i Current Gain : Ai = o iI (dB) 20log Ai dB Power Gain: Ap =Av AI (dB) 10log ApdB Note: multiplication of two numbers is equivalent to adding their logarithms AP (dB ) 1 AV (dB) AI (dB) 2 A few words about dB When is the Gain in dB a negative number? Inverting amplifier (180 degrees phase difference between input and output) Or when the amplifier is attenuating dB is unitless: 20log (V/V) or 20log (I/I) or 10log(W/W) Find the log of 0.1, 1, 10 , 100 -10dB, 0dB, 20dB, 40dB If the gain is -6dB, what is the gain in V/V? -6dB=20log(x) -> x=10-6/20 = 0.5 If gain is -3dB, what is the gain in V/V? -6dB=20log(x) -> x=10-3/20 = 0.707 (i.e. 3 dB BW, Half Power). Why? 0.7072 = 0.5 Power = 10 log (p), Voltage = 20 log (v) but power prop to voltage squared. Addition in dB is multiplication of term inside (): 40dB + 6dB = 46dB = 100x2=200 3 Amplifier Models Voltage Amplifier Current Amplifier Transconductance Amplifier Tranresistance Amplifier 1. Voltage Amplifier Voltage controlled voltage source (VCVS) Av = open circuit voltage gain o Vo Vi V V io 0 Ri= input resistor Ro= output resistor 4 With Signal and Load Ri Vi Vs Ri Rs Vo Avo Vi RL RL Ro Find overall Gain Ri high, Ro low Unity Gain Av = 1 o Ri RL Vo Av Ri Rs R L Ro Vs o Voltage Buffer Amp 2. Current Amplifier Model current controlled current source (CCCS) Ais = Short Circuit Current Gain io ii A A Vo 0 Current Buffer Amp Ri low, Ro high Unity gain, Ais = 1 5 3. Transconductance Amp Model voltage controlled current source (VCCS) Gm = Short Circuit Transconductance io Vi A V Vo 0 4. Transresistance Amp Model current controlled voltage source (VCVS) Rm = Open Circuit Transresistance Vo ii V A io 0 6 High Frequency Roll-off of an Amplifier As frequency of operation increases, the gain of amplifier decreases. This chapter analyzes this problem. Example: Human Voice I Natural Voice Telephone System Natural human voice spans a frequency range from 20Hz to 20KHz, however conventional telephone system passes frequencies from 400Hz to 3.5KHz. Therefore phone differs conversation from face-to-face conversation. 7 Example: Human Voice II Path traveled by the human voice to the voice recorder Mouth Air Recorder Path traveled by the human voice to the human ear Mouth Air Ear Skull Since the paths are different, the results will also be different. Example: Video Signal High Bandwidth Low Bandwidth Video signals without sufficient bandwidth become fuzzy as they fail to abruptly change the contrast of pictures from complete white into complete black. 8 Frequency Response of Amplifiers Frequency Response of Amplifiers Assumptions: Linear amplifier Small signal analysis Given: Sinusoidal input vi (t ) Vi sin t Output is: VO (t ) VO sin(t ) Ref. Sedra and Smith, Figure 1.20 Amplifier frequency response: Amp bandwidth: band of frequencies over which gain is almost constant (typically 3dB) 1 to 2 Ref. Sedra and Smith, Figure 1.21 Frequency Response Analysis Review of Single Time-Constant Networks Circuits that can be reduced to one reactive component (capacitance or inductance) and one resistive component Low Pass Filter High Pass Filter Ref. Sedra and Smith, Figure 1.22 9 Find Magnitude and Phase Voltage Amplifier with Input Ci Example: Effect of input capacitance A V0Vi Find the amplifier voltage transfer function, DC gain, and high frequency roll-off. Ref. Sedra and Smith, Figure 1.25 10 Analysis Voltage divider at input Vi ( s ) Voltage divider at output Vo ( s ) Overall amplifier transfer function T (s) Vo ( s ) Vi ( s ) Frequency Response Example 1.5 Rs 20k , Ri 100k , Ci 60 pF A V0 V 144 , Ro 200, RL 1k V 0 -10 -20 DC gain: 1 1 K A V0 R R 1 o 1 s RL Ri -30 0.1 1 10 Direct-coupled High frequency rolloff: 0 1 1 Ci RS // Ri 11 Gain Roll-off: Common Source The capacitive load, CL, is the culprit for gain roll-off since at high frequency, it will steal away some signal current and shunt it to ground. At low frequency, the capacitor is effectively open and the gain is flat. As frequency increases, the capacitor tends to a short and the gain starts to decrease. A special frequency is =1/(RDCL), where the gain drops by 3dB. 1 Vout g mVin RD || CL s Identify the poles 12 Identify the poles Relationship between Frequency Response and Step Response The relationship is such that as R1C1 increases, the bandwidth drops and the step response becomes slower. H s j t Vout t V0 1 exp u t R1C1 R12C12 2 1 1 13 Examples: Amplifier Frequency Response Capacitively coupled ac-amplifier Lower Corner Direct-coupled dc-amplifier Upper Corner Tuned or bandpass amplifier Ref. Sedra and Smith, Figure 1.26 14
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University of Florida - ECE - Biomedical
Lecture 3: Opamp Review Inverting amplifier Generalized impedances Inverting integrator Inverting differentiator Weighted summer Non-inverting amplifier Voltage buffer Non-linear amplifiersFirst, assume ideal op amp.Basic Opamp Op amp is a circuit
University of Florida - ECE - Biomedical
Lecture 4: Opamp Review Effect of finite open-loop gain, A Frequency dependence of open-loop gain Frequency dependence of closed-loop gain Output voltage and current saturation Output slew rate Offset voltage Input bias and offset current Non-zero output
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University of Florida - ECE - EEL6323
Lecture 6: Multistage Logic Networks Multistage Logic NetworksMultistage Logic Networks Path Logical Effort Reading: Ch. 410 g1 = h1 = x g2 = h2 = y g3 = h3 = z g4 = h4 =20Multistage Logic Networks Path Electrical EffortMultistage Logic Networks
University of Florida - ECE - EEL6323
Lecture 7: Multistage Logic Networks Multistage Logic Networks (cont. from Lec 06) Examplesx x A 8 xExample: 3-stage pathy 45 y BSelect gate sizes x and y for least delay from A to B45 Reading: Ch. 4Logical Effort Electrical Effort Branching Effor
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University of Florida - ECE - EEL6323
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University of Florida - ECE - EEL6323
Todays Lecture Part I: Digital IC Design Tools Tutorials(1) RTL Simulation Cadence NCSim (2) Logic Synthesis Synopsys Design Compiler (3) Physical Implementation Cadence SOC EncounterNCLaunch Tutorial (1/12) Log in to your ECEL account. Create a desig
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University of Florida - ECE - EEL6323
Lecture 12: Power Dissipation Power and Energy Dynamic Power Static Power LeakagePower and EnergyPower is drawn from a voltage source attached to the VDD pin(s) of a chip.Instantaneous Power: Energy: Average Power:P(t ) iDD (t )VDDE P (t )dt iDD (t
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University of Florida - ECE - EEL6323
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University of Florida - ECE - EEL6323
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