23: Lecture Process variations
Process Variations Process Independent Techniques
Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably work for any variation.
Transistors have uncertainty in parameters
Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values
Gate oxide thickness Mobility Gate length Threshold voltages Doping levels Parameter spread
Parameter Variation
Describe corner with four letters (T, F, S)
nMOS speed pMOS speed Voltage Temperature
PMOS
Environmental Variation
VDD and T also vary in time and space Fast:
VDD: high T: low Corner F T S Voltage 1.98 1.8 1.62
fastP/slowN
fastP/fastN
Fast (F)
Leff: short Vt: low tox: thin
Temperature 0C 70 C 125 C
Some critical simulation corners include
slowP/slowN slowP/fastN
NMOS
Purpose Cycle time Power
nMOS S F
pMOS S F
VDD S F
Temp S F
Slow (S): opposite
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Process Dependent Clock Skew in CMOS VLSI
NI (Non-inverting)
Example process of spread and delay variation
Process High current (H) NFET delay ratio 88ps 0.556 158ps 273ps 1.0 1.73 PFET delay ratio 201ps 0.62 325ps 530ps 1.0 1.63
I (inverting)
Multiple clock grids Power down when not used
Nom. current (M) Low. current (L)
D (Decoded/Clock Gated) How to account for skew with process spread?
Timing waveforms
Delay for fastN and fastP
TA changes by a factor fN >1 TB changes by a factor fP >1
TB(H)=TB(1/fP), TA(H)=TA(1/fN), 1/fN=NMOS ratio=0.556
1/fP=PMOS ratio=0.62
Design carried out assuming nominal parameters Consider what happens when same circuit is processed by (fastN-fastP) high current process
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Conditions for zero skew (1)
Skew=TI(H)-TNI(H)=0 if
T2=TB or fN=fP
Conditions for zero skew (2)
Case (2)
TB=T2 (pull down delays) TA+TC=T1 (pull-up delays)
Case (1) fN=fP
Sum of pull down delays of 1st chain = sum of pulldown delays of 2nd logic chain Sum of pull up delays of 1st chain = sum of pull-up delays of 2nd logic chain
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