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Course: ELECTRONIC 313, Spring 2011
School: Hacettepe Üniversitesi
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UNIVERSITY DEPARTMENT HACETTEPE OF ELECTRICAL AND ELECTRONICS ENGINEERING ELE-314 ELECTRONICS LABORATORY III EXPERIMENT 5 COLLECTOR COUPLED MONOSTABLE/ASTABLE MULTIVIBRATOR 1. PURPOSE: To analyse the collector coupled monostable and astable multivibrators. 2. THEORY : There are three types of multivibrators, known as monostable, bistable and astable multivibrators. 2.1. MONOSTABLE MULTIVIBRATORS In this part the...

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UNIVERSITY DEPARTMENT HACETTEPE OF ELECTRICAL AND ELECTRONICS ENGINEERING ELE-314 ELECTRONICS LABORATORY III EXPERIMENT 5 COLLECTOR COUPLED MONOSTABLE/ASTABLE MULTIVIBRATOR 1. PURPOSE: To analyse the collector coupled monostable and astable multivibrators. 2. THEORY : There are three types of multivibrators, known as monostable, bistable and astable multivibrators. 2.1. MONOSTABLE MULTIVIBRATORS In this part the monostable multivibrator will be examined. Monostable multivibrators are mainly used in delaying and extending the duration of a pulse. If an external trigger is not applied, the monostable is at its stable state. When it is triggered externally, it switches to a quasi-stable state. Figure 1. Typical monostable multivibrator with discrete components. For the circuit shown above, Vcc=10V, assume VBEsat=0.6V, VCEsat=0.2V, =125. After a period of time determined by R and C (see fig.1) it returns to its stable state. As long as a trigger is not applied to the input, the circuit remains at stable state. A monostable multivibrator is depicted in fig.1. In stable state the base current of transistor T2 which flows through the supply and R is sufficient to force T2 into saturation. The collector-emitter saturation voltage VCEsat of T2 is coupled through Rf to the base of T1 and hence T1 is OFF. Therefore VC1 = Vcc. This state, i.e. when T1 is OFF and T2 is SAT, is the stable state and the circuit remains at this state unless an external trigger is applied. Assume that the circuit is at stable state at t=0- , and at t=0+ , an external trigger pulse brings the circuit to the quasi-stable state. At t = 0- , VC1 (0-) = Vcc and VB2(0-) = VBE2sat the capacitor is, VS1(0-) = Vcc - VBE2sat . and the voltage across At t = 0+ T1 becomes ON by the impulse applied to the base of T1. This pulse is amplified and inverted by T1, and coupled to the base of T2 through the capacitor C. If it is sufficiently negative T2 will be OFF and VC2 will be equal to Vcc. Since this voltage is coupled through R to B1 (base of T1) T1 will be saturated. However, this state (T1 is saturated and T2 is off) has a finite duration. This is how the monostable circuit is used in modern electronic circuits. At t = 0+ , VC2 (0+)= Vcc , VC1(0+)=VCE1sat and VB2(0+)= - [Vcc - VBE2sat - VCE1sat ] . At this instant B2 is as negative as VB2 (0+ ). The capacitor will charge to Vcc with a time constant = RC, therefore VB2 will increase exponentially. VB2(t)= [-Vcc +VBE2sat +VCE1sat -Vcc ] e -t/ +Vcc (1) When VB2 is 0.6V, T2 is initially active and then immediately saturated. This time is represented by Ts and given as, Ts = ln2 = 0.69 R C (2) The circuit stays at stable state until a new trigger pulse is applied. Everything repeats with the application of a new trigger . Refer to Fig.2. Ts=ln(2)RC=0.69RC Figure 2. Monostable multivibrator with periodic input waveform. 2.2. ASTABLE MULTIVIBRATORS: In these circuits both states are quasi-stable and hence the circuit switches from one to another state in the absence of an external trigger. In digital systems these circuits are used to obtain periodic pulse trains. The durations of two quasi-stable states can be adjusted independently. A collector coupled astable multivibrator is depicted in fig.3. VCC=10 V R2 R1 R3 R4 C2 C1 T1 T2 Figure 3 The circuit is symmetric and continuously changes states. The reason for this state change is the same as the one described in the monostable multivibrator, due to the symmetry this phenomenon occurs at both stages of the circuit. Assume that the circuit has changed at state t=0, and T1 is SAT and T2 is OFF. Then VC1(0-) = Vcc ; VB2(0-) = VBE2SAT ; and the voltage VS1 on the capacitor C1 VC1(0+) = VCE1SAT VS1(0- ) = Vcc - VBE2SAT VC1 VCC VCE1SAT VB2 0 TS TS+ TR t VBE2SAT t S = R1C1 VC2 TS = 0.69R1C1 TR = 0.69R3C2 VCC 2 = R4C2 VCE2SAT t VB1 VBE1SAT R = R3C2 t Figure 4 The voltage at B2 (base of T2) is VCE1SAT - VS1(0-) at t = 0+. Hence T2 is OFF. The voltage VB2 increases with a time constant S = R1C1 and T2 eventually becomes SAT. The elapsed time TS is 0.69 R1C1. Meanwhile, since T2 is OFF, VC2 = Vcc and since T1 is SAT, VC1 = VCE1SAT. In the time interval 0 < t < TS only VB2 is changing. When VBE2(t) reaches 0.6V, T2 becomes initially ACTIVE and immediately SAT. The voltages at instant TS are : VC2(TS-) = Vcc ; VB1(TS-) = VBE1SAT ; and the voltage VS2 on the capacitor C2 VC2(TS+) = VCE2SAT VS2(TS-) = Vcc - VBE1SAT Since VB1(TS+) = VCE2SAT - VS2(TS-) < 0, T1 is now OFF. VB1 increases with a time constant R = R3C2, and when VB1 = 0.6V, the circuit changes state. VB1 reaches 0.6V in a time interval TR = 0.69R3C2. When the transistors are saturated their collector voltages immediately decrease to VCESAT. However, when they are OFF, the collector voltages do not immediately rise to Vcc because the collector voltages increase with a certain time constant as shown in fig.4 and fig.5. VCC R3 VCC R4 C2 R2 T2 VBE1SAT R1 C1 T1 VBE2SAT Figure 5a. T1 in SAT, T2 at cut-off Figure 5b. T1 at cut-off, T2 in SAT When T2 is OFF, C2 charges through R4 and VC2 reaches Vcc with a time constant 2=R4C2. When T1 is OFF, C1 charges through R2 and VC1 reaches Vcc with a time constant 1=R2C1. In order to obtain sharp rising pulses at the collectors, the collectors of the OFF transistors have to be isolated from the corresponding capacitors. This can be achieved by using diodes and resistors as shown in fig.6. VCC = 10 V R2 T1 R5 R1 R3 R6 R4 C2 C1 T2 Figure 6 When the transistors are SAT currents through R5 and R6 force the diodes to be ON, and hence the collectors are connected to the capacitors. However, when the transistors become OFF, the diodes are reverse biased and they are OFF, hence, the collectors are isolated from the capacitors. The collector voltages, therefore, immediately rise to Vcc. The capacitors now charge through R5 and R6 , and their voltages can reach to steady state values during the pulse duration if the following inequalities are satisfied. R5C1 << R3C2 R6C2 << R1C1 3.1. PRELIMINARY WORK 3.1.1. Draw the waveform of VC2 (t), VB2 (t), VC1(t) for a 500 Hz square wave input in fig.1 (take R1= 15K, R2 = 1K, R = Rf = 47K, C = 10nF). 3.1.2. How can we change the pulse duration at the output ? 3.1.3. What is the method of choosing R1 and R3 if the resistors R2 and R4 are fixed in fig.3? (Note that saturation of the transistors depends on the values of R1 and R3) 3.1.4. If R2 =R4 =2.2K and R1 =R3 =47K, what must the values of C1 and C2 be so that TS =0.16msec and TR =0.33msec? 3.1.5. With the values of C1 and C2 you determined above, sketch VB2(t), VC2(t), VC1(t) and VB1(t) indicating the times and amplitudes. 3.1.6. Discuss how you can modify the ratio TR / TS . 3.1.7. Do the Pspice simulations of step 3.1.1 for three different frequencies of square wave 500Hz, 1kHz and 2kHz. 3.1.8. Do the Pspice simulation by setting up the circuit shown in fig. 3 and use component values given in step 3.1.4. 3.1.9. Do the Pspice simulation by setting up the circuit shown in fig. 6. Use component values given in step 3.1.4. and R5 =R6 =2.2K.
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