749 ELE Lecture 01: Introduction
Ali Ziya Alkar
[Adapted from Computer Organization and Design, Patterson & Hennessy, 2005, UCB]
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Course Administration
Instructor: Office Hrs: Labs: URL: Text: Ali Ziya Alkar [e-mail] Fridays 13:30-15:00 VLSI Laboratory http://www.ee.hacettepe.edu.tr/~alkar/ELE749 Required: Computer Org and Design, 3rd Edition, Patterson and Hennessy 2005 Optional: Superscalar Microprocessor Design Johnson, 1991 pdf on the course web page after lecture
Slides:
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Grading Information
Grade determinates
Midterm Exam
- Date To be determined
~30% ~30% ~30%
Final Exam
- TBD
Homeworks (3-4)
- Due at the beginning of class (or, if its code to be submitted electronically, by 17:00 on the due date). No late assignments will be accepted.
Class participation & pop quizzes
~10%
Grades will be posted on the course homepage
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Course Content
Content
Principles of computer architecture: CPU datapath and control unit design (single-issue pipelined, superscalar, VLIW), memory hierarchies and design, I/O organization and design, advanced processor design (multiprocessors and SMT)
Course goals
To learn the organizational paradigms that determine the capabilities and performance of computer systems. To understand the interactions between the computer's architecture and its software so that future software designers (compiler writers, operating system designers, database programmers, ...) can achieve the best cost-performance trade-offs and so that future architects understand the effects of their design choices on software applications.
Course prerequisites
ELE413 and/or ELE414 and ELE 313 Digital Electronics
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What You Should Know
Basic logic design & machine organization
logical minimization, FSMs, component design processor, memory, I/O
Create, assemble, run, debug programs in an assembly language
MIPS?
Create, simulate, and debug hardware structures in a hardware description language
VHDL or verilog
Create, compile, and run C (C++, Java) programs Unix/Linux?
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Course Structure
Design focused class
Some homework assignments throughout the semester Simulation of architecture alternatives using SimpleScalar
Lectures:
2 weeks review of the MIPS ISA and basic architecture 2 weeks pipelined datapath design issues 3 weeks superscalar/VLSI datapath design issues 2 week memory hierarchies and memory design issues 2 weeks I/O design issues 2 weeks multiprocessor design issues 1 week exams
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How Do the Pieces Fit Together?
Application Operating System Compiler Memory system Firmware Instruction Set Architecture I/O system
Instr. Set Proc. Datapath & Control Digital Design Circuit Design
Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation
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How Do the Pieces Fit Together?
Application Operating System Compiler Memory system Firmware Instruction Set Architecture I/O system
Instr. Set Proc. Datapath & Control Digital Design Circuit Design
Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation
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Where is the Market?
Embedded Desktop Servers
1200
Millions of Computers
1122 892 862
1000 800 600 400 290 200 0 93 3 1998 114 3 1999 488
135 4 2000
129 4 2001
131 5 2002
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By the architecture of a system, I mean the complete and detailed specification of the user interface. ... As Blaauw has said, "Where architecture tells what happens, implementation tells how it is made to happen." The Mythical Man-Month, Brooks, pg 45
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Instruction Set Architecture (ISA)
ISA: An abstract interface between the hardware and the lowest level software of a machine that encompasses all the information necessary to write a machine language program that will run correctly, including instructions, registers, memory access, I/O, so and on.
"... the attributes of a [computing] system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls, the logic design, and the physical implementation." Amdahl, Blaauw, and Brooks, 1964 Enables implementations of varying cost and performance to run identical software
ABI (application binary interface): The user portion of the instruction set plus the operating system interfaces used by application programmers. Defines a standard for binary portability across computers.
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ISA Type Sales
Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM
1400 1200
Millions of Processor
1000 800 600 400 200 0 1998 1999 2000 2001 2002
PowerPoint "comic" bar chart with approximate values (see text for correct values)
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Moore's Law
In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i.e., grow exponentially with time).
Amazingly visionary million transistor/chip barrier was crossed in the 1980's.
2300 transistors, 1 MHz clock (Intel 4004) - 1971 16 Million transistors (Ultra Sparc III) 42 Million transistors, 2 GHz clock (Intel Xeon) 2001 55 Million transistors, 3 GHz, 130nm technology, 250mm2 die (Intel Pentium 4) - 2004 140 Million transistor (HP PA-8500)
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Processor Performance Increase
10000 Performance (SPEC Int)
Intel Pentium 4/3000 DEC Alpha 21264A/667 DEC Alpha 21264/600 Intel Xeon/2000 DEC Alpha 5/500 DEC Alpha 5/300
1000
DEC Alpha 4/266
100
DEC AXP/500
IBM POWER 100
10
HP 9000/750 IBM RS6000 MIPS M2000 MIPS M/120
1989 1991 1993 1995 1997 1999 2001 2003
SUN-4/260
1
1987
Year
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DRAM Capacity Growth
1000000 100000 Kbit capacity
16M 64M 512M 256M 128M
10000
1M
4M
1000 100
16K 64K
256K
10
1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year of introduction
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Impacts of Advancing Technology
Processor
logic capacity: performance: increases about 30% per year 2x every 1.5 years
Memory
DRAM capacity: 4x every 3 years, now 2x every 2 years memory speed: cost per bit: 1.5x every 10 years decreases about 25% per year
Disk
capacity:
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increases about 60% per year
Impacts of Advancing Technology
Processor
logic capacity: performance: increases about 30% per year 2x every 1.5 years ClockCycle = 1/ClockRate
500 MHz ClockRate = 2 nsec ClockCycle 1 GHz ClockRate = 1 nsec ClockCycle 4 GHz ClockRate = 250 psec ClockCycle
Memory
DRAM capacity: 4x every 3 years, now 2x every 2 years memory speed: cost per bit: 1.5x every 10 years decreases about 25% per year
Disk
capacity:
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increases about 60% per year
Example Machine Organization
Workstation design target
25% of cost on processor 25% of cost on memory (minimum memory size) Rest on I/O devices, power supplies, box
Computer CPU Control Datapath Memory Devices Input Output
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PC Motherboard Closeup
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Inside the Pentium 4 Processor Chip
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Example Machine Organization
TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20
SuperSPARC Floating-point Unit Integer Unit L2 $ CC MBus DRAM Controller MBus Module
Inst Cache
Ref MMU
Data Cache Store Buffer
L64852 MBus control
M-S Adapter STDIO
serial kbd mouse audio RTC Boot PROM Floppy
SBus
SBus
DMA
SCSI Ethernet
Bus Interface
SBus Cards
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MIPS R3000 Instruction Set Architecture
Instruction Categories
Load/Store Computational Jump and Branch Floating Point
coprocessor PC HI LO Registers R0 - R31
Memory Management Special
3 Instruction Formats: all 32 bits wide OP OP OP rs rs rt rt rd sa
funct
immediate
jump target
Q: How many already familiar with MIPS ISA?
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Next Lecture and Reminders
Next lecture
MIPS ISA Review
- Reading assignment PH, Chapter 2
Reminders
HW1 out next lecture,
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