749 ELE Lecture 02: MIPS
Ali Ziya Alkar [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005, UCB] + Mary Jane Irwin @ Penn State
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(vonNeumann) Processor Organization
Control needs to
1. 2.
CPU Control Datapath
Memory
Devices Input Output
input instructions from Memory issue signals to control the information flow between the Datapath components and to control what operations they perform control instruction sequencing
Fetch
3.
Datapath needs to have the
Exec
Decode
components the functional units and storage (e.g., register file) needed to execute instructions interconnects - components connected so that the instructions can be accomplished and so that data can be loaded from and stored to Memory
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For a given level of function, however, that system is best in which one can specify things with the most simplicity and straightforwardness. Simplicity and straightforwardness proceed from conceptual integrity. Ease of use, then, dictates unity of design, conceptual integrity. The Mythical Man-Month, Brooks, pg 44
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RISC - Reduced Instruction Set Computer
RISC philosophy
fixed instruction lengths load-store instruction sets limited addressing modes limited operations
MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq) Alpha, Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memory space (embedded systems)
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MIPS R3000 Instruction Set Architecture (ISA)
Instruction Categories
Computational Load/Store Jump and Branch Floating Point
coprocessor PC HI LO Registers R0 - R31
Memory Management Special
3 Instruction Formats: all 32 bits wide OP OP OP
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rs rs
rt rt
rd
sa
funct
R format I format J format
immediate
jump target
Review: Unsigned Binary Representation
Hex
0x00000000 0x00000001 0x00000002 0x00000003 0x00000004 0x00000005 0x00000006 0x00000007 0x00000008 0x00000009 0xFFFFFFFC 0xFFFFFFFD 0xFFFFFFFE 0xFFFFFFFF
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Binary
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 11100 11101 11110 11111
Decimal
0 1 2 3 4 5 6 7 8 9 232 - 4 232 - 3 232 - 2 232 - 1
231 230 229 31 30 29 ... ... 23 22 21 3 2 1 20 0 bit weight bit position
111
...
1111
bit
1000
...
0000
-
1
232 - 1
Aside: Beyond Numbers
American Std Code for Info Interchange (ASCII): 8-bit bytes representing characters
ASCII Ch ar ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char
0 1 2 3 4 5 6 7 8 9 10 11 12 15
Null
32 33 34 35
space ! # $ % & ( ) * + , /
48 49 50 51 52 53 54 55 56 57 58 59 60 63
0 1 2 3 4 5 6 7 8 9 : ; < ?
64 65 66 67 68 69 70 71 72 73 74 75 76 79
@ A B C D E F G H I J K L O
96 97 98 99 100 101 102 103 104 105 106 107 108 111
` a b c d e f g h i j k l o
112 113 114 115 116 117 118 119 120 121 122 123 124 127
p q r s t u v w x y z { | DEL
EOT ACK bksp tab LF FF
36 37 38 39 40 41 42 43 44 47
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MIPS Arithmetic Instructions
MIPS assembly language arithmetic statement add sub $t0, $s1, $s2 $t0, $s1, $s2
Each arithmetic instruction performs only one operation Each arithmetic instruction fits in 32 bits and specifies exactly three operands
destination source1 op source2
Those operands are all contained in the datapaths register file ($t0,$s1,$s2) indicated by $ Operand order is fixed (destination first)
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MIPS Arithmetic Instructions
MIPS assembly language arithmetic statement add sub $t0, $s1, $s2 $t0, $s1, $s2
Each arithmetic instruction performs only one operation Each arithmetic instruction fits in 32 bits and specifies exactly three operands
destination source1 op source2
Operand order is fixed (destination first) Those operands are all contained in the datapaths register file ($t0,$s1,$s2) indicated by $
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Aside: MIPS Register Convention
Register Number $zero 0 $at 1 $v0 - $v1 2-3 $a0 - $a3 4-7 $t0 - $t7 8-15 $s0 - $s7 16-23 $t8 - $t9 24-25 $gp 28 $sp 29 $fp 30 $ra 31
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Name
Preserve on call? constant 0 (hardware) n.a. reserved for assembler n.a. returned values no arguments yes temporaries no saved values yes temporaries no global pointer yes stack pointer yes frame pointer yes return addr (hardware) yes
Usage
MIPS Register File
Holds thirty-two 32-bit registers
Two read ports and One write port
src1 addr src2 addr dst addr write data
5 5 5 32 32 locations 32 src2
Register File
32 bits 32 src1
data
Registers are
Faster than main memory Easier for a compiler to use
data
write control - e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack - code density improves (since register are named with fewer bits than a memory location)
Can hold variables so that
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Machine Language - Add Instruction
Instructions, like registers and words of data, are 32 bits long Arithmetic Instruction Format (R format): add $t0, $s1, $s2
op rs rt rd shamt funct
op rs rt rd funct
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6-bits 5-bits 5-bits 5-bits 6-bits
opcode that specifies the operation register file address of the first source operand register file address of the second source operand register file address of the results destination shift amount (for shift instructions) function code augmenting the opcode
shamt 5-bits
MIPS Memory Access Instructions
MIPS has two basic data transfer instructions for accessing memory lw sw $t0, 4($s3) $t0, 8($s3) #load word from memory #store word to memory
The data is loaded into (lw) or stored from (sw) a register in the register file a 5 bit address The memory address a 32 bit address is formed by adding the contents of the base address register to the offset value
A 16-bit field meaning access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register Note that the offset can be positive or negative
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Machine Language - Load Instruction
Load/Store Instruction Format (I format): lw $t0, 24($s2)
op rs rt 16 bit offset Memory
2410 + $s2 =
0xf f f f f f f f
. . . 0001 1000 + . . . 1001 0100 . . . 1010 1100 = 0x120040ac
$t0 $s2
0x120040ac 0x12004094 0x0000000c 0x00000008 0x00000004 0x00000000 word address (hex)
data
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Byte Addresses
Since 8-bit bytes are so useful, most architectures address individual bytes in memory
The memory address of a word must be a multiple of 4 (alignment restriction)
Big Endian: Little Endian:
leftmost byte is word address rightmost byte is word address
little endian byte 0 0 lsb 1 2 3
IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
Intel 80x86, DEC Vax, DEC Alpha (Windows NT)
3 msb 0 big endian byte 0
2
1
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Aside: Loading and Storing Bytes
MIPS provides special instructions to move bytes lb sb $t0, 1($s3) $t0, 6($s3)
op rs rt
#load byte from memory #store byte to
16 bit offset
memory
What 8 bits get loaded and stored?
load byte places the byte from memory in the rightmost 8 bits of the destination register
- what happens to the other bits in the register?
store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory
- what happens to the other bits in the memory word?
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MIPS Flow Control Instructions
MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1
Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1 ...
Lbl1:
Instruction Format (I format):
op rs rt 16 bit offset
How is the branch destination address specified?
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Specifying Branch Destinations
Use a register (like in lw and sw) added to the 16-bit offset
which register? Instruction Address Register (the PC)
- its use is automatically implied by instruction - PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction
limits the branch distance to -215 to +215-1 instructions from the (instruction after the) branch instruction, but most branches are local anyway
from the low order 16 bits of the branch instruction
16
offset sign-extend
00 32 32 Add 32 4 32 Add 32
branch dst address
32
PC
32
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?
More Branch Instructions
We have beq, bne, but what about other kinds of brances (e.g., branch-if-less-than)? For this, we need yet another instruction, slt Set on less than instruction:
slt $t0, $s0, $s1 # if $s0 < $s1 # $t0 = 1 # $t0 = 0 then else
Instruction format (R format):
op rs rt rd funct
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2
More Branch Instructions, Cont
Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions
less than slt bne blt $s1, $s2, Label $at, $s1, $s2 $at, $zero, Label #$at set to 1 if # $s1 < $s2
less than or equal to greater than great than or equal to
ble $s1, $s2, Label bgt $s1, $s2, Label bge $s1, $s2, Label
Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler
Its why the assembler needs a reserved register ($at)
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Other Control Flow Instructions
MIPS also has an unconditional branch instruction or jump instruction: j label #go to label
Instruction Format (J Format):
op 26-bit address
from the low order 26 bits of the jump instruction
26
00 32
4
PC
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32
Aside: Branching Far Away
What if the branch destination is further away than can be captured in 16 bits?
The assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition beq becomes bne j L2: $s0, $s1, L2 L1 $s0, $s1, L1
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Instructions for Accessing Procedures
MIPS procedure call instruction: jal ProcedureAddress #jump and link
Saves PC+4 in register $ra to have a link to the next instruction for the procedure return Machine format (J format):
op 26 bit address
Then can do procedure return with a jr $ra #return
Instruction format (R format):
op
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rs
funct
Aside: Spilling Registers
What if the callee needs more registers? What if the procedure is recursive?
uses a stack a last-in-first-out queue in memory for passing additional values or saving (recursive) return address(es)
high addr
One of the general registers, $sp, is used to address the stack (which grows from high address to low address)
add data onto the stack push
top of stack $sp
$sp = $sp 4 data on stack at new $sp remove data from the stack pop
low addr
data from stack at $sp $sp = $sp + 4
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MIPS Immediate Instructions
Small constants are used often in typical code Possible approaches?
put typical constants in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants !
addi $sp, $sp, 4 slti $t0, $s2, 15 Machine format (I format):
op rs rt
#$sp = $sp + 4 #$t0 = 1 if $s2<15
16 bit immediate
I format
The constant is kept inside the instruction itself!
Immediate format limits values to the range +2151 to -215
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Aside: How About Larger Constants?
We'd also like to be able to load a 32 bit constant into a register, for this we must use two instructions a new "load upper immediate" instruction lui $t0, 1010101010101010
6 0 8 1010101010101010
Then must get the lower order bits right, use ori $t0, $t0, 1010101010101010
1010101010101010 0000000000000000 1010101010101010
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0000000000000000 1010101010101010 1010101010101010
MIPS Organization So Far
Processor
Register File src1 addr src2 addr dst addr write data 5 32 32 bits branch offset 32 PC 4 32 Add 32 Add 32 32 ALU 32 32 32 5 5 32 registers ($zero - $ra) src1 data 32
Memory
11100
src2 32 data
read/write addr
32
230 words
read data
32
Fetch PC = PC+4 Exec
write data
32 32 4 0 5 1 6 2 7 3
Decode
32 bits byte address (big Endian)
01100 01000 00100 00000 word address (binary)
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MIPS ISA So Far
Category Instr Op Code Example Meaning
Arithmetic (R & I format) Data Transfer (I format)
add subtract add immediate or immediate load word store word load byte store byte load upper imm
0 and 32 add $s1, $s2, $s3 0 and 34 sub $s1, $s2, $s3 8 13 35 43 32 40 15 4 5 addi $s1, $s2, 6 ori $s1, $s2, 6 lw lb sb lui $s1, 24($s2) $s1, 25($s2) $s1, 25($s2) $s1, 6 sw $s1, 24($s2)
$s1 = $s2 + $s3 $s1 = $s2 - $s3 $s1 = $s2 + 6 $s1 = $s2 v 6 $s1 = Memory($s2+24) Memory($s2+24) = $s1 $s1 = Memory($s2+25) Memory($s2+25) = $s1 $s1 = 6 * 216 if ($s1==$s2) go to L if ($s1 !=$s2) go to L if ($s2<$s3) $s1=1 else $s1=0 if ($s2<6) $s1=1 else $s1=0 go to 10000 go to $t1 go to 10000; $ra=PC+4
Cond. Branch (I & R format)
br on equal br on not equal set on less than set on less than immediate
beq $s1, $s2, L bne $s1, $s2, L $s1, $s2, $s3
0 and 42 slt 10 2 0 and 8 3
slti $s1, $s2, 6 j jr jal 2500 $t1 2500
Uncond. Jump (J & R format)
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jump jump register jump and link
Review of MIPS Operand Addressing Modes
Register addressing operand is in a register
op rs rt rd funct
Register
word operand
Base (displacement) addressing operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction
op rs rt offset
Memory
word or byte operand
base register
Register relative (indirect) with Pseudo-direct with
0($a0) addr($zero)
Immediate addressing operand is a 16-bit constant contained within the instruction
op
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rs
rt
operand
Review of MIPS Instruction Addressing Modes
PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction
op rs rt offset
Memory
branch destination instruction
Program Counter (PC)
Pseudo-direct addressing instruction address is the 26bit constant contained within the instruction concatenated with the upper 4 bits of the PC
op jump address || Program Counter (PC)
Memory
jump destination instruction
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MIPS (RISC) Design Principles
Simplicity favors regularity
fixed size instructions 32-bits small number of instruction formats opcode always the first 6 bits
Good design demands good compromises
three instruction formats
Smaller is faster
limited instruction set limited number of registers in register file limited number of addressing modes
Make the common case fast
arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands
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Next Lecture and Reminders
Next lecture
MIPS ALU Review
- Reading assignment PH, Chapter 3
Reminders
HW1 will be due for next week!
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