schaum's outlines-digital principles 3rd edition
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schaum's outlines-digital principles 3rd edition

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This page intentionally left blank S C H U M ’ S OUTLINE OF THEORY AND PROBLEMS OF DIGITAL PRINCIPLES Third Edition ROGER L. TOKHEIM, M.S. SCHAUM’S OUTLINE SEiRIES McGraw-Hill New York San Francisco Washington, D.C. Auckland Bogota Caracas Lisbon London Madrid Mexico City Milan Montreal New Delhi San J uan Singapore Sydney Tokyo Torontcl R OGER L. TOKHEIM holds B.S., M .S., a nd Ed.S. degrees from St....

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page This intentionally left blank S C H U M ’ S OUTLINE OF THEORY AND PROBLEMS OF DIGITAL PRINCIPLES Third Edition ROGER L. TOKHEIM, M.S. SCHAUM’S OUTLINE SEiRIES McGraw-Hill New York San Francisco Washington, D.C. Auckland Bogota Caracas Lisbon London Madrid Mexico City Milan Montreal New Delhi San J uan Singapore Sydney Tokyo Torontcl R OGER L. TOKHEIM holds B.S., M .S., a nd Ed.S. degrees from St. Cloud State University and the University of Wisconsin-Stout. He is t he author of Digital Electronics a nd its companion Activities Manual for Digital Electronics, Schaum ’s Outline of Microprocessor Fundamentals, and numerous other instructional materials on science and technology. A n experienced educator at the secondary and college levels, he is presently an instructor of Technology Education and Computer Science at Henry Sibley High School, Mendota Heights, Minnesota. Schaum’s Outline of Theory and Problems of D IGITAL PRINCIPLES Copyright 0 1994, 1988, 1980 by The McGraw-Hill Companies, Inc. All Rights Reserved. Printed i n the United States of America. Except as permitted under the Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a data base or retrieval system. without the prior written permission of the publisher. 7 8 9 1 0 1 1 1 2 1 3 14 15 16 1 7 I 8 19 2 0 B A W B A W 9 9 I SBN 0-07-0b5050-0 Sponsoring Editor: John Aliano Production Supervisor: Denise Puryear Editing Supervisor: Patty Andrews Library of Congress Cataloging-in-Publication Data Tokheim, Roger L. Schaum’s outline of theory and problems of digital prinicples/by Roger L. Tokheim-3rd ed. p. cm.-(Schaum’s outline series) Includes index. ISBN 0-07-065050-0 1. Digital electronics. I . ‘Title. 11. Series. TK7868.D5T66 1994 93-64 62 1.3815-dc20 CIP McGraw -Hill A Division of The McGraw-HiUCompanies z Digital electronics is a rapidly growing technology. Digital circuits are used in most new consumer products, industrial equipment and controls, and office, medical, military, and communications equipment. This expanding use of digital circuits is the result of the development of inexpensive integrated circuits and the application of display, memory, and computer technology. Schaum’s Outline of D igitd Principles provides inforrnation necessary to lead the reader through the solution of those problems in digital electronics one might encounter as a student, technician, engineer, or hobbyist. While the principles of t he subject are necessary, the Schaum’s Outline philosophy is dedicated to showing the student how to apply the principles of digital electronics through practical solved problems. This new edition now contains over 1000 solved and supplementary problems. The third edition of Schaum’s Outline of Digital Principles contains many of t he same topics which made the first two editions great successes. Slight changes have been made in many of t he traditional topics to reflect the technological trend toward using more CMOS, NMOS, and P MOS integrated circuits. Several microprocessor/microcomputer-related topics have been included, reflecting the current practice of teaching a microprocessor course after or with digital electronics. A chapter detailing t he characteristics of T TL and CMOS devices along with several interfacing topics has been added. Other display technologies such as liquid-crystal displays (LCDs) and vacuum fluorescent (VF) displays have been given expanded coverage. The chapter on microcomputer memory has been revised with added coverage of hard and optical disks. Sections on programmable logic arrays (PLA), magnitude comparators, demultiplexers, and Schmitt trigger devices have been added. The topics outlined in this book were carefully selected to coincide with courses taught at the upper high school, vocational-Iechnical school, technical college, and beginning collcge level. Several of t he most widely used textbooks in digital electronics were analyzed. The topics and problems included in this Schaum’s Outline reflect those encountered in standard textbooks. Schuiini’s Outline of Digital Principles, Third Edition, begins with number systems and digital codes and continues with logic gates and combinational logic circuits. I t then details the characteristics of both TTL and CMOS ICs, along with various interfacing topics. Next encoders, decoders, and display drivers are explored, along with LED, LCD, and VF seven-segment displays. Various arithmetic circuits are examined. I t then covers flip-flops, other rnultivibrators, and sequential logic, followed by counters and shift registers. Next semiconductor and bulk storage memories are explored. Finally, n iul tiplexers, demultiplexers, latches and buffers, digital data transmission, magnitude comparators, Schmitt trigger devices, and programmable logic arrays are investigated. The book stresses the use of industry-standard digital ICs (both TTL and CMOS) so that the reader becomes familiar with the practical hardware aspects of digital electronics. Most circuits in this Schaum’s Outline can be wired using standard digital ICs. I wish to thank my son Marshall for his many hours of typing, proofreading, and testing circuits to make this book as accurate as possible. Finally, I extend my appreciation to other family members Daniel and Carrie for their help and patience. ROGER . TOKHEIM L ... 111 This page intentionally left blank Chapter 1 .................... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BinaryNumbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ikxadecimal Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2s Complement Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NUMBERS USED IN DIGITAL ELECTRONICS. 1-1 1-2 1-3 1-4 1 1 1 6 10 Chapter 3 BINARY CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2-1 2-2 2-3 2-4 Chapter 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weighted Binary Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonweighted Binary Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alphanumeric Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 20 24 BASIC LOGIC GATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ............................................ TheANDGate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TheORGate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TheNOTGate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combining Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Practical Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3-1 3-2 3-3 3-4 3-5 3-6 Chapter 4 OTHER LOGIC GATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 31 34 36 39 48 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Exclusive-OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Exclusive-NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Converting Gates When Using Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . NAND as a Universal Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Practical Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 50 52 54 55 58 60 SIMPLIFYING LOGIC CIRCUITS: MAPPING ...................... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sum-of-Products Boolean Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . Product-of-Sums Boolean Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . Using De Morgan’s Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using NAND Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Usins NOR Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Karnaugh Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Karnaugh Maps with Four Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5-1 5-2 5-3 69 69 72 75 77 79 82 85 4- 1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 Chapter 5 Introduction 5-4 5-5 5-0 5-7 5-8 V vi CONTENTS 5-9 Using Maps w ith Maxterm Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Don't Cares on Karnaugh Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Karnaugh Maps with Five. Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 'ITL AND CMOS ICS: CHARACTERISTICS AND INTERFACING . . . . . . . . 104 6- 1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 Chapter 7 104 105 109 114 118 125 129 131 140 I ntroduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decoding: BCD to Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decoding: BCD-to-Seven-Segment Code . . . . . . . . . . . . . . . . . . . . . . . . . . Liquid-Crystal Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driving LCDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vacuum Fluorescent Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driving VF Displays w ith CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 140 143 147 152 154 158 161 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS . . . . . . . . . . . . . . . 170 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Binary Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Adders and Subtractors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Full Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Adders for Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2s Complement Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . 170 170 175 180 184 188 193 FLIP-FLOPS AND OTHER MULTMBRATORS . . . . . . . . . . . . . . . . . . . . . 204 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSFlip.Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocked RS Flip.Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JKFliP.FlOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triggering of Flip.Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Astable Multivibrators-Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monostable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 204 206 209 212 217 220 224 8-1 8-2 8-3 8-4 8-5 8-6 8-7 Chapter 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital IC Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T TL Integrated Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMOS Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing TTL a nd CMOS ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfacing TTL and CMOS w ith Switches. . . . . . . . . . . . . . . . . . . . . . . . . Interfacing TTL/CMOS with Simple Output Devices . . . . . . . . . . . . . . . . . D /A and A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CODE CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 Chapter 8 88 91 93 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 vii CONTENTS Chapter 10 COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ripplecounters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTL IC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMOS IC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Division: The Digital Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 230 234 236 240 245 251 11 S H I m REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Serial-Load Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Parallel-Load Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 TTL Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 CMOS Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Chapter 12 MICROCOMPUTER MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read-Only Memory ( ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcomputer Bulk Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 280 286 293 300 Chapter 13 OTHER DEVICES AND TECHNIQUES . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Selector/Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexing Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latches and Three-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schmitt Trigger Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 309 313 316 319 324 326 335 341 10-1 10-2 10-3 10-4 10-5 10-6 10-7 Chapter 12-1 12-2 12-3 12-4 12-5 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 260 261 264 268 271 ~ INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 This page intentionally left blank Chapter 1 Numbers Used in Digital Electronics 1-1 INTRODUCTION T he decimal number system is familiar to everyone. This system uses the symbols 0, 1, 2, 3, 4, 5, 6, 7, 8, a nd 9. T he decimal system also has a place-value characteristic. Consider the decimal number 238. T he 8 is in the 1s position or place. The 3 is in the 10s position, and therefore the three 10s stand for 30 units. The 2 is in the 100s position and means two loos, or 2,OO units. Adding 200 + 30 + 8 gives the total decimal number of 238. T he decimal number system is also called the base 10 system. I t is referred to as base 10 because i t has 10 different symbols. The base 10 system is also said to have a radix of 10. “Radix” and “base” are terms that mean exactly the same thing. Binary numbers (base 2) a re used extensively in digital electronics and computers. Both hexadecimal (base 16) and octal (base 8) numbers are used to represent groups of binary digits. Binary and hexadecimal numbers find wide use in modern microcomputers. All t he number systems mentioned (decimal, binary, octal, and hexadecimal) can be used for counting. All these number systems also have the place-value cha.racteristic. 1-2 BINARY NUMBERS T he binary number system uses only two symbols ( 0,l). I t is said to have a radix of 2 and is commonly called the base 2 number system. Each binary digit is called a bit. Counting in binary is illustrated in Fig. 1-1. T he binary number is shown on the right with its decimal equivalent. Notice that the least significant bit (LSB) is the 1s place. In other words, if a 1 a ppears in the right column, a 1 is added to the binary count. The second place over from the right is the 2s place. A 1 appearing in this column (as in decimal 2 row> means that 2 is added to the count. Three other binary place values also are shown in Fig. 1-1 (4s, 8s, and 16s places). Note that each larger place value is an added power of 2. T he 1s place is really Z 0, t he 2s place 2 *,t he 4s place 2 2, t he 8s place 2 3, and the 16s place z 4. It is customary in digital electronics to memorize at least the binary counting sequence from 0000 t o 1111 (say: one, one, one, one) or decimal 15. Consider the number shown in Fig. 1 -2a. This figure shows how to convert the binary 10011 (say: one, zero, zero, one, one) to its decimal equivalent. Note that, for each 1 bit in the binary number, the decimal equivalent for that place value is written below. The decimal numbers are then added (16 + 2 + 1 = 19) to yield the decimal equivalent. Binary 10011 then equals a decimal 19. Consider the binary number 101110 in Fig. 1-2b. Using the same procedure, each 1 bit in the binary number generates a decimal equivalent for that place value. The most signijicant bit (MSB) of the binary number is equal to 32. Add 8 plus 4 plus 2 to t he 32 for a total of 46. Binary 101110 t hen equals decimal 46. Figure 1-2b also identifies the binary point (similar to the decimal point in decimal numbers). I t is customary to omit the binary point when working with whole binary numbers. What is the value of the number 111? It could be one hundred and eleven in decimal or one, one, one in binary. Some books use the system shown in Fig. 1-2c to designate the base, or radix, of a number. I n this case 10011 is a base 2 number as shown by the small subscript 2 after the number. The number 19 is a base 10 number as shown by the subscript I 0 after the number. Figure 1-2c is a summary of the binary-to-decimal conversions in Fig. 1 -2a and b . How about converting fractional numbers? Figure 1-3 illustrates the binary number 1110.101 being converted to its decimal equivalent. The place values are given across the top. Note the value of each position to the right of the binary point. The procedure for making the conversion is t he same as with whole numbers. The place value of each 1 bit in the binary number is added to form the decimal number. In this problem 8 + 4 + 2 + 0.5 + 0.125 = 14.625 in decimal. I 2 [CHAP. 1 NUMBERS USED IN DIGITAL ELECTRONICS Binary count Decimal count 16s 8s 4s 2s 1s 0 0 1 2 3 4 5 6 1 1 1 1 1 1 1 1 1 0 0 0 0 7 8 9 10 11 12 13 14 15 16 17 18 19 , I 24 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 23 22 21 20 Fig. 1-1 Counting in binary and decimal Powers of 2 2" 23 72 21 20 Place value 16s 8s 4s 25 Is Binary 1 0 0 1 1 Decimal 16 > I + (U) 2 + . +--Binary point 1=19 Binary-to-decimal conversion Powers of 2 25 24 23 22 2' 20 Place value 3 2s 16s 8s 4s 25 Is Binary 1 0 1 1 1 0 Deci m a I 32 + 8 + 4 + 2 -Binary = 46 ( h ) Binary-to-decimal conversion l Oollz == 1910 101 1 1 0 2 = 4610 ( c ) Summary of conversions and use of small subscripts to indicate radix of number Fig. 1-2 point 1 1 ~ 22 23 2' 2O 1!2' 4s Powers o f 2 3 NUMBERS USED I N DIGITAL ELECTRONICS CHAP. 1 1 2s Is 0.5s ~ ~ 1/z2 1p3 -- 0.25s 0.125s ~~~~~~~~ Binary 1 Decimal 8 1 + 1 4 + 0 . + 2 1 0 + 0.5 1 0.125 = 14.625 Fig. 1-3 Binary-to-decimal conversion Convert the decimal number 87 t o a binary number. Figure 1-4 shows a convenient method for making this conversion. The decimal number 87 is first divided by 2, leaving 43 with a remainder of 1. T he remainder is important and is recorded at the right. It becomes the LSB in the binary number. The quotient (43) then is transferred as shown by the arrow and becomes the dividend. The quotients are repeatedly divided by 2 until the quotient becomes 0 with a remainder of 1, as in the last line of Fig. 1-4. Near the bottom the figure shows that decimal 87 equals binary 1010111. -+ 2 = 87; 4" remainder of 1 I.SB 43 i 2 = f l remainder of 1 +7 21 -+ 2 = 10 remainder 10 -+ 2 = 1 of 1 remainder of 0I-- 4 5 -+ 2 = 2 remainder of 1 F---l remainder of 0 2 i2 = 1 5+ 2 0 remainder of 1 ----1 1 = 1 1 -1 1 MSH 8 7,,-l III 0 1 01 1 " 1 1, Fig. 1-4 Decimal-to-binary conversion Convert the decimal number 0.375 to a binary number. Figure 1-51 illustrates one method of performing this task. Note that the decimal number (0.375) is being multiplied by 2. This leaves a product of 0.75. T he 0 from the integer place (1s place) becomes the bit nearest the binary point. The 0.75 is then multiplied by 2, yielding 1.50. T he carry of 1 t o the integer (1s place) is the next bit in the binary number. The 0.50 is then multiplied by 2, yielding a product of 1.00. T he carry of 1 in t he integer place is the final 1 in the binary number. When the product is 1.00, t he conversion process is complete. Figure 1-5a shows a decimal 0.375 being converted into a binary equivalent of 0.011. Figure 1-5b shows the decimal number 0.84375 being Converted into binary. Again note that 0.84375 is multiplied by 2. T he integer of each product is placed below, forming the binary number. When the product reaches 1.00, t he conversion is complete. This problem shows a decimal 0.84375 being converted to binary 0.1 1011. Consider the decimal number 5.625. Converting this number to binary involves two processes. The integer part of t he number ( 5 ) is processed by repeated division n ear the top in Fig. 1-6. Decimal 5 is converted to a binary 101. T he fractional part of t he decimal number (.625) is converted to binary .101 at the bottom in Fig. 1-6. T he fractional part is converted to binary through the repeated multiplication process. The integer and fractional sections are then combined to show that decimal 5.625 equals binary 101.101. 4 NUMBERS USED IN DIGITAL ELECTRONICS 0.6875 x 2 0.375 x 2 = 6.751 0.7; x 2 = i [CHAP. 1 = 1 1.375 0.375 0.75 x 2 = 1.50 0.50 n 1 x 2 = 0 .75 x 2 = 1.00 . * 0.84375,0= .1 1 + 0 * 1 + 1, (h) Fig. 1-5 Fractional decimal-to-binary conversions 5 + 2 = 2 remainder of 1 c--l 2 + 2 1 remainder of 0 5----1 remainder of 1 1+2 0 = = 111 0.625 x 2 = 1.25 i---' + 0.25 x 2 = 0.50 0.50 x 2 = 1.00 Fig. 1-6 Decimal-to-binary conversion SOLVED PROBLEMS 1.1 T he binary number system is the base system and has a radix of . Solution: T he binary number system is the base 2 system and has a radix of 2. 1.2 T he term bit means when dealing with binary numbers. Solution: Bit means binary digit. 1.3 How would you say the number 1001 in ( a ) binary and ( b ) decimal? Solution: T he number 1001 is pronounced as follows: ( a ) one, zero, zero, one; ( b ) one thousand and one. 1.4 T he number l l O l o is a base number. Solution: T he number l l O , o is a base 10 number, as indicated by the small 10 after the number. 1.5 5 N UMBERS USED IN DIGITAL ELECTRONICS CHAP. 1 3 Write the base 2 number one, one, zero, zero, one. Solution: 110012 1.6 Convert the following binary numbers to their decimal equivalents: ( a ) 001100 ( b ) 000011 ( c ) 011100 ( d ) 111100 ( e ) 101010 ( g ) 100001 ( h ) 111000 ( f) 111111 Solution: Follow the procedure shown in Fig. 1-2. T he decimal equivalents of t he binary numbers are as follows: ( a ) 001100, = 1 zl0 ( c ) 011100, = 28,O ( e) 101010, = 42,, ( 8) 100001, = 33,, ( b ) 000011, = 3,, ( d ) 111100, = 601, ( f) 111111, = 63,, ( h ) 111000, = 56,, 1.7 11110001111, = 10 Solution: Follow the procedure shown in Fig. 1-2. 11110001111, = 19351,. 1.8 11100.011, = 10 Solution: Follow the procedure shown in Fig. 1-3. 19 . 110011.100 11, = 10 Solution: Follow the procedure shown in Fig. 1-3. 1.10 1010101010.1~ = 1100.011, = 28.375,,. 10011.10011, = 51.59375,,. 10 Solution: Follow the procedure shown in Fig. 1-3. 1010101010.1, = 682.5,,. 1.11 Convert the following decimal numbers to their binary equivalents: (f) 500. ( a ) 64, ( b ) 100, ( c ) 111, ( d ) 145, ( e ) 255, Solution: Follow the procedure shown in Fig. 1-4. T he binary equivalents of t he decimal numbers are as follows: ( a) 64,, = 1000000, ( c ) l ll,, = 1101111, ( e ) 25!&, = 11111111, ( b ) 100,, = 1100100, ( d ) 145,, = 10010001, ( f) 500,, = 111110100, 1.12 34.7510 = 2 Solution: Follow the procedure shown in Fig. 1-6. 34.75,, = 1OOOl0.11,. 6 1.13 N UMBERS USED I N D IGITAL ELECTRONICS 25.25,, = [CHAP. 1 2 Solution: Follow t hc proccdurc shown in Fig. 1.6. 2S.2S1,, = 1 IoO1.01 2 . 1.14 27.1875,, = 2 Solution: Follow thc proccdurc shown in Fig. 1-6. 27.187s1,, = 1 1 0 1 1 .OOlI ?. 1-3 HEXADECIMAL N UhlBERS T he hexadecimal n umber system has a radix of 16. I t is referred t o a s the h e 16 rtirnibvr sysiern. I t uscs t he symbols 0-9, A, B, C. D. E, and F as shown i n t hc hexadecinial coluniri of the table i n Fig. 1-7. T he letter A stands for a count of 10. B for 1 1, C for 12, D for 13, E for 14, and F for 15. T hc advantage of t he hexadecimal system is its usefulness i n converting dircctly f rom a 4-bit binary numbcr. Notc in thc shaded section of Fig. 1-7 that each 4-bit binary n unibcr f roni oo(K)t o 1 1 1 1 can be represented by a unique hexadecimal digit. Fig. 1-7 C ounting in dccimal. binary, and hcxadccimal numbcr systcms Look a t the linc labcled 16 in t he decimal column in Fig. 1-7. ' Ihe hexadecimal cquivalent is 10. This shows that thc hcxadccimal number system uses the placc-value idea. The 1 ( in 10J stands for 16 units, whilc thc 0 s tands for zcro units. Convert the hexadecimal number 2Bb into a decimal numbcr. Figure 1-80 shows the familiar process. The 2 is in the 256s placc s o 2 x 256 = 512. which is written i n the decimal line. T he hexadecimal digit B a ppcars i n t hc 16s column. Notc i n Fig. 1-8 that hexadecinial B corresponds to decimal 11. This means that there a re clcvcn 16s ( 16 X 1 1 1, yiclding 176. I 'hc 176 is added i nto the decimal total n ear the bottom i n Fig. 1-8a. T hc 1s column shows six Is. T hc 6 is added i nto t he dccimal line. The decimal values arc added (512 + 176 + 6 = 694). yiclding 694,(,. Figurc 1-0a shows that 2 86,, equals 694,,,. 7 NUMBERS USED I N DIGITAL ELECTRONICS CHAP. 11 P okers of 16 2 56s Hexadecimal number 16s 2 B 2 56 x2 - Place value 16 x 11 512 Decimal (U) + 6 176 I + x6 6 6 941,, =: Hexadecimal-to-decimal conversion Powers of 16 1/16' ___.__________- 2 56s Place value H exadecimalnumber A 256 x 10 2560 Decimal .0625s 3 16 x3 + 48 + F - ,0625 I x 1s - 15 C x 1' +6 % = 2 623.7510 ( h ) Fractional hexadecimal-to-decimal conversion Fig. 1-8 Convert the hexadecimal number A3F.C to its decimal equivalent. Figure 1-8b details this m problem. First consider the 256s column. The hexadecimal digit ,4 eans that 256 must be multiplied by 10, resulting in a product of 2560. The hexadecimal number shows that i t contains three 16s, and therefore 16 x 3 = 48, which is added to the decimal line. The 1s column contains the hexadecimal digit F, which means 1 X 15 = 15. T he 15 is added to the decimal line. The 0.0625s column contains the hexadecimal digit C, which means 12 X 0.0625 = 0.75. The 0.75 is added to the decimal line. Adding the contents of the decimal line (2560 + 48 -t 15 + 0.75 = 2623.75) gives the decimal number 2623.75. Figure 1-8h converts A3F.C 1 6 t o 2623.75,,,. Now reverse the process and convert t he decimal number 45 to its hexadecimal equivalent. Figure 1-9a details the familiar repeated divide-by-16 process. The decimal number 45 is first divided by 16, resulting in a quotient of 2 with a remainder of 13. The remainder of 13 ( D in hexadecimal) becomes the LSD of the hexadecimal number. The quotient (2) is transferred to the dividend position and divided by 16. This results in a quotient of 0 with a remainder of 2. The 2 becomes the next digit in the 2 SO + 16 = 15 remainder of 10 15 +- 16 = 0 remainder of 15 45 -+ 16 = 2 remainder of 13 250.25 A * 4 16 I r--J -+ 16 = 0 remainder of 2 0.25 :< 16 = 4.00 2 4 51@=2 =F .I c 0.00 D,, :K 16 = 0.00 ( b) Fractional decimal-to-hexadecimal conversion ( a) Decimal-to-hexadecimal conversion Fig. 1-9 8 NUMBERS USED IN DIGITAL ELECTRONICS [CHAP. 1 hexadecimal number. The process is complete because the integer part of the quotient is 0. T he process in Fig. 1-9a converts the decimal number 45 to the hexadecimal number 2D. Convert the decimal number 250.25 t o a hexadecimal number. The conversion must be done by using two processes as shown in Fig. 1-9b. T he integer part of the decimal number (250) is converted to hexadecimal by using the repeated divide-by-16 process. The remainders of 10 ( A in hexadecimal) and 15 ( F in hexadecimal) form the hexadecimal whole number FA. The fractional part of the 250.25 is multiplied by 16 (0.25 X 16). T he result is 4.00. T he integer 4 is transferred to the position shown in Fig. 1-9b. T he completed conversion shows the decimal number 250.25 equaling the hexadecimal number FA.4. The prime advantage of t he hexadecimal system is its easy conversion to binary. Figure 1-10a shows the hexadecimal number 3B9 being converted to binary. Note that each hexadecimal digit forms a group of four binary digits, or bits. The groups of bits are then combined to form the binary number. In this case 3B9,, equals 1110111001,. ( a ) Hexadecimal-to-binaryconversion ( 6) Fractional hexadecimal-to-binaryconversion 1010 1 A 1000 0101 1 8 (c) 1 0 101010000101~ A 8516 = 5 Binary-to-hexadecimalconversion ( d ) Fractional binary-to-hexadecimalconversion Fig. 1-10 A nother hexadecimal-to-binary conversion is detailed in Fig. 1-106. Again each hexadecimal digit forms a 4-bit group in the binary number. The hexadecimal point is dropped straight down to form the binary point. The hexadecimal number 47.FE is converted to the binary number 1000111.1111111.I t is apparent that hexadecimal numbers, because of their compactness, are much easier to write down than the long strings of 1s a nd OS in binary. The hexadecimal system can be thought of as a shorthand method of writing binary numbers. Figure 1-1Oc shows the binary number 101010000101being converted to hexadecimal. First divide the binary number into 4-bit groups starting at the binary point. Each group of four bits is then translated into an equivalent hexadecimal digit. Figure 1-10c shows that binary 101010000101equals hexadecimal A85. A nother binary-to-hexadecimal conversion is illustrated in Fig. 1-10d. H ere binary 10010.011011 is to be translated into hexadecimal. First the binary number is divided into groups of four bits, starting at the binary point. Three O S a re added in the leftmost group, forming 0001. Two OS a re added to t he rightmost group, forming 1100. Each group now has 4 bits and is translated into a hexadecimal digit as shown in Fig. 1-10d. T he binary number 10010.011011 then equals 12.6C,,. A s a practical matter, many modern hand-held calculators perform number base conversions. Most can convert between decimal, hexadecimal, octal, and binary. These calculators can also perform arithmetic operations in various bases (such as hexadecimal). C HAP. 1 1 9 NUMBERS USED IN DIGITAL ELECTRONICS SOLVED PROBLEMS 1.15 The hexadecimal number system is sometimes called the base system. Solution: T he hexadecimal number system is sometimes called the base 16 system. 1.16 List the 16 symbols used in the hexadecimal number system. Solution: Refer to Fig. 1-7. The 16 symbols used in the hexadecimal number system are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. 1.17 Convert the following whole hexadecimal numbers to their decimal equivalents: ( a ) C, ( 6) 9F, ( c) D52, ( d ) 67E, ( e ) ABCD. Solution: Follow the procedure shown in Fig. I -8a. Refer also to Fig. 1-7. T he decimal equivalents of the hexadecimal numbers are as follows: ( a ) C ,, = 12,,, ( c ) D52,, = 34101, ( e ) ABCD,, = 439811,, ( 6) 9F,, = 159,, ( d ) 67E1, = 1662," 1.18 Convert the following hexadecimal numbers to their decimal equivalents: ( b ) D3.E, ( c ) 1111.1, ( d ) 888.8, ( e ) EBA.C. ( a ) F.4, Solution: Follow the procedure shown i n Fig. 1-8b. Refer also to Fig. 1-7. The decimal equivalents of the hexadecimal numbers are as follows: ( a > F.4,, = 15.25," ( c ) 1111.1,, = 4369.0625,, ( e ) EBA.C16= 3770.75,, ( 6) D3.E1, 211.8751, ( d ) 888.81, 2184.51, 1.19 Convert the following whole decimal numbers to their hexadecimal equivalents: ( 6) 10, ( c) 14, ( d ) 16, ( e ) 80, ( f) 2560, ( 8) 3000, ( h ) 62,500. ( a ) 8, Solution: Follow the procedure shown in Fig. 1 -9a. Refer also to Fig. 1-7. T he hexadecimal equivalents of the decimal numbers are as follows: ( a ) 8 ,,=8,, ( c ) 1 41,=El, ( e ) 8Ol,=5O1, (g 3000 = BB8 ( 6) l O l 0 = A , , ( d ) 16,, = 10,, ( f ) 25601, = AOO,, ( h ) 625001,,= F424,, 1.20 Convert the following decimal numbers to their hexadecimal equivalents: ( b ) 255.875, ( c) 631.25, ( d ) 10000.00390625. ( a ) 204.125, Solution: Follow the procedure shown in Fig. 1-9b. Refer also to Fig. 1-7. The hexadecimal equivalents of the decimal numbers are as follows: ( a ) 204.1251,,= CC.2,, ( c ) 631.25,, = 277.4,, ( b ) 255.875,,, = FF.E,, ( d ) 10 000.003 906 25," = 2710.0116 1.21 Convert the following hexadecimal numbers to their binary equivalents: B, ( b ) E, ( c ) 1C, ( d ) A64, ( e ) 1F.C, I f ) 239.4 (a) 10 NUMBERS USED I N DIGITAL ELECTRONICS [CHAP. 1 Solution: Follow t he procedure shown in Fig. 1-10a and b. Refer also to Fig. 1-7. The binary equivalents of the hexadecimal numbers are as follows: (U) B,, = 1011, ( c) l C,, = 11100, ( e ) l F.C,, = 11111.11, ( b ) E,, = 1110, ( d ) A64,, = 101001100100, ( f ) 239.4,, = 1000111001.01, 1.22 Convert the following binary numbers to their hexadecimal equivalents: ( a ) 1001.1111 ( c ) 110101.O11001 ( e ) IOIOOI 11.I11011 ( b ) 10000001.1101 ( d ) 10000.1 ( f ) 1000000.0000111 Solution: Follow the procedure shown in Fig. 1-1Oc and d . Refer also t o Fig. 1-7. The hexadecimal equivalents of the binary numbers are as follows: (U) 1001.11112 = 9.F1, ( c) 110101.011001, = 35-64,, ( e ) 10100111.111011, = A’I.EC,, ( b ) 10000001.1101, = 81.D,, ( d ) 10000.1, = 10.8,, ( J ’ ) 1000000.0000111, = 4 0.0E1, 1-4 2s COMPLEMENT NUMBERS T he 2s c omplement method of representing numbers is widely used in microprocessor-based equipment. Until now, we have assumed that all numbers are positive. However, microprocessors must process both positive and negative numbers. By using 2s complement representation, t he sign as well as the magnitude of a number can be determined. Assume a microprocessor register 8 bits wide such as that shown in Fig. 1 -llu. T he mostsignificant bit (MSB) is the sign bit. If this bit is 0, t hen the number is ( + ) positive. However, if t he sign bit is 1, t hen the number is ( - ) negative. The other 7 bits in this 8-bit register represent the magnitude of t he number. The table in Fig. 1 -llb shows the 2s c omplement representations for some positive and negative numbers. For instance, a + 127 is represented by the 2s c omplement number 01111111. A decimal - 128 is represented by the 2s c omplement number 10000000. N ote that t he 2s complement representations for allpositiiie ualues are the same as the binary equivalents f or that decimal number. Convert the signed decimal - 1 t o a 2s c omplement number. Follow Fig. 1-12 a s you m ake the conversion in the next five steps. Step 1. S eparate the sign and magnitude part of - 1. T he negative sign means the sign bit will be 1 in the 2s c omplement representation. S tep 2. Convert decimal 1 t o its 7-bit binary equivalent. In this example decimal 1 e quals 0000001 in binary. S tep 3 . Convert binary 0000001 t o its I s c omplement form. In this example binary 0000001 e quals 1111110 in I s c omplement. Note that each 0 is changed to a 1 a nd each 1 t o a 0. S tep 4. Convert the 1s c omplement to its 2s c omplement form. In this example 1s c omplement 1111110 e quals 1111111 in 2s c omplement. Add + 1 t o the 1s c omplement to get the 2s c omplement number. S tep 5. The 7-bit 2s c omplement number (1111111 in this example) becomes the magnitude part of t he entire 8-bit 2s c omplement number. The result is that the signed decimal - 1 e quals 11111111 in 2s c omplement notation. The 2s c omplement number is shown in the register near the top of Fig. 1-12. CHAP. 11 N UMBERS USED I N D IGITAL ELECTRONICS 11 Fig. 1-11 Reverse the process and convert the 2s complement 11111000 to a signed decimal number. Follow Fig. 1-13 as the conversion is made in the following four steps. Step 1. Separate the sign bit from the magnitude part of the 2s complement number. The MSB is a 1; therefore, the sign of decimal number will be ( - ) negative. Step 2. Take the I s complement of the magnitude part. The 7-bit magnitude 1111000 equals 0000111 in I s complement notation. Step 3. Add + 1 t o the I s complement number. Adding 0000111 t o 1 gives us 0001000. T he 7-bit number 0001000 is now in binary. 12 NUMBERS USED IN DIGITAL ELECTRONICS [CHAP. 1 Fig. 1-12 Converting a signed decimal number to a 2s complement number Step 4. Convert the binary number to its decimal equivalent. In this example, binary 0001000 equals 8 in decimal notation. The magnitude part of the number is 8. T he procedure in Fig. 1-13 shows how to convert 2s complement notation to negative signed decimal numbers. In this example, 2s complement 11111000 equals - 8 in decimal notation. Regular binary-to-decimal conversion (see Fig. 1-4) is used to convert 2s complements that equal positive decimal numbers. Remember that, for positive decimal numbers, the binary and 2s complement equivalents are the same. Fig. 1-13 Converting a 2s complement number to a signed decimal number N UMBERS USED IN DIGITAL ELECTRONICS C HAP. 1 1 13 SOLVED PROBLEMS 1.23 T he (LSB, MSB) of a 2s complement number is the sign bit. T he MSB (most-significant bit) of a 2s c omplement number is the sign bit. 1.24 T he 2s complement number 10000000 is equal to in signed decimal. Solution: Follow the procedure shown in Fig. 1-13. T he 2s complement number 10000000 e quals -128 in decimal. 1.25 T he number 01110000 is equal to in signed decimal. Solution: The 0 in the MSB position means this is a positive number, and conversion to decimal follows the rules used in binary-to-decimal conversion. The number 01 110000 is equal to + 112 in signed decimal. 1.26 T he signed decimal number + 75 equals in %bit 2s complement. Solution: Follow the procedure shown in Fig. 1-4. Decimal + 75 e quals 01001011 in 2s c omplement and binary. 1.27 T he 2s complement number 11110001 is equal to in signed decimal. Solution: Follow the procedure shown in Fig. 1-13. T he 2s complement number 11110001 is equal to - 15 in signed decimal. 1.28 T he signed decimal number -35 equals in 8-bit 2s complement. Solution: Follow the procedure shown in Fig. 1-12. Decimal -35 e quals 11011101 in 2s c omplement. 1.29 T he signed decimal number - 100 equals in 8-bit 2s complement. Solution: Follow the procedure shown in Fig. 1-12. Decimal - 100 e quals 10011100 in 2s complement. 1.40 T he signed decimal number + 20 equals in 8-bit 2s complement. Solution: Follow the procedure shown in Fig. 1-4. Decimal + 20 e quals 00010100 in 2s c omplement and binary 14 NUMBERS USED IN DIGITAL ELECTRONICS [CHAP. 1 Supplementary Problems 1.31 T he number system with a radix of 2 is called the number system. 1.32 The number system with a radix of 10 is called the 1.33 The number system with a radix of 8 is called the 1.34 The number system with a radix of 16 is called the 1.35 A binary digit is sometimes shortened and called a(n) 1.36 How would you pronounce the number 1101 in ( a ) binary and ( b ) decimal? Ans. ( a ) o ne, one, zero, one ( b ) o ne thousand one hundred and one 1.37 The number 1010, is a base ( a ) n umber and is pronounced Ans. ( a ) 2 ( 6) o ne, zero, one, zero 1.38 Convert the following binary numbers to their decimal equivalents: 00001110, ( b ) 11100000, ( c ) 10000011, ( d ) 10011010. Ans. ( a ) 00001110, = 141, ( c ) 10000011, = 1 3lIo ( b ) 11100000, = 224,, ( d ) 10011010, = I %,,, number system. number system. . Ans. (b) 1.39 110011.11, 1.40 11110000.0011, = 1.41 Conver: the following decimal numbers to t heir binary equivalents: 32, ( 6) 200, ( c ) 170, ( d ) 258. Ans. ( a ) 32,, = 100000, ( c ) 170,,, = 10101010, ( b ) 2001, = 11001000, ( d ) 258,,, = 100000010, Ans. 51.75 Ans. 240.1875 (a) , 1.42 40.875,, 1.43 999.125,, 1.44 Convert the following hexadecimal numbers to their decimal equivalents: 13AF, (6) 25E6, ( c ) B4.C9, ( d ) 78.D3. Ans. ( a ) 13AE1, = 5039,(, ( c ) B4.C91, = 180.78515,,, ( 6) 25E6,, = 9702," ( d ) 78.D3,, = 120.824211 o = = Ans. Ans. 101000.111 1111100111.001 (a) 1.45 Convert the following decimal numbers to their hexadecimal equivalents: ( a ) 3016, ( b ) 64881, ( c ) 17386.75, ( d ) 9817.625. Ans. ( a ) 3016," = BC8,, ( c ) 17386.75,,,= 43EA.C,, ( 6) 64881,, 1.46 = FD71,, ( d ) 9817.625,,, = 2659.A,, Convert the following hexadecimal numbers to their binary equivalents: A6, ( b ) 19, ( c ) E5.04, ( d ) 1B.78. Ans. ( a ) A616 = 10100110, ( c ) 135.04 I h = 11~ 0 0 1 0 ~ . 0 0 0 0 0 ~ ( b ) 1916 = 11001, ( d ) 1B.78,, = 11011.01111, (a) 1.47 Convert the following binary numbers 11110010, ( b ) 11011001, ( c ) Ans. ( a ) 11110010, = F2,, (c) ( b ) 11011001, = D9,, (d) (a) , to their hexadecimal equivalents: 111110.000011, ( d ) 10001.11111 111110.000011, = 3E.OC,, 10001.11111, = l l.F8,, binary A ns. decimal Ans. octal number system. (a) = Ans. bit Ans. hexadecimal CHAP. 1 1 N UMBERS USED I N DIGITAL ELECTRONICS 1.48 W hen 2s complement notation is used, the MSB is t he 1.49 Convert the following signed decimal numbers to their 8-bit 2s complement equivalents: +13, ( b ) +110, (c) - 25, ( d ) -90. Ans. ( a ) 00001101 ( b ) 01101110 ( c ) 11100111 ( I d ) 10100110 bit. Ans. sign (a) 1.50 Convert the following 2s complement numbers to their signed decimal equivalents: ( a ) 01110000, ( b ) 00011111, ( c ) 11011001, ( d ) 11001000. Ans. ( a ) +112 ( b ) + 31 ( c ) -39 ( d ) - 56 15 Chapter 2 Binary Codes 2-1 INTRODUCTION Digital systems process only codes consisting of OS and 1s (binary codes). That is due to the bistable nature of digital electronic circuits. The straight binary code was discussed in Chap. 1. Several other, special binary codes have evolved over the years to perform specific functions in digital equipment. All those codes use OS and Is, but their meanings may vary. Several binary codes will be detailed here, along with the methods used to translate them into decimal form. In a digital system, electronic translators (called encoders and d ecoders) a re used for converting from code to code. The following sections will detail the process of conversion from one code to another. 2-2 WEIGHTED BINARY CODES Straight binary numbers are somewhat difficult for people to understand. For instance, try to convert the binary number 10010110, to a decimal number. It turns out that 10010110, = 1501,,,but it takes quite a lot of time and effort to make this conversion without a calculator. The binary-coded decimal (BCD) code makes conversion to decimals much easier. Figure 2-1 shows the 4-bit BCD code for the decimal digits 0-9. Note that the BCD code is a weighted code. The most significant bit, has a weight of 8, and the least significant bit has a weight of only 1. This code is more precisely known as the 8421 B CD c ode. T he 8421 part of the name gives the weighting of each place in the 4-bit code, There are several other BCD codes that have other weights for the four place values. Because the 8421 BCD code is most popular, it is customary to refer to it simply as the BCD code. BC I> Decimal 8s 4s 2s Is 0 1 0 0 0 0 0 7 I 3 4 5 0 0 0 0 1 0 0 I 1 0 010 01 1 01 1 100 6 7 8 9 0 1 0 1 0 1 0 1 0 100 1 Fig. 2-1 The 8421 BCD code How is the decimal number 150 expressed as a BCD number? Figure 2 -2a shows the very simple technique for converting decimal numbers to BCD (8421) numbers. Each decimal digit is converted to its 4-bit BCD equivalent (see Fig. 2 -1). T he decimal number 150 then equals the BCD number 000101010000. Converting BCD numbers to decimal numbers also is quite simple. Figure 2-26 shows the technique. The BCD number 10010110 is first divided into groups of 4 bits starting at the binary point. Each group of 4 bits is then converted to its equivalent decimal digit, which is recorded below. The BCD number 10010110 then equals decimal 96. 16 BINARY CODES CHAP. 21 I BCD (U) 5 0 1 Decimal 1 1 Decinia I 0 110. 1 1 ( c) 6 9 1 0011 . 8 1 0010 4 1 loo0 0100 Fractional decimal-to-BCD conversion 0111 0001 BCD 1 1 7 Deci ma 1 * 2 1 BCD Decimal-to-BCD conversion 1001 3 Decimal 0001 0101 0000 BCD 17 0 0000 1 1.0 1000 1 8 ( d ) Fractional BCD-to-decimal conversion ( h ) BCII-to-decimal conversion Fig. 2-2 Figure 2-2c illustrates a fractional decimal number being converted to its BCD equivalent. Each decimal digit is converted to its BCD equivalent. The decimal point is dropped down and becomes the binary point. Figure 2-2c shows that decimal 32.84 equals the I3CD number 00110010.10000100. Convert the fractional RCD number 01110001.00001000 to its decimal equivalent. Figure 2-2d shows the procedure. The BCD number is first divided into groups of 4 bits starting at the binary point. Each group of four bits is then converted to its decimal equivalent. The binary point becomes the decimal point in t he decimal number. Figure 2-2d shows the BCD number 01110001.00001000 being translated into its decimal equivalent of 71.08. Consider converting a BCD number to its straight binary equivalent. Figure 2-3 shows the three-step procedure. Step 1 shows the BCD number being diivided into 4-bit groups starting from t he binary point. Each 4-bit group is translated into its decimal e:quivalent. Step 1 in Fig. 2-3 shows the BCD number 000100000011.0101 being translated into the decimal number 103.5. Oool BCD oooo 0011 1 0 3 Deci ma I 103 t 2 51 -+ 2 2 5 -+ 2 12 + 2 6t2 3+2 I 1 1 1 01011 . 1 5 = 51 remainder of 1 = 2 5 remainder of I = 12 remainder of 1 = 6 remainder of 0 = 3 remainder of 0 = 1 remainder of I + 2 = 0 remainder + Binary of 1 I 1 00 I I I+ 0.5 x 2 = i .0 0.0 x 2 = 0.0 Fig. 2-3 BCD-to-binary conversion S tep 2 in Fig. 2-3 shows the integer part of t he decimal nuniber being translated into binary. The 103,o is converted into 1100111, in step 2 by the repeated divide-by-2 procedure. Step 3 in Fig. 2-3 illustrates the fractional part of the decimal number being translated into binary. The 0.510 is converted into 0.1, in step 3 by the repeated multiply-by-2 procedure. The integer and fractional parts of the binary number are joined. The BCD nu:mber 000100000011.0101 then equals the binary number 1100111.1. BINARY CODES 18 [CHAP. 2 1 v w 6 * * 6 w Fig. 2-4 Binary-to-BCD conversion N ote that it is usually more efficient to write down a figure in straight binary numbers than in BCD numbers. Binary numbers usually contain fewer 1s and OS, a s seen in the conversion in Fig. 2-3. Although longer, BCD numbers are used in digital systems when numbers must be easily converted to decimals. Translate the binary number 10001010.101 into its BCD (8421) equivalent. The procedure is shown in Fig. 2-4. T he binary number is first converted to its decimal equivalent. The binary number 10001010.101 then equals 138.625,,. Each decimal digit is then translated into its BCD equivalent. Figure 2-4 shows decimal 138.625 being converted into the BCD number 000100111000.011000100101. The entire conversion, then, translates binary 10001010.101, into the BCD number 000100111000.011000100101. “Binary-coded decimal (BCD)” is a general term that may apply to any one of several codes. The most popular BCD code is the 8421 code. The numbers 8, 4, 2, and 1 stand for the weight of each bit in the 4-bit group. Examples of o ther weighted BCD 4-bit codes are shown in Fig. 2-5. 842 1 BCD 422 1 BCD 542 1 BCD 8 s 4s 2s Is 8s 4s 2s 1s 4s 2s 2s Is 4s 2s 2s Is 5 s 4s 2s Is 5 s 4 s 2s Is Decimal 0 0 0 0 0 0 0 0 01 0 1 2 3 4 5 I 6 7 8 9 10 11 12 13 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 00 01 10 11 00 01 0 01 1 01 1 100 100 000 1 0 1 0 1 0 0001 00 10 00 1 1 0000 0001 0000 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0000 OOOJ 0010 0011 Fig. 2-5 Three weighted BCD codes 001 001 0 10 100 100 101 101 110 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 1 0 0000 0001 0010 0011 CHAP. 21 BINARY CODES 19 SOLVED PROBLEMS 2.1 - T he letters BCD stand for . Solution: The letters BCD stand for binary-coded decimal. 2.2 Convert the following 8421 BCD numbers to their decimal equivalents: ( a ) 1010 ( b ) OOOZOlll < c) 10000110 ( d ) 0101O10OOO11 ( e ) OOIIOOIO.1OO1OIOO (f) 0001000000000000.0101 Solution: The decimal equivalents of the BCD numbers are as follows: ( a ) 1010 = E RROR (no such BCD number) ( d ) 010101~000011 543 = ( b ) 000101 11 = 17 ( e ) 00110010.10010100 = 32.94 ( c) 10000110 = 86 ( f) 0001000000000000.0101 = 1000.5 2.3 Convert the following decimal numbers to their 8421 BCD equivalents: 6, ( b ) 13, ( c ) 99.9, ( d ) 872.8, ( e ) 145.6 ( f) 21.001. (a) Solution: The BCD equivalents of the decimal numbers are as follows: ( a ) 6 =0110 ( c) 99.9 = 10011001.1001 ( I?) 145.6 = 000101000101.01 10 ( b ) 13 = 00010011 ( d ) 872.8 = 100001110010.1000 ( f ) 21.001 = 00100001.000000000001 2.4 Convert the following binary numbers to their 8421 BCD equivalents: ( a ) 10000, ( b ) 11100.1, Cc) 101011.01, ( d ) 100111.11, ( e ) 1010.001, ( f ) 1111110001. Solution: The BCD equivalents of the binary ( a ) 10000 = 00010110 ( b ) 11100.1 = 00101000.0101 ( c ) 101011.01 = 01000011.00100101 2.5 Convert the following 8421 BCD numbers to their binary equivalents: ( a ) 00011000 ( b ) 01001001 ( c) 0110.01110101 ( 6 ) 00110111.0101 ( e) 01100000.00100101 ( f, 0001.001101110101 Solution: The binary equivalents of ( a ) 0001 1000 = 10010 ( b ) 01001001 = 110001 ( c ) 0110.01110101 = 110.11 2.6 numbers are as follows: ( d ) 100111.11 = 00111001.01110101 ( e 10 10.001 = 000 10000.00010010010 1 ( f) 1111110001 = 0001000000001001 the BCD numbers are as follows: ( d ) 00110111.0101 = 100101.1 ( e ) 01 100000.00100101 = 111100.01 ( f) 0001.001101110101 = 1.01 1 List three weighted BCD codes. Solution: T hree BCD codes are: ( a ) 8421 BCD code, ( b ) 4221 BCD code, ( c ) 5421 BCD code. 20 2.7 [CHAP. 2 BINARY CODES . T he 4221 BCD equivalent of decimal 98 is S ohtion: T he 4221 BCD equivalent of decimal 98 is 11111110. 2.8 . T he 5421 BCD equivalent of decimal 75 is Solution: T he 5421 BCD equivalent of decimal 75 is 10101000. 2.9 What kind of number (BCD or binary) would be easier for a worker to translate to decimal? Solution: BCD numbers are easiest to translate to their decimal equivalents. 2-3 NONWEIGHTED BINARY CODES Some binary codes are nonweighted. Each bit therefore has no special weighting. Two such nonweighted codes are the excess-3 and Gray codes. The excess-3 (XS3) code is related to the 8421 BCD code because of its binary-coded-decimal nature. In other words, each 4-bit group in the XS3 code equals a specific decimal digit. Figure 2-6 shows the XS3 code along with its 8421 BCD and decimal equivalents. Note that the XS3 number is always 3 more t han the 8421 BCD number. 8421 BCD XS3 BCD Decima I 0 1 2 3 4 5 6 7 8 9 1s 10s Is OOOO OOOl 0010 10s 0011 0011 0011 0 011 0011 0011 0011 0011 0011 0011 0100 0100 0011 0100 0101 0110 0111 001 1 0 100 0101 01 10 0111 1000 1001 0001 0000 1OOO 1001 1010 1011 1100 0011 0100 Fig. 2-6 T he excess-3 (XS3) code Consider changing the decimal number 62 to an equivalent XS3 number. Step 1 in Fig. 2-7a shows 3 being added to each decimal digit. Step 2 shows 9 and 5 being converted to their 8421 BCD equivalents. The decimal number 62 t hen equals the BCD XS3 number 10010101. Convert the 8421 BCD number 01000000 to its XS3 equivalent. Figure 2-7b shows the simple procedure. The BCD number is divided into 4-bit groups starting at the binary point. Step 1 shows 3 (binary 0011) being added to each 4-bit group. The sum is the resulting XS3 number. Figure 2-7b shows the 8421 BCD number 01000000 being converted to its equivalent BCD XS3 number, which is 01110011. BINARY CODES CHAP. 21 Decimal I xs3 6 2 9 5 +3 +3 1 @ Add 3 BCD @ Convert to binary 1 1 0 0101 01 (U) 21 Decimal-to-XS3 conversion xs3 I loo0 BCD 1100 -ydt -0011 0101 1 1 Decimal 1 5 9 1 a xs3 0100 oo00 +0011 + 0 0 1 1 0111 0011 @Add3 ( b ) BCD-to-XS3 conversion Subtract 3 Convert to decimal ( c ) XS3-to-decimal conversion Fig. 2-7 Consider the conversion from XS3 code to decimal. Figure 2-7c shows the XS3 number 10001100 being converted to its decimal equivalent. The XS3 number is divided into 4-bit groups starting at the binary point. Step 1 shows 3 (binary 0011) being subtracted from each 4-bit group. An 8421 BCD number results. Step 2 shows each 4-bit group in the 8421 BCD number being translated into its decimal equivalent. The XS3 number 10001100 is equal to decimal 59 according to the procedure in Fig. 2-7c. T he XS3 code has significant value in arithmetic circuits. The value of the code lies in its ease of complementing. If each bit is complemented (OS t o 1s and 1s t o OS), t he resulting 4-bit word will be the 9s complement of t he number. Adders can use 9s complement numbers to perform subtraction. The Gray code is another nonweighted binary code. The Gray code is not a BCD-type code. Figure 2-8 compares the Gray code with equivalent binary and decimal numbers. Look carefully at the Gray code. Note that each increase in count (increment) is accompanied by only I bit changing state. Look a t the change from the decimal 7 line to the decimal 8 line. In binary all four bits change state (from 0111 t o 1000). I n this same line the Gray code has only the left bit changing state (0100 t o 1100). This change of a single bit in the code group per increment characteristic is important in some applications in digital electronics. Decimal Binary I Gray code I Decimal ~~ 0 1 2 3 4 5 6 7 m m OOOl 0010 001 1 01 0 0 0101 01 10 0111 OOOl 001 1 001 0 01 10 0111 0101 0100 8 9 1 0 11 12 13 1 4 15 1 Binary Gray code ~~ loo0 10 01 1010 1 11 0 1100 10 11 1110 1111 1100 10 11 1111 1110 1010 1 11 0 10 01 loo0 Fig. 2-8 The Gray code Consider converting a binary number to its Gray code equivalent. Figure 2-9a shows the binary number 0010 being translated into its Gray code equivalent. Start at the MSB of t he binary number. Transfer this to the left position in the Gray code as shown by the downward arrow. Now add t he 8s bit to the next bit over (4s bit). The sum is 0 (0 + 0 = 0), which is transferred down and written as the second bit from the left in the Gray code. The 4s bit is now added to the 2s bit of t he binary number. The sum is 1 (0 + 1 = 1) and is transferred down and written as ithe third bit from the left in the Gray 22 [CHAP. 2 BINARY CODES A;// B inary 0 I l sum sum 0 I G r a y code l s um 1 1 B inary 1 0 1 1 Gray code (4 A ;/ i ! I s um 1 l 1 1 1 l 1 sum 1 sum sum 0 I 1 (b) Fig. 2-9 Binary-to-Gray code conversion code. The 2s bit is now added to the 1s bit of the binary number. The sum is 1 (1 + 0 = 1) and is transferred and written as the right bit i n t he Gray code. The binary 0010 is then equal to t he Gray code number 0011. This can be verified in the decimal 2 line of the table in Fig. 2-8. T he rules for converting from any binary number to its equivalent Gray code number are as follows: 1. T he left bit is the same in the Gray code as i n t he binary number. 2. Add the MSB to the bit on its immediate right and record the sum (neglect any carry) below in the Gray code line. 3 . Continue adding bits to the bits on their right and recording sums until the LSB is reached. 4. The Gray code number will always have the same number of bits as the binary number. Try these rules when converting binary 10110 to its Gray code equivalent. Figure 2-96 shows the MSB(1) in the binary number being transferred down and written as part of the Gray code number. The 16s bit is then added to t he 8s bit of t he binary number. The sum is 1 ( 1 + 0 = 11, which is recorded in the Gray code (second bit from left). Next the 8s bit is added to the 4s bit of the binary number. The sum is 1 (0 + 1 = I ), which is recorded in t he Gray code (third bit from the left). Next the 4s bit is added to the 2s bit of the binary number. The sum is 0 (1 + 1 = 10) because the carry is dropped. The 0 is recorded in the second position from the right in the Gray code. Next the 2s bit is added to the 1s bit of t he binary number. The sum is 1 (1 + 0 = 11, which is recorded in the Gray code (right bit). The process is complete. Figure 2-9b shows the binary number 10110 being translated into the Gray code number 11101. Convert the Gray code number 1001 to its equivalent binary number. Figure 2-10a details the procedure. First the left bit (1) is transferred down to t he binary line to form the 8s bit. The 8s bit of t he binary number is transferred (see arrow) up above the next Gray code bit, and the two are added. The sum is 1 (1 + 0 = 1), which is written in the 4s bit place in the binary number. The 4s bit ( 1) is then added to t he next Gray code bit. The sum is 1 (1 + 0 = 1). This 1 is written in t he 2s place of the binary number. The binary 2s bit ( 1) is added to the right Gray code bit. The sum is 0 (1 + 1 = 10) because the carry is neglected. This 0 is written in the 1s place of the binary number. Figure 2-10a shows the Gray code number 1001 being translated into its equivalent binary number 1110. This conversion can be verified by looking at decimal line 14 in Fig. 2-8. Convert the 6-bit Gray code number 01 1011 to its 6-bit binary equivalent. Start at the left and follow the arrows in Fig. 2 -lob. Follow the procedure, remembering that a 1 + 1 = 10. T he carry of 1 is neglected, and the 0 is recorded on the binary line. Figure 2-106 shows that the Gray code number 011011 is equal to the. binary number 010010. r-* 1 -0 1 Gray code 0 I s um 1J I- 1 I s um 1 I B inary -1 B inary ( a) (h) Fig. 2-10 Gray code-to-binary conversions s um 1- 0 1 1 CHAP. 21 BINARY CODES 23 SOLVED PROBLEMS 2.10 T he letters and numbers XS3 stand for - code. Solution: XS3 stands for the excess-3 code. 2.11 T he . (8421, XS3) BCD code is an example of a nonweighted code. Solution: The XS3 BCD code is an example of a nonweighted code. 2.12 T he (Gray, XS3) code is a BCD code. Solution: The XS3 code is a BCD code. 2.13 Convert the following decimal numbers to their XS3 code equivalents: ( b:) 18, ( c) 37, ( d ) 42, ( e ) 650. ( a ) 9, Solution: The XS3 equivalents of the decimal numbers are as follows: ( a ) 9 = 1100 ( c) 37 = 01 101010 ( e ) 650 = 100110000011 ( 6) 18 = 01001011 ( d ) 42 = 01 110101 2.14 Convert the following 8421 BCD numbers to their XS3 code equivalents: 0001, ( b ) 0111, ( c) 011OOOO0, ( d ) 00101001, ( e ) IOOOOIOO. (a) . Solution: The XS3 equivalents of the 8421 BCD numbers are as follows: ( c) 01100000 = 10010011 ( e ) 10000100 = 10110111 ( b ) 0111 = 1010 ( d ) 00101001 = 01011100 ( a ) 0001 = 0100 2.15 Convert the following XS3 numbers to their decimal equivalents: 10011010, ( e ) IOOOOIOI. ( a ) 0011, ( b ) 01100100, ( c ) 11001011, ( d ) Solution: The decimal equivalents of the XS3 numbers are as follows: ( a ) 0011 = 0 ( c) 11001011 = 98 ( e ) 10000101 = 52 ( h ) 01 100100 = 31 ( d ) 10011010 = 67 2.16 T he (Gray, XS3) code is usually used in arithmetic applications in digital circuits. Solution: The XS3 code is usually used in arithmetic applications. 2.17 Convert the following straight binary numbers to their Gray code equivalents: ( a ) 1010, ( b ) 10000, ( c ) 10001, ( d ) 10010, ( e ) 10011. Solution: The Gray code equivalents of the binary numbers are as foIlows: ( a ) 1010 = 11 11 ( c ) 10001 = 11001 ( e ) 10011 = 11010 ( b ) 10000 = 11000 ( d ) 10010 = 11011 24 21 .8 [CHAP. 2 BINARY CODES Convert the following Gray code numbers to their straight binary equivaIents: ( a ) 0100, ( b ) 11111, ( c ) 10101, ( d ) 110011, ( e ) 011100. Solution: T he binary equivalents of the Gray code numbers are as follows: ( a ) 0100 = 0111 ( c ) 10101 = 11001 ( e ) 01 1100 = 0101 11 ( b ) 11111 = 10101 ( d ) 110011 = 100010 21 .9 T he Gray code’s most important characteristic is t hat, when the count is incremented by 1, -(more than, only) 1 bit will change state. Solution: The Gray code’s most important characteristic is that, when the count is incremented by I , only 1 bit will change state. 2-4 ALPHANUMERIC CODES Binary OS and 1s have been used to represent various numbers to this point. Bits can also be coded to represent letters of t he alphabet, numbers, and punctuation marks. One such 7-bit code is the A merican Standard Code for Information Interchange (ASCII, pronounced “ask-ee”), shown in Fig. 2-11. Note that the letter A is represented by 1000001, whereas B in the ASCII code is 1000010. Character Space ! I/ # $ ”/, & I ( ) * + 9 I ASCII 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 EBCDIC Character m 0100 0101 0111 0111 0101 0110 0101 0111 0100 0101 0101 0100 0110 0110 0100 0110 oooo A 1010 1 111 1011 1011 1100 0000 1101 1101 1101 1100 1110 1011 0000 1011 oO01 B C D E F G H I J K L M N 0 P oooo 1 111 1111 1 111 1 111 1 111 1 111 1 111 1 111 1 111 1111 0000 oO01 0010 0011 0100 0101 0110 0111 1oO0 1001 oO01 0010 0011 0100 0101 0110 0111 1oO0 1001 1010 1011 1100 1101 1110 1 111 ASCII 100 100 100 100 100 100 1 00 100 100 100 100 100 100 EBCDIC oO01 0010 0011 0100 0101 0110 0111 1oO0 1001 1010 1011 1100 1101 100 1110 100 1 111 101 oooo 1100 1100 1100 1100 1100 1100 1100 1100 1100 1101. 1101 1101 1101 1101 1101 1101 Oool 0010 0011 0100 0101 0110 0111 1000 1001 oO01 0010 0011 0100 0101 0110 0111 101 101 101 101 101 101 101 101 101 101 1101 1101 1110 1110 1110 1110 1110 1110 1110 1110 1000 1001 0010 0011 0100 0101 0110 0111 1000 1001 ~~ 0 1 2 3 4 5 6 7 8 9 011 011 011 011 011 011 011 011 011 011 Oool 0010 0011 0100 0101 0110 0111 1oO0 1001 Q R S T U v w X Y z Fig. 2-11 Alphanumeric codes oO01 0010 0011 0100 0101 0110 0111 loo0 1001 1010 BINARY CODES CHAP. 21 25 The ASCII code is used extensively in small computer systems to translate from the keyboard characters to computer language. The chart in Fig. 2-11 is not ,a complete list of all the combinations in the ASCII code. Codes that can represent both letters and numbers are called alphanumeric codes. A nother alphanumeric code that is widely used is the Extended Binary-Coded Decimal Interchange Code (EBCDIC, pronounced “eb-si-dik”). Part of t he EBCDIC code is shown in Fig. 2-11. Note that the EBCDIC code is an 8-bit code and therefore can have more variations and characters than the ASCII code can have. The EBCDIC code is used in many larger computer systems. The alphanumeric ASCII code is the modern code for getting information into and out of microcomputers. ASCII is used when interfacing computer keyboards, printers, and video displays. ASCII has become the standard input/output code for microcomputers. Other alphanumeric codes that you may encounter are: 1. 7-bit BCDIC ( Binary-Coded Decimal Interchange Code). 2. 8-bit EBCDIC (Extended Binary-Coded Decimal Interchange Code). Used on some IBM equipment. 3. 7-bit Selectric. Used to control the spinning ball on IBM Selectric typewriters. 4. 12-bit Hollerith. Used on punched paper cards. SOLVED PROBLEMS 2.20 Binary codes that can represent both numbers and letters are called codes. Solution: Alphanumeric codes can represent both numbers and letters. 2.21 T he following are abbreviations for what? ( a ) ASCII ( b ) E BCDIC Solution: ( a) ASCII = American Standard Code for Information Interchange ( b ) EBCDIC = Extended Binary-Coded Decimal Interchange Code 2.22 if the K on the Refer to Fig. 2-12. The ASCII keyboard-encoder output would be typewriter-like keyboard were pressed. MSR Message for keyboard operator --+ Input I encoder b To computer system U 4 L o utput J I LSB Fig. 2-12 ASCII keyboard-encoder system Solution: The ASCII output would be 1001011 if the K on the keyboard were pressed. 26 2.23 R efer to Fig. 2-12. List the 12 ASCII keyboard-encoder outputs for entering the message “pay $1000.00.” Solution: T he ASCII codes for ( a ) P = 1010000 (d) ( b ) A = 1000001 (e) ( c) Y = 1011001 (f) 2.24 [CHAP. 2 BINARY CODES the characters in the Space = 0100000 $ = 0100100 1 = 0110001 message are as follows: (g) O =OI O O ZO O ( j ) . = OIO111O ( h ) 0 = 0110000 ( k ) 0 = 0110000 ( i) 0 = 0110000 ( I) 0 = 0110000 code is a 12-bit alphanumeric code used on punched paper cards. T he Solution: T he 12-bit Hollerith code is used on punched cards. 2.25 T he 7-bit ers. code is considered the industry standard for input/output on microcomput- Solution: The 7-bit ASCII (American Standard Code for Information Interchange) code is considered the industry standard for microcomputer inputs and outputs. Supplementary Problems 2.26 Electronic devices that translate from one code to another are called ( a ) or ( b ) -Ans. ( a ) encoders ( b ) decoders 2.27 Convert the following 8421 BCD numbers to their decimal equivalents: 10010000, ( b ) 111 11111, ( c) 0111.0011, ( d ) 01100001.00000101. Ans. ( a ) 10010000 = 90 ( c) 0111.0011 = 7.3 ( b ) 11111111 = E RROR (no such BCD number) ( d ) 01100001.00000101 = 61.05 (a) 2.28 Convert the following decimal numbers to their 8421 BCD equivalents: 10, ( 6) 342, ( c) 679.8, ( d ) 500.6. Ans. ( a ) 10 = 00010000 ( c ) 679.8 = 011001111001.1000 ( b ) 342 = 001101000010 ( d ) 500.6 = 010100000000.01 10 (a) 2.29 Convert the following binary numbers to their 10100, ( b ) 11011.2, ( c) 100000.01, Ans. ( a ) 10100 = 00100000 (c) ( b ) 11011.1 = 00100111.0101 (d) (a) 2.30 8421 BCD equivalents: ( d ) 111011.11. 100000.01 = 00110010.00100101 111011.11 = 01011001.01110101 Convert the following 8421 BCD numbers to their binary equivalents: 01011000, ( h ) 000100000000, ( c) 1001.01110IO1, ( d ) 0011.0000011000100101. Ans. ( a ) 01011000 = 111010 ( c) 1001.01110101 = 1001.11 ( b ) 000100000000 = 1100100 ( d ) 0011.0000011000100101 = 11.0001 (a) . 2.31 The 4221 BCD equivalent of decimal 74 is 2.32 The 5421 BCD equivalent of decimal 3210 is 2.33 The BCD code is convenient when translations must be made to Ans. decimal Ans. . 11011000 Ans. 001 1001000010000 (binary, decimal) numbers. CHAP. 21 23 .4 23 .5 BINARY CODES “Excess-3” code is often shortened to . 27 Ans. XS3 Convert the following decimal numbers to their XS3 code equivalents: ( d ) 4089. ( c ) 32 = 01100101 ( b ) 16 = 01001001 ( d ) 4089 = 0111001110111100 ( a ) 7, ( b:) 16, ( c ) 32, Ans. ( a ) 7 = 1010 23 .6 Convert the following XS3 numbers to their decimal equivalents: 1100, ( b ) 10101000, ( c ) 100001110011, ( d ) 0100z01101100101. Ans. ( a ) 1100 = 9 ( c ) 100001110011 = 540 ( b ) 10101000 = 75 ( d ) 0100101101100101 = 1832 (a) 23 .7 Convert the following straight binary numbers to their Gray code equivalents: ( a ) 0110, ( b ) 10100, ( c ) 10101, ( d ) 10110. Ans. ( a ) 0110 = 0101 ( b ) 10100 = 11110 ( c ) 10101 = 11111 ( d ) 10110 = 11101 23 .8 Convert the following Gray code numbers to their straight binary equivalents: ( a ) 0001, ( b ) 11100, ( c ) 10100, ( d ) 10101. Ans. ( a ) 0001 = 0001 ( b ) 11100 = 10111 ( c ) 10100 = 11000 ( d ) 10101 = 11001 23 .9 EBCDIC is a(n) Ans. 8 24 .0 T he 7-bit alphanumeric computers. Ans. ASCIl -bit alphanumeric code used in some IBM equipment. code serves as the industry standard for input/output on micro- Chapter 3 Basic Logic Gates 3-1 INTRODUCTION T he logic gate is the basic building block in digital systems. Logic gates operate with binary numbers. Gates are therefore referred to as binary logic gates. All voltages used with logic gates will be either HIGH or LOW. In this book, a HIGH voltage will mean a binary 1. A LOW voltage will mean a binary 0. Remember that logic gates are electronic circuits. These circuits will respond only to HIGH voltages (called 1s) o r LOW (ground) voltages (called OS). All digital systems are constructed by using only three basic logic gates. These basic gates are called the AND gate, the O R gate, and the NOT gate. This chapter deals with these very important basic logic gates, or functions. 3-2 THE AND GATE T he AND gate is called the “all or nothing” gate. The schematic in Fig. 3 - la shows the idea of the AND gate. The lamp ( Y )will light only when both input switches ( A and B ) a re closed. All the possible combinations for switches A and B a re shown in Fig. 3-lb. The table in this figure is called a truth table. The truth table shows that the output ( Y ) is enabled (lit) only when both inputs are closed. +ll ( a) A N D c ircuit using s witches Input switches open open closed closed output light open closed open closed no no no Yes ( b ) T ruth table Fig. 3-1 T he standard logic symbol for the AND gate is drawn in Fig. 3-2a. This symbol shows the inputs as A and B . T he output is shown as Y . This is the symbol for a 2-input A ND gate. The truth table for the 2-input AND gate is shown in Fig. 3-2b. The inputs are shown as binary digits (bits). Note that only when both input A and input B a re 1 will t he output be 1. Binary 0 is defined as a LOW, or ground, voltage. Binary 1 is defined as a HIGH voltage. I n this book, a HIGH voltage will mean about + 5 volts (V) if t he integrated circuits (ICs) being used are from the TTL family. Boolean algebra is a form of symbolic logic that shows how logic gates operate. A Boolean expression is a “shorthand” method of showing what is happening in a logic circuit. The Boolean expression for the circuit in Fig. 3-2 is 28 CHAP. 31 29 BASIC LOGIC GATES Inputs Output + B ( a ) A ND-gate symbol Inputs 0 0 1 1 Output 0 1 0 1 0 0 0 1 0 = low voltage 1 = high voltage ( b ) A ND truth table Fig. 3-2 A-B=Y T he Boolean expression is read as A AND ( . means AND) B equals the output Y . T he dot means the logic function AND in Boolean algebra, not multiply as in regular algebra, Sometimes the dot ( - ) is left out of the Boolean expression. The Boolean expression for the 2-input AND gate is then: (a) AB=Y T he Boolean expression reads A A ND B equals the output Y . A logic circuit will often have three variables. Figure 3-3a shows the Boolean expression for a 3-input AND gate. The input variables are A , B , and C. T he output is shown as Y . T he logic symbol for this 3-input AND expression is drawn in Fig. 3-3b. The three inputs ( A , B , C ) a re on the left of t he symbol. The single output ( Y ) is on the right of the symbol. The truth table in Fig. 3-3c shows the eight possible combinations of the variables A , B , and C. Note that the top line in the table is the binary count 000. T he binary count then proceeds upward to 001, 010, 011, 100, 101, 110, and finally 111. Note that only when all inputs are 1 is t he output of the AND gate enabled with a 1. Inputs A.B*C=Y * ( a ) Three-variable Boolean expression Inputs :3->y . 0 0 0 0 1 1 1 1 Output C ( b) 3-input A N D gate symbol Fig. 3-3 Output 00 01 10 11 00 01 10 11 0 0 0 0 0 0 0 1 30 BASIC LOGIC GATES [CHAP. 3 Consider the AND truth tables shown in Figs. 3-2b and 3 -3c. In each truth table the unique output from the AND gate is a HIGH only when all inputs are HIGH. Designers look at each gate’s unique output when deciding which gate will perform a certain task. The laws of Boolean algebra govern how AND gates operate. The formal laws for the A ND function are: A*0=0 A.l=A A*A=A A.A=O You can prove the accuracy of these laws by referring back to the truth table in Fig. 3-2. T hese are general statements that are always true about the AND function. AND gates must follow these laws. Note the bar over the variable in the last law. The bar over the variable means not A , o r the opposite of A . SOLVED PROBLEMS 3.1 Write the Boolean expression for a 4-input AND gate. Solution: A - B . C - D = Y or A B C D = Y 32 . Draw the logic symbol for a 4-input AND gate. Solution: See Fig. 3-4. Fig. 3-4 Symbol for a 4-input AND gate 3.3 Draw a truth table for a 4-input AND gate. Solution: I nputs I nputs o utput D C B A 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y o utput D C B A 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y BASIC LOGIC GATES CHAP. 31 3.4 31 I n Fig. 3-5, what would the output pulse train look like‘? 0 h g f e d 0 1 c b a F g 3-5 Pulse-train problem i. Solution: In Fig. 3-5, t he output waveform would look exactly like the input waveform at input A . pulse c1 = 1 pulse c = 0 pulse g = 1 pulse e = 1 pulse b = 0 pulse d = 1 pulse f = 0 pulse h = 0 35 . In Fig. 3-6, what would the output pulse train look like? Note that two pulse trains are being ANDed. h g f e d c o o oJi 1 b a 1 F g 3-6 Pulse-train problem i. Solution: In Fig. 3-6, the output pulses would be as follows: pulse a = 0 pulse c = 0 pulse e = 0 pulse g = 0 pulse b = 1 pulse d = 1 pulse f = 0 pulse h = 0 3-3 THE OR GATE T he OR gate is called the “any or all” gate. The schematic in Fig. 3-7a shows the idea of t he O R gate. The lamp ( Y ) will glow when either switch A or switch B is closed. The lamp will also glow when both switches A and B a re closed. The lamp ( Y )will no2 glow when both switches ( A and B ) a re open. All the possible switch combinations are shown in Fig. 3-7h. T he truth table details the OR function of t he switch and lamp circuit. The output of t he OR circuit will be enabled (lamp lit) when any or all input switches are closed. Input switches output light 41 B Y + wFig. 3-7 A Y open open closed closed open closed open closed no Yes Yes Yes 32 [CHAP. 3 BASIC LOGIC GATES T he standard logic symbol for an OR gate is drawn in Fig. 3-8a. Note the different shape of the OR gate. The OR gate has two inputs labeled A and B . T he output is labeled Y . T he shorthand Boolean expression for this OR function is given as A + B = Y . Note that the plus ( + ) symbol means O R in Boolean algebra. The expression ( A + B = Y ) is read as A O R ( + means O R) B equals output Y . You will note that the plus sign does nut mean to add as it does in regular algebra. A A Y output +(U) + Inputs OR-gate symbol Inputs Output I 00 01 10 11 0 1 1 1 0 = l ow voltage 1 = high voltage ( h ) OR truth table Fig. 3-8 T he truth table for the 2-input OR gate is drawn in Fig. 3-8b. The input variables ( A and B ) a re given on the left. The resulting output ( Y ) is shown in the right column of t he table. The O R gate is enabled ( output is 1) anytime a 1 a ppears at any or all of t he inputs. As before, a 0 is defined as a LOW (ground) voltage. A 1 in the truth table represents a HIGH ( + 5 V) voltage. The Boolean expression for a 3-input OR gate is written in Fig. 3-9a. The expression reads A OR B OR C equals output Y . T he plus sign again signifies the O R function. A logic symbol for the 3-input O R gate is drawn in Fig. 3-9h. Inputs A , B , and C a re shown on the left of the symbol. Output Y is shown on the right of t he O R symbol. This symbol represents some circuit that will perform the OR function. Inputs 1 Output I CBAl A+B+C=Y (a) Three-variable Boolean expression A3> Inputs B C 0 0 0 0 1 1 1 1 Y output Y 00 01 10 11 00 01 10 11 ( c ) Truth table with three variables ( b ) 3-input OR gate symbol Fig. 3-9 CHAP. 31 33 BASIC LOGIC GATES A t ruth table for the 3-input O R gate is shown in Fig. 3-9c. The variables ( A , B , and C ) a re shown on the left side of the table. The output ( Y ) is listed in the right column. Anytime a 1 a ppears at any input, the output will be 1. Consider the OR t ruth tables in Figs. 3-86 and 3-9c. In each truth table the unique output from the OR gate is a LOW only when all inputs are LOW. Designers look at each gate’s unique output when deciding which gate will perform a certain task. The laws of Hoolean algebra govern how an O R gate will operate. The formal laws for t he OR function are: AdO=A A+l=l A+A=A A+A=l Looking at the truth table in Fig. 3-8 will help you check these laws. These general statements are always true of the O R function. The bar over the last variable means not A , o r the opposite of A . SOLVED PROBLEMS 3.6 Write the 13001ean expression for a 4-input O R gate. Solution: A +B 3.7 +-C + D = Y Draw the logic symbol for a 4-input O R gate. Solution: S ee Fig. 3-10. Fig. 3-10 Symbol used for a 4-input O R g ate 3.8 Draw a truth table for a 4-input OR gate. Solution: I nputs D C B 0 0 0 O 0 0 0 0 0 0 0 0 O 0 0 0 1 1 1 1 1 0 0 0 l1 1 1 0 0 0 1 1 I nputs output A 0 l1 I O0 ( l1 I 01 1 0 1 output Y 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 34 3.9 - (CHAP. 3 BASIC LOGIC GATE.!! I n Fig. 3-11, what would the output pulse train look like? I1 I frd - c ho \ - V F g 3-11 Pulsc-train problcm i. salallan: In Fig. 3-11. t he output wavcform would l ook exactly like t he input wavcform a t input A . PUk 4 1 PUIW C 1 PUkC C 1 P UlSC R 0 pulse h 0 p ulw n = 0 p u l v I= 1 - - 3.10 - 9 I n Fig. 3-12, what would the output pulse t rain look like? Note that two prilse trains are k i n g ORed together. F g 3-12 Pulsc-train problem i. Solulion: In Fig. 3-12. thc o utput pulscs would bc as follows: pulsc U - I pulsc c - 0 pulsc e - 1 pulsc R - 0 pulsc h = 1 pulse d = 1 ~ U I W f- 1 p ulw h 1 - 3 4 T HENOTGATE A N OT gate is a lso callcd an inverter. A N OT gate, or inverter, is a n unusual gate. T he N OT gate has only one input and onc output. Figure 3-13a illustrates the logic symbol for t he inverter, or N OT gate. Input A -D- (a) A=A Y O uIDUI ( c) NOT Bookan expression NOT-pate symbol A o; u t A 0 t ;I I 7 - 0 ( d ) Douhle invenion Input A ( h) NOT-pte truth tabk -0- y Output ( r ) Alternative inverter symbol Fig. 3-13 CHAP. 31 35 BASIC LOGIC GATES T he process of inverting is simple. Figure 3-13b is the truth table for the NOT gate. The input is always changed to its opposite. If t he input is 0, t he NOT gate will give its c omplement, o r opposite, which is 1. If the input to the NOT gate is a 1, t he circuit will complement it to give a 0. This inverting is also called complementing o r negating. T he terms negating, complementing, and inverting all mean the same thing. The Boolean expression for inverting is shown in Fig. 3-1%. T he expression A r eads as A equals the output not A . T he bar over the A means to complement A . Figure 3-13d illustrates what would happen if two inverters were used. The Boolean expressions are written above the lines between the inverters. The input A is inverted to A h o t A ). T he A is then inverted again to form A (not not A ) . T he double inverted A (2)equal to the original A , as shown in Fig. 3-13d. In the is shaded section below the inverters, a 0 bit is the input. The 0 bit is complemented to a 1. T he 1 bit is complemented again back to a 0. After a digital signal goes through two inverters, it is restored to its original form. A n alternative logic symbol for the NOT gate or inverter is shown in Fig. 3-13e. T he invert bubble may be on e ither the input or the output side of the triangular symbol. When the invert bubble appears on t he input side of the NOT symbol (as in Fig. 3-13e), t he designer is usually trying to suggest that this is an active LOW input. An active LOW input requires a LOW to activate some function in the logic circuit. The alternative NOT gate symbol is commonly used in manufacturer’s logic diagrams. The laws of Boolean algebra govern the action of t he inverter, or NOT gate. The formal Boolean algebra laws for the NOT gate are as follows: =A 6=i If A If A = i=o 1, then then - = 0, A=O A=1 A =A You can check these general statements against the truth table and diagrams in Fig. 3-13. SOLVED PROBLEMS 3.11 In Fig. 3-14, what is the output at point ( e) if t he input at point ( a ) is a 0 bit? Fig. 3-14 Inverter problem Solution: T he output at point ( e ) is a 0 bit. 3.12 What is the Boolean expression at point ( b ) in Fig. 3-14? Solution: T he Boolean expression at point ( b ) is A(not A ). 3.13 What is the Boolean expression at point ( c) in Fig. 3-14? Solution: The Boolean expression at point ( c ) is z ( n o t not A ). A equals A according to t he laws of Boolean algebra. 36 BASIC LOGIC GATES 3.14 [CHAP. 3 W hat is the Boolean expression at point ( d ) in Fig. 3-14? Solution: - T he Boolean expression at point ( d ) is z ( n o t not not A ) . 3.15 - equals A (not A ). What is the output at point ( d ) in Fig. 3-14 if t he input at point ( a ) is a 1 bit? Solution: The output at point ( d ) is a 0 bit. 3.16 T he NOT gate is said to invert its input. List two o ther words we can use instead of “invert.” Solution: The words complement and negate also mean to invert. 3.17 T he NOT gate can have (one, many) input variableh). Solution: The NOT gate can have one input variable. 3-5 COMBINING LOGIC GATES Many everyday digital logic problems use several logic gates. The most common pattern of gates is shown in Fig. 3-15a. This pattern is called the AND-OR pattern. The outputs of t he AND gates (1 a nd 2) a re feeding the inputs of t he OR gate (3). You will note that this logic circuit has three inputs ( A , B , a nd C). T he output of t he entire circuit is labeled Y . A B Inputs C C (U) C ( b) Boolean expressions at the outputs of the A ND gates AND-OR logic circuit (c) Boolean expression at the output of the OR gate Fig. 3-15 CHAP. 31 BASIC LOGIC GATES 37 Let us first determine the Boolean expression that will describe this logic circuit. Begin the examination at gate (1). This is a 2-input AND gate. The output of this gate will be A - B ( A A ND B ) . This expression is written at the output of gate (1) in Fig. 3-15b. G ate (2) is also a 2-input AND gate. The output of this gate will be B C ( B A ND C ) . This expression is written at the output of gate (2). Next the outputs of gates (1) and (2) a re ORed together by gate ( 3). Figure 3-15c shows A B being ORed with B C. T he resulting Boolean expression is A B + BC = Y . T he Boolean expression A B + BC = Y is read as ( A A ND B ) O R ( B A ND C ) will equal a 1 a t output Y . You will note that the ANDing is done first, and finally the ORing is done. The next question arises. What is the truth table for t he AND-OR logic diagram in Fig. 3-15? Figure 3-16 will help us determine the truth table for the Boolean expression A B + BC = Y . T he Boolean expression tells us that if both variables A A ND B a re 1, t he output will be 1. Figure 3-16 illustrates that the last two lines of the truth table have 1s in both t he A and B positions. Therefore an output 1 is placed under the Y column. Fig. 3-16 Complementing output column of truth table from a Boolean expression T he Boolean expression then goes on to say that another condition will also generate an output of 1. T he expression says that B A ND C will also generate a 1 o utput. Looking at the truth table, it is found that the fifth line from the bottom has 1 s in both t he B A ND C positions. The bottom line also has 1 s in both t he B A ND C positions. Both of these lines will generate a 1 o utput. The bottom line already has a 1 u nder the output column ( Y ) .T he fifth line up will also get a 1 in the output column ( Y ) .These are the only combinations that will generate a 1 o utput. The rest of t he combinations are then listed as 0 o utputs under column Y . SOLVED PROBLEMS 3.18 What is the Boolean expression for the AND-OR logic diagram in Fig. 3-17? Solution: T he Boolean expression for the logic circuit shown in Fig. 3-17 is AB+ A C = Y T he expression is read as (not A AND B ) O R ( A AND C ) equals output Y . 38 [CHAP. 3 BASIC LOGIC GATES I I A C C Fig. 3-17 AND-OR logic-circuit problem 3.19 W hat is the truth table for the logic diagram in Fig. 3-17? Solution: Output Inputs Inputs Output A C Y A B C Y 0 0 0 0 3.20 B 0 0 1 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 W hat is the Boolean expression for t he AND-OR logic diagram in Fig. 3-18? A B C Y Fig. 3-18 AND-OR logic-circuit problem Solution: The Boolean expression for the logic circuit shown in Fig. 3-18 is The expression reads as ( A AND B AND C ) OR (not A AND not B AND not C ) equals output Y. 3.21 W hat is t he truth table for the logic diagram in Fig. 3-18? CHAP. 3 1 39 BASIC LOGIC GATES Solution: * * 0 3.22 1 0 1 0 0 1 1 1 0 0 1 What is the Boolean expression for the AND-OR logic diagram in Fig. 3-19? Fig. 3-19 AND-OR logic-circuit problem Solution: T he Boolean expression for the logic circuit shown in Fig. 3-19 is ABT +A’C + x E = Y . T he expression reads a s ( A AND B AND not C ) O R (not A A ND C ) O R (not A A ND not B ) equals output Y . 3.23 What is the truth table for the logic diagram in Fig. 3-19? Solution: Inputs 1 O utput I Inputs 1 Output 3-6 USING PRACTICAL LOGIC GATES Logic functions can be implemented in several ways. In the past, vacuum-tube and relay circuits performed logic functions. Presently tiny integrated circuits (ICs) perform as logic gates. These ICs contain the equivalent of miniature resistors, diodes, and transistors. 40 [CHAP. 3 BASIC LOGIC GATES Pin 1 Fig. 3-20 14-pin DIP integrated circuit A popular type of IC is illustrated in Fig. 3-20. This case style is referred to as a dual-in-line package (DIP) by IC manufacturers, This particular IC is called a 14-pin DIP integrated circuit. Note that immediately counterclockwise from the notch on the IC shown in Fig. 3-20 is pin number 1. T he pins a re numbered counterclockwise from 1 t o 14 when viewed from the top of the IC. Manufacturers of ICs provide pin diagrams similar to the one in Fig. 3-21 for a 7408 IC. Note that this IC contains four 2-input A ND gates; thus it is called a quadruple 2-input A ND gate. Figure 3-21 shows the IC pins numbered from 1 through 14 in a counterclockwise direction from the notch. The power connections t o the IC a re the GND (pin 7) and Vcc (pin 14) pins. All other pins are the inputs and outputs to t he four A ND gates. The 7408 IC is part of a family of logic devices. It is one of many qq 6:: x p 1Y 3 1 1 4Y 2Y 6 GND~ 1 I Fig. 3-21 Pin diagram for a 7408 IC Inputs o utput y--)- B ( a ) AND-gate logic symbol I A jInputs bl. , w !B, p (7408) ( b ) Wiring an AND gate using a 7408 1C Fig. 3-22 o utput 150 R L CHAP. 3 1 41 BASIC LOGIC GATES devices in the transistor-transistor logic (TTL) family of logic circuits. TTL devices are currently among the most popular logic devices. Given the logic diagram in Fig. 3-22a, wire a circuit using a 7408 IC. A wiring diagram for the circuit is shown in Fig. 3-226. A 5-V power supply is used with all TTL devices. The positive (V',) and negative (GND) power connections are made to pins 14 and 7. Input switches ( A and B ) a re wired to pins 1 and 2 of the 7408 IC. Note that, if a switch is in the up position, a logical 3 ( + 5 V) is applied to limiting the input of the AND gate. At the right, a light-emitting diode (LED) and 150-ohm (a) resistor are connected to ground. If the output at pin 3 is HIG'H ( + 5 V), c urrent will flow through the LED. Lighting the LED indicates a HIGH, or a binary 1, a t the output of t he AND gate. The truth table in Fig. 3-23 shows the results of operating the 2-input AND circuit. The LED in Fig. 3-22b lights only when both input switches ( A and B ) a re at 5 V. + I Inputs Output Voltage G ND GND +5 v LED lights? GND GND GND no no no GND +5 v G ND Fig. 3-23 Truth table €or a TTL-type A ND gate Manufacturers o integrated circuits also produce other logic functions. Figure -24 illustrates pin diagrams for two basic TTL ICs. Figure 3-24a is the pin diagriam for a quadruple 2-input OR gate. In other words, the 7432 IC contains four 2-input O R gates. It c:ould be wired and tested in a manner similar to the testing of the AND gate shown in Fig. 3-22b. :fcJ IA IY 3 IY ZA 2Y 3A 3Y G ND ( a ) Pin diagram for a 7432 IC ( b ) Pin diagram for a 7404 IC Fig. 3-24 T he 7404 IC shown in Fig. 3-24b is also a TTL device. The 7404 IC contains six N OT gates, or inverters. The 7404 is described by the manufacturer as a hex inverter IC. Note that each IC has its power connections (V,, and GND). A 5-V dc power supply is always used with TTL logic circuits. Two variations of DIP ICs are illustrated in Fig. 3-25. The integrated circuit shown in Fig. 3-25a has 16 pins with pin 1 identified by using a dot instead of a notch. The IC shown in Fig. 3-25b is a 24-pin DIP integrated circuit with pin 1 located immediately counterclockwise (when viewed from the top) from the notch. 42 [CHAP. 3 BASIC LOGIC G ATES (a) 16-pin D IP i ntegrated circuit ( h ) 24-pin D IP integrated circuit Fig. 3-25 T he 7408, 7432, and 7404 ICs you studied in this section were all from the T TL logic family. The newer complementary metal oxide semiconductor (CMOS) family of ICs has been gaining popularity because of its low power requirements. Logic gates ( AND, O R, and NOT) also are available i n D IP IC form in the CMOS family. Typical DIP ICs might be the CMOS 74C08 quad 2-input A ND gate, 74C04 hex inverter, or the 74C32 quad 2-input O R gate. The 74CXX series of CMOS gates is not directly compatible with the TTL 7400 series of integrated circuits. SOLVED PROBLEMS 3.24 What logic function is performed by the circuit illustrated in Fig. 3-26? T v r o utput Y + - 0 0 - 4 11 -2 91 Solution: T he 7432 I C performs as a 2-input O R gate when wired as shown in Fig. 3-26. 3.25 Write the Boolean expression for the circuit shown in Fig. 3-26. Solution: T he Boolean expression for the 2-input O R function (Fig. 3-26) is A 32 .6 + B = Y. What is the voltage of the power supply at the left in Fig. 3-26? The 7432 IC is a TTL device. Solution: TTL devices use a 5-V d c power supply. CHAP. 31 3.27 43 BASIC LOGIC GATES If both switches A and B in Fig. 3-26 a re in the down positiori (toward ground) the output LED will be (lit, not lit). Solution: When both inputs are 0, t he output of t he O R gate will be 0 and the output LED will be not lit. 3.28 In Fig. 3-26, if switch A is up and switch B is down, the output LED will be lit). (lit, not Solution: When input A is 1 and input B is 0 (Fig. 3-26), the output of the OR gate will be 1 and the output L ED will be lit. 3.29 Pins 7 and 14 of the 7432 IC a re (input, output, power) connections. Solution: Pins 7 and 14 of the 7432 IC are power connections. 3.30 A level. ( + 5 V, GND) voltage at pin 4 of t he 7432 IC will cause pin 6 t o go to a HIGH logic Solution: T he output (pin 6) goes HIGH anytime as input (such as pin 4) is HIGH (near + 5 V). 3.31 T he letters TTL stand for . Solution: T he letters T TL stand for the popular transistor-transistor logic family of integrated circuits. 3.32 T he - (CMOS, TTL) logic family is characterized by its very low power consumption. Solution: T he CMOS logic family is noted for its very low power consumption. 3.33 Integrated circuits from the T TL and CMOS families a digital circuit. (can,cannot) be interchanged in Solution: T TL and CMOS ICs cannot be interchanged in a digital circuit. They may have the same logic function or even have the same pin diagram, but their input and output characteristics are quite different. Supplementary Problems 3.34 Draw the logic symbol for a 6-input AND gate. Label the inputs A , B , C , D , E , a nd F . Label the output Y . Ans. S ee Fig. 3-27. 3.35 Draw the logic symbol for a 7-input OR gate. Label the inputs A , B , C , D , E , F , a nd G. Label the output Y . Ans. S ee Fig. 3-28. BASIC LOGIC G ATES 44 AA :=py B ”+ ) E E F F Fig. 3-27 A 6-input AND gate 3.36 Fig. 3-28 A 7-input O R gate Describe the pulse train at output Y of the AND gate shown in Fig. 3-29, if input B is 0. Register to View Answer0 will disable the AND gate, and the output will be 0. h g f e d c b a Fig. 3-29 Pulse-train problem 3.37 Describe the pulse train at output Y of the AND gate shown in Fig. 3-29 if input B is 1. A m. T he output waveform will look exactly like the input waveform at input A (Fig. 3-29). 3.38 Describe the pulse train at output Y of the OR gate shown in Fig. 3-30 if input B is 0. Register to View Answerhe output waveform will look exactly like the input waveform at input A (Fig. 3-30). h g f e [CHAP. 3 d c b a Fig. 3-30 Pulse-train problem 3.39 Describe the pulse train at output Y of the OR g ate shown in Fig. 3-30 if input B is 1. A m. T he output will always be 1. 3.40 Write the Boolean expression for the logic circuit shown in Fig. 3-31. Register to View Answer. B + B . C = Y o r A B + B C = Y -A B + C Fig. 3-31 AND-OR logic-circuit problem CHAP. 31 34 .1 45 BASIC LOGIC GATES Draw the truth table for the logic circuit shown in Fig. 3-31. Ans. I Output I I nputs I I nputs O utput 1 C AI Y IC 0 0 34 .2 B 1 0 1 0 0 1 B AI Y 0 1 0 W rite the Boolean expression for - - _ circuit shown in Fig. 3-32. - the logic Ans. x . B . c + B - c = Y o r A B C + B C = Y Fig. 3-32 A ND-OR logic-circuit problem 34 .3 Draw the truth table for the logic circuit shown in Fig. 3-32. Ans. I I nputs O utput I I Output I nputs m I 1 C B A Y C B A Y 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 0 1 0 1 0 34 .4 Write the Boolean expression for the logic circuit shown in Fig. 3-33. Ans. 2.B. C B - +A . B - = Y o r + x B c +A B c = Y 34 .5 0 0 0 Draw the truth table for the logic circuit shown in Fig. 3-33. Ans. + x. c c I nputs x&' output Inputs output C B A Y C B A Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 0 46 [CHAP. 3 BASIC LOGIC GATES 1 I 1 1 I Fig. 3-33 AND-OR logic-circuit problem 3.46 Describe the pulse train at output Y of t he A ND gate shown in Fig. 3-34. Ans. pulse a = 0 pulse c = 0 pulse e = 0 pulse g = 0 pulse h = 1 pulse b = 1 pulse d = 0 pulse f = 1 h g f e d c b a Fig. 3-34 Pulse-train problem 3.47 Describe the pulse train at output Y of the O R gate shown i n Fig. 3-35. Ans. pulse c = 1 pulse e = 1 pulse a = 0 pulse g = 1 pulse b = 1 pulse d = 1 pulse f = 1 pulse h = 0 h g f e d c h a 1 Fig. 3-35 Pulse-train problem 3.48 Write the Boolean expression for the logic circuit shown in Fig. 3-36. o r A BCD+&?=Y Am. A - B - C . D + x ? = Y C HAP. 31 47 BASIC LOGIC G ATES Fig. 3-36 AND-OR logic-circuit problem 3.49 Draw the truth table for the logic circuit shown in Fig. 3-36. Note that the circuit has four input variables. The truth table will have 16 possible combinations. Am. I nputs D B A 1 1 1 1 1 1 1 1 3.50 C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 T he part number 74C08 is a q uad 2-input AND g ate from the (CMOS,TTL) family of ICs. A m. The 74C08 is a part number from the CMOS family of K s. T he C in the center of t he part number means the part is a CMOS-type IC. Chapter 4 Other Logic Gates 4-1 INTRODUCTION T he most complex digital systems, such as large computers, are constructed from basic logic gates. The AND, OR, and NOT gates are the most fundamental. Four other useful logic gates can be made from these fundamental devices. The other gates are called the NAND gate, the NOR gate, the exclusive-OR gate, and the exclusive-NOR gate. At the end of this chapter, you will know the logic symbol, truth table, and Boolean expression for each of the seven logic gates used in digital systems. 4-2 THE NAND GATE Consider the logic diagram at the top of Fig. 4-1. A n A ND gate is connected to an inverter. Inputs A and B a re ANDed to form the Boolean expression A . B . T he A . B is then inverted by the NOT gate. On the right side of the inverter, the overbar is added to the Boolean expression. The Boolean expression for the entire circuit is A . B = Y . I t is said that this is a n ot-AND o r NAND circuit. Fig. 4-1 T he NAND gate T he standard logic symbol for the NAND gate is shown in the bottom diagram in Fig. 4-1. Note that the NAND symbol is an AND symbol with a small bubble at the output. The bubble is sometimes called an invert bubble. T he invert bubble provides a simplified method of representing the NOT gate shown in the top diagram in Fig. 4-1. T he truth table describes the exact operation of a logic gate. The truth table for the NAND gate is illustrated in the unshaded columns of Fig. 4-2. T he AND-gate truth table is also given to show how each output is inverted to give the NAND output. Some students find i t useful to think of the NAND gate as an AND gate that puts out a 0 when it is enabled (when both inputs are 1). Fig. 4-2 T he AND- a nd NAND-gate truth tables 48 OTHER LOGIC GATES CHAP. 41 49 T he NAND function has traditionally been the universal gate in digital circuits. The NAND gate is widely used in most digital systems. Consider the NAND gate truth table in Fig. 4 -2. T he unique output from the NAND gate is a LOW when all inputs are HIGH. SOLVED PROBLEMS 4.1 Write the Hoolean expression for a 3-input NAND gate. Solution: . A - B - C = Y o r A BC= Y 4.2 Draw the logic symbol for a 3-input NAND gate. Solution: See Fig. 4-3. zj-->Y C Fig. 4-3 A 3 -input N AND g ate 4.3 Draw the truth table for a 3-input NAND gate. Solution: I nputs O utput C A Y 0 0 0 0 4.4 B 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 What would the output pulse train shown in Fig. 4-4 look like if input B were O? Fig. 4-4 Pulse-train problem Solution: T he output of t he NAND g ate shown in Fig. 4-4 would always be 1. 50 4.5 O THER LOGIC GATES [CHAP. 4 W hat would the output pulse train shown in Fig. 4-4 look like if input B were l ? Solution: T he output would be an inverted copy of the waveform at input A (Fig. 4-4).T he output pulses would be as follows: pulse c = 1 pulse a = 0 pulse e = 1 pulse g = 0 pulse b = 1 pulse d = 0 pulse f = 0 pulse h = 1 4.6 Draw a logic diagram of how you could connect a 2-input NAND gate to perform as an inverter. Label inverter input as A . Label inverter output as 2 . Solution: See Fig. 4-5. There are two possibilities. Fig. 4-5 Wiring the N AND g ate as an inverter 4-3 THE N OR GATE Consider the logic diagram in Fig. 4-6. An inverter has been connected to the output of an O R gate. The Boolean expression at the input to the inverter is A + B . T he inverter then complements the ORed terms, which a re shown in the Boolean expression with an overbar. Adding the overbar produces the Boolean expression A B = Y . This is a n ot-OR function. The not-OR function can be drawn as a single logic symbol called a N OR g ate. T he standard symbol for the NOR gate is illustrated in the bottom diagram of Fig. 4-6. Note that a small invert bubble has been added to the O R symbol to form the NOR symbol. + Fig. 4-6 T he NOR gate T he truth table in Fig. 4-7 details the operation of the NOR gate. Note that the output column of the NOR gate is the complement (has been inverted) of the shaded OR column. In other words, the Fig. 4-7 T he OR- and NOR-gate truth tables 51 OTHER LOGIC GATES CHAP. 41 N OR gate puts out a 0 where the OR gate would produce a 1. T he small invert bubble at the output of t he NOR symbol serves as a reminder of the 0 o utput idea. Consider the NOR gate truth table in Fig. 4-7. T he unique output from the NOR gate is a HIGH when all inputs are LOW. SOLVED PROBLEMS 4.7 Write the Boolean expression for a 3-input NOR gate. Solution: A+B+C=Y 4.8 Draw the logic symbol for a 3-input NOR gate. Solution: S ee Fig. 4-8. Fig. 4-8 A 3-input NOR g ate 4.9 What is the truth table for a 3-input N OR gate? Solution: 1 I nputs 0 0 0 0 4.10 0 0 1 1 O utput 0 1 0 1 I I O utput I nputs 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 W hat would the output pulse train shown in Fig. 4-9 look like if input B were l ? h g f e d c b a - l$ J Fig. 4-9 Pulse-train problem Solution: T he output of t he NOR g ate in Fig. 4-9 would always be 0. 52 4.11 OTHER LOGIC GATES [CHAP. 4 W hat would the output pulse train shown in Fig. 4-9 look like if input B were O? Solution: The output pulse would be the one shown in Fig. 4-9 but inverted. The pulses would be as follows: pulse c = 1 pulse a = 0 pulse e = 0 pulse g = 1 pulse b = 1 pulse d = 0 pulse f = 0 pulse h = 0 4-4 THE EXCLUSIVE-OR GATE T he exclusive-OR gate is referred to as the “any but not all” gate. The exclusive-OR term is often shortened to read as X OR. A t ruth table for the XOR function is shown in Fig. 4-10. Careful examination shows that this truth table is similar to the OR t ruth table except that, when both inputs are 1, t he XOR gate generates a 0. T he XOR gate is enabled only when an o dd number of 1 s appear at the inputs. Lines 2 and 3 of the truth table have odd numbers of Is, a nd therefore the output is enabled with a 1. Lines 1 and 4 of the truth table contain even numbers (0,2) of Is, and therefore the XOR gate is disabled and a 0 a ppears at the output. The XOR gate could be referred to as an odd-bits check circuit. +Inputs Output 00 0 0 1 1 1 1 1 0 1 0 Fig. 4-10 The exclusive-OR-gatetruth table A Boolean expression for the XOR gate can be developed from the truth table in Fig. 4-10. T he expression is A - B + 2 - = Y . With this Boolean expression, a logic circuit can be developed by using B AND gates, OR gates, and inverters. Such a logic circuit is drawn in Fig. 4-11a. This logic circuit will perform the XOR logic function. ( a ) Logic circuit that performs the XOR function ( b) Standard logic symbol for the XOR gate Fig. 4-11 T he standard logic symbol for the XOR gate is shown in Fig. 4-11b. Both logic symbol diagrams in Fig. 4-11 would produce the same truth table (XOR). T he Boolean expression at the right in Fig. 4-11b is a s implped X OR expression. T he @ symbol signifies the XOR function in Boolean algebra. It is said that inputs A and B in Fig. 4 - l l b a re exclusively ORed together. CHAP. 41 OTHER L OGIC GATES 53 SOLVED PROBLEMS 4.12 Write the Boolean expression (simplified form) for a 3-input XOR gate. Solution: A@B@C=Y 4.13 Draw the logic symbol for a 3-input XOR gate. Solution: S ee Fig. 4-12. Fig. 4-12 A 3-input XOR g ate 4.14 What is the truth table for a 3-input XOR gate? Remember that an odd number of 1s generates a 1 output. Solution: Inputs Output Inputs Output ~, 4.15 T he XOR gate might be considered an (even-, odd-) number-of-1s detector. Solution: The XOR gate generates a 1 when an odd number of 1 bits are present. For this reason it might be considered as an odd-number-of-1s detector. 4.16 What will the pulse train at the output of t he XOR gate shown in Fig. 4-13 look like? g f e d c b a Fig. 4-13 Pulse-train problem Solution: T he output pulses from the XOR gate shown in Fig. 4-13 will be as follows: pulse e = 0 pulse g = 1 pulse c = 1 pulse a = 0 pulse f = 1 pulse d = 0 pulse b = 1 54 O THER LOGIC GATES [CHAP. 4 4-5 THE EXCLUSIVE-NOR GATE T he output of an XOR gate is shown inverted in Fig. 4-14. T he output of the inverter on the right side is called the exclusive-NOR ( XNOR) function. The XOR gate produces the expression A @ B . When this is inverted, it forms the Boolean expression for the XNOR gate, A @ B = Y . T he standard logic symbol for the XNOR gate is shown in the bottom diagram of Fig. 4-14. N ote that the symbol is an XOR symbol with an invert bubble attached to the output. Fig. 4-14 T he XNOR gate T he right-hand column of t he truth table in Fig. 4-15 details the operation of t he XNOR gate. Note that all outputs of the XNOR gate are the complements of the XOR-gate outputs. While the XOR gate is an odd-number-of-1s detector, the XNOR gate detects even numbers of I s. T he XNOR gate will produce a 1 o utput when an even number of I s a ppear at the inputs. Fig. 4-15 T he XOR- and XNOR-gate truth tables SOLVED PROBLEMS 4.17 Write the Boolean expression for a 3-input XNOR gate. Solution: A@B@C=Y 4.18 Draw the logic symbol for a 3-input XNOR gate. Solution: See Fig. 4-16. Fig. 4-16 A 3-input XNOR gate 4.19 55 OTHER LOGIC GATES CHAP. 41 C onstruct a truth table for a 3-input XNOR gate. Remember that an even number of 1s g enerates a 1 o utput. Solution: Inputs output C A 0 0 0 0 4.20 B 0 0 1 1 0 1 Inputs output Y C B A Y 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 - 0 1 1 0 W hat will the pulse train at the output of t he XNOR gate shown in Fig. 4-17 look like? g f e d c b a Fig. 4-17 Pulse-train problem Solution: The output pulses from the X NOR gate shown in Fig. 4-1’7 will be as follows: pulse c = 0 pulse e = 0 pulse g = 0 pulse a = 0 pulse f = 1 pulse b = 1 pulse d = 1 4-6 CONVERTING GATES WHEN USING INVERTERS W hen using logic gates, the need will arise to convert to another logic function. A n easy method of converting is t o use inverters placed at the outputs or i nputs of gates. It has been shown that an inverter connected at the output of an A ND gate produces the NAND function. Also, an inverter placed at the output of an O R gate produces the NOR function. The chart in Fig. 4-18 illustrates these and other conversions. Placing inverters at all the inputs of a logic gate produces the results illustrated in Fig. 4-19. I n the first line the inputs to an AND gate are being inverted (the plus symbol indicates addition in this figure). This produces the NOR function at the output of t he AND gate. The second line of Fig. 4-19 shows the inputs of a n O R gate being inverted. This produces the NAND function. The first two examples suggest new symbols for the NOR and NAND functions. Figure 4-20 illustrates two logic symbols sometimes used for the NOR and NAND functions. Figure 4-20a is an alternative logic symbol f or a NOR gate. Figure 4-206 is an alternative logic symbol f or a NAND gate. These symbols are encountered in some manufacturers’ literature. The effect of inverting both the inputs and output of a logic gate is shown in Fig. 4-21. Again the plus symbol stands for a ddition. This technique is probably not used often because of t he large number of gates needed. Note that this is the method of converting from the AND to the O R t o the AND function. This is also the method of converting from the NAND to the NOR to the NAND function. 56 O THER LOGIC GATES ~ Original gate ~ Add inverter to o utput I7c>- [CHAP. 4 New logic function + = = = Original gate Inputs -cQ- N OR New logic function A ND + to N AND + _i)D_ Add inverters = __oo__ + -o D- +>= -o D- + =+ + ) symbol means adding on this chart = "_a--)-m-= Y ( a ) N OR g ate symbol Y B ( b) N AND gate symbol Fig. 4-20 Alternative logic symbols -P-GQ- Original gate + A ND Fig. 4-19 Effect of inverting inputs of gates B to inputs OR ( + ) symbol means adding on this chart Fig. 4-18 Effect of inverting outputs of gates Add inverters NOR A dd inverter to output > + New logic function -> . I (- = N AND ( + ) symbol means adding on this chart Fig. 4-21 Effect of inverting both inputs and outputs of gates OTHER LOGIC GATES CHAP. 41 57 SOLVED PROBLEMS 4.21 Given an OR gate and inverters, draw a logic diagram that will perform the 2-input NAND function. Solution: See Fig. 4-22. = A B = Fig. 4-22 2-input NAND function 4.22 Given an O R gate and inverters, draw a logic diagram that will perform the 3-input AND function. Solution: See Fig. 4-23. 'ts * c Fig. 4-23 3-input AND function 4.23 Given a NAND gate and inverters, draw a logic diagram that will perform the 2-input OR function. Solution: See Fig. 4-24. Fig. 4-24 2-input OR function 4.24 Given a N AND gate and inverters, draw a logic diagram that will perform the 3-input AND function. Solution: See Fig. 4-25. 58 [CHAP. 4 OTHER LOGIC GATES Fig. 4-25 3 -input AND f unction 4.25 Given an AND g ate and inverters, draw a logic diagram that will perform the 2-input NOR function. Solution: See Fig. 4-26. A A+B=Y. B Fig. 4-26 2-input N OR function 4-7 NAND AS A UNIVERSAL GATE Consider the logic circuit shown in Fig. 4-27a. This is referred to as an A ND-ORpattern of gates. T he AND gates feed into the final OR gate. The Boolean expression for this circuit is shown at the B right as 2. + A - B = Y . In constructing the circuit, you need three different types of gates (AND gates, an O R gate, and an inverter). From a manufacturer’s catalog, you would find that three different ICs would be needed to implement the circuit shown in Fig. 4-27a. A A T B + A .B= Y (a) An AND-OR logic circuit ( h ) A n equivalent NAND logic circuit Fig. 4-27 CHAP. 41 59 OTHER LOGIC GATES It was mentioned earlier that the NAND gate is considered a universal gate. Figure 4-276 shows NAND gates being used to implement the logic A . B + A *.B Y . This logic is the same as that = performed by the AND-OR circuit shown in Fig. 4-27a. Remember that the OR-looking gate (gate 4) with the invert bubbles at the inputs is a NAND gate. The circuit shown in Fig. 4-27b is simpler because all the gates are NAND gates. It is found that only one IC (a quadruple 2-input NAND gate) is needed to implement the NAND logic of Fig. 4-27b. Fewer ICs are needed to implement the NAND logic circuit than the AND-OR pattern of logic gates. It is customary when converting from AND-OR logic to NAND logic to draw the AND-OR pattern first. This can be done from the Boolean expression. The AND-OR logic diagram would be similar to that in Fig. 4-27a. A N AND gate is then substituted for each inverter, AND gate, and O R gate. The NAND logic pattern will t hen be similar to the circuit shown in Fig. 4-276. A clue to why t he AND-OR logic can be replaced by N AND logic is shown in Fig. 4-276. N ote the two invert bubbles between the output of gate 2 and the input of gate 4. Two invert bubbles cancel one another. T hat leaves the AND-OR symbols just as in Fig. 4-27a. T he double inversion also takes place in Fig. 4-27b between gates 3 and 4. This leaves AND gate 3 feeding O R gate 4. N AND gate 1 acts as an inverter when its inputs are tied together as shown in Fig. 4-276. SOLVED PROBLEMS 4.26 Redraw the AND-OR circuit shown in Fig. 4 -lla by using five 2-input NAND gates. The NAND logic circuit should perform the logic A B + A. = Y . B Solution: See Fig. 4-28. +A*B=Y Fig. 4-28 Solution using NAND logic 4.27 -- Draw a logic diagram for the Boolean expression A - B + A - B and O R gates. = Y . Use inverters, AND gates, Solution: See Fig. 4-29. 4.28 Redraw the logic diagram- f-Prob. 4.27 by using only five 2-input NAND gates. The circuit o should perform the logic A - B + A - B = Y . Solution: See Fig. 4-30. 60 [CHAP. 4 O THER LOGIC GATES Fig. 4-29 A ND-OR logic circuit A B +A.B= Y Fig. 4-30 Equivalent NAND logic circuit 4-8 USING PRACTICAL LOGIC GATES T he most useful logic gates are packaged as integrated circuits. Figure 4 -31 illustrates two TTL logic gates that can be purchased in IC form. A pin diagram of the 7400 IC is shown in Fig. 4 -31a. T he 7 400 is described b y t he manufacturer as a quadrupZe 2-input N AND gate IC. Note that the 7 400 I C does have the customary power connections ( Vcc and GND). All other pins are the inputs and outputs from the four 2-input NAND gates. 1A v, 1B 4B I S 1 c 1Y 4A 2A 1Y 2A 4Y 2B 3B 2Y 3A 2Y 2c GND 3Y G ND i (U) 2B U @:; d all 11 6 ( b ) Pin diagram for a 7410 IC Pin diagram for a 7400 IC Fig. 4-31 3 c CHAP. 4 1 61 OTHER L OGIC GATES T hree 3-input NAND gates are housed in the 7410 W L IC. The pin diagram for the 7410 IC is shown in Fig. 4-31b. This device is described by the manufacturer as a triple 3-input NAND gate IC. NAND gates with more than three inputs also are available. The 7400 and 7410 ICs were from the common TTL logic family. Manufacturers also produce a variety of NAND, NOR, and XOR gates in CMOS-type ICs. Typical NAND gates might be the CMOS 74COO quad 2-input NAND gate, 74C30 8-input NAND gate, and 4012 dual 4-input NAND gate DIP ICs. Some CMOS NOR gates in DIP IC form are the 74C02 quad 2-input NOR gate and the 4002 dual 4-input NOR gate. Several exclusive-OR gates are produced in CMOS; examples are the 74C86 quad 2-input XOR gate and the 4030 quad 2-input X OR gate. Note that CMOS ICs come in both a 74COO series and a 4000 series. It must be remembered that without special interfacing, T TL a nd CMOS ICs a re not compatible. SOLVED PROBLEMS 4.29 Construct the truth table for the circuit shown in Fig. 4-32. I I I 1 150 R Fig. 4-32 Wiring diagram of a logic-circuit problem Solution: I nputs Output -+. 0 0 1 1 4.30 0 1 0 1 0 1 0 1 What is t he voltage of t he power supply at the left in Fig. 4-32? The 7400 IC is a TTL device. Solution: A TTL device uses a 5-V d c power supply. 4.31 If both switches ( A and B ) shown in Fig. 4-32 are in the up position (at logical l), t he output LED will be (lit, not lit). Solution: W hen both inputs are 1, t he output of t he circuit will be 1 and the output LED will be lit. 62 43 .2 O THER LOGIC GATES [CHAP. 4 . The 7400 IC is described by the manufacturer as a quadruple Solution: T he 7400 IC is a quadruple 2-input NAND gate. 43 .3 The circuit shown in Fig. 4-32 could be described as a(n) circuit. (AND-OR, NAND) logic Solution: T he circuit shown in Fig. 4-32 uses NAND logic. 434 (CMOS, TTL) technology. The 4012 is a dual 4-input NAND gate IC using the Solution: T he 4000 series part numbers designate CMOS digital ICs. Supplementary Problems 4.35 Write the Boolean expression for a 4-input NAND gate. Register to View Answer. B - C . D = Y o r A B C D = Y 4.36 Draw t he logic symbol for a 4-input NAND gate. Ans. See Fig. 4-33. Fig. 4-33 A 4-input NAND gate 4.37 Construct the truth table for a 4-input NAND gate. Ans. o utput Inputs D C B A ~ 0 0 0 0 0 0 0 0 4.38 Inputs Y D ~ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 C B ~~~ 1 1 1 1 1 1 1 1 o utput 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Y A ~~~ ~~ 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 What would the output pulse train shown in Fig. 4-34 look like if input C were O? A m. T he output of t he NAND gate would be 1 a t all times. OTHER LOGIC GATES CHAP. 41 g f e d c b 63 a ? Fig. 4-34 Pulse-train problem 4.39 W hat would the output pulse train shown in Fig. 4-34 look like if input C w ere l ? Ans. pulse n = 0 pulse c = 1 pulse e = 1 pulse g = 1 pulse h = 1 pulse d = 0 pulse f = 0 4.40 W rite the Boolean expression for a 4-input NOR gate. Register to View Answer 4.41 D raw the logic symbol for a 4-input NOR gate. S ee Fig. 4-35. Ans. + B + C +D= Y Fig. 4-35 A 4-input NOR gate 4.42 C onstruct the truth table for a 4-input NOR g ate. Ans. I nputs output I nputs output D 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 C R A 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Y 0 1 0 1 0 1 0 1 4.43 W hat would the output pulse train shown in Fig. 4-36 look like i:f i nput C w ere l ? Register to View Answerhe output of t he NOR g ate would always be 0. 4.44 W hat would the output pulse train shown in Fig. 4-36 look like if input C w ere O? Ans. pulse a = 0 pulse c = 1 pulse e = 0 pulse g = 1 pulse b = 1 pulse d = 0 pulse f = 0 64 O THER LOGIC G ATES 0 Je 1 0 0 110 g oJ1 0 1 0 [CHAP. 4 1 or- b 5 Fig. 4-36 Pulse-train problem 4.45 Write the Boolean expression for a 4-input XOR gate. Register to View Answer@ B @ C @ D = Y 4.46 Draw the logic symbol for a 4-input XOR gate. A m. See Fig. 4-37. Fig. 4-37 A 4-input XOR gate 4.47 Construct the truth table for a 4-input XOR gate. Ans. output I nputs Inputs output D B A Y D C B A Y 0 0 0 0 0 0 0 0 4.48 C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 What would the pulse train at the output of the XOR gate shown in Fig. 4-38 look like? Ans. pulse a = 0 pulse c = 1 pulse e = 0 pulse g = 0 pulse b = 1 pulse d = 1 pulse f = 0 pulse h = 1 ? h g f e d c b a Fig. 4-38 Pulse-train problem C HAP. 41 65 OTHER LOGIC GATES 4.49 Write the Boolean expression for a 4-input XNOR gate. -~ A m. A @ B @ C @ D = Y 4.50 Draw the logic symbol for a 4-input XNOR gate. Ans. See Fig. 4-39. Fig. 4-39 A 4-input XNOK gate 4.5 1 Construct a truth table for a 4-input XNOR gate. A m. I nputs output I nputs D 0 0 0 0 0 0 0 0 4.52 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 C B A 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W hat would t he pulse train at the output of the XNOR gate shown in Fig. 4-40 look like? Ans. pulse a = 1 pulse c = 0 pulse e = 0 pulse g = 1 pulse b = 0 pulse d = 1 pulse f = 1 pulse h = 0 \ h g f e d c b a Fig. 4-40 Pulse-train problem 4.53 Given an O R gate and inverters, draw a logic diagram that will perform the 3-input NAND function. Ans. S ee Fig. 4-41. Fig. 4-41 3-input NAND function 66 4.54 O THER LOGIC GATES [CHAP. 4 Given a NOR gate and inverters, draw a logic diagram that will perform the 3-input AND function. Ans. See Fig. 4-42. Fig. 4-42 3-input AND function 4.55 Given a NOR gate and inverters, draw a logic diagram that will perform the 5-input OR function. Ans. See Fig. 4-43. A B c '4 D E + B + C ' + fl fE=Y Fig. 4-43 5-input O R function 4.56 Draw a logic diagram for the Boolean expression Ans. See Fig. 4-44. gates, and an OR gate. 2. - C + A B - C + A - B - c = Y . Use inverters, AND B * A B C Y 1- c Fig. 4-44 An AND-OR logic circuit 4.57 Redraw the logic diagram for Prob. 4.56 by using three 2-input NAND gates and four 3-input NAND gates. Ans. See Fig. 4-45. 4.58 Write the Boolean expression for the circuit shown in Fig. 4-46. C =Y Register to View Answer- B + x* * ( ‘€{AP. 4 68 O THER LOGIC GATES [CHAP. 4 4.60 If switches A , B , and C shown in Fig. 4-46 are in the u p position (logical 11, the output LED will be (lit, not lit). Ans. When all inputs are 1, the output of the circuit will be 1 according to the truth table and the output LED will be lit. 4.61 The unique o utput for the Ans. N AND logic gate is a LOW when all inputs are HIGH. 4.62 T he unique output for the Ans. NOR logic gate is a HIGH when all inputs are LOW. 4.63 T he logic gate generates a HIGH output when an odd number of inputs are HIGH. Ans. exclusive-OR or XOR. Chapter 5 Simplifying Logic Circuits: Mapping 5-1 INTRODUCTION Consider the Boolean expression A B + A . B = Y , a logic diagram for which is in Fig. 5 - l a . Note that six gates must be used to implement this logic circuit, which performs the logic detailed in the truth table (Fig. 5 -lc). From examination of the truth table, it is determined that a single 2-input OR gate will perform the function. It is found that the OR gate shown in Fig. 5-16 will be the simplest method of performing this logic. The logic circuits in Fig. 5 - l a and b perform exactly the same logic function. Obviously a designer would choose the simplest, least expensive circuit, shown in Fig. 5 -lb. I t has been shown that the unsimplified Boolean expression ( A + A. + A B = Y ) could be simplified to A + R = Y . T he simplification was done by simple examinaB tion of the truth table and recognizing the O R p attern. Many Boolean expressions can be greatly simplified. Several systematic methods of simplification will be examined in this chapter. + x. * A 1 A - 1 A AB B + AB + AB Inputs = Y Output P ”ay (a) Unsimplified logic circuit B A Y 0 It 0 0 01 10 111 1 1 1 ( c ) Truth table for OR function B ( b ) Simplified ‘logic circuit Fig. 5-1 I n this chapter simple logic gates will be used to implement combinational logic. Other techniques also are commonly used for simplifying more complex logic problems. They include the use of d ata selectors (multiplexers), decoders, P U S (programmable logic arrays), ROMs (read-only memories) and PROMS (programmable read-only memories). 5-2 SUM-OF-PRODUCTS BOOLEAN EXPRESSIONS I t is customary when starting a logic-design problem to first construct a truth table. The table details the exact operation of t he digital circuit. Consider the truth table in Fig. 5 -2a. I t contains the three variables C, B , and A . Note that only two combinations of variables will generate a 1 o utput. These combinations are shown in the shaded second and eighth lines of the truth table. From line 2 , we say that “a not C AND a not B A ND an A input will generate a 1 output.” This is shown near the -right side of line 2 as the Boolean expression C * B . A . T he other combination of variables that will generate a 1 is shown in line 8 of the truth table. Line 8 reads as “a C A ND a B A ND an A input will generate a 1 output.” The Boolean expression for line 8 is shown at the right as C * B . A . T hese two 69 70 [CHAP. 5 SIMPLIFYING LOGIC CIRCUITS: MAPPING Fig. 5-2 possible combinations are then ORed together to form the complete Boolean expression for the truth -table. The -complete Boolean expression is shown in Fig. 5 -2b as C B . A + C . B . A = Y . T he C . B . A + C . B - A = Y in Fig. 5 -2b is sometimes called a sum-of-products form of a Boolean expression. Engineers also call this form of expression the minterm form. Note that this expression can -be translated into a familiar AND-OR pattern of logic gates. The logic diagram in Fig. 5 -2c performs the logic described by the minterm Boolean expression C - B . A + C B . A = Y and will generate the truth table in Fig. 5 -2a. I t is typical procedure in logic-design work to first construct a truth table. Second, a minterm Boolean expression is then determined from the truth table. Finally, t he AND-OR logic circuit is drawn from the minterm Boolean expression. This procedure is outlined in the sample problem in Fig. 5-2. + * SOLVED PROBLEMS 5.1 Write a rninterm Boolean expression for the truth table in Fig. 5 -3. I Inputs O utput I I Inputs O utput C B A Y C B A Y 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 0 Fig. 5-3 Solution: C .B - A + c . B 5.2 -A Y = or CBA + CBZ Y = T he Boolean expression developed in Prob. 5.1 was a (maxterm, minterm) expression. This type of expression is also called the (product-of-sums, sum-of-products) form. Solution: This type of Boolean expression sum-of-products form. ( C. B . A + C -B .A= ) Y is called the minterm form or the CHAP. 51 53 . SIMPLIFYING LOGIC CIRCUITS: MAPPING 71 Diagram a logic circuit that will perform the logic in the truth table in Fig. 5-3. Solution: See Fig. 5-4. --C*B.A+C*B.A= Y Fig. 5-4 Logic-diagram solution 5.4 Write a sum-of-products Boolean expression for the truth table in Fig. 5-5. Solution: C .B-X+ B . A c . & A F + =Y 1 I nputs O utput I 1 I nputs 0 1 0 1 1 0 0 '~ 1 1 1 1 O utput 1 Fig. 5-5 5.5 Diagram a logic circuit that will perform the logic in the truth table in Fig. 5-5. Solution: See Fig. 5 -6. c Fig. 5-6 Logic-diagram solution A= Y 72 SIMPLIFYING LOGIC CIRCUITS: MAPPING [CHAP. 5 5-3 PRODUCT-OF-SUMS BOOLEAN EXPRESSIONS Consider the OR t ruth table in Fig. 5 -7b. T he Boolean expression for this truth table can be written in two forms, as was observed in the introductory section. The minterm Boolean expression is developed from the output 1s in the truth table. Each 1 in the output column becomes a term to be ORed in the minterm expression. The minterm expression for this truth table is given in Fig. 5-7c a s B-A+B.A+B.A=Y Fig. 5-7 T he truth table in Fig. 5-7 can also be described by using a rnaxterrn form of Boolean expression. This type of expression is developed from the OS in the output column of the truth table. For each 0 in the output column, an ORed term is developed. Note that the input variables are inverted and then O Red. T he maxterm Boolean expression for this truth table is given in Fig. 5 -7a. T he maxterm expression for the O R truth table is shown as B + A = Y . This means the same thing as the familiar OR expression A + B = Y . For the truth table in Fig. 5 -7, t he maxterm Boolean expression turns out to be the simplest. Both the minterm and maxterm expressions accurately describe the logic of the truth table in Fig. 5-7. Consider the truth table in Fig. 5 -8a. T he minterm expression for this truth table would be rather long. The m axtenn Boolean expression is developed from the variables in lines 5 and 8. Each of these Fig. 5-8 Developing a maxterm expression C HAP. 51 73 SIMPLIFYING LOGIC CIRCUITS: h4APPING lines has a 0 in the output column. The variables are inverted and ORed with parentheses around them. The terms are then ANDed. The complete maxterm Boolean expression is given in Fig. 5-8b. The maxterm expression is also called the product-of-sums form of a Boolean expression. The product-of-sums term comes from the arrangement of the sum ( + ) and product ( .) symbols. A maxterm Boolean expression would be implemented by using an OR-AND pattern of logic gates illustrated in Fig. 5-9. Note that the outputs of the two OR gates are feeding into an AND gate. The maxterm expression + +2) + B + A ) = Y is implemented by using the OR-AND pattern of gates in Fig. 5-9. (c (c . (C + B + A ) * (C+B+A)= Y Fig. 5-9 Maxterm expression implemented with OR-AND circuit SOLVED PROBLEMS 5.6 Write a muxterm Boolean expression for the truth table in Fig. 5-10. Inputs C B Output A l & Inputs Y Output Fig. 5-10 Solution: (C+ B -t- 2 - (C + B + A ) = Y ) 5.7 T he Boolean expression developed in Prob. 5.6 is a (maxterm, minterm) expression. (product-of-sums, sum-of-products) form. This type of expression is also called the Solution: The type of Boolean expression developed in Prob. 5-6 is called the maxterm form or the product-of-sums form. 74 5.8 [CHAP. 5 SIMPLIFYING LOGIC CIRCUITS: MAPPING Diagram a logic circuit that will perform the logic in the truth table in Fig. 5-10. Solution: See Fig. 5-11. (C+B++)=Y Fig. 5-11 Maxterm expression implemented with OR-AND circuit 5.9 T he logic diagram of Prob. 5.8 is called the gates. (AND-OR, OR-AND) p attern of logic I Solution: T he pattern of gates shown i n Fig. 5-11 is called the OR-AND pattern. 5.10 Write the product-of-sums Boolean expression for the truth table in Fig. 5-12. Inputs o utput CBA Y 0 0 0 0 0 0 0 1 1 1 0 1 :I 0 1 1 1 0 1 1 1 0 1 Fig. 5-12 Solution: (C +B + A ) (C + B * 5.11 + X)- ( C + B + 2)= Y Diagram a logic circuit that will perform the logic in the truth table in Fig. 5-12. Solution: See Fig. 5-13. 75 Bcx)lcan algebra, the algctva o logic circuits, has m a n y l aws o r thcorcmh. I l c , \f~or~citi'slrcwrcrn.r f t a rc v c v u wful. They a llow for c a\> transicr back and forth froni ttic niintcrm to the mastcrni form, of B t x h n cxprcssion. 'I'hcy a lso allow tor cliniination oi ovcrhars that ;ire oc'cr sc\cr;il wiri;iblcs. Dc Morgan's thcorcms c;in be stated ;is t ollows: _ __ first t hcorcni A + -- B = C! U a sccond theorem .$I . fl - f t + fi T he first theorem changes thc basic O K situation to an Ah'D situation. A practical cxamplc of the first theorem is illustrated in F'ig. 5 -14a. T hc N O R gatc on thc lcft is cqual i n function to the A ND gatc ( with invcrtcd inputs) on thc right. N ote that thc convcrsion is frorn ttic h i c OK situatic)ri t o ttic basic A ND situation a s shown by thc gatcs i n Fig. 5 - 1 4 ~ ) This conversion is u x f u l i ii gcttinp rid o f . the long overbar on the N OR a nd can bc uscd i n converting f rom a mintcrni to ; niristcrni expression. i Thc A ND-boking symbol a t the right i n I :ig 5-13u would produce i i NOR t ruth t;ihlc. /I B 1' (U) NOR funcrioom -n - Y 'I'hc sccond theorem changes thc basic AND situation t o ;in O K situation. A practical cxaniple of the second theorem is illustrated in Fig. 5-14h.The K AND gate on the left is cqual i n tunction to the OR gate ( with invcrtcd inputs) o n the r ight. A p i n the long ovcrhar is climinatcd, and conversions can be done froni mnstcrni t o niintcrm forms of I3oolcan cxprcssions. 'I'hc OK-looking symbol a t thc right i n € :ig 5-14h w ould produce ;I N AND t r u t h table. The s ynihls i it thc right i n 1;ig. 5 -14 ;ire thc altcrnatc symbols used for the NOR and N AND logic functions. Figure 5 - 14 illustrates b ut o ne usc of I lc Xlorgan's thcorcnis. Four stcps a rc needed to transform 3 basic r 1ND situation t o an O K situation ( o r an O R t o an A ND situation). T he four stcps. based on I>c Morgan's thcorcms. arc ;IS follows: 1 . Change (111 O Ks to A KDs and all A ND5 t o OKs. 2 . Coniplcmcnt cach iiidividwil t,ari;iblc (add ovcrbar to each). 3. Complement thc cntirc function ( add ocerbar to cntirc function). 4. Eliminate all groups o f double ovcrbars. 76 [CHAP. 5 SIMPLIFYING LOGIC CIRCUITS: MAPPING Consider the maxterm expression in Fig. 5 -15a. By using the above procedure, transform this maxterm expression into a minterm expression. The first step (Fig. 5 1 % ) is to change all ORs t o ANDs and ANDs t o ORs. T he second step (Fig. 5 1 % ) is to add an overbar to each individual variable. The third step (Fig. 5 -15d) is to add an overbar to the entire function. The f ourth step is to eliminate all double overbars and rewrite the final minterm expression. The five groups of double overbars which will be eliminated are shown in the shaded areas in Fig. 5 -15e. T he final minterm expression appears in Fig. 5 -15f. T he maxterm expression in Fig. 5-15a a nd the minterm expression in Fig. 5 -15f will produce the same truth table. ( A+ B + C )- (A +B +C)= Y A.jj.C+'j.B.C ( a ) M axterm expression -- (d) Third step L A-B.C+A-B*C A (b) First step m ( e ) F ourth step J.B.C+A.B.C A-B-c+A-B.c=Y (c) Second step ( f ) Minterm expression Fig. 5-15 From maxterm to minterm expressions using De Morgan's theorems SOLVED PROBLEMS 5.12 Convert the Boolean expression ( A each step as in Fig. 5-15. Solution: Maxterm expression ( A+ First step + + c )- ( x+ + c )= Y t o its minterm B B + c ) ( A+ + c )= Y A * Second step . B . C +A.B 2.E. + Z .g . F Third step Fourth step Minterm expression 5.13 form. Show 2. C + A B eliminate double overbars * C =Y -- - Convert the Boolean expression C * B . A the procedure. Solution: Minterm expression +C * B .x= to its maxterm form. Show each step in Y c - B .A+ - B -A= C Y First step ( C + B +A) ( C+ B +A) Second step (c=+B=+K).(C+B+K) Third step Fourth step Maxterm expression eliminate double overbars ( C+ B + A ) - + B + A ) = Y * ( c=+E+A=) - ( C + B + A = ) (c C HAP. 51 77 SIMPLIFYING LOGIC CIRCUITS: MAPPING -Convert the Boolean expression A - B = Y to a sum-of-products form. 5.14 Solution: A+B=Y Convert the Boolean expression A+ E = Y to a product-of-sums form. 5.15 Solution: A*B=Y 5-5 USING NAND LOGIC All digital systems can be constructed from the fundamental AND, OR, and NOT gates. Because of their low cost and availability, NAND gates are widely used to replace AND, OR, and NOT gates. There are several steps in converting from AND-OR logic to NAND logic: 1. 2. 3. 4. Draw an AND-OR logic circuit. Place a bubble at the output of each AND gate. Place a bubble at each input to the O R gate. Check the logic levels on lines coming from the inputs and going to the outputs. Consider the minterm Boolean expression in Fig. 5-16a. T o implement this expression by using NAND logic, the steps outlined above will be followed. The first step (Fig. 5-16b) is to diagram an AND-OR logic circuit. The second step is to place a bubble (small circle) at the output of each AND gate. This changes the AND gates to NAND gates. Figure 5-16c shows bubbles added to gates 1 and 2. The third step is to place a bubble (small circle) at each input of the OR gate. This will convert the OR gate to a NAND gate. Figure 5-16c shows three bubbles added to the inputs of gate 3. T he fourth step involves examination of the input and output lines from the AND and OR symbols to see if any of the logic levels have been changed by the addition of bubbles. On examination of the circuit shown in Fig. 5-16c, it is found that the added bubble at point X has changed the input logic level on OR symbol 3. T he AND-OR diagram in Fig. 5-16b shows that a HIGH logic level is connected from input E t o the O R gate. The HIGH, or 1, activates the OR gate. A HIGH must also arrive at the input of symbol 3 in Fig. 5-16c. This is accomplished by adding the shaded inverter in input line E . In actual practice, a NAND gate is used as the inverter. The double inversion will deliver the HIGH logic level to the OR symbol to activate the OR. The invert bubbles between gates 1 and 3 cancel one another. Likewise, the invert bubbles between gates 2 and 3 cancel. The NAND logic circuit shown in Fig. 5-16c will produce the same truth table as that for the AND-OR circuit. A-1 B-- C I D- Y Y E E ...... ; : ...;. 1' N AND wired as inverter ( c ) E quivalent NAND logic circuit ( b ) Equivalnet AND-OR logic circuit Fig. 5-16 78 [CHAP. 5 SIMPLIFYING LOGIC CIRCUITS: MAPPING Using NAND logic does not always simplify a circuit. The example shown in Fig. 5-16 shows that the AND-OR circuit would probably be preferred over the NAND circuit because of the fewer gates used. Most manufacturers of ICs d o produce a good variety of all types of gates. The logic designer can usually select the logic that produces the simplest circuitry. SOLVED PROBLEMS 5.16 Diagram an AND-OR logic circuit for the Boolean expression A - B + c+D - E = Y. Solution: See Fig. 5-17. .+%= A.B+C+D.E=Y Fig. 5-17 AND-OR logic-circuit solution 5.17 Diagram a NAND logic circuit from the AND-OR circuit in Prob. 5.16. T he NAND circuit should perform the logic in the expression A B + + D - E = Y . * c Solution: See Fig. 5-18. Fig. 5-18 NAND logic-circuit solution 5.18 Diagram an AND-OR logic circuit for the Boolean expression A Solution: See Fig. 5-19. + ( B - C >+ = Y. CHAP. 51 SIMPLIFYING LOGIC CIRCUITS: MAPPING 79 Fig. 5-19 A ND-OR logic-circuit solution 5.19 Diagram a NAND logic circuit from the AND-OR circuit in Prob. 5.18, T he NAND circuit should perform the logic in the expression A + ( B - C ) + = Y . Solution: See Fig. 5-20. D Fig. 5-20 N AND logic-circuit solution 5-6 USING NOR LOGIC T he NAND gate was the ‘‘universal gate” used for substituting in an AND-OR logic pattern. When a maxterm Boolean expression forms an OR-AND gate pattern, the NAND gate does not work well. The NOR gate becomes the ‘‘universal gate” when substituting in OR-AND logic patterns. The NOR gate is not as widely used as the NAND gate. Consider the maxterm Boolean expression written in Fig. 5-21a. The expression is drawn as an OR-AND logic diagram in Fig. 5-21h . T he OR-AND p attern is redrawn with NOR gates in Fig. 5-21c. Each OR gate and AND gate is replaced by a NOR gate. Gates 1 and 2 in Fig. 5-21c a re shown as the (A + B) * (C + 0)= Az>9 Y (4 B A B +D)= Y czP c2Y D D (c) Equivalent NOR logic circuit ( b ) Equivalent OR-AND logic circuit Fig. 5-21 80 SIMPLIFYING LOGIC CIRCUITS: MAPPING [CHAP. 5 standard NOR symbols. Gate 3 is the alternate NOR symbol. The substitution works because the two invert bubbles between gates 1 and 3 cancel each other. Likewise, the two invert bubbles between gates 2 and 3 cancel. This leaves the two OR symbols (1 and 2 ) driving an AND symbol (3). This is the pattern used in the original OR-AND logic diagram in Fig. 5 -216. T he procedure for converting from a maxterm Boolean expression to a NOR logic circuit is similar to that used in NAND logic. The steps for converting the NOR logic are as follows: 1. 2. 3. 4. Draw an OR-AND logic circuit. Place a bubble at each input to the AND gate. Place a bubble at the output of each O R gate. Check the logic levels on lines coming from the inputs and going to the output. Consider the maxterm Boolean expression in Fig. 5 -22a. T o implement this expression by using NOR logic, the four steps outlined above will be followed. The f irst step (Fig. 5 -226) is to draw an OR-AND logic circuit. The second step is to place a bubble (small circle) at each input to the AND gate. This changes it to a NOR gate. The “AND looking” symbol with the three bubbles at the inputs is then a NOR gate (Fig. 5 -22c). T he third step is to place a bubble (small circle) at the output of each OR gate. The bubbles are added to gates 1 and 2 in Fig. 5 -22c. T he f ourth step is to examine the input and output lines for changes in logic levels due to added bubbles. The bubble added at point Z in Fig. 5 -22c is a change from the original OR-AND pattern. The inverting effect of bubble 2 is canceled by adding the shaded inverter 4. T he double inversion (inverter 4 and invert bubble Z ) cancels in input line E . In actual practice, inverter 4 would probably be a NOR gate. By shorting all inputs together, a NOR gate becomes an inverter. The NOR and the OR-AND circuits pictured in Fig. 5-22 perform the same logic function. The NOR gate was used as a “universal gate” in the previous example. Using NOR logic may or may not simplify the circuit. In this case the OR-AND circuit might be preferred. Fig. 5-22 SOLVED PROBLEMS 5.20 Diagram an OR-AND logic circuit for the Boolean expression ( A Solution: See Fig. 5-23. + B ) c -( D + E ) = Y . CHAP. 51 SIMPLIFYING LOGIC CIRCUITS: MAPPING 81 Fig. 5-23 OR-AND logic-circuit solution 5.21 Diagram a NOR logic circuit from the OR-AND circuit in Prob. 5.20. T he NOR circuit should perform the logic in the Boolean expression ( A + B ) (D E ) = Y. * c' + Solution: See Fig. 5-24. A B Fig. 5-24 NOR logic-circuit problem 5.22 Diagram an OR-AND logic circuit for the Boolean expression 2 .( B + C ) - D = Y . Solution: See Fig. 5-25. B C A * ( B + C ) * D =Y D Fig. 5-25 OR-AND logic-circuit solution 5.23 Diagram a NOR logic circuit from the OR-AND circuit in Prob. 5.22. T he NOR circuit should perform the logic in the Boolean expression ( B + C )- D = Y. x- Solution: See Fig. 5-26. 82 SIMPLIFYING LOGIC CIRCUITS: MAPPING [CHAP. 5 Fig. 5-26 N OR logiccircuit solution 5-7 K ARNAUCHMAPS Boolean algebra is thc basis for any simplification of logic circuits. One of the easiest ways t o simplify logic circuits is t o use the Khmuugh m p method. This graphic method is bascd on Boolcan theorems. It is only one of several methods used by logic designers to simplify logic circuits. Karnaugh maps are sometimes referred to as K maps. The first step in the Karnaugh mapping proccdurc is t o develop a minterm Boolean expression from a truth table. Consider the familiar truth table in Fig. S-27a. Each 1 in the Y column of the truth table produces two variables ANDed together. These ANDed groups are thcn ORed to form a sum-of-products (minterm) type of Boolean exprcssion (Fig. 5-276). This expression will be referred to as the unsimpiijied Boolean expression. The second srep in the mapping procedurc is to plot 1s in the Karnaugh map in Fig. 5-27c. Each ANDed set of variables from the minterm expression is placed in Fig. 5-27 Using a map CHAP. 51 SIMPLIFYING LOGIC CIRCUITS: MAPPING 83 the appropriate square of thc map. The map is just a very special output column of the t ruth table. The third step is to loop adjacent groups of two, four, or eight Is together. Figure 5-27d shows two loops drawn on the map. Each loop contains two Is. The foiuth step is to eliminatc variables. Considcr first the shaded loop in Fig. 5-27d. Note that a 5 and a E ( not R ) are containcd within the shaded loop. W ien a rariable and its cornplcrncnt are within a l oop. that iaariable i s eliminated. From t hc shaded I mp, thc R and terms arc eliminated, leaving the A variable (Fig. 5 - 2 7 ~ )Next . consider the unshadcd loop in Fig. 5 -276. I t contains an A and a A(not A ) . T he A and Atcrms are eliminated, leaving only the U variable (Fig. 5-27e). Thc f ifth step is to OR thc remaining variables. T hc final simplijied Fkwlean cxpression i s A + 8 = Y (Fig. 5-27e).The simplified cxpression is that of a 2-input OR gatc. Pig. 5-28 Using a thrcc-variablc map 84 SIMPLIFYING LOGIC CIRCUITS: MAPPING [CHAP. 5 In summary, the steps in simplifying a logic expression using a Karnaugh map are as follows: 1. Write a minterm Boolean expression from the truth table. 2. Plot a 1 o n the map for each ANDed group of variables. (The number of 1s in the Y column of the truth table will equal the number of I s on the map.) 3. Draw loops around adjacent groups of two, four, or eight 1s on the map. (The loops may overlap.) 4. Eliminate the variable(s) that appear(s) with its (their) complement(s) within a loop, and save the variable(s) that is (are) left. 5. Logically O R t he groups that remain to form the simplified minterm expression. Consider the truth table in Fig. 5 -28a. T he first step in using the Karnaugh map is to write the minterm Boolean expression for the truth table. Figure 5 -28b illustrates the unsimplified minterm expression for the truth table. The second step is plotting I s on the map. Five 1s a re plotted on the map in Fig. 5 -28c. Each 1 corresponds to an ANDed group of variables (such as A - B - C ). T he third step is to loop adjacent groups of I s on t he map. Loops are placed around groups of eight, four, or two 1s. Two loops are drawn on the map in Fig. 5 -28d. T he shaded loop contains two 1s. T he larger loop contains four 1s. T he f ourth step is to eliminate variables. The shaded loop in Fig. 5-28d contains both the C and terms. The C variable can thus be eliminated, leaving the x . B term. The large loop terms. These can be eliminated, leaving only the contains the A and A as well as the B and C variable. The f ifth step is to O R t he remaining terms. The C and A - B terms are ORed in Fig. 5 -28e. T he final simplified Boolean expression is then C + A - = Y . This is much easier to implement B with ICs than the unsimplified version of Fig. 5 -28b. T he simplified expression will generate the truth table in Fig. 5 -28a. c SOLVED PROBLEMS 5.24 Write the unsimplified minterm Boolean expression for the truth table in Fig. 5-29. Inputs Output ABC Y 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 1 Inputs Output A B C Y 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Fig. 5-29 Solution: A . B . C + A . B .C + A .B. + A . B - c = Y c 5.25 Draw a 3-variable Karnaugh map. Plot four 1s on the map from the Boolean expression developed in Prob. 5.24. Draw the appropriate loops around groups of I s o n the map. Solution: See Fig. 5-30. CHAP. 51 85 SIMPLIFYING LOGIC CIRCUITS: MAPPING , l.B 1.B A.B A*B Fig. 5-30 Karnaugh map solution 5.26 Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.25. Solution: A - + A * C= Y C 5-8 KARNAUGH M A P S WITH FOUR VARIABLES Consider the truth table with four variables in Fig. 5-31a. The first step in simplification by using a Karnaugh map is to write the minterm Boolean expression. The lengthy unsimplified minterm expression appears in Fig. 5-31b. A n A NDed group for four variables is written for each 1 in the Y column of the truth table. The second step is to plot 1s on the K.arnaugh map. Nine 1s are plotted on the map in Fig. 5-31c. Each 1 on the map represents an ANDed group of terms from the unsimplified expression. The third step is to loop adjacent groups of 1s. Adjacent groups of eight, four, or two 1s are looped. Larger loops provide more simplification. Two loops have been drawn in Fig. 5-31c. The larger loop contains eight 1s. The fourth step is to eliminate variables. The large loop in Fig. 5-31c eliminates the A , B , and C variables. This leaves the D term. The small loop contains two 1s and (c) Plotting and looping 1s on map C.6 C.0 C*D C.6 D (d) Simplified Boolean expression: Fig. 5-31 Using a four-variable map D +A .B - C= Y 86 [CHAP. 5 SIMPLIFYING LOGIC CIRCUITS: MAPPING eliminates the D variable. That leaves the A - B . C t erm. The fifth step is to logically OR t he remaining terms. Figure 5-31d shows the remaining groups ORed to form the simplified minterm expression D + 2. - C = Y . T he amount of simplification in this example is obvious when the two B Boolean expressions in Fig. 5-31 are compared. Consider the 3-variable Karnaugh map in Fig. 5-32a. The letters have been omitted from the edges o f t he map to simplify the illustration. How many loops can be drawn on this map? There are no adjacent groups of I s, a nd therefore no loops are drawn in Fig. 5-32a. N o simplification is possible in the example shown in Fig. 5-32a. Fig. 5-32 Some unusual looping variations T he 3-variable Karnaugh map in Fig. 5-326 contains two Is. T hink of t he top and bottom edges of the map as being connected as if rolled into a tube. The 1s can then be looped into a group of two, a s shown in Fig. 5-326. One variable can thus be eliminated. Consider the 4-variable Karnaugh maps in Fig. 5-32c and d . T he top and bottom edges of t he map are considered connected for looping purposes i n Fig. 5-32c. The 1s can then be looped into a group of f our Is, a nd two terms can be eliminated. In Fig. 5-32d the right edge of the map is considered connected to the left edge. The four 1s are looped into a single loop. Two variables are thus eliminated. Another looping variation is illustrated in Fig. 5-32e. The corners of t he map are considered connected as if t he map were wrapped around a ball. The four 1s in {he corners of the map are then looped into a single loop. The single loop of f our 1s thereby eliminates two variables. SOLVED PROBLEMS 5.27 W rite the unsimplified minterm Boolean expression for the truth table in Fig. 5-33. Inputs A B Inputs o utput C D 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Y o utput A B C D 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ~ 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Fig. 5-33 Y CHAP. 51 5.28 SIMPLIFYING LOGIC CIRCUITS: MAPPING 87 Draw a 4-variable Karnaugh map. Plot six 1s on the map from the Boolean expression developed in Prob. 5.27. Draw the appropriate loops around groups of I s on the map. Solution: See Fig. 5-34. Fig. 5-34 Karnaugh map solution 52 .9 Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.28. Solution: - - _ . A.C+A*C-D=Y 5.30 Write the unsimplified sum-of-products Boolean expression for the truth table in Fig. 5-35. Inputs A B C D Y A 0 0 0 0 0 0 0 0 53 .1 I Inputs output 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 10CI 100 101 101 110 110 111 111 B C D Output Iy O 1 0 1 0 1 0 1 Draw a 4-variable Karnaugh map. Plot five 1s on the map from the Boolean expression developed in Prob. 5.30. Draw the appropriate loops around groups of I s on the map. Solution: See Fig. 5-36. 88 SIMPLIFYING LOGIC CIRCUITS: MAPPING [CHAP. 5 A. Fig. 5-36 K arnaugh map solution 5.32 Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.31. Solution: 2 i+ A . B . C . D = Y -3 5-9 USING M A P S WITH MAXTERM EXPRESSIONS A different form of the Karnaugh map is used with maxterm Boolean expressions. The steps for simplifying maxterm expressions are as follows: 1. Write a maxterm Boolean expression from the truth table. (Note the inverted form in Fig. 5-37a.) 2. Plot a 1 on the map for each ORed group of variables. The number of OS in the Y column of t he truth table will equal the number of 1s on the map. 3. Draw loops around adjacent groups of two, four, or eight 1 s on the map. 4. Eliminate the variable(s) that appear(s) with its (their) complement(s) within a loop, and save the variable(s) that is (are) left. 5 . Logically AND the groups that remain to form the simplified maxterm expression. Consider the truth table in Fig. 5-37a. T he first step in simplifying a maxterm expression by using a Karnaugh map is to write the expression in unsimplified form. Figure 5-37a illustrates how a maxterm is written for each 0 i n the Y c olumn of the truth table. The terms of the ORed group are inuerted from the way they appear in the truth table. The ORed groups are then ANDed to form the unsimplified maxterm Boolean expression in Fig. 5-37b. T he second step is to plot I s on the map for each ORed group. The three maxterms in the unsimplified expression are placed as three 1s on the reuised Karnaugh map (Fig. 5 -37c). T he third step is to loop adjacent groups of eight, four, or two 1s o n the map. Two loops have been drawn on the map in Fig. 5-37c. Each loop contains two 1s. T he f ourth step is to eliminate variables. The shaded loop in Fig. 5-37c is shown to eliminate the A variable. This leaves the maxterm ( B + C ) . T he partially unshaded loop is shown to eliminate the B variable. This leaves the maxterm ( A+ ). T he f ifth step is the ANDing of the remaining terms. C Figure 5-37d shows the two maxterms being ANDed to form the simplified maxterm Boolean + expression ( B + C ) - (2 C ) = Y . Compare this simplified maxterm expression with the simplified minterm expression from Fig. 5 -28e. T hese two expressions were developed from the s ame t ruth table. The minterm expression ( C + z . B = Y ) is slightly easier to implement by using logic gates. The maxterm mapping procedure and Karnaugh map are different from those used for minterm expressions. Both techniques should be tried on a truth table to find the less costly logic circuit. A 4-variable Karnaugh map f or m axterm expressions is illustrated in Fig. 5-38. Note the special pattern of letters o n t he left and top edges of the map. Care must always be used to position all the terms correctly when drawing maps. SIMPLIFYING LOGIC CIRCUITS: MAPPING CHAP. 51 89 Fig. 5-38 A four-variable m axterm K arnaugh map SOLVED PROBLEMS 5.33 Write the unsimplified rnaxterm Boolean expression for the truth table in Fig. 5-39. (Be sure to note the inverted form.) Solution: (A+B + C ) - ( A + B+ C > * ( A + B C ) . ( A + B+ C) = Y + 90 SIMPLIFYING LOGIC CIRCUITS: MAPPING I I nputs O utput I 1 I nputs [CHAP. 5 O utput ABC Y ABC Y 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 Fig. 5-39 5.34 Draw a 3-variable Karnaugh map for maxterm expressions. Plot four 1s on the map for the maxterm Boolean expression developed in Prob. 5.33. Draw the appropriate loops around groups of 1s on the map. Solution: See Fig. 5-40. A+B A+B A+B A+B Fig. 5-40 M axterm map solution 5.35 Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.34. Solution: ( A+ ) ( B + C) = Y B * 5.36 Write the unsimplified product-of-sums Boolean expression for the truth table in Fig. 5-41. I nputs 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 output 0 1 0 1 0 1 0 1 Fig. 5-41 Solution: ( A + B + c +D ) * ( A B +c +m ( A +B + + C + D ) . ( A + B + c + D)*(LT+ + C + D ) = Y B CHAP. 51 5.37 SIMPLIFYING LOGIC CIRCUITS: MAPPING 91 Draw a 4-variable product-of-sums Karnaugh map. Plot five 1s on the map for the Boolean expression developed in Prob. 5.36. Draw the appropriate loops around groups of I s o n the map. Solution: See Fig. 5-42. A+B A+B A+B A+B Fig. 5-42 Maxterm Karnaugh map solution 5.38 Write the simplified product-of-sums Boolean expression based on the Karnaugh map from Prob. 5.37. Solution: (A + B t C) * ( B + D )= Y 5-10 DON’T CARES O N KARNAUGH M A P S Consider the table for BCD (8421) numbers given in Fig. 5-43. Note that the binary numbers 0000 t o 1001 on the table are used to specify decimal numbers from 0 to 9. For convenience, the table is completed in the shaded section, which shows other possible combinations of t he variables D , C , B , and A . These six combinations (1010, 1011, 1100, 1101, 1110, and 1111) are not used by the BCD code. These combinations are called don’t cares when plotted on a Karnaugh map. The don’t cares may have some effect on simplifying any logic diagram that might be constructed. Suppose a problem specifying that a warning light would come O N when the BCD count reached 1001 (decimal 9); see the truth table in Fig. 5-44. See 1 is placed in the output column ( Y )of t he truth table after the input 1001. The Boolean expression for this table (above the shaded section) is D - C - B . A = Y . This is shown to the right of the table. The “not used” combinations in the shaded section of t he truth table_might have some effect on this problem. A Karnaugh map is drawn in Fig. 5-45b. The 1 for the D - C B . A term is plotted on the map. The six don’t cares (X’s from the truth table) are plotted a s X’s on the map. An X on the map means that square can be either a 1 or a 0. A loop is drawn around adjacent 1s. The X’s on t he map can be considered Is, so t he single loop is drawn around the 1 and three X’s. Remember that only groups of two, four, or eight adjacent 1s and X’s a re looped together. The loop contains four squares, which will eliminate two variables. The B and C variables are eliminated, leaving the simplified Boolean expression D - A = Y in Fig. 5-45c. As was said earlier, unused combinations from a truth table are called don’t cares. They are shown as X’s on a Karnaugh map. Including don’t cares (X’s) in loops on a map helps to further simplify Boolean expressions. -_. * SIMPLIFYING LOGIC CIRCUITS: MAPPING [CHAP. 5 Big. S-45 Using a map SOLVED PROBLEMS 5.39 Write the unsimplified minterm Boolean expression for the BCD truth table in Fig. 5-46. Solution: D . ~ . B . ~ .+~ D B . A y . I CHAP. 51 93 SIMPLIFYING LOGIC CIRCUITS: MAPPING I nputs Inpit t s output D C B 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 D 0 0 0 0 0 C B A 0 0 0 1 1 A 0 0 0 0 0 output 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 1 1 Fig. 5-46 5.40 Draw a 4-variable minterm Karnaugh map. Plot two 1s and six X’s (for the don’t cares) on the map based on the truth table in Fig. 5-46. Draw the appropriate loops around groups of 1s and X’s on the map. Solution: See Fig. 5-47. A.B A.B A.B A-B Fig. 5-47 Karnaugh m ap solution 5.41 Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.40. Solution: D=Y 5-11 KARNAUG n WS VITH FIVE ES A three-dimensional Karnaugh map can be used to solve logic problems with five variables. The map used to simplify 5-variable minterm Boolean expressions is shown in Fig. 5-48c. Notice that both the top ( E ) plane and bottom ( E ) plane are duplicates of the 4-variable minterm map used in Sec. 5-8. The procedure for simplifying a minterm logic expression using a 5-variable Karnaugh map is like those used previously. Consider the truth table with five variables in Fig. 5-48a. The first step in simplification is to write the minterm Boolean expression. The lengthy unsimplified miriterm Boolean expression appears in Fig. 5-48b. A n A NDed group of five variables is written for each 1 in the Y column of the truth table. The second step is to plot 1s on the 5-variable map. Seven 1s a re plotted on the map in Fig. 5-48c. 94 S M PI-IFYING I .OGlC Cl RCUITS: M APPING I Fig. 5-48 Karnaugh m ap solution--5 [ CHAP. 5 variablc Each 1 on t he map represents an ANDed group of terms from the unsimplificd mintcrm expression. The rhird s fep is to loop adjacent groups of Is. Adjacent groups of eight, four, or two 1s a re lociped. Two loops have been drawn i n Fig. 5-48c. T he largcr loop contains four Is a nd forms a cylindcr between the t op and bottom planes of t he map. I'hc smaller loop contains two 1s and forms the cylinder at the lower left in Fig. 5 -48c. Thc singlc 1 ncar thc b ottom of the map does not have any Is adjacent to it on c ithcr thc E or planc. T hc fourth step is to climinatc- ariables. Thc largc loop vACD (cylinder) in Fig. 5 -48c climinatcs t hc B and E variables leaving the term - - - -.T he smallcr loop (cylinder) contains two Is and climinatcs the E tcrm lcaving the term A R . C D.T he single 1 ncar thc bottom is not loopcd and allows no simplification. Thc f ifth srvp is to logically OR thc rcmaining - - CHAP. 51 95 SIMPLIFYING LOGIC CIRCUITS: MAPPING terms. Figure 5-48d shows the remaining groups ORed, yielding the simplified minterm expression of E - - D + A. - D + A . E - C - D E = Y . T he amount of simplification in this example is obvious when the two Boolean expressions in Fig. 5-48 a re compared. A c c * SOLVED PROBLEMS 5.42 Write the unsimplified minterm Boolean expression for the truth table in Fig. 5-49. I nputs output output Inputs A C D E Y A B C D E Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 0 54 .3 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Draw a 5-variable Karnaugh map. Plot ten I s on the map from the Boolean expression developed in Prob. 5.42. Draw the appropriate loops around groups of I s on the map. Solution: See Fig. 5-50. Fig. 5-50 96 5.44 [CHAP. 5 SIMPLIFYING LOGIC CIRCUITS: MAPPING Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.43. Solution: -A - c-D -E + A. = Y D Supplementary Problems 5.45 Write a minterm Boolean expression for the truth table i n Fig. 5-51. -Ans. X - B C + x . B - c + A . B - C + A . B C = Y * Inputs Output Inputs ABC Y A B C Y 0 0 0 0 5.46 Output 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 Draw an AND-OR logic diagram that will perform the logic specified by the Boolean expression developed in Prob. 5.45. A m. See Fig. 5-52. Y U Fig. 5-52 A ND-OR logic circuit 5.47 Write the maxterm Boolean expression for the truth table in Fig. 5-51. Ans. ( A + B + C ) - ( A+ E + C ) - ( A + + c ) . ( A + B + ) = Y B C 5.48 Draw an OR-AND logic diagram that will perform the logic specified by the Boolean expression developed in Prob. 5.47. Ans. See Fig. 5-53. 97 SIMPLIFYING LOGIC CIRCUITS: MAPPING CHAP. 51 A A 1 B 2 C 1 Fig. 5-53 OR-AND logic circuit 5.49 Use De Morgan’s theorem to convert the Boolean expression ( A+ B + c + D ) - ( A + B + C-10) =Y to its minterm form. Show each step as in Fig. 5-15. Ans. Maxtermexpression ( A + B + C + D ) - ( A + B + C + W ) = Y First step A.B-c.D+A.B.C.D Second step x.E . c .jj + A. . F . D E Third sfep A.Z.C.D+A.E.?.D Fourth step eliminate double overbars A . B - C . 0 + A. C * D = Y B Minterm expression * 5.50 Draw a 4-variable minterm Karnaugh map. Plot two 1s on the map for the terms in the minterm expression developed i n Prob. 5.49. Draw the appropriate loops around groups of 1s on the map. Ans. See Fig. 5-54. Fig. 5-54 Completed minterm Karnaugh map 5.51 Write the simplified minterm Boolean expression based on the Karnaugh map from Prob. 5.50. Ans. X - B . D = Y 5.52 Use De Morgan’s theorem to convert the Boolean expression A - B - C D maxterm form. Show each step as i n Fig. 5-15. _--- a -- + A- - C - D = Y to its B 98 SIMPLIFYING L OGIC CIRCUITS: MAPPING Ans. Minterm expression First step [CHAP. 5 ( A+ + c + 0 ) ( A +B + c + 0 ) B * Second step ( A=+ B= + c= + E ) . ( A=+ B + c= + 5 ) ( A=+ E + F + E ) . B + +E) Third step Fourth step eliminate double overbars Maxterm expression ( A + B + c + D ) - ( A + B + c + D ) = Y (A=+ 5.53 F Draw a 4-variable Karnaugh map. Plot two 1s on the map for the terms in the maxterm expression developed in Prob. 5.52. Draw the appropriate loops around groups of 1s on the map. Am. See Fig. 5-55. C+D C+D c+D c + D A+B A+B A+B A+B Fig. 5 -55 Completed maxterm map 5.54 Write the simplified maxterm Boolean expression based on the Karnaugh map from Prob. 5.53. +C +D =Y Register to View Answer 5.55 Draw an AND-OR logic circuit from the Boolean expression A B See Fig. 5 -56. Ans. + c- D +E + F = Y. B : E F 5.56 Fig. 5-56 AND-OR logic circuit Draw a NAND logic circuit for the AND-OR circuit in Prob. 5.55. T he NAND logic circuit should perform the logic in t he expression A B + - D + E + = Y . Ans. See Fig. 5-57. * c CHAP. 51 99 SIMPLIFYING LOGIC CIRCUITS: M.APPING E I F Fig. 5-57 NAND logic circuit 5.57 Draw an OR-AND logic circuit for the Boolean expression See Fig. 5-58. Register to View Answer A. B+ C ) - E = Y . ( * - C A . ( B + C ) * i S * E =Y D j E Fig. 5 -58 OR-AND logic circuit 5-58 Draw a NOR logic circuit for the OR-AND circuit i n Prob. 5.57. T he NOR circuit should perform the ( logic in the expression 2.E + C ) - D E = Y . Ans. See Fig. 5 -59. * A 1 I D E 0 Fig. 5 -59 NOR logic circuit 5.59 NOR logic can be easily substituted in an (AND-OR, OR-AND) circuit. NOR logic can be substituted for OR-AND circuits. Ans. 5.60 Write the unsimplified sum-of-products Boolean expression for the truth table in Fig. 5-60. - + .A - C * D + A B - * D + A. * D + A. - C * + A. - C + A B B B A-B-C~=Y Register to View Answer * * c * c 100 Inputs Inputs Output A B C 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 A B C D 1 0 0 0 0 0 0 0 0 output Y D 0 5.61 [CHAP. 5 S IMPLIFYING LOGIC CIRCUITS: MAPPING 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 Y 1 0 1 0 1 0 1 0 Draw a 4-variable rninterm Karnaugh map. Plot seven 1s o n the map from the Boolean expression developed in Prob. 5.60. Draw the appropriate loops around groups of 1s o n the map. Ans. S ee Fig. 5-61. Fig. 5-61 Completed minterm map 5.62 Write the simplified rninterm Boolean expression based on the Karnaugh map from Prob. 5.61. -Register to View Answer- B + A - B + B . D = Y 5.63 Write the unsimplified product-of-sums Boolean expression for the truth table in Fig. 5-60. Ans. ( A + B + C -+ 0 )- ( A + B + 0 ) ( A + + C + D )* ( A + + C + I s) - ( A + + * ( A + B+ C + D).(A++ B D)*(A+ C + o ) - ( A + B + = Y E+ 5.64 c+ c+ * c+D) c +D ) Draw a 4-variable maxterm Karnaugh map. Plot nine 1s on t he map from the Boolean expression developed in Prob. 5.63. Draw the appropriate loops around groups of 1s on t he map. Ans. S ee Fig. 5-62. CHAP. 51 SIMPLIFYING LOGIC CIRCUITS:MAPPING 101 C+n C + b C+b C+D A+B A+B A+R A+R Fig.5-62 Complctcd maxtcrm map 5.65 Writc t he simplified maxterm Boolean cxprcssion based on the Karnaugh map f rom Prob. 5.64. Am. 5.66 (A+B+C)*6=Y (maxtcrm. minterm) form of Boolean cxprcssion is the easiest circuit to implcmcnt for the t ruth table i n Fig. 5 -60. A m. T he muxrmn expression ( A + E + C ) . 6 - Y appears to bc simpler to implement w ith logic gates -= t han the minterm expression C 6 + A * E + R * D Y. The simplified - 5.67 - Design a logic circuit that will respond with a 1 when evcn numbers (decimals 0. 2 ,4.6,8) appear at the inputs. Figurc 5-63 is thc D CD (84421) truth table you will use in this problem. Write the unsimplificd m intem Roolcan expression for the truth table. . ~ h cxpression epreA ~ W . B . ( ' I . ~ . ~ ~ + ~ . T . R . ~ + ~ . c . ~ ~ . / ~ + ~Y. c . Re. ~ ~ + Dr. ~ . B . X sents the Is i n the Y column of t he t ruth tahlc. Six other g roups of don't cares (X's) might also be considered and will be plotted on the map. Fig.5-63 T ruth table with don't c a m 5.68 Draw a 4-variable mintcrm Karnaugh map. Plot five Is and six X's (for t he don't cares) on the map based on the truth table in Fig. 5-63.Draw thc appropriate loops around groups of 1s and X's on the map. Am. Sce Fig. 564. 102 SIMPLIFYING LOGIC CIRCUITS: MAPPING [CHAP. 5 Fig. 5-64 Completed minterm maps using don’t cares 5.69 Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.68. Ans. L =Y 5.70 Write the simplified Boolean expression based on the Karnaugh map from Prob. 5.68 without using the don’t cares for _ _ _ simplification. -Register to View AnswerD + A - B C = Y . T he use of the don’t cares greatly aids simplification i n this problem because using them reduces the expression to J=Y . * * 5.71 In this chapter, individual logic gates were used to simplify combinational logic problems. List several more complex ICs used for logic circuit simplification. Ans. Several ICs used to simplify combinational logic problems are data selectors (multiplexers), decoders, PLAs, ROMs, and PROMS. 5.72 Write the unsimplified minterm Boolean expression for the truth table in Fig. 5-65. Register to View Answer- .C - D E +A.B. D - E + A. . C - B E + A. - C D E + B C B B A . B .C.D. E + A . B . C - D * E+ A * B. C * D- E + A * B* C. D * E= Y * * * o utput Inputs Inputs 1 o utput A R C D E Y 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 A B C D E Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fig. 5-65 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 CHAP. 51 5.73 SIMPLIFYING LOGIC CIRCUITS: MAPPING Draw a 5-variable minterm Karnaugh map. Plot eight 1s on the map from the Boolean expression developed in Prob. 5.72. Draw the appropriate loops around groups of 1s o n the map. Ans. See Fig. 5-66. Fig. 5-66 5.74 103 Write the simplified minterm Boolean expression based on the Karnaugh map from Prob. 5.73. Register to View Answer- B . D + x * C . E = Y Chapter 6 TTL and CMOS ICs: Characteristics and Interfacing 6-1 INTRODUCTION T he growing popularity of digital circuits is due in part to the availability of inexpensive integrated circuits (ICs). Manufacturers have developed many families of digital ICs-groups that can be used together in building a digital system. The ICs in a family are said to be compatible, and they can be easily connected. Digital ICs can be categorized as either bipolar or unipolar . Bipolar digital ICs a re fabricated from parts comparable to discrete bipolar transistors, diodes, and resistors. The TTL (transistor-transistor logic) family is the most popular of t he ICs using the bipolar technology. Unipolar digital ICs are fabricated from parts comparable to insulated-gate field-effect transistors (IGFETs). The CMOS (complementary-metal-oxide semiconductor) family is a widely used group of ICs based o n t he metal-oxide semiconductor (MOS) technology. Integrated circuits are sometimes grouped by manufacturers as to their circuit complexity. Circuit complexity of ICs is defined as follows: 1. S SI (small-scale integration ): less than 12 Number of gates: Typical digital devices: gates and flip-flops 2. M SI (medium-scale integration): Number of gates: 12 to 99 Typical digital devices: adders, counters, decoders, encoders, multiplexers, and demultiplexers, registers 3. L SI (large-scale integration 1: Number of gates: 100 t o 9999 Typical digital devices: digital clocks, smaller memory chips, calculators 4. V LSI (uery -1arge-kcale integration ): Number of gates: 10,000 t o 99,999 Typical digital devices: microprocessors, larger memory chips, advanced calculators 5 . U LSI (ultra-large-scale integration): Number of gates: over 100,000 Typical digital devices: advanced microprocessors Many digital IC families are available to the digital circuit designer, and some of them are listed below: 1. Bipolar families: R TL resistor-transistor logic DTL diode-transistor logic TTL transistor-transistor logic (types: standard TTL, low-power TTL, high-speed TTL, Schottky TTL, advanced low-power Schottky TTL, advanced Schottky TTL) E CL emitter-coupled logic (also called CML, current-mode logic) HTL high-threshold logic (also called HNIL, high-noise-immunity logic) integrated-injection logic IIL 104 CHAP. 61 105 T TL A ND CMOS ICs: CHARACTERISTICS AND INTERFACING 2. M OS families: PMOS P-channel metal-oxide semiconductor NMOS N-channel metal-oxide semiconductor CMOS complementary metal-oxide semiconductor The TITL and CMOS technologies are commonly used to fabricate SSI and MSI integrated circuits. Those circuits include such functional devices as logic gates, flip-flops, encoders and decoders, multiplexers, latches, and registers. MOS devices (PMOS, NMOS, and CMOS) dominate in the fabrication of LSI and VLSI devices. NMOS is especially popular for use in microprocessors and memories. CMOS is popular for use in very low power applications such as calculators, wrist watches, and battery-powered computers. 6-2 DIGITAL IC TERMS Several terms that appear in IC manufacturers’ literature assist the technician in using and comparing logic families. Some of the more important terms and characteristics of digital ICs will be outlined. How is a logical 0 (LOW) o r a logical 1 (HIGH) defined? Figure 6 -la shows an inverter (such as the 7404) from the TTL IC family. The manufacturers specify tha-t,for proper operation, a LOW input Output voltage Input voltage +5 +4 Typical 3 .5 V 2 .4 V +3 t 0.4 V (a) TTL input and output voltage levels 9.95 v Output Output voltage + I0 v +5 v CMOS 0.05 v ( 6) CMOS input and output voltage levels Fig. 6-1 Defining logical HIGH and LOW GND 106 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 must range from GND to 0.8 V. Likewise, a H IGH input must range from 2.0 V to 5.0 V. T he unshaded section in Fig. 6 - l ( a ) between 0.8 V and 2.0 V o n the input side is the forbidden region. An input voltage of 0.5 V would then be a LOW input, whereas an input of 2.6 V would be a HIGH input. A n input of 1.5 V would yield unpredictable results and is considered a forbidden input. The forbidden region might also be called the uncertain or undefined region. The expected outputs are shown on the right side of the TTL inverter shown in Fig. 6 - l a . A LOW o utput would typically be 0.1 V but could be as high as 0.4 V. A H IGH output would typically be 3.5 V b ut could be as low as 2.4 V. T he H IGH o utput depends on the resistance value of the load at the output. The greater the load current, the lower the HIGH output voltage. The unshaded portion on the output voltage side in Fig. 6 - l a , is the forbidden region. Observe the difference in the definition of a HIGH from input to output in Fig. 6 - l a . T he input HIGH is defined as greater than 2.0 V, whereas the output HIGH is g reater than 2.4 V. T he reason for this difference is to provide for noise immunity-the digital circuit's insensitivity to undesired electrical signals. The input LOW is less than 0.8 V and the output LOW is 0.4 V o r less. Again the margin between those figures is to assure rejection of unwanted noise entering the digital system. The voltage ranges defining HIGH and LOW are different for each logic family. For comparison, the input and output voltages for a typical CMOS inverter are given in Fig. 6 - l b . In this example the manufacturer specifies that the HIGH o utput will be nearly the full supply voltage (over +9.95 V). A LOW o utput will be within 0.05 V of ground (GND) potential. Manufacturers also specify that a CMOS IC will consider a ny input voltage from + 7 V t o + 10 V a s a HIGH. Figure 6-1b also notes that a CMOS IC will consider any input voltage from GND to + 3 V as a LOW. CMOS ICs have a wide swing of output voltages approaching both rails of t he power supply (GND and + 10 V in this example). CMOS ICs also have very good noise immunity. Both these characteristics, along with low power consumption, are listed as advantages of CMOS over TTL ICs. Because of the high operating speeds of many digital circuits, internal switching delays become important. Figure 6-2 is a waveform diagram of t he input and output from an inverter circuit. At point a on the diagram, the input is going from LOW to HIGH (0 to 1). A short time later the output of the inverter goes from HIGH to LOW (1 to 0). T he delay time, shown as t P L I 1is called the propagation , delay of the inverter. This propagation delay may be about 20 nanoseconds (ns) for a standard TTL inverter. At point b in Fig. 6 -2, t he input is going from HIGH to LOW. A short time later, the output s goes from LOW to HIGH. The propagation delay ( t p k j Li) shown as about 15 ns for this standard 'ITL inverter. Note that the propagation delay may be different for the L-to-H transition of the input than for the H-to-L transition. Some IC families have shorter propagation delays, which makes them more adaptable for high-speed operation. Propagation delays range from an average low of about 1.5 ns for the Advanced Schottky TTL family to a high of about 125 ns for the HTL IC family. b a I 1 Time (sn) I ! I I o utput I 0 ~PLH ~PHL z 20 ns z 15 n s Fig. 6-2 Waveforms showing propagation delays for a standard TTL inverter CMOS ICs are noted for their low speed (higher propagation delays). A common type of CMOS IC may have a propagation delay of from 25 to 100 ns, depending on t he device. However, a newer subfamily of high-speed CMOS ICs has reduced the propagation delays. For instance, the 74HC04 CMOS inverter has a propagation delay of only 8 ns. These high-speed CMOS ICs make this family much more suitable for higher-speed applications. CHAP. 61 TTL AND CMOS ICs: CHARACTERISTICS A N T ) INTERFACING 107 Integrated circuits are grouped into f amilies because they are compatible. Figure 6 -3a shows the left T TL inverter driving the right load inverter. In this case conuentional current flows from the load device to the driver gate and to ground as illustrated in Fig. 6 -3a. It is said that the driver inverter is sinking the current (sinks current to ground). This sinking current may be as high as 1.6 mA (milliamperes) from a single T TL load. Note the direction of a sinking current. TTL T TL driver +5 v load +5 v HIGH HIGH (U) Sinking drive current to ground 'TTL load TTL driver +5, v ( h ) Source drive current Fig. 6-3 When the output of the TTL driver goes HIGH, t he situation in Fig. 6 -3b is created. In this case c onventional current flows from the driver to the load device as illustrated. It is said that the driver inverter is sourcing t he current. This sourcing current is quite low when it is driving a single load (perhaps only 40 p A, microamperes). The current driving capabilities of logic gates vary from family to family. As a general rule, TTL ICs can sink more current than they can source. For instance, a standard TTL gate used for driving a load can sink up to 16 mA, whereas a low-power Schottky T TL gate can sink only a maximum of 8 mA. CMOS output drive currents are nearly the same when sinking or sourcing current. A typical CMOS gate might have a drive capability of about 0.5 mA. The high-speed CMOS series of ICs (such as t he 7 4HC02) feature sinking or sourcing drive currents of 4 mA. It is common in logic circuits to have one gate drive several others. The limitation of how m any gates can be driven by a single output is called the f an-out of a logic circuit. The typical fan-out for T TL logic circuits is 10. This means that a single T TL output can drive up to 10 TTL inputs. The CMOS logic family has a fan-out of 50. O ne of the many advantages of ICs over other circuits is their low power dissipation. Some IC families, however, have much lower power dissipation than others. The power consumption might average about 10 milliwatts (mW) p er gate in the standard TTI, family, whereas it might be as low as 1 mW per gate in the low-power TTL family. The CMOS family is noted for its extremely low power consumption and is widely used in battery-operated portable products. SOLVED PROBLEMS 6.1 Refer to Fig. 6 - l a . A 2.2-V input to the TTL inverter is a logical ( 0 , I ) input. Solution: A 2.2-V input to a T TL inverter is a logical 1 input, because i t is in the HIGH range. TT'L AND CMOS ICs: CHARACTERISTICS AND INTERFACING 108 6.2 Refer to Fig. 6 -la. A 2.2-V o utput from the TTL inverter is a logical [CHAP. 6 o utput. Solution: A 2.2-V output from a TTL inverter is defined as a forbidden output caused by a faulty IC or too heavy a load at the output. 6.3 W hat are typical TTL LOW and HIGH output voltages? Solution: The typical LOW output voltage from a TTL IC is 0.1 V. The typical HIGH output voltage from a TTL I C is about 3.5 V, but the voltage varies widely with loading. 6.4 A 0.7-V input would be considered a (forbidden, HIGH, LOW) input to a TTL device. Solution: S ee Fig. 6 -la. A 0.7-V input would be considered a LOW input to a TTL IC. 6.5 T he time it takes for the output of a digital logic gate to change states after the input changes is . called Solution: Propagation delay is the time i t takes for the output to change after the input has changed logic states. See Fig. 6-2. 6.6 Propagation delays in modern digital ICs are measured in (milli, micro, nano) seconds. Solution: Propagation delays in modern digital ICs are measured i n nanoseconds. A nanosecond (ns) is 10-9 s. 6.7 T he number of parallel loads that can be driven by a single digital IC o utput is a characteristic called . Solution: Fan-out is t he number of parallel loads that can be driven by a single digital IC o utput. 6.8 T he (CMOS, TTL) digital IC family is noted for its very low power consumption. Solution: T he CMOS digital IC family is noted for its very low power consumption. 6.9 R efer to Fig. 6 -lb. An 8.5-V input to the CMOS inverter is a logical ( 0,l) input. Solution: 8.5-V input to a CMOS inverter is a logical 1 input because it is in the HIGH range shown in Fig. 6 -lb. 6.10 R efer to Fig. 6 -lb. W hat are the typical CMOS LOW a nd HIGH output voltages? Solution: T he typical output CMOS voltages are very near the rails of the power supply. A typical LOW might be 0 V (GND), and a HIGH might be + 10 V. CHAP. 61 6.11 T he TTL A ND CMOS ICs: CHARACTERISTICS AND INTERFACING 109 (CMOS, T TL) logic family is noted for its very good noise immunity. Solution: The CMOS family is noted for its good noise immunity. 6.12 R efer to Fig. 6-4u. The NAND gate is said to be circuit shown. (sinking, sourcing) current in the logic ( a ) N AND gate driving an inverter input (6) Inverter driving an OR input Fig. 6-4 Solution: The output of the NAND gate shown in Fig. 6-4a is LOW. The NAND gate is therefore said to be sinking the drive current. 6.13 Refer to Fig. 6-4b. The inverter is said to be circuit shown. (sinking, sourcing) current in the logic Solution: The output of the inverter shown in Fig. 6 -4b is HIGH. The inverter is therefore said to be sourcing the drive current. 6-3 l T L INTEGRATED CIRCUITS T he famous 7400 series of TTL logic circuits was introduced by Texas Instruments in 1964. The TTL family of ICs is still one of the more widely used for constructing logic circuits. T-TL ICs a re manufactured in a wide variety of SSI and MSI integrated circuits. Over the years, improvements in TTL logic circuits have been made, which has led to subfumilies of transistor-transistor logic ICs. T he following six T TL subfamilies are currently available from National Semiconductor Corporation: 1. Standard TTL logic Typical IC marking: 2. Low-power TTL logic Typical IC marking: 3. Low-power Schottky TTL logic Typical IC marking: 4. Schottky 'ITL logic Typical IC marking: 7404 (function: hex inverter) 74L04 (hex inverter) 74LS04 (hex inverter) 74S04 (hex inverter) 110 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 5 . Advanced low-power Schottky TTL logic Typical IC marking: 74ALS04 (hex inverter) 6 . Advanced Schoitky TTL logic Typical IC marking: 74AS04 (hex inverter) The code letters L, LS, S , ALS, and AS a re used in t he middle of t he 7400 series n umber to designate the subfamily. This can be observed above where typical IC markings for the various TTL subfamilies are listed. Notice that no special code letter is used in the middle of a standard TTL logic 1C. The subfamilies with the code letter S contain a Schottky barrier diode to increase switching speed. Several companies also use the code letter F (as i n 74F04) for a f ast advanced Schottky TTL IC. It should be noted that the voltage characteristics of all the TTL subfamilies are the same. Their power and speed characteristics are different, and under some conditions, substituting one subfamily for another might cause trouble. For instance, a technician would not want to replace a very fast 74AS04 inverter IC with a much slower 74L04 IC from the low-power TTL logic subfamily. The internal details of a standard T TL NAND gate are shown in Fig. 6-5. National Semiconductor Corporation’s description follows. T TL logic was the first saturating logic integrated circuit family introduced; it set the standard for all future families. I t offers a combination of speed, power consumption, output source, and sink capabilities suitable for most applications, and i t offers the greatest variety of logic functions. The basic gate (see Fig. 6 -5) features a multiple-emitter input configuration for fast switching speeds and active pull-up output to provide a low driving source impedance which also improves noise margin and device speed. Typical device power dissipation is 10 mW per gate, and the typical propagation delay is 10 ns when driving a 15 p F per 400 - load. vcc I I nput A I nput B 1 t put Fig. 6-5 Schematic diagram of a s tandard T TL NAND g ate (Courtesy of National Semiconductor Corporation) Digital logic designers must consider two important factors when selecting a logic family. They are speed and power consumption. I n Fig. 6 -6a t he TTL subfamilies are ranked from best to worst (fastest to slowest) by speed, or low propagation delay. Note that the advanced Schottky subfamily is the fastest. In Fig. 6 -6b t he TTL subfamilies are ranked by power consumption. Note that the low-power TTL is best in power consumption. Both the low-power Schottky and the advanced low-power Schottky are excellent compromise subfamilies with both low power consumption and high speed. Currently, both the low-power Schottky and the advanced low-power Schottky are very popular. CHAP. 6 1 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING I Speed 1 1 Fastest S1owest TTL subfamily 111 I Advanced Schottky Schottky Advanced low-power Schottky Low-power Schottky Standard TTL Low power ( a) TTL subfamilies ranked by speed Power cons um pt ion Low I High TTL subfamily - Low power Advanced low-power Schottky Low-power Schottky Advanced Schottky Standard TTL Schottky ( h) TTL subfamilies ranked by power consumption Fig. 6-6 Devices in the 7400 T TL series are referred to as commercial grade ICs; t hey o perate over a temperature range of 0 to 70°C. T he 5400 T TL series have the same logic functions, but they will operate over a greater temperature range ( - 55 to 125°C). The 5400 T TL series is sometimes called the military series of T TL logic circuits. ICs in the 5400 series are more expensive. The N A N D gate output shown in Fig. 6-5 is connected between two transistors ( Q3 and Q 4). This is called a t otem pole o utput. For the output to sink current (LOW output), transistor Q 4 must be “turned on” or saturated. For a HIGH o utput as shown in Fig. 6-5, transistor Q 3 must be saturated, which will allow t he N A N D gate to become a source of drive current. Most T TL logic gates have the totem pole type of output. Some TTL circuits have an open-collector o utput i n which transistor Q 3 (see Fig. 6 -5) is missing. A pull-up resistor is used with open-collector outputs. Pull-up resistors are connected from the output to the + 5-V rail of t he power supply outside the logic gate. A third type of TTL o utput used on some devices is the three-state output. I t has three possible outputs (HIGH, LOW, o r high impedance). The three-state output will be explored in connection with the three-state buffer. As a general rule, outputs of T TL devices cannot be connected together. T hat is true of gates with totem pole outputs. T TL o utputs can be connected together with no damage if they are of t he open-collector or three-state type. Markings on TTL ICs vary with the manufacturer. Figure 6-7a shows a typical marking on a TTL digital IC. Pin 1 is identified with a dot, a notch, or a colored band across the end of the IC. The manufacturer’s logo is shown at the upper left in Fig. 6-7a. In this example the manufacturer is National Semiconductor Corporation. The part number is D M7408N. T he core number (generic number) is 7408, which means this is a TTL quad 2-input A N D gate IC. The part number ( DM7408N) is further decoded in Fig. 6 -7b. T he prefix ( DM in this example) is a manufacturer’s code. The core number of 7408 is divided. The 7 4 portion means that this is a commercial grade TTL IC from the 7400 series. The 08 identifies the IC by function (quad 2-input AND gate in this example). The N suffix is the manufacturer’s code for a dual-in-line package IC. 112 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING (a) Markings on a typical TTL IC 7 Manufacturer’s code [CHAP. 6 TT 7 408 7400 T TL series (commercial grade) Manufacturer’s code for dual-in-line package Function of IC ( NAND gate in this example) ( b ) Decoding a typical TTL IC p art number b SN74LS04N 1 ( c ) Markings o n another TTL IC Fig. 6-7 Consider the IC shown in Fig. 6-7c. T he logo represents Texas Instruments, the manufacturer. The SN portion of the part number is a prefix used by Texas Instruments. The 74 specifies this to be a commercial grade TTL IC. The LS means that this is a low-power Schottky TTL digital IC. The 04 specifies the function of the IC (hex inverter in this example). The trailing N specifies a DIP IC. Another characteristic of TTL inputs should be understood. Unconnected inputs to a TTL gate are said to be “floating HIGH.” In other words, any TTL input left disconnected (floating) will be assumed to be at a logical 1. SOLVED PROBLEMS 6.14 List six T TL subfamilies. Solution: The six ITTL subfamilies currently available are standard TTL, low-power, low-power Schottky, Schottky, advanced low-power Schottky, and advanced Schottky. 6.15 T he (speed, voltage) characteristics of all the TTL subfamilies are the same. Solution: T he voltage characteristics of all the ITTL subfamilies are the same. They are shown in Fig. 6 -la. 6.16 T he TTL logic family was first developed in the Solution: T he first T TL logic family was developed i n 1964. (1960s, 1970s). CHAP. 61 6.17 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING 113 When a designer selects a logic family, what two very important characteristics must be considered? Solution: Designers must consider the speed and power consumption characteristics of various logic families in any design. 6.18 Which TTL subfamily is t he fastest? Solution: Refer to Fig. 6 -6a. The advanced Schottky TTL family provides the lowest propagation delays and therefore the best high-speed characteristics. 6.19 Re€er to Fig. 6-5. This standard TTL 2-input N AND gate uses pole) outputs. (open-collector, totem Solution: T he 2-input TTL NAND gate in Fig. 6-5 uses a totem pole output configuration. 6.20 Which two TTL subfamilies consume the least power? Solution: Refer to Fig. 6 -6b. T he low-power and advanced low-power Schottky 'ITL subfamilies are the best for low-power consumption. 6.21 TTL ICs with totem pole outputs (may, may not) have their outputs connected together. Solution: T TL totem pole outputs may not have their outputs connected together. 6.22 T he (5400, 7400) series of TTL logic devices will operate over a wider temperature range, is more expensive, and is referred to as military grade. Solution: The 5400 series of TTL logic devices will o perate over a wider temperature range, is more expensive, and is referred to as military grade. 6.23 TTL open-collector outputs require a resistor connected from the output to the + 5-V rail of the power supply. Solution: T TL open-collector outputs require pull-up resistors. 6.24 Refer to Fig. 6-8. I nterpret the markings on this TTL D IP IC. Fig. 6-8 T TL IC 114 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 Solution: The logo and the DM prefix indicate that National Semiconductor is the manufacturer of this IC. The N suffix indicates that this is a dual-in-line package IC. The 74ALS76 is the generic section of the part number. The 74 means this is a commercial grade 7400 series digital TTL IC. The 76 specifies the function, which is a dual J K flip-flop. The ALS identifies this IC as part of the advanced low-power Schottky ?TL subfamily. 6.25 An unconnected TTL input floats at a (HIGH, LOW) logic level. Solution: H IGH 6-4 CMOS INTEGRATED CIRCUITS T he first complementary metal-oxide semiconductor ( CMOS) family of ICs was introduced in 1968 by RCA. Since then, it has become very popular. CMOS 1Cs are growing in popularity because of their extremely low power consumption, high noise immunity, and their ability to operate from an inexpensive nonregulated power supply. Other advantages of CMOS ICs over TTLs are low noise generation and a great variety of available functions. Some analog functions available in CMOS ICs have no equivalents in TTLs. The schematic diagram of a CMOS inverter is shown in Fig. 6 -9a. I t is fabricated by using both N-channel and P-channel MOSFETS (metal-oxide semiconductor field-effect transistors). The bottom transistor ( Ql) in Fig. 6 -9a is t he N-channel enhancement-mode MOSFET. The top transistor (Q2) is the P-channel enhancement-mode MOSFET. Note that the gate (G), source (S), and drain (D) connections of each FET are labeled. l npu t Q output = vss I nput o utput ( b) Power connections on 4000 series C MOS ICs G ND (a) Schematic diagram of a C MOS inverter (c) Power connections on 74COO and 74HCOO C MOS ICs Fig. 6-9 When the input to the CMOS inverter in Fig. 6 -9a goes LOW (GND), the negative voltage causes the P-channel FET (Q2) t o conduct. However, the N-channel FET (Q1) is not conducting. This connects the output terminal to the positive ( V D Dof the power supply through the low-resistance P ) channel of Q2. T he CMOS circuit shown in Fig. 6 -9a produced a HIGH (positive) output with a LOW input. This is the proper action for an inverter. TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING CHAP. 61 115 When the input to the CMOS inverter shown in Fig. 6-9a goes HIGH ( V,lIl),t he positive voltage causes the N-channel FET (Q1) to conduct. However, the P-channel FET (Q2) is not conducting. ‘This connects the output terminal through the N channel to ground ( V&) of the power supply. In this example a HIGH input generates a LOW output. The general arrangement of transistors and the operation of the CMOS o utput shown in Fig. 6-9a a re comparable to the TTL totem pole outputs diagrammed in Fig. 6-5. I n each case only one of the two output transistors is conducting at a time. The CMOS arrangement is simpler and the currents used to switch the CMOS a re extremely small compared to those of the bipolar TTL counterpart. A logic symbol for the CMOS inverter is shown in Fig. 6-9b. Note especially the labeling on the power supply connections. The VDUand V ss ( GND) labels are used with the older 4000 series and many LSI CMOS ICs. T he newer 74COO and 74HCOO families of CMOS digital logic ICs use the Vcc and G ND labels shown in Fig. 6-9c. This labeling is similar to that of the power connections on T TL ICS. Manufacturers produce at least three common families of SSI/MSI CMOS integrated circuits. They include the older 4000 series, the 74COO series, and the newer 74HC00 series. The CMOS 4000 series has a wide variety of circuit functions. The 4000 series has been improved, and most ICs in this family are now bufSered and referred to as the 4000B series. Some of the circuit functions available in t he 4000 series are logic gates, flip-flops, registers, latches, adders, buffers, bilateral switches, counters, decoders, multiplexers/demultiplexers, and multivibrators (astable and monostable). A typical 4000 series IC is sketched in Fig. 6-10a. T he manufxturer is RCA. Pin 1 is located immediately counterclockwise from the notch. The part number (CD4024BE) is decoded in Fig. 6-10b. T he prefix CD is RCA’s code for CMOS digital. The s u f i E is RCA’s code for a plastic dual-in-line package. The generic 4024B is the core number. The 40 identifies this as part of the 4000 series of CMOS ICs. T he 2 4 identifies the function of the IC as a 7-stage binary counter. The B stands for series B o r buffered CMOS. CD 4024B Manufacturer’s code for CMOS digital Manufacturer’s code for plastic DIP I 1 (a) M arkings on a typical CMOS IC E F unction of device. 7-s t age binary count er ( h ) Decoding a CMOS IC p art number Fig. 6-10 T he 4000 series of CMOS ICs f eatures a wide voltage supply range from 3 t o 15 V. T he ICs also have high noise immunity and very low power consumption (10 nW is typical). Many 4000 series devices can drive two low-power T TLs o r one low-power Schottlcy TTL IC. The 4000 series suffers in the area of speed. Propagation delays may range from 20 t o 300 ns depending on the device, temperature, and supply voltage. Static electricity can also be a problem with CMOS ICs. Unfortunately, the power consumption of CMOS devices does increase somewhat as the frequency of operation increases. The 74COO series of CMOS digital ICs features functions and pin outs compatible with the industry standard 7400 T TL series. This helps designers alrea.dy familiar with the 7400 series. The 74COO family has the same characteristics as the 4000 series. A typical 74C00 series IC is shown in Fig. 6-1 1 . T he logo indicates that the manufacturer is National Semiconductor. Pin 1 is located by using a dot, co!or band, or notch. The IC has both 4000 series and 74COO series part numbers. The 74COO series part number is MM74C192N. T he prefix M M 116 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 Fig. 6-11 A typical 74COO CMOS IC is the manufacturer’s code for MOS monolithic. The suffix N is National Semiconductor’s code for a plastic DIP IC. 74C192 is the generic part number. The 74C indicates that the IC is part of the 74COO series of CMOS ICs. The 192 defines the function of the IC, which is a synchronous 4-bit up/down decade counter. This IC can also substitute in the 4000 series family. CD40192BCD is the 4000 series part number. The 74HC00 series of high-speed CMOS digital ICs is an improved version of the 4000 and 74COO series. The propagation delays have been improved to attain bipolar (74LS) speed. A typical propagation delay of a 74HC00 series gate might be from 8 t o 12 ns. The normal CMOS advantages have been retained but with improved output drive capabilities of up to 4 mA for good fan-out. Some 74HC00 series ICs have a fan-out of 10 LS-TTL loads. The 74HC00 series reproduces the most popular 7400 and 4000 series functions. A 2- to 6-V power supply operating range was chosen for the 74COO series. A subfamily called the 74HCT00 series is used for interfacing from TTL to the 74HC00 series. Typical markings on a 74HC00 series high-speed CMOS IC a re reproduced in Fig. 6-12. Pin 1 is located next to the dot. The manufacturer is National Semiconductor Corporation. Two part numbers appear on the IC; each has the same core number of 74HC32N. The prefix MM is used by National Semiconductor to mean MOS monolithic, and the prefix MC is used by Motorola. The N suffix means a DIP IC. The 74HC means the IC is from the high-speed CMOS family. The 32 describes the function of the IC (quad 2-input OR gate). Fig. 6-12 Typical markings o n a 74HC00 s eries high-speed CMOS IC T he CMOS technology may be most suitable for large-scale and very-large-scale integrations instead of SSI/MSI ICs. Because of simple internal circuitry and low power consumption, many elements can be squeezed onto a very tiny area of t he silicon chip. Some LSI and VLSI ICs that are available in CMOS are microprocessors, memory devices (RAMS, PROMS), microcontrollers, clocks, modems, filters, coders-decoders, and tone generators for telecommunications, analog-to-digital (A/D) and digital-to-analog (D/A) converters, LCD display decoders/drivers, UARTS for serial data transmission, and calculator chips. CHAP. 61 “ TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING 117 Manufacturers suggest that, when CMOS ICs are being worked with, damage from static discharge and transient voltages can be prevented by: 1. Storing CMOS ICs in special conductive foam 2. Using battery-powered soldering irons when working on CMOS chips or grounding the tips of ac-operated irons 3. Turning power off when removing CMOS ICs or changing connections on a breadboard 4. Ensuring that input signals do not exceed power supply voltages 5. Turning input signals off before turning circuit power off 6 . Connecting all unused input leads t o either positive or GND of the power supply (only unused CMOS outputs may be left unconnected) SOLVED PROBLEMS 6.26 List three SSI/MSI families of CMOS ICs. Solution: Three popular SSI/MSI families of CMOS ICs are the 4000, 74C00, and the 74HC00 series. 6.27 T he (CMOS, TTL) family of digital ICs was first introduced in 1964. Solution: T he T TL family was first introduced in 1964. RCA came out with CMOS in 1968. 6.28 Refer to Fig. 6 -9a. If the input is at GND potential, which MOSFET transistor is turned on (conducting)? Solution: If the inverter input (Fig. 6-9a) is negative (GND), then the P-channel transistor (Q2) will conduct (be turned on). When the input is LOW, the output from the inverter will be HIGH. 6.29 Decode the markings on the IC depicted in Fig. 6-13. T o interpret all the markings, a manufacturer’s logic manual or IC Master would probably be required. Fig. 6-13 Dual-in-line package IC Solution: T he manufacturer is National Semiconductor (logo); the core number is 4001B. CD is t he manufacturer’s code for the CMOS 4000 series of ICs. The suffix N is the manufacturer’s code for a plastic DIP. The suffix C is for a temperature range of -40 to 85°C. The 40 indicates the 4000 series of CMOS ICs. The 01 indicates the function of the IC (quad 2-input NOR gate in this example), and B stands for a buffered CMOS IC. A manufacturer’s CMOS logic data manual or general manual such as the IC Master is needed to find some of this information. 118 6.30 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 List several advantages of CMOS ICs over TTL devices. Solution: The advantages of CMOS ICs over T TLs a re lower power consumption, better noise immunity, lower noise generation, and the ability to operate on an inexpensive, nonregulated power supply. 6.3 1 List some disadvantages of CMOS ICs compared with TTLs. Solution: The disadvantages of CMOS ICs compared with TTLs a re poorer speed characteristics, unwanted sensitivity to static discharges and transient voltages, and lower output current drive capabilities. 6.32 Unused CMOS inputs (may, may not) be left disconnected. Solution: Unused CMOS inputs may not be left disconnected. 6.33 When (CMOS, TTL) chips are being worked on, battery-operated soldering irons are recommended to protect the circuitry. Solution: When CMOS chips are being worked on, battcry-operated soldering irons are used to protect the circuits from possible static discharges or transient voltages. 6.34 (CMOS, TTL) family has better noise immunity. T he Solution: T he CMOS family has better noise immunity than T TL ICs. 6.35 T he (4000, 74HC00) series of CMOS ICs has lower propagation delays. Solution: The 74HC00 series of CMOS ICs has lower propagation delays and can therefore be used at high frequencies. 6-5 INTERFACING TTL AND CMOS ICs Interfacing is the method of connecting two electronic devices such as logic gates. Manufacturers guarantee that, within a family of logic circuits, one gate will drive another. As an example, the two TTL gates shown in Fig. 6 -14a a re simply connected together with no extra parts required and no problems. A second example of two CMOS gates interfaced is illustrated in Fig. 6-14b. In both examples the manufacturer has taken great care to make sure the devices would interface easily and properly. TTL d river T TL CMOS driver CMOS load 74C04 ( a ) Interfacing two ( h ) Interfacing two CMOS gates TTL gates Fig. 6-14 Regular TTL i nput CMoS CMOS - output GND 7 ( a) Standard TTL-to-CMOS interfacing using pull-up resistor f& f. $ +5 v 2 .2 k&2 i nput Low-power (LS)TTL CMOS -ITL GND - Cutput o MOS + ( h ) Low-power Schottky TTL-to-CMOS interfacing using a pull-up resistor +5 v 1 Any CMOS input Low-power TTL output t (c) CMOS-to-low-power Schottky TTL interfacing input M c o s s uffer (4049 > A b n G ND y output TTL 5 ( d ) C MOS-to-standard TTL interfacing using a CMOS buffer IC +5 Input any TI'L o r NMOS v Any CMOS output HTC 74HCT34 G ND GND ( e ) TTL-to-CMOS interfacing using a 74HCTOO series IC Fig. 6-15 I nterfacing T TL a n d CMOS w hen both devices o p er at e on a c ommon D igital Electronics, 3d e d., M cGruw-Hill, N ew Y ork, 1 990) 119 + 5-Vs upply (Roger L. Tokheim, 120 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 What about interfacing families of ICs such as TTL and CMOS? CMOS and TTL logic levels (voltages) are defined differently. Refer to Fig. 6-1 f or details on the definition of LOW and HIGH logic levels of both TTL and CMOS ICs. Because of the differences in voltage levels, CMOS and TTL ICs usually cannot simply be connected directly together as within a family. Current requirements for CMOS and TTL ICs also are different. Therefore, TTL and CMOS ICs usually cannot be connected directly. Special simple interface techniques will be outlined. Interfacing a CMOS with a TTL IC is quite easy if both devices operate on a common + 5-V power supply. Figure 6-15 shows five examples of TTL-to-CMOS and CMOS-to-TTL interfacing. Figure 6-15a shows the use of a 1 - k R pull-up resistor for interfacing standard TTL with CMOS ICs. Figure 6 -191 shows the use of a 2.2-kR pull-up resistor for interfacing low-power TTL ICs with CMOS ICs. CMOS-to-TTL interfacing is even easier. Figure 6-15c shows both CMOS and low-power TTL ICs sharing the same + 5-V power supply. A direct connection between a CMOS output and any one low-power TTL input can be made. Note that the CMOS gate can drive only one low-power T TL input. The exception would be 74HC00 series CMOS, which can drive up to 10 low-power TTL inputs. +10 v 4t +5 v 10 kS2 voltage) A ny TTLinput .. - 2 N3904 ( a) TTL-to-CMOS interfacing using a transistor +10 v + 5, v Any TTL input 4 ( b) TTL-to-CMOS interfacing using an TTL open-collector buffer IC +10 v CMOS +5,v . T TL output I (c) CMOS-to-TTL interfacing using a CMOS buffer IC Fig. 6-16 Interfacing TTL and CMOS devices when each device uses a different power supply voltage ( Roger L . Tokheim, Digital Electronics, 3d e d., M cCraw-Hill, N ew York, 1990) TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING C H A P . 61 121 For more driving power, Fig. 6-15d shows the use of a special 4049 CMOS buffer between the CMOS and TTL units. The CMOS buffer can drive up to two standard TTL inputs. A noninverting buffer which is similar to the unit shown in Fig. 6-15d is the 4050 CMOS IC. The problem of voltage incompatibility from TTL (or NMOS) to CMOS can be solved using a pull-up resistor as in Fig. 6-15a. A second method of solving this interface problem is shown in Fig. 6-15e. T he 74HCT00 series of CMOS ICs is designed as an interface element between TTL (or NMOS) and CMOS. A 74HCT34 noninverting IC is used as the interface element between TTL and CMOS ICs in Fig. 6-15e. T he 74HCT00 series of CMOS ICs is used for interfacing between LSI NMOS devices and CMOS. The NMOS output characteristics are almost the same as for low-power Schottky TTL ICs. Interfacing a CMOS device with a TTL device requires some additional components when each operates on a difierent voltage power supply. Figure 6-16 shows three examples of TTL-to-CMOS and CMOS-to-TTL interfacing. Figure 6-16a shows the TTL inverter driving a general-purpose NPN transistor. The transistor and associated resistors translate the lower-voltage ITTL o utputs to the high-voltage inputs needed to operate the CMOS inverter. The CMOS output has a voltage swing from GND to +10 V. Figure 6-16b shows an open-collector TTL buffer and a 10-kR pull-up resistor being used to translate from the lower TTL to the higher CMOS voltages. The 7406 and 7416 ITTL ICs are two +5 v +5 v CMOS input Light = LOW ( a) ( b) LED lights when output is LOW LED lights when output is HIGH + I0 v - +15 v +1ov-+15v \ \ input c M t = H I G H o 2vDD w f@1k~ s 1 kS2 (c) L ED lights when output is HIGH +5 v - +15 v s: , Light = LOW CMOS o utput ( d ) LED lights when output is LOW +5 v-+15 v Light = LOW (e) CMOS inverting buffer-to-LED interfacing (f) CMOS noninverting buffer-to-LED interfacing Fig. 6-17 C MOS-to-LED interfacing ( Roger L . Tokheim, D igital Electronics, 3d e d., McGruw-Hill, New York, 1990 ) 122 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 inverting, open-collector buffers. The 7407 and 7417 T TL ICs are similar noninverting, open-collector buffers which can also be used in the circuit in Fig. 6-16b. Interfacing a higher-voltage CMOS inverter to a lower-voltage TTL inverter is illustrated in Fig. 6-16c. T he 4049 buffer is used between the higher-voltage CMOS inverter and the lower-voltage TTL IC. Note that the CMOS buffer is powered by the lower-voltage ( +5-V) power supply shown in Fig. 6-16c. Digital circuits can also drive devices other than logic gates. Interfacing CMOS devices with simple LED indicator lamps is easy. Figure 6-17 shows six examples of CMOS ICs driving LED indicators. Figure 6-17a and b shows the CMOS supply voltage at + 5 V. At this low voltage, no limiting resistors are needed in series with the LEDs. In Fig. 6-17a, when the output of the CMOS inverter goes HIGH, the LED output indicator lights. The opposite is true i n Fig. 6-17b; when the CMOS output goes LOW, the LED indicator lights. Figure 6-17c and d shows the CMOS ICs being operated on a higher supply voltage ( + 10 to + 15 V). Because of t he higher voltage, a 1 -kR limiting resistor is placed in series with the LED output indicator lights. When the output of t he CMOS inverter shown in Fig. 6-17c goes HIGH, the LED output indicator lights. In Fig. 6-17d, however, the LED indicator is shown activated by a LOW at the CMOS output. Figure 6-17e and f shows CMOS buffers being used to drive LED indicators. The circuits may operate on voltages from + 5 t o + 15 V. Figure 6-17e shows the use of a n inverting CMOS buffer (like the 4049 IC), and Fig. 6-17.f uses the noninverting buffer (like the 4050 IC). In both cases, a 1 -kfl limiting resistor must be used in series with the LED output indicator. Several simple circuits that interface a TTL with one or two LED indicators are illustrated in Fig. 6-18. T TL inverters are shown driving the LEDs directly in Fig. 6-18a, b, and c. T he LED shown +5 po. . ( a ) L ED lights when output H IGH & +5 G reen T TL input v 680 TTL input v output ( h ) L E D lights when output L O W +ilV LOW 1 O utput 9 % HIGH ( c) H IGH a nd L OW LED indicators ( d ) T’TL to LED interfacing using a driver transistor Fig. 6-18 TTL-to-LED i nterfacing CHAP. 61 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING 123 in Fig. 6-18a lights when the inverter’s output is HIGH, but the LED shown in Fig. 6-18b lights when the inverter’s output is LOW. These ideas are combined to form the circuit shown in Fig. 6-18c. When the red LED lights, the output of t he inverter is HIGH, but when the output of the inverter goes LOW, the green LED will light. The circuit shown in Fig. 6-18c has an additional feature. If the output of the inverter were between HIGH and LOW (in the undefined region), both LEDs would light. This circuit therefore becomes a simple logic indicator for checking logic levels at the outputs of logic circuits. Figure 6-18d shows the use of a driver transistor to turn the LED on and off. When the output of t he TTL inverter goes LOW, the transistor is turned off and the LED does not light. When the inverter output goes HIGH, the transistor conducts and causes the LED to light. This circuit reduces the output drive current from the TTL inverter. SOLVED PROBLEMS 6.36 What is interfacing? Solution: Interfacing is the method used to interconnect two separate electronic devices in such a way that their output and input voltages and currents are compatible. 6.37 Show the interfacing of two TTL gates (an O R gate driving an AND gate). Solution: See Fig. 6-19. Note that, within a family of logic ICs, a direct connection can usually be made between the output of one gate and the input of the next. Input O utput Fig. 6-19 Solution to Prob,.6 .37 6.38 Show the interfacing of a CMOS NAND gate driving a low-power Schottky TTL OR gate. Use a + 5-V power supply. Solution: See Fig. 6-20. By using Fig. 6-1% as a guide, it was determined that the output of the CMOS gate can drive one LS-TTL load. I nput output 7 Fig. 6-20 Solution to Prob. 6.38 124 6.39 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 Show the interfacing of a standard TTL OR gate driving a CMOS inverter. Use a + 5-V power supply. Solution: See Fig. 6-21. By using Fig. 6-150 as a guide, it was determined that a l-kn pull-up resistor was needed to help pull the TTL output to a HIGH that was positive enough to have the CMOS input accept i t as a logical 1. +5 v 4 Fig. 6-21 Solution to Prob. 6.39 6.40 Show the interfacing of a s tandard TTL A N D gate (using + 5-V supply) driving a CMOS inverter (using a + 10-V supply). Solution: A n interface circuit using a driver transistor is shown in Fig. 6-22. An open-collector TI'L buffer and pull-up resistor could also be used as in the circuit shown in Fig. 6-16b. +10 v +5 v vcc o utput GND . A Fig. 6-22 O ne solution to Prob. 6.40 6.41 Show a TTL N AND gate driving an LED output indicator so t he LED goes on when the output of t he N AND gate goes HIGH. Solution: See Fig. 6-23. When the output of the NAND gate goes HIGH, the LED is forward-biased, current flows, and the LED lights. CHAP. 61 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING 125 output indicator HIGH + Fig. 6-23 Solution to Prob. 6.41 6.42 Refer to Fig. 6 -18c. If the output of the inverter drops near ground potential, the (HIGH, LOW) logic level. (green, red) LED lights to indicate a Solution: W hen the o utput of t he inverter shown in Fig. 6-18c is near GND o r LOW, t he green LED lights. 6.43 Show the interfacing for a CMOS NAND gate directly driving an LED so t he indicator lights when the gate output is HIGH. Use a + 10-V power supply. Solution: See Fig. 6-24. +10 v output 1 kS2 Fig. 6-24 Solution to Prob. 6.43 6-6 INTERFACING 'ITL AND CMOS WITH SWITCHES A common method of entering information into a digital system is by way of switches (or keyboards). This section details several methods of interfacing a switch to e ither TTL or CMOS ICs. Consider the simple switch interface circuit drawn in Fig. 6 -25a. When the switch is open (not pressed), the input to the TTL inverter is connected directly to the positive of the power supply through the 1 0-kfl pull-up resistor; the switch input is HIGH in Fig. 6-25a when the switch is open. Pressing the normally open switch in Fig. 6 -251 grounds the TTL input, driving it LOW. The circuit in Fig. 6 -25a might be called an a ctive-LOW switch interface because the TTL input goes LOW when the switch is activated. 126 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING +5 ( a ) Simple +5 v [CHAP. 6 v active-LOW switch interface +5 v ( b ) Simple active-HIGH switch interface Fig. 6-25 Switch-to-TTL interfaces An a ctive-HIGH input switch is diagrammed in Fig. 6 -25b. When the switch is activated (pressed), the + 5 V is connected directly to the input of the TTL inverter. When the switch is released (opened), the inverter input is pulled LOW by the 330-52 pull-down resistor. Two simple switch-to-CMOS interface circuits are detailed in Fig. 6-26. An active-LOW input switch is drawn in Fig. 6 -26a. T he l OO-kil pull-up resistor pulls the voltage to + 5 V when the input switch is open. The CMOS inverter input goes LOW when the normally open switch is closed in Fig. 6 -26a. An active-HIGH input switch is shown in Fig. 6 -266. T he CMOS inverter input is LOW (connected through the pull-down resistor) when the switch is open. When the switch is closed (pressed) in Fig. 6 -26b, t he input of the inverter is driven HIGH. Consider the circuit in Fig. 6 -27a. Each press and release of the input switch should cause the counter to increment by 1 . Unfortunately the counter increases by 1, 2 , 3, o r sometimes more. This problem is caused by switch bounce. When a mechanical switch closes or opens, the contacts do not make or break the circuit cleanly, generating several short voltage spikes. This means that several (instead of one) pulses are fed into the clock (CLK) input of t he counter IC on each switch closure. The counting circuit in Fig. 6-27a needs extra circuitry to eliminate the switch bounce problem. Switching debouncing circuitry has been added to the counter circuit in Fig. 6 -27b. T he TTL decade (0 t o 9) counter IC will now count (increment by only 1) on each HIGH-to-LOW cycle of the input switch. The cross-wired N AND gates in the debouncing circuit are sometimes referred to as a latch o r RSJEip-Pop. Flip-flops are covered in greater detail in Chap. 9. Two other general-purpose switch debouncing circuits are diagrammed in Fig. 6-28. T he debouncing circuit in Fig. 6-28a will drive any 4000 series, 74C00 series, or 74HC00 series CMOS or TTL ICs. Another debouncing circuit is drawn in Fig. 6 -28b. This circuit uses open-collector 7403 TTL ICs in CHAP. 61 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING ( a) Simple active-LOW switch interface +5 v +5 v Input output 100 k f l ( b ) Simple active-HIGH switch interface Fig. 6-26 Switch-to-CMOSinterfaces +5 v Decade counter Input ( a) output Switch interfacing with decimal counter causes problems ( b ) Added switch debouncing circuit makes counter work properly Fig. 6-27 127 128 TTL AND C MOS ICs: CHARACTERISTICS AND I NTERFACING +5 [CHAP. 6 v output To 4000 series CMOS or 74HC00 series CMOS or 7400 T TL, ( a ) Using a 74HC00 CMOS NAND gate +5 v Input 1 0 output To 4000 series CMOS or 74HC00 series CMOS or 7400 series TTL ( b) Using a 7403 open-collector T TL gate Fig. 6-28 G eneral-purpose switch debouncing circuits t he latch with the required pull-up resistors at the outputs of each NAND gate. The switch debouncing circuit in Fig. 6-28b will drive 4000 series, 74COO series, or 74HC00 series CMOS or TTL ICS. SOLVED PROBLEMS 6.44 R efer to Fig. 6-25a. Component S , is considered an activebecause closing the switch causes the input of t he inverter to go (HIGH, LOW) input switch (HIGH, LOW). Solution: I n Fig. 6 .25a, S, is an active-LOW input switch because closing S,causes the input of t he inverter to go LOW. 6.45 R efer to Fig. 6-2%. T he 33042 resistor is called a pull(down, up) resistor as it holds the input of t he inverter (HIGH, LOW) when the input switch is open (not pressed). Solution: In Fig. 6 -25b t he resistor is called a pull-down resistor as it holds the input of t he inverter LOW when the input switch is open. CHAP. 61 6.46 ? TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING 129 Refer to Fig. 6 -27(a). T he counter IC does not accurately count the number of times the input switch is pressed because of a problem called switch (bounce, hysteresis). Solution: In Fig. 6 -27(a),the counter does not accurately count the number of times the input switch is pressed because of a problem called switch bounce. 6.47 Switch debouncing circuits are typically (latches, multiplexers). Solution: Switch debouncing circuits are typically latches. 6.48 Refer to Fig. 6 -28b. T he 7403 TTL NAND gates have outputs which require pull-up resistors at the gate outputs. (open-collector, totem pole) Solution: The 7403 TTL NAND gates have open-collector outputs which require pull-up resistors at the gate outputs. 6-7 INTEKFACING TTL/CMOS WITH SIMPLE OUTPUT DEVICES T he task of many digital systems is to control simple output devices that may have very different voltage and current characteristics. This section explores simple interface techniques with logic elements driving buzzers, relays, electric motors, and solenoids. Most logic families do not have the current capabilities to drive output devices directly. Using a logic element to turn on a transistor is a common interface technique. Consider the circuit in Fig. 6-29. This circuit uses the N PN transistor as a switch. When the output of the inverter goes LOW, t he voltage between the base ( B ) and emitter ( E ) of the bipolar transistor is n ear 0. This turns the transistor off (very high resistance between E and C terminals), and the buzzer does not sound. When the output of the inverter goes HIGH, the positive voltage on the base ( B ) of the transistor turns on the transistor (resistance between E and C terminals becomes very low), allowing current to flow through to the buzzer (buzzer sounds). The diode protects against transient voltages (voltage spikes that may be produced within the buzzer). Notice that the interface circuit will work with either TTL or CMOS logic elements. RJ A +5 v buzzer Output Input Fig. 6-29 T TL or CMOS interfaced with buzzer using a transistor driver 130 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 A relay is an excellent means of isolating a logic element from a high-voltage or high-current circuit. Figure 6-30 illustrates how a logic element could be used with a relay to control an electric motor or solenoid. +s v TTL or Input 2N3904 - + ( a ) Interfacing TTL or CMOS with an electric motor +s v -I A 2N3904 Input - - Solenoid ( b ) Interfacing 'ITL or CMOS with a solenoid Fig. 6-30 Interfacing using a relay Consider the interface circuit in Fig. 6 -30a. T he same NPN transistor driver employed previously is used to snap the relay contacts closed and open. When the output of the inverter is LOW, the transistor is turned off and no current flows through the coil of the relay. The spring-loaded normally closed (NC) relay contacts are held closed as shown in the schematic in Fig. 6 -30a. When the output of t he inverter goes HIGH, t he transistor turns on (conducts) and current flows through the coil of the relay. The magnetic force from the energized relay coil attracts the armature (moving part of relay), and the normally open (NO) contacts close. The N O relay contacts function as a simple mechanical switch which turns on the higher-voltage electric motor. The c lamp diode across the relay coil prevents voltage spikes which might be induced in the system by the relay coil. Notice in Fig. 6 -30a that either TTL o r CMOS logic circuits may be interfaced in this fashion. Also n ote the excellent isolation (no electric connection) between the logic elements and the higher-voltage/current motor circuit. A solenoid is an electrical device that can produce linear motion. The circuit in Fig. 6 -30b shows how the output of a TTL o r CMOS logic gate can be used to control the higher currents and voltages 131 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING CHAP. 61 in the solenoid circuit. Once again the driver transistor is turned on and off by the output of the logic gate. The transistor controls the current through the relay coil. The magnetic force from the relay coil snaps the N O contacts closed when energized. Closing the N O relay contacts completes the higher-voltage circuit energizing the solenoid coil. The solenoid coil causes the core of t he solenoid to produce a linear motion. SOLVED PROBLEMS 6.49 Refer to Fig. 6-29. T he buzzer will sound only when the output of the inverter goes (HIGH, LOW) and the transistor (conducts, does not conduct) current. Solution: The buzzer in Fig. 6-29 will sound when the output of the inverter goes HIGH and the transistor conducts current. 6.50 Refer to Fig. 6-29. If the output of t he inverter goes LOW, the transistor (is silent, sounds). conduct current and the buzzer (will, will not) Solution: I f the output of the inverter in Fig. 6-29 goes LOW, the transistor will not conduct and the buzzer is silent. 6.51 What is the function of the relay in the circuits in Fig. 6-30? Solution: The relay serves to isolate the logic circuitry from the higher-voltage and higher-current motor/solenoid circuits i n Fig. 6-30. 6.52 Refer to Fig. 6 -30a. T he electric motor operates when the output of the logic element (inverter) goes (HIGH, LOW). Solution: T he motor in Fig. 6-30a operates when the output of the inverter goes HIGH. 6.53 Refer to Fig. 6 -30b. What is the purpose of the diode placed in parallel with the relay coil? Solution: The diode eliminates harmful voltage spikes that may be generated by the relay coil. It is sometimes called a clamp diode. 6.54 R efer to Fig. 6-29. T he transistor acts most like an (amplifier, switch) in this circuit. Solution: T he transistor acts like a switch in this circuit. 6-8 D / A AND A / D CONVERSION Digital systems must often be interfaced with analog equipment. To review, a digital signal is one that has only two discrete voltage levels. A n analog signal is o ne that varies continuously from a minimum to a maximum voltage or current. Figure 6-31 illustrates a typical situation in which the digital processing unit or system has analog inputs and outputs. The input on the left is a continuous voltage ranging from 0 t o 5 V. T he special encoder, called an analog-to-digital converter (A/D 132 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING 1 I A /D converter / Analog input / Digital system [CHAP. 6 D/A D /A converter h a l o g output I - Fig. 6-31 Using A /D and D /A converters in an electronic system converter), translates the analog input into digital information. On t he output side of the digital system shown in Fig. 6-31, a special decoder translates from digital information to an analog voltage. This decoder is called a digital-to-analog converter ( D/A converter). The task of a D / A converter is to transform a digital input into an analog output. Figure 6 -32a illustrates the function of the D /A converter. A binary number is entered at the inputs on the left Binary inputs (U) Block diagram Binary input Analog output R ow 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (b) T ruth table Fig. 6-32 D /A converter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CHAP. 61 TTL A ND CMOS ICs: CHARACTERISTICS AND INTERFACING 133 with a corresponding output voltage at the right. As with other tasks in electronics, it is well to define exactly the inputs and expected outputs from the system. The truth table in Fig. 6 -32b details one set of possible inputs and outputs for the D /A converter. Consider the truth table in Fig. 6 -32b for the D /A converter. If each of the inputs is LOW, the output voltage (V,,,) is 0 V as defined in row 1 of the table. Row 2 shows just the 1s input ( A )being activated by a HIGH. With the input as LLLH ( OOOl), t he output from the D /A converter is 1 V. Row 3 shows only input B activated (0010). This produces a 2-V o utput. Row 5 shows only input C activated ( 0100). This yields a 4 -V o utput. Row 9 shows only input D ( 1000) activated; this produces an 8 -V o utput from the D /A converter. Note that the inputs ( D ,C, B , A ) a re weighted so t hat a HIGH at input D generates an 8-V o utput and a HIGH at input A produces only a 1-V o utput. The relative weighting of each input is given as 8 for input D , 4 for input C , 2 for input B , and 1 for input A in Fig. 6 -32a. A simple D /A converter consists of two functional parts. Figure 6 -32a shows a block diagram of a D /A converter. The converter is divided into a resistor network and a s umming amplijier. T he resistor network weights the I s, 2s, 4s, and 8s inputs properly, and the summing amplifier scales t he output voltage according to the truth table. An op a mp, or operationa1 amplifier, is commonly used as the summing amplifier. A few of the important specifications of commercial D /A converters are resolution, linearity, settling time, power dissipation, type of input (binary, complemented binary, and sign and magnitude), technology (TTL, CMOS, or ECL), and special features. One manual lists more than a hundred different D /A converter ICs having resolutions from 4 t o 18 bits. Consider the simplified block diagram of a commercial A /D converter reproduced in Fig. 6 -33a. This is the ADC0804 8-bit microprocessor-compatible A / D converter. T he control lines to the T op View (b) Fig. 6-33 ADC0804 8-bit A / D converter IC 1 34 TTL A ND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 ADC0804 A /D converter direct the A /D converter to first sample and digitise t he analog voltage at the input. Second, the control lines direct the A /D converter to generate an 8-bit binary output. The 8-bit output will be directly proportional to the analog input voltage. If the input voltage is 5 V, t he binary output will be 11111111. But if the input voltage were 0 V, t he binary output would read 00000000. A pin diagram of t he ADC0804 A/D converter IC is shown i n Fig. 6-33b. T he ADC0804 I C is a CMOS 8-bit successive approximation A /D converter which is designed to operate with the 8080A microprocessor without extra interfacing. The ADC0804 IC’s conversion time is under 100 ps, and all inputs and outputs are TTL compatible. It operates on a 5-V power supply, and it can handle a f ull range 0- t o 5-V analog input between pins 6 and 7. T he ADC0804 IC has an on-chip clock generator which needs only an external resistor and capacitor (see Fig. 6-34). A simple lab setup using the ADC0804 A/D converter is shown in Fig. 6 -34. T he analog input voltage is developed across the wiper and ground of the 10-kiZ potentiometer. The resolution of the A /D converter is & ( 28 - 1 ) of the full-scale analog voltage (5 V in this example). For each increase X 5 V = 0.02 V), t he binary output increments by 1. Therefore, if t he analog input of 0.02 V equals 0.1 V, t he binary output will be 00000101 (0.1 V/0.02 V = 5, and decimal 5 = 00000101 in binary). (A +5 v +5 I b l9 converter C LR I Binary output indicators v D B, DB, l7 I I Fig. 6-34 Wiring a test circuit with the ADC0804 8-bit A / D converter IC input to the ADC0804 I C shown in Fig. 6 -34 T he H-to-L transition of the clock pulse at the starts the conversion process. The binary output appears about 100 ps later at the indicators on the right. This A /D converter can make more than 5000 conversions per second. The outputs are three-state buffered, so they can be connected directly to the data bus of a microprocessor-based system. The A DC0804 A /D coriverter has an interrupt output ( INTR, see pin 5 , Fig. 6 -33b) which signals the microprocessor system when the current analog-to-digital conversion is finished. Interrupts are needed in microprocessor systems when interfacing very “slow” asynchronous devices such as an A /D converter to “very fast” synchronous devices such as a microprocessor. Important specifications of commercial A /D converters are resolution, linearity, conversion time, power dissipation, type of output (binary, decimal, complemented binary, sign and magnitude, parallel, serial), and special features. One manual lists hundreds of different A /D converter ICs with resolutions between 8 a nd 20 bits. A /D converters with decimal outputs (like digital voltmeter ICs) are available with resolutions of 3 and 4; digits. ; CHAP. 61 135 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING SOLVED PROBLEMS 6.55 Explain the fundamental difference between A /D a nd D /A converters. Solution: An A / D converter changes an analog voltage proportionately into a digital output (usually binary). A D/A Converter transforms a digital input (usually binary) proportionately into an analog output voltage. 6.56 A simple D /A c onverter consists of two functional parts, a amplifier. network and a Solution: A simple D/A converter consists of two functional parts, a resistor network and a summing amplifier. 6.57 R efer to Fig. 6-326. List the output voltage (V,,,) f or each input combination shown in Fig. 6-35. converter i k j i h g f e d c b vo -?w a Fig. 6-35 D /A converter pulse-train problem Solution: T he analog outputs (V,,,) from the D/A converter i n Fi,g. 6-35 are as follows: pulse a = 2 V pulse d = 13 V pulse g = 0 V pulse j = 11 V pulse b = 9 V pulse e = 1 V pulse h = 15 V pulse k = 3 V pulse c' = 6 V pulse f = 8 V pulse i = 5 V pulse 1 = 7 V 6.58 R efer to Fig. 6-32a. The summing amplifier in a D /A c onverter is commonly a(n) (multiplexer, op amp). Solution: An op amp (operational amplifier) is typically used as the summing amplifier in a D/A converter as in Fig. 6 -32a. 6.59 T he ADC0804 IC is an A /D c onverter with a (parallel, serial) output. Solution: The ADC0804 IC is an A/D converter with parallel three-state outputs that may be connected directly to a microprocessor data bus. 136 6.60 TTL AND CMOS ICs: CHARACTERISTICS AND INTERFACING T he ADC0804 IC has a resolution of [CHAP. 6 (4,8,12) bits. Solution: T he ADC0804 A/D converter has a resolution of 8 bits, or 1 of 255 (28 - 1 = 255). 6.61 R efer to Fig. 6-34. If t he input voltage is 2 V, t he binary output from the A/D converter should be binary . Solution: T he calculation is as follows: 2v - 100 0.02 v -- decimal 100 = 01100100 in binary The binary output from the A/D converter shown in Fig. 6-34 is 01100100 when the input voltage is 2 V. 66 .2 T he ADC0804 IC (is, is not) compatible with microprocessor-based systems. Solution: The ADC0804 A/D converter IC is compatible with microprocessor-based systems. It has buffered three-state outputs, microprocessor-compatible control inputs, and an interrupt output. 6.63 T he ADC0804 A /D converter has a conversion time of about 100 seconds. (micro, nano) Solution: T he ADC0804 IC has a conversion time of less than 100 ps (microseconds). 6.64 T he ADC0804 A/D converter operates microprocessor. (at the same speed as, slower than) a Solution: A/D converters operate slower than microprocessors and therefore use an interrupt to signal the system when they are ready to send valid data. Supplementary Problems 6.65 A group of compatible digital ICs that can be connected directly together to form a digital system is said . Ans. family to form a 6.66 Digital ICs from the ( a ) and Ans. ( a ) T TL (b)MOS 6.67 An IC containing from 12 t o 99 equivalent gates is defined as an 6.68 R efer to Fig. 6 -la. A 2.1-V input to the TTL inverter is a logical 6.69 R efer to Fig. 6 - l a . A 2.1-V o utput from the TT'L inverter is a logical output. Register to View Answer2.1-V o utput from the TTL inverter is defined as a forbidden output caused by a defective IC or too heavy a load at the output. ( 6) families are the most popular. (LSI, MSI, SSI). ( 0,l) input. A m. MSI Ans. 1 m A ND CMOS ICS:HARACTERISTICS C CHAP. 6 1 6.70 137 A ND INERFACING What is the propagation delay of a digital I C? Thc time i t takcs for thc output to changc aftcr thc input has changcd logic statcs. Thc propagation delay for modem digital 1Cs m ay ranpc from a b u t 1.5 ns to about 125 ns. Am. 6.71 What is the fan-out of a digital IC? Thc number of parallcl loads that can be drivcn by a single digital IC output. Am. 6.72 The CMOS digital I family is noted for its C 6.73 Refer to Fig. 6 l h . A I-V input to the CMOS inverter is considered a logical Am. O orLOW 6.74 Which ?TL subfamily is best for low-powerconsumption? 6.75 List thrcc typcs o ITL outputs. f 6.76 7TL logic devices of the gradc I s C . Am. 7 4 0 6.77 Am. (high. low) power consumption. A m. Am. low ( 0.1) input. low-power 7 T L (see Fig. 6-66) totcm polc. opcnallcctor. thrcc-state ( 5 4 0 , 7 4 0 ) scrics arc lcsc expensive and arc considered c ommercial Refer to Fig. 6 36. T he manufacturcr of the I shown i s C ART. National Scmiconductor Corporation (sec logo) . F i i 6-36 Dual-in-linc packagc I C (CMOS. TZ) intcgratcd circuit is shown. T 6.78 Rcfcr to Fig. 6-36. A 6.79 Refer to Fig. 6-36. W hat is thc function of thc I shown? C 68 .0 T he l ettcn CMOS stand for 6.81 T he cquipmcnt. 6.82 T he A m. . Am. A m. ITL quad 2-input SAND (7400 I C) Am. complementary mctal&de semiconductor (CMOS.lTL) families are generally better suited for u sc in portable hattcry-operated Am. CMOS ( 400.7411CO) scrics of CMOS I Cs are better suited for high-speed operation. 74HCOr) (4000.7400) scrics of I s m ight u sc a 10-Vdc power supply. C 6.83 T he 6.84 T he (CMOS.7TL) familics are gcncrally bettcr suited for use when the power source is unregulated. such as a battery source. A m CMOS 6s ICc of thc voltagcs. Am. 6.86 If an I has the marking 74CO8. i t is a C (CMOS.ITL)family are especially scnsitivc CMOS Am. 4ooo to static dischargcs and transient (CMOS. TTZ) device. Am. CMOS 138 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING [CHAP. 6 6.87 Refer to Fig. 6-18c. When the output of the TTL inverter goes to about 3 V, the Ans. red, HIGH LED lights. That indicates a (HIGH, LOW) logic level. 6.88 Refer to Fig. 6-18d. When the output of the TTL inverter goes LOW, the transistor conducting and the LED (does not light, lights). Ans. is not, does not l ight 6.89 Refer to Fig. 6-15d. T he buffer is used for interfacing the CMOS and standard TTL gate because it has (fewer, more) output current drive capabilities than the standard CMOS inverter. Ans. more 6.90 In Fig. 6-16b and c, special in interfacing. Ans. buffers 6.91 Refer to Fig. 6-2%. Component S is considered an active, closing the switch causes the input of the inverter to go 6.92 Refer to Fig. 6-27b. T he NAND gates forming the switch debouncing circuit are wired like a latch or . Ans. R S flip-flop 6.93 Refer to Fig. 6-28b. T he 7403 T TL NAND gates have open-collector outputs which require (pull-down, pull-up) resistors at the gate outputs. Ans. pull-up 6.94 When a mechanical switch closes and opens, the contacts do not make and break the circuit cleanly, . Ans. bounce generating unwanted voltage spikes. This is called switch 6.95 Refer to Fig. 6-29. When the output of the inverter goes HIGH, the transistor (blocks current, Ans. conducts current, sounds conducts current) and the buzzer (is silent, sounds). 6.96 Refer to Fig. 6-30a. T he motor circuit. Ans. relay 6.97 Refer to Fig. 6-30a. When the output of the inverter goes LOW, the transistor (blocks current, conducts current), the (NC, NO) contacts of the relay close, and the electric motor (does not operate, operates). Ans. blocks current, NC, does not operate 6.98 (green, red) (is, is not) (buffers, transistors) are used between TTL and CMOS gates to aid (HIGH, LOW) input switch because (HIGH, LOW). Ans. H IGH, HIGH (diode, relay) isolates the logic circuitry from the higher-voltage electric A special decoder that interfaces a digital system and an analog output is called a(n) D /A converter . A special encoder that interfaces an analog input and a digital system is called a(n) A /D converter . Ans. 6.99 Ans. 6.100 Refer to Fig. 6-32b. A 6-V output from the D/A converter could be generated only by a input. Ans. 0110 6.101 T he abbreviation op amp stands for 6.102 A digital voltmeter is one application of a(n) . Ans. . binary operational amplifier Ans. 6.103 T he resolution of an A/D converter can be given as the number of Ans. ( a ) bits ( b ) resolution A /D converter (a) or as the percent (6) . CHAP. 61 6.104 T he ADC0804 A/D converter has an %bit 6.105 139 T TL AND CMOS ICs: CHARACTERISTICS AND INTERFACING (BCD, binary) output. R efer to Fig. 6-34. If the input voltage is 3 V , the binary output should be Ans. 10010110 (3 V/0.02 V = 150 = 10010110 i n binary) Ans. binary . 6.106 Refer to Fig. 6-34. The 10-kSZ resistor and the 150-pF capacitor are associated with the Ans. clock power supply) of the ADC0804 A/D converter IC. 6.107 T he ADC0804 IC uses the Ans. successive approximation conversion A-to-D conversion technique. (clock, Chapter 7 Code Conversion 7-1 INTRODUCTION Onc application of logic gates in digital systems is a s code conr'errers. Common codes used are binary, BCD (8421), octal, hcxadccimal, and, of course, dccimal. Much of thc "mystcry" surrounding computers and other digital systcms stems from the unfamiliar language of digital circuits. Digital dcviccs can process only 1 and 0 bits. However. it is dificult for humans to understand long strings of 1s and 0s. For that reason, codc convcrtcrs arc ncccssary to convert f rom thc languagc of pcoplc to the language of t he machine. Considcr t he simple block diagram of a hand-held calculator i n Fig. 7-1. The input dcvicc on the left is thc common keyboard. Bctwcen thc kcyboard and thc central processing u nit (CPU) of the calculator is an encoder. This encoder transla'tcs thc dccimal number pressed on thc keyboard into a binary code such as tlic RCD (R4421) a t e . The CPU performs its operation in binary and puts o ut a binary code. T he decoder translatcs thc binary codc from t hc CPU to a spccial c a l c which lights the correct segments on the scvcn-segment display. Thc decodcr thereby translatcs from binary to decimal. The encoder and dccodcr in this system are clectronic code translators. T he encoder can be thought of as translating from thc language of people to t hc languagc o f the machine. T h e decoder does the opposite; it translatcs f rom machine language to human languapc. Ourput Input Decimal Keyboard dicplay Fig. 7-1 Basic block diagram of a calculator 7-2 ENCODING The job of the cncodcr in thc calculator is to translate a decimal input to a BCD (8421) number. A logic diagram, in simplified form, for a decimal-to-RCD encodcr is shown i n F ig 7-2. T hc cncodcr Fig. 7-2 Logic symbol for a dccimal-to-BCD cncodcr 140 CHAP. 71 141 CODE CONVERSION has ten inputs on the left and four outputs on the right. The encoder may have o ne active input, which in turn p roduces a unique output. Decimal input 7 is shown being activated in Fig. 7-2. This results in the BCD output of 0111, as shown on the BCD output indicators at the right. The block diagram for a commercial decimal-to-BCD encoder is shown in Fig. 7-3a. The most unusual features are the small bubbles at the inputs and outputs. The bubbles at the inputs mean that the inputs are activated by logical OS, or LOWs. The bubbles at the outputs mean that the outputs are normally HIGHS, or at logical Is, but when activated, they go LOW, or to logical OS. Four inverters have been added to the circuit to invert the output back to its more usual form. Another unusual feature of the encoder is that there is no zero input. A decimal 0 input will mean a 1111 o utput (at D , C, B , and A ) , which is true when all inputs (1-9) are not connected to anything. When the inputs are not connected, they are said to be f loating. T he 74147 encoder is a TTL device, which means that unconnected inputs will float HIGH. Inputs outputs BCD output indicators 8s 4s 2s Is HHHHHHHHH xxxxxxxxL X X L H H H H H X L H H H H H H L H H H H H H H H H H H H H H H H L H L H L H L H L H ( a) Logic symbol with output indicators X X X L H H H H H H H L L H H L L H X X X X X X L H H IGH logic lebel, L = LOW logic level, X = irrelevant = X X X X L H H H H H H L L L L H H H X X X X X X X L Decimal input X X X X X L H H H L L H H H H H H 1H ( b ) Truth table Fig. 7-3 Commercial TTL 74 147 decimal-to-BCD priority encoder T he encoder diagrammed in Fig. 7-3 is called a 10-line-to-4-line priority encoder by the manufacturer. This TTL device is referred to as a 74147 encoder. A t ruth table for the 74147 encoder is in Fig. 7-3b. The first line on the truth table is for no i nputs. With all inputs floating HIGH, the outputs are HIGH. This is interpreted as a 0000 on the BCD output indicators in Fig. 7 -3a. T he second line of the truth table in Fig. 7-36 shows decimal input 9 being activated by a LOW, or 0. This produces an LHHL at outputs D , C, B , A . T he LHHL is inverted by the four inverters, and the BCD indicators read 1001, which is the BCD indication for a decimal 9. The second line of the truth table in Fig. 7-3b shows inputs 1 through 8 marked with Xs. A n X in the table means irrevelant. A n irrelevant input can be either HIGH or LOW. This encoder has a priority feature, which activates the highest number that has a LOW input. If LOWs were simultaneously placed on inputs 9 and 5, t he output would be 1001 for the decimal 9. The encoder activates the output of the highest-order input number only. The logic diagram for the 74147 encoder, as furnished by Texas Instruments, Inc., is shown in Fig. 7-4. All 30 gates inside the single 74147 TTL IC a re shown. First try activating the decimal 9 input (LOW at input 9). This 0 input is inverted by inverter 1, and a 1 is applied to NOR gates 2 and 3. NOR gates 2 and 3 are thus activated, putting out LOWs. NOR gates 4 and 5 a re deactivated by the presence of OS a t their inputs from the deactivated AND gates 7 through 18. These AND gates (7 through 18) are deactivated by the OS at their bottom inputs produced by NOR gate 6. T he AND gates (7 through 18) make sure that the higher decimal input has priority over small numbers. 142 C ODE CONVERSION [CHAP. 7 4 7- 8 q& p : --4tr- 7 Fig. 7-4 Logic diagram of 74147 decimal-to-BCD priority encoder (Reprinted by permission of Texas Instruments) A n encoder using the CMOS technology also is available. The 74HC147 10- t o 4-Line Priority Encoder is one of many DIP ICs available from National Semiconductor Corporation in its 74HC00 series. SOLVED PROBLEMS 7.1 T he 74147 encoder translates from the octal) code. ~. (decimal, Gray) code into the (BCD, Solution: T he 74147 translates from decimals into the BCD code. 7.2 A t a given time, an encoder may have unique output. (one, many) active input(s) which produceb) a Solution: By definition an encoder will have only one input activated at any given time. I f several inputs appear to be activated by having LOWS, t he highest decimal number will be encoded on a u nit such as the 74147 encoder. 7.3 I n Fig. 7-3a, if input 3 is activated with a will read (four bits). ( HIGH, LOW), the BCD output indicators Solution: A LOW a t input 3 will produce a 0011 at the output indicators. 7.4 143 CODE CONVERSION CHAP. 71 If both inputs 4 and 5 a re activated with LOWS, the output indicators shown in Fig. 7-3a will read (four bits). Solution: T he 74147 encoder gives priority to input 5, producing a 0101 output on the BCD indicators. 7.5 (0, 1) is needed to activate input 1. Refer to Fig. 7-4. A logical Solution: A logical 0 is needed to activate any input on the 74147 encoder. 76 . Assume that only input 1 is activated in the circuit of Fig. 7-4. O utput (activated, dkabled). be LOW because AND gate 18 is ( A , B , C, D ) will Solution: O utput A will be LOW because the AND gate is activated by all 1s at its inputs. 77 . List the outputs at the BCD indicators for each of the eight input pulses shown in Fig. 7-5. (Remember the priority feature, which activates the highest number that has a LOW input.) BCD o utput indicators 8s 4s 2s 1s P Fig. 7-5 Encoder pulse-train problem Solution: The indicators will read the following BCD (8421) outputs: pulse c = 0001 pulse e = 01 11 pulse g = 0011 pulse a = 0000 pulse b = 0111 pulse d = 1001 pulse f = 0101 pulse h = 0000 7-3 DECODING: BCD TO DECIMAL A decoder may be thought of as the opposite of an encoder. To reverse the process described in Sec. 7-2 would produce a decoder that translated from the BCD code to decimals. A block diagram of such a decoder is in Fig. 7-6. T he BCD (8421) code forms the input on the left of the decoder. The 10 o utput lines are shown on the right. Only one output line will be activated at any one time. Indicators (LEDs or lamps) have been attached to the output lines to help show which output is activated. Inputs B and C ( B = 2s place, C = 4s place) are activated in Fig. 7-6. This causes the decimal 6 o utput to be activated, as shown by indicator 6 being lit. If no inputs are activated, the zero output indicator should light. A BCD 0011 input would activate the 3 o utput indicator. 144 CODE CONVERSION Fig. 7-7 Commercial 7442 B CD-to-decimal decoder/driver [CHAP. 7 CHAP. 71 145 C ODE CONVERSION A commercial BCD-to-decimal decoder is shown in Fig. 7-7a. This TTL device is given the number 7442 by the manufacturer. The four BCD inputs on the left of the logic symbol are labeled D , C, B , and A . T he D input is the 8s input, and the A input is the I s input. A logical 1, o r HIGH, will activate an input. On the right in Fig. 7-7a a re 10 outputs from the decoder. The small bubbles attached to the logic symbol indicate that the outputs are active LOW outputs. They normally float HIGH except when activated. For convenience, 10 inverters were added to the circuit to drive the decimal-indicator lights. A n active output will then be inverted to a logical 1 at the output indicators. The truth table for the 7442 decoder is in Fig. 7-7b. T he first line (representing a decimal 0) shows all inputs LOW (U. With an input of LLLL (OOOO), the decimal 0 o utput is activated to a LOW (L) state. The bottom inverter complements this output to a HIGH, which lights decimal output indicator 0. None of the other indicators are lit. Likewise, the f ifth line (representing a decimal 4) shows the BCD input as LHLL (0100). Output 4 is activated to a LOW. The LOW is inverted in Fig. 7-7a, thereby lighting output decimal indicator 4. This decoder then has active HIGH inputs and active LOW outputs. Consider line 11 in Fig. 7-7b. T he input is HLHL (1010), and it would normally stand for a decimal 10. Since the BCD code does not contain that number, this is an inualid input and no output lamps will light (no outputs are activated). Note that the last six lines of the truth table show invalid inputs with no outputs activated. The logic diagram for the 7442 BCD-to-decimal decoder is shown in Fig. 7-8. T he BCD inputs are on the left, and the decimal outputs are on the right. 'The labeling at the inputs is somewhat different from that used before. The A , input is the most significant bit (MSB), or the 8s input. The A , input is the least significant bit (LSB), or the I s input. The outputs are labeled with decimal numbers. The decoder's active LOW outputs are shown with bars over the decimal outputs (9, and so forth). s, Fig. 7-8 Logic diagram of 7442 BCD-to-decimal decoder Assume a BCD input of LLLL (0000) on the decoder shown in Fig. 7-8. Through careful tracing from the four inputs through inverters 12, 14, 16, and 18, four logical I s a re seen to be applied to NAND gate 1, which activates the gate and thus puts out a logical 0. All other NAND gates are 146 [CHAP. 7 C ODE CONVERSION disabled by OS a t some of their inputs. In like manner, each combination of inputs could be verified by analysis of the logic diagram in Fig. 7-8 for the 7442 decoder. All 18 gates shown in Fig. 7-8 are contained inside the single IC referred to as the 7442 decoder. As is customary, the power connections (Vcc and GND) to the IC are not shown in the logic diagram. BCD-to-decimal decoders also are available in CMOS form from several manufacturers. Several representative CMOS ICs are the 4028, 74C42 and 74HC42 BCD-to-decimal decoders. SOLVED PROBLEMS 7.8 R efer to Fig. 7-7. When inputs A , B , and C a re activated by (decimal number) will be active. (OS, Is), output Solution: When inputs A , B , and C are activated by logical I s, output 7 will be active. 7.9 R efer to Fig. 7-7. If inputs are at HHHH ( l l l l ) , which output will be activated? Solution: Input HHHH (1111) is an invalid BCD input according to the truth table, and therefore no outputs will be activated. 7.10 Refer to Fig. 7-7. Decimal output indicator is LHLH (0101). (decimal number) will be lit when the input Solution: A 0101 input activates output 5, and the inverter lights the output 5 indicator. 7.11 Refer to Fig. 7-8. Gate number (1000) to this logic circuit. (decimal number) is activated when the input is HLLL Solution: NAND gate 9 is activated, producing a LOW output at 7.12 8 with an HLLL (1000) input. List the active output for each of the input pulses shown in Fig. 7-9. output 8s I I h g f e d c h U (7442) Fig. 7-9 Decoder pulse-train problem Solution: The active output (output pulse a = 8 pulse b = 3 pulse c = (no active output) = LOW) for each of the inputs shown i n Fig. 7-9 is as follows: pulse d = 9 pulse g = 1 pulse j = (no active output) pulse e = 7 pulse h = 6 pulse f = 0 pulse i = 4 CODE CONVERSION CHAP. 71 147 7 4 DECODING RCD-TO-SEVEN-SEGMENT CODE A common task for a digital circuit is to dccodc f rom machine languagc t o decimal numbers. A common output device uscd to display decimal numbcrs is t hc ser-en-sepnenr d hp/uy. shown in Fig. 7-IOU.The seven scgmcnts arc labclcd w ith standard letters from u through g. T hc first 10 displays. representing decimal digits 0 through 9. are shown on the left side of I:ig. 7-10h. For instance. i f segments h and c o f the scvcn-segment display light. a dccimal 1 appcars. I f segmcnts U . h. and c light. a decimal 7 appears, and so f orth. Seven-segment displays arc' manufacturcd hy using several tcchnologics. Each of thc wvcn scgmcnts may bc a t hin filamcnt which glows. This typc of display is callcd an incundescenr display, and it is similar to a rcgular lamp. Another typc of display is thc gm-dischaqc tube, which opcratcs at a ( a ) Segment dcnrification ( h ) Decimal number with typical display Fig. 7-10 S ewn-scpmcnt display high voltagcs. This u nit gives off an orangc glow. A flrtoreweitr tithe display givcs off a grccnish glow when l it and operates at low voltagcs. Thc newer /iqriid.qsra/ di.vphv ( LCD) creates black numbers on a silvcry background. LCD displays a rc extrcmcly popular on hand-hcld calculators. T he common /i&-etnirring diode ( LED) display givcs off a charactcristic rcddish glow whcn l it. LED displays do come i n several colors o thcr than rcd. Thc LED. LCD. and fluorcsccnt displays a rc c urrcntly thc most popular. but liquid-crystal displays a re uscd i n almost all solar-powcrcd and battcry-opcratcd dcviccs. lkcausc i t is quitc common and easy to use. thc LED typc of scvcn-scgmcnt display will bc covered in grcatcr dctail. Figurc 7-1 l a shows a 5 -V power supply connected to 3 single LED. When i lw thc switch (SWI)s closed. currcnt will f o in the circuit and light t he LED. About 20 mA (milliamperes) of current would flow i n t his circuit, which is thc typical currcnt draw for an LED. Thc 1 30-0 (ohm) rcsistor is placed i n thc circuit to limit thc current to 20 mA. Without the rcsistor, thc LED would bum out. LEDs typically can accept only about 1.7 V a cros their terminals. Being a diode, thc LED is scnsitivc to polarity. The cathodc ( K ) ust bc toward t hc ncgativc (GND) of rhc m p ower supply. 'Ihc anodc ( A ) must hc toward the.positivc of thc powcr supply. A s cvcn-scment LED display is shown i n Fig. 7-111). Each scgmcni ( U through g ) contains an LED, as shown by the scvcn symbols. 'Ihc display shown has all thc anodcs ticd topcthcr and coming out the right sitlc a s a single connection (common anode). The inputs on t hc left go to thc various s c p c n t s o f thc display. To understand how scgmcnts of the display 3rc activatcd and lightcd. considcr thc circuit i n Fig. 7-1 Ic. I f switch h is closed. current will flow from GKD through the limiting rcsistor to t he h scgmcnt LED and o ut thc common anodc connection to t he powcr supply. O nly scgmcnt h will light. Supposc you wantcd the dccimal numhcr 7 to light on the display i n Fig. 7-1 lc. Switchcs a. h . and c would he closed, which would l ight thc LED scgmcnts U, h , and c . The decimal 7 would light on the display. Likewise. i f thc decimal 5 wcrc to hc l it. switches ( I . c. d . f , and R would he closed. Those five switches would ground t hc corrcct scpmcnts. and a dccimal 5 would appear o n thc display. Notc that i t t:ikcs a GND voltagc ( LOW) to activatc thc LED segments on t his display. 1-48 [ CHhP. 7 I Fig. 7 -1 I ('onsidcr the c o ~ i i i ~ i o cioniiiicrcial d ccodcr s liowri i n 1:ig. 7- 13u. This T TI, dcvicc is called ;i r 7447A H~:l)-to-scvcn-scpmcnt dccodcr/drivcr by the ni;iiiuf;ictiircr. The input is ;I 4-bit IX'I) number shown on the Icft ( inputs A . H. ('. a nd / I). T hc l3C'I) numbcr is d ccodcd t o f orm a seven-scgnicnt code t h a t w ill light t he ;tppropriatc scgniciits on the 1,t;D display hhown i n 1:ig. 7-1 1 h . 'Three extra inpiits i I l S < ) a rc shoum o n the logic symbol. The lamp t est input will t urn all segments 0 3 to sec if all o f them operate. F.sscnti;illy, t hc hlanking inputs t u r n a ll the wgmcnts 0 I:F when activated. The Iiinlp t est iInd h l;inking input5 ;ire activ;itctl b y l .OW\. ;is s h o w n b y t lic s niall bubbles a t the inputs. T h c BCI) inputs arc activated by lopicxl Is. 'I'hc 7447A dccodcr h a s active LOW outputs, ;IS s hown by the sniall bubbles a t the o utputs ( ( I through I:) of the logic symbol i n Fig. i - l 3 ( i . T hc o peration o f the 7-447A d ccodcr is dctailcd i n t lic t rutli table furnished by I'cxiis l nstrunicnts and shown i n F3g. 7-12h. (:orisider line 1 on thc t r u t h tithlc. To light the dccimal 0 on the display. the UCL) inputs ( D . C'. U . and A 1 must be a t LLLL. 'l'his w ill activate or t u r n O N segments ( 1, h . c . t l . P . a nd f t o fomi 111cdccini;il ( 1 0 1 1 t lic s c\'cn-xgniciit d i q h y . Kotc the invalid 13('I) inputs (decimals 10. 1 1. 1 2, 13. 14. i llid 15). They arc n ot I3C1) numbers. h owever. they d o p cncratc ;I unique output, ;is shown i n t he truth tahlc i n Fig. 7-12h. ('onsidcr t he decimal I line. With inputs o f I tLItL. t hc output 0 column say\ that o utputs t l , v , and ,g a rc ;ictiviitctl. T hi5 f orni> A sni:ill c. 'I'hc unique outputs o f this dccodcr f or decimals 10 through 15 ;ire shown ;is they would iippcar on the seven-scgnicnt display on t he right sidc o f Fig. 7-10b. N ote that ;I decimal 15 will rcsult i n ;t t h i i i k display ( ;ill segments OFF). A practic;il tlccotlcr > >\tcni is 5 liowri i n Ia'ig. 7-13. A t3CD numhcr is c iitcrcd i it t he Icft i n t o t he 7 U7A d ccodcr. The dccodcr activates the p roper outputs a nd alto\vs the correct dccimiil number t o a ppcar on t h c displa). N ote t h a t t he displny is a common-anode seven-segment 1.F.I) display. CHAP. 71 149 CODE CONVERSION f-b number ~C c- D Inputs Lamp-test Blanking Blanking d- LT o utput > 7-segment code e- B I/RBO 4 RBI (U) (7447) g Logic symbol H = H IGH level, L = LOW level, X = irrelevant Notes: 1. The blanking input ( B I )must be open or held at a HIGH logic level when output functions 0 through 15 a re desired. The ripple-blanking input ( R B I ) must be open or H IGH if blanking of a decimal zero is not desired. 2 . When a LOW logic level is applied directly to the blanking input ( B I ) ,all segment outputs are O FF regardless of the level of any other input. 3. When ripple-blanking input ( R B I )a nd inputs A , B , C, a nd D a re at a LOW level with the lamp-test input H IGH, all segment outputs go O FF and the ripple-blanking output ( RBO)goes to a L OW level (response condition). 4. When the blanking input/ripple-blanking output ( BIIRBO) is open or held H IGH a nd a LOW is applied to the lamp-test input, all segment outputs are O N. ( b ) T ruth table (Reprinted b y permission of T a u s Instruments, Inc.) Fig. 7-12 Commercial 7447 BCD- to-seven-segment decoder/driver 150 C ODE CONVERSION +5 I v I 4< 1s BCD input Decoder 2s +5 D (7447A) GND - v Decimal output U -a -b Common anode d 4 s 8s [CHAP. 7 f g- 150 R Fig. 7-13 Wiring of decoder and seven-segment LED display Suppose the inputs to the decoder shown in Fig. 7-13 are LLLH (0001). This is the code for a decimal 1. According to the truth table for the 7447A decoder, this combination of inputs turns ON segments b and c. A decimal 1 is formed. Note that, when the truth table says ON, it means that the output of the 7447A decoder has gone to the LOW active state. It might also be said that the segment is being grounded through the decoder. The seven 150-0 resistors limit the current from GND through the LED segment to a safe level. Recall that the 7447A was described as a decoder/driuer. The driver description suggests that the current from the display LED flows directly through the 7447A IC. The decoder is directly driuing the display. The 7447A IC is said to be sinking the current from the display. It is assumed in Fig. 7-13 that the two blanking inputs ( R B Z and B I/RBO) plus the lamp test input are allowed to float HIGH. They are therefore not active and not shown on t he logic symbol in Fig. 7-13. Many CMOS display decoders are available. One example is the CMOS 74C48 BCD-to-sevensegment decoder, which is similar to the TTL 7447A IC. The 74C48 IC does need extra drive circuitry for most LED displays. Other examples of CMOS decoder ICs are the 4511 and 74HC4511 BCD-to-seven-segment latch/decoder/driver. The CMOS 4543 and 74HC4543 BCD-to-seven-segment latch/decoder/driver for liquid-crystal displays are also sold in convenient DIP IC form. SOLVED PROBLEMS 7.13 Refer to Fig. 7 -lla. Turn just the 5-V battery around and the LED will as before. (light, not light) Solution: T he LED will not light as before because it is sensitive to polarity. 7.14 R efer to Fig. 7-llc. A (GND, + 5-V) voltage is applied to the cathodes of the LED segments through the switches and limiting resistors. Solution: A G ND voltage is applied to the cathodes of the LED segments when a switch shown in Fig. 7 -llc is closed. 7.15 R efer to Fig. 7-11c. When switches 6, c , f , and g a re closed, a(n) will be displayed on the seven-segment LED display. (decimal number) 151 CODE CONVERSION C HAP. 71 Solution: Lighting segments b , c, f , a nd g will form a 4 on the display. 7.16 Refer to Fig. 7-11c. When switches b and c are closed, a(n) (decimal number) is displayed, and about (1, 40) mA of current will be drawn by the LEDs. Solution: Lighting segments h a nd c will form a 1 o n the display, which will cause about 40 m A of current to b e drawn by the LEDs. 7.17 Refer to Fig. 7-12b. To display a decimal 2, the BCD inputs must be (H, L), which will turn O N segments (list all O N segments). Solution: Displaying a decimal 2 r equires a BCD input of LLHL, which turns on segments a , b , d , e , a nd g . 7.18 Invalid BCI) inputs on the 7447A decoder produce seven-segment display. (OFF, unique) readings on the Solution: Invalid BCD inputs ( 10,11, 1 2,13,14, and 15) o n the 744714 decoder produce unique readings on the display. See Fig. 7-10h. 7.19 List the decimal indication of the seven-segment display for each input pulse in Fig. 7-14. +5 v IRa 150 c:, b A B 4 Decoder d - d C D j i h g f e d c b a (7447A) 1_ G ND -f g f y- g Fig. 7-14 Decoder-display pulse-train problem Solution: T he decimal outputs for the various input pulses in Fig. 7-14 a re as follows: pulse i = U (invalid BCD input) pulse e = 2 pulse U = 9 pulse j = 6 pulse f = display blank (invalid BCD input) pulse b = 3 pulse g = 0 pulse c = 5 pulse h = 7 pulse d = 8 +v 152 7.20 C ODE CONVERSION List the segment of the seven-segment display that will be lit for each of the pulses in Fig. 7-14. Solution: T he lit segments on t he pulse a = a , b , c , f , g pulse b = a , b , c , d , g pulse c = a , c , d , f , g pulse d = a , b , c, d , e, f , g pulse e = a , b , d , e , g 7-5 [CHAP. 7 seven-segment display in Fig. 7-14 a re as follows: pulse f = display blank (invalid BCD input) pulse g = a , b , c , d , e, f pulse h = a , b , c pulse i = b , f , g (invalid BCD input) pulse j = c, d , e , f,g LIQUID-CRYSTAL DISPLAYS Most battery- or solar-powered electronic equipment use liquid-crystal displays (LCDs). The LCD in your calculator, wristwatch, portable telephone, or portable computer are but a few examples of the use of liquid-crystal displays. The main advantages of the liquid-crystal display is its extremely low power consumption and long life. T he main disadvantage of the LCD is its slow switching time (on-off and off-on) which might be about 40 t o 100 ms. Slow switching time becomes even more troublesome at low temperatures. A second disadvantage is the need for ambient light because the LCD reflects (controls) light but does not emit light like LED, VF, or incandescent displays. A cutaway view of a typical f ield-efect L CD is detailed in Fig. 7-15. When a voltage is applied across the metalized segments on the top glass and the back plane, the segment changes to black on a silvery background. This is because the liquid crystal, or nematic fluid, sandwiched between the front and back pieces of glass transmits light differently when activated. The field-effect LCD uses polarized filters on the top and bottom of the display shown in Fig. 7-15. Each segment and the back plane are internally wired to contacts on the edge of t he LCD package. The simplified diagram in Fig. 7-15 shows only three of many edge connectors. Fig. 7-15 Field-effect LCD LCDs are driven by low-frequency (30 t o 200 Hz) square-wave signals with a 50% duty cycle (50% of the time it's HIGH). Consider the signals entering the LCD in Fig. 7-15. Note that the signal entering the back plane (b.p.) is HLH (HIGH-LOW-HIGH). The square-wave signal applied to segment e is LHL (LOW-HIGH-LOW) which is 180" o ut of phase (inverted) with the back plane signal. A n out-of-phase signal on a segment will activate the display as is the case with segment e in CHAP. 71 C ODE CONVERSION 153 Fig. 7-15. Next consider the signal applied to segment d of the LCD in Fig. 7-15. The signal goes HLH, which is a duplicate of the back plane signal, and they are said to be in phase. In-phase signals between the back plane and segment d produce no voltage difimnce, and segment d is not activated and remains invisible. In summary, in-phase signals do not activate the display while 180”out-of-phase signals activate an LCD segment. A typical LCD is illustrated in Fig. 7-16. This unit comes in. a 40-pin package ready for mounting in a printed circuit board. Notice that segments that can be activated can be manufactured in any shape, including numbers, symbols, and letters. Each segment, decimal point, word, and symbol is assigned a pin number. Only the back plane or common pin is noted on the drawing. Manufacturer’s data sheets must be consulted for actual pin numbers. This is a commercial display that you might expect on a digital meter. In Fig. 7-16, note the construction of this field-effect LCD with nematic fluid sandwiched between glass plates and polarizers on the top and bottom. Plastic headers secure the glass plates of the LCD to the pins. Plastic header Glass A” Common (back plane) Fig. 7-16 Commercial 3 5 digit LCD C are must be taken when using LCDs because they are made of glass and are somewhat fragile. Also, t he driving signals should be generated by CMOS ICs for two reasons. CMOS ICs consume very little power like the LCD. The second reason is that signals from CMOS ICs do not have a dc voltage offset like that present when using TTL ICs. A d c voltage applied across the nematic fluid will destroy the L CD after a time. A n older type liquid-crystal display that produces frosty-white characters on a dark background is the dynamic-scattering L CD. T he dynamic-scattering LCD uses a different nematic fluid and no polarizers. These must be viewed in very good light and consume more power than the more popular field-effect LCD. SOLVED PROBLEMS 7.21 Digits appear (black, silver) on a liquid-crystal display. (black, silver) background on a field-effect Solution: When using a field-effect LCD, digits will appear black on a silver background. 154 7.22 C ODE CONVERSION [CHAP. 7 List two advantages of LCDs over LED displays. Solution: A dvantages of using an LCD a re low-power consumption and long life. 7.23 List two disadvantages of LCD. Solution: An LCD h as the disadvantage of slow switching times, especially at low temperatures. A second disadvantage is that the LCD c annot be viewed in darkness. 7.24 Refer to Fig. 7 -15. When a voltage is applied across the nematic fluid in this LCD, the segment will be (activated, deactivated). Solution: Voltage applied across the nematic fluid in an LCD activates the segment. An activated segment on t he LCD in Fig. 7-15 will appear black on a silver background. 7.25 LCDs should be driven by (low, high)-frequency square-wave signals. Solution: LCDs should be driven by low-frequency (30 t o 200 H z) square-wave signals with a 50% duty cycle. 7.26 When the signals applied to the back plane and segment of an LCD are 180" o ut of phase, the segment will be (activated, deactivated). Solution: O ut-of-phase signals activate LCD s egment. 7.27 R efer to Fig. 7 -16. What is sandwiched between the two glass plates in this LCD? Solution: N ematic fluid (liquid crystal) is sandwiched between the glass plates in the LCD p ictured in Fig. 7-16. 7.28 LCDs can be damaged if driven by (ac, dc) voltages. Solution: LCDs can be damaged if driven by dc voltages. 7-6 D RNING LCDs A block diagram of a simple LCD decoder/driver circuit is drawn in Fig. 7 -17a. T he input is in 8421 BCD code. The decoder converts the incoming BCD to seven-segment code. This decoder would operate much like the 7 447 T TL decoder from Sec. 7 -4 except it is a CMOS unit. Next, the LCD driver unit would take the 100-Hz square-wave signal from the free-running clock and send inverted (180" out-of-phase) signals to only the LCD segments that are to be activated. The LCD driver would send in-phase signals to the LCD segments that are inactive. The free-running clock is an astable multiuibrator t hat continuously generates a string of square-wave pulses with a 50% duty cycle. 155 CODE C ONVERSION CHAP. 71 ' BCD 2 Input 7-segment code BCD-to7-segment \ ,/ decoder LCD driver 7-segment code !:::!: : ;.: ? : :: ;; :. : : . . .: . .:..............:i . . : ................. :.' . .. .. .. .. . .. .. . . . . . .: . . . . . :.. .....-.............. 2 . * ................ *I.? ,- * Common , Free-running clock a -( a) Block diagram abcde BCD Input -1 U a 0111 U b LA B C CMOS c D BCD-toseven- d segment decoder I U E+-- n I 100 Hz ( b) Wiring diagram Fig. 7-17 D ecoding/driving a s even-segment LCD A more detailed diagram of the LCD decoder/driver is shown in Fig. 7-17b. I n this example, the BCD input to the CMOS BCD-to-seven-segment decoder is 0111. T he decoder translates the BCD input and activates outputs a , 6 , and c with HIGH, which is the proper seven-segment code to display a decimal 7. All o ther decoder outputs ( d , e, f,and g ) remain LOW or deactivated. Notice that the, LCD driver section contains seven CMOS 2-input XOR gates. The 100-Hz square-wave signal drives the top input of each XOR gate. If t he bottom input on an XOR gate is LOW, the signal passes through the gate with no change (in phase with clock signal). But if the bottom input of an XOR gate is driven HIGH, t he signal is inverted as it passes through the gate (180" o ut of phase with clock signal). Refer back to Fig. 4-10 to verify the operation of a n XOR gate. The out-of-phase signals in Fig. 7-176 a re driving segments a , 6, and c , which are activated and appear dark on a silver background on the LCD. 156 CODE CONVERSION [CHAP. 7 T he clock signal is generated by an astable multivibrator in Fig. 7-17b. The 100-Hz signal is routed to both the common (back plane) of the LCD and each of t he XOR gates in the driver section. Two commercial CMOS ICs are available that perform the task of t he LCD decoder/driver. These are the 4543 and 74HC4543 ICs, described by the manufacturer as a BCD-to-seven-segment latch/decoder/driver for L CDs. A block diagram of an LCD decoder/driver circuit using the 74HC4543 IC is drawn in Fig. 7-18a. Note that the 74HC4543 chip contains the BCD-to-seven-segment decoder and LCD driver sections. ( a ) Block diagram of 74HC4543 driving LCD BCD Input 1001 +5 I v LCD output LV Is A 2 s,g 4s 8s b CMOS c BCD-tosevensegment decoder D d f BI 1 Clock - GND Ph 100 Hz m 1 1 d Common m ( b)Wiring diagram of 74HC4543 driving LCD ( c ) F ormat of decimal numbers Fig. 7-18 T he 74HC4543 latch/decoder/driver CMOS I C CHAP. 71 157 C ODE CONVERSION It also has an added 4-bit latch section to “lock in” the BCD input at a given time. Think of t he latch as a memory unit that holds the four input bits on the input of the decoder section for a time. A wiring diagram for the LCD decoder/driver circuit using the 74HC4543 IC is detailed in Fig. 7-18b. T he BCD input is 1001 (decimal 9) in this example. The 1001 input is decoded into seven-segment code. The 100-Hz clock signal is routed to both the common (back plane) of the LCD and the Ph (phase) input of the 74HC4543 IC. Notice that. the LCD driver section within the 74HC4543 IC inverts the signals to the segments that are to be activated. In this example segments a , b, c , d , f , and g a re activated, displaying the decimal 9 on the LCD. T he only in-phase signals passing to the LCD a re those of the inactive segments. Only segment e is inactive in this example. The format of‘ t he numbers generated by the 74HC4543 decoder is detailed in Fig. 7-18c. Note especially the numbers 6 and 9. These numbers are shaped differently from those generated by the 7447 decoder studied earlier in Sec. 7-4. Compare Fig. 7-18c with Fig. 7-10 to verify the different shapes for the numbers 6 and 9. SOLVED PROBLEMS 7.29 Refer to Fig. 7-17a. What is the job of the decoder block? Solution: T he decoder in Fig. 7-17a translates from a BCD number to seven-segment code. 7.30 Refer to Fig. 7-17a. What is the job of the LCD driver block? Solution: The LCD driver sends inverted signals to each segment that is to be activated and in-phase signals to e ach inactive segment of the liquid-crystal display. 7.31 Refer to Fig. 7-17a. T he LCD driver block consists of (NAND, XOR) gates. Solution: T he LCD driver consists of XOR gates (see Fig. 7-17b). 7.32 Refer to Fig. 7-17b. If the input to the decoder were 0001,,,, inverted outputs and which number does the LCD display. which XOR gates produce Solution: With an input of 0001, only XOR gates a a nd b will produce inverted signals at their outputs, activating segments a a nd b o n t he LCD (decimal 1 will show on display). 7.33 A free-running clock is also called a(n) (astable, monostable) multivibrator. Solution: T he free-running clock may also be called an astable multivibrator. 7.34 Refer to Fig. 7-19. What is the decimal reading on the LCD for each input pulse ( a through e). Solution: Decimal outputs in Fig. 7-19 a re as follows: pulse a = 2 pulse b = 4 pulse c = 8 pulse d = 5 pulse e = 6 158 [ CHAP. 7 C ODE CONVERSION m o 00 7 1 Is 00 o omo A n llolllo 0 0 edcba V CCa LE Inputs b B CD-tosevensegment latch1 decoder1 driver B ~ 8s D a C e (74HC4543) f ~ BI 1 - G ND 100 Hz Clock 1 Ph t ' d Common A 1 I Fig. 7-19 D ecoder pulse-train problem 73 .5 R efer to Fig. 7-19. For input pulse e only, which drive line or lines to the LCD have in-phase signals appearing on them? Solution: Decimal 6 a ppears on the LCD during pulse e in Fig. 7-19. Only segment b is inactive, and therefore only drive line b has an in-phase signal. Also see Fig. 7-18c for the formation. of decimal 6 . 7.36 R efer to Fig. 7-19. For input pulse h only, which drive lines to the LCD have out-of-phase signals appearing on them? Solution: Decimal 4 a ppears on the LCD during pulse b in Fig. 7-19. Segments 6 , c, f , a nd g a re activated, a nd therefore drive lines b , c , f , a nd g must have out-of-phase signals. 7-7 VACUUM FLUORESCENT DISPLAYS T he uacuum fluorescent ( V F ) display is a relative of the earlier triode vacuum tube. A schematic symbol for a triode vacuum tube is illustrated in Fig. 7-20. T he parts of the triode tube are shown as the plate ( P I , control grid (G), and the cathode ( K ) . T he plate is sometimes referred to as the anode, while the cathode may be called the filament or heater. The cathode/filament is a fine wire that when coated with a material such as barium oxide will emit electrons when heated. The control grid is a screen placed between the cathode and plate. Fig. 7-20 Schematic symbol of a triode vacuum tube 159 C ODE CONVERSION CHAP. 71 W hen the cathode/filament is heated, it "boils off" e lectrons into the vacuum surrounding the cathode. This is sometimes called thermionic emission. If the grid and plate are driven positive, the negatively charged electrons will be attracted and flow through the screenlike grid onto the plate. The triode is conducting current from cathode to anode. To s top the triode from conducting, two methods can be employed. First, a negative charge can be placed on the control grid. This will repel the electrons and stop them from passing through the grid to the plate. Second, the voltage on the plate can be dropped from its normal positive to 0 volts. With no voltage on the plate, it will not attract electrons and the triode tube will not conduct. The VF display has parts closely resembling those in the triode vacuum tube. Consider the schematic diagram of t he vacuum fluorescent display shown in Fig. 7 -2lu. T his schematic represents a single seven-segment digit having seven plates each coated with a zinc oxide fluorescent material. The VF display in Fig. 7-21a also has a single grid that controls the entire display. A single cathode/filament ( K ) is also shown, while the entire unit is enclosed in glass which contains a vacuum. Fluorescent material K ( a ) S chematic diagram of a single digit ov +12v+12v ov ov ov ov ( h ) Lighting two segments o n V F display Fig. 7-21 Seven-segment vacuum fluorescent display Typical operation of a single digit in a VF display is illustrated in Fig. 7-216. T he cathode/filament is heated using a dc voltage. The control grid has + 12 C a pplied, which "turns on" the entire ' display. In this example, only segments b a nd c a re to be activated, so only plates Pb a nd Pc a re energized with + 12 V. E lectrons flow from the cathode/filament to only p1ufe.s Ph a nd Pc of t he V F display. As t he electrons strike the plates of the b a nd c segments, they will glow the characteristic blue-green color. In the example shown in Fig. 7-21b with only segment 6 a nd c e nergized, the number 1 a ppears on the seven-segment VF display. Also note in the exampIe in Fig. 7-216 t hat the plates of t he deactivated segments ( P,, P d, P e, P f , a nd P g ) have 0 V a pplied to them. In summary, a plate voltage of + 12 V lights a s egment, whereas 0 V a t a plate means the segment will not glow. The physical layout of c athode/filament, grids, and plates in a V F display is shown in Fig. 7-22. Notice in Fig. 7-22a t hat the plates are shaped to form the individual segments of t he seven-segment display. The cathode or heaters are thin wires stretched across the top. The grid is a screenlike panel 160 [CHAP. 7 C O D E CONVERSION K K ( b ) Four-digit commercial VF display Fig. 7-22 V acuum fluorescent display t hat is positioned directly over the plates. The cathodes and grid are physically above the plates but are transparent so t he plates show up when they light. A commercial vacuum fluorescent display is shown in Fig. 7-22b. It contains 4 seven-segment V F displays as well as a few other symbols that make it suitable for a digital clock readout. The cathode/filaments are stretched lengthwise across the display and appear as very thin wires in a commercial VF u nit. The VF unit shown in Fig. 7-22b h as five control grids shown as rectangles surrounding seven-segment and colon displays. The five control grids can be activated separately to “turn on” an individual display. The control grids are commonly used for rnultiplexing t he displays (turning on seven-segment displays one at a time in rapid succession). The fluorescent-coated plates are shaped like the number segments, triangles, or colons. Vacuum fluorescent displays are commonly used in readouts found in a wide variety of electronic equipment, especially those found in automobiles. A V F display has extremely long life, fast response times, operates at relatively low voltages (commonly 1 2 V), consumes little power, has good reliability, and is inexpensive. Although a VF display emits a blue-green color, filters can be used to display other colors. V F displays are compatible with the CMOS family of ICs. SOLVED PROBLEMS 7.37 A vacuum fluorescent display glows with a color when activated. Solution: W ithout a filter, the V F display glows with a blue-green color. 7.38 R efer to Fig. 7-216. If + 12 V was applied to the grid and all the plates of this VF display, which segments would glow and which number would appear? C HAP. 71 C ODE CONVERSION Solution: The + 12 V a t each plate will activate (light) all the segments (number 8 a ppears), while the on t he grid turns on the entire seven-segment VF display. 7.39 161 + 12 V R efer to Fig. 7-23. What are the parts labeled X , Y , a nd 2 o n the VF display? Solution: P art X = c athode, filament, or heater Part Y = control grid Part Z = p late or anode 7.40 R efer to Fig. 7-23. Which segments of this VF display will glow and which number will appear? Fig. 7-23 V F display problem Solution: Segments a , b , d , e , and g a re activated ( + 1 2 V a t these plates) and will glow. The number 2 will show o n t he seven-segment V F display. 7.41 List a few of t he advantages of the VF display. Solution: Advantages of V F displays include long life, fast response time, low power consumption, good reliability, compatibility with CMOS ICs, and ability to operate at relatively low voltages. 7-8 DRIVING VF DISPLAYS WITH CMOS Consider the decoder/driver and VF display circuit drawn in Fig. 7-24. In this example the O l l l B c D is being decoded by the 4511 l atch/decoder/driver IC, and the VF display reads decimal 7. Notice that only outputs a , b , a nd c a re activated ( HIGH) o n the 4511 IC. These three HIGHS drive the plates of segments a , b , a nd c of t he V F display to 12 V. The grid of t he VF display in Fig. 7-24 is c onnected directly to positive of the 12-V power supply which activates the entire seven-segment display. The cathode ( K ) is connected in series with a limiting resistor ( R I ) o heat the filament. The t resistor limits the current through the filament (cathode) to a safe level. In this example, the inactive segments of the VF display ( d , e , f ,a nd g ) have their plates held LOW (0 V), and they do not light. + 162 [CHAP. 7 C ODE CONVERSION Fig. 7-24 Using the 4511 I C t o drive a V F display T he block diagram for the 45 11 BCD-to-seven-segment latch/decoder/driver IC is the same as for the 74HC4543 IC in Fig. 7-18a. The 4511 latch/decoder/driver has a 4-bit latch (memory unit). The latch section ( L E i nput) of the 4511 IC is disabled in Fig. 7-24 by holding it LOW. With the latch disabled, data from the BCD input passes through to the decoder section of t he 4511 IC. Note that a + 12-V dc power supply is used for both the vacuum fluorescent display and the 4511 CMOS chip. The 4000 CMOS series is ideally suited for driving VF displays because this family of ICs can operate on a wide range of higher dc voltages up to + 18 V. The decoder section of the 4511 translates from 8421 BCD code to seven-segment code. Figure 7-25b shows how the numbers are formed using the 4511 decoder. Note especially the formation of the 6 a nd 9 in Fig. 7-25b. The driver section of the Dual-in-line package B F C -f 16 15 VDD 14 -g -a l3 12 -b LE L D 10 -d -e 9 A Top view ( a ) Pin d iagram 0 1 2 3 4 5 6 7 8 9 ( 6 ) F ormat of decimal numbers Fig. 7-25 T he 451 1 BCD-to-seven-segment latch/decoder/driver IC C HAP. 71 163 CODE C ONVERSION 4511 IC has its outputs connected directly to t he plates (anodes) of the VF display. A H IGH at the output of the driver activates (lights) the segment on the seven-segment VF display (assuming the display’s control grid is activated). A LOW at the output of the driver deactivates the segment of the VF display, and it does not light. A pin diagram for the 45 11 BCD-to-seven-segment latch/decoder/driver CMOS IC is reproduced in Fig. 7-25a. Recall that the power pins are labeled V DDfor positive (pin 16) and Vss for negative (pin 7 ) . T he LE pin on the 4511 IC is a latch enable input. Latch enable is an active HIGH input and is shown disabled in the circuit in Fig. 7-24. To disable the latch means data will pass through the latch from BCD inputs to the decoder. The latch is said to be transparent when disabled. With the L E enabled (HIGH), four memory cells (or latches) hold current data on t he input to the 4511 decoder. With the latches enabled, changes at the BCD inputs (labeled A , B , C , and D )t o the (light test) input is 4511 I C will be disregarded. The 451 1 IC has two active LOW inputs. When the (blanking activated with a LOW, all IC outputs go HIGH to test the attached display. When the input) is activated with a LOW, all outputs go LOW and all segments of the attached display go blank. SOLVED PROBLEMS 7.42 Refer to Fig. 7-24. A decoder/driver IC and the (5, 12)-V dc power supply is being used because the CMOS 4511 (LCD, VF) display both operate at this voltage. Solution: In Fig. 7-24, a 12-V power supply is used because the CMOS 451 1 IC a nd V F display both operate at this voltage. 7.43 Refer to Fig. 7-24. In this example, the control grid on the VF display is deactivated) by being connected directly to 1 2 V. + (activated, Solution: I n this example, the control grid on t he V F display is activated by being connected directly to 7.44 R efer to Fig. 7-24. In this example, which plates of the VF display have to them. + 12 V. + 12 V ( HIGH) applied Solution: I n this example, decimal 7 a ppears on the V F display, meaning that segments (plates) a , b , a nd c a re activated ( + 12 V applied to them). 7.45 R efer to Fig. 7-24. What is the purpose of resistor R , in this circuit? Solution: Series resistor R , in Fig. 7-24 limits current through the filaments (cathode) to a safe level. 7.46 Refer to Fig. 7-24. If the BCD input was 0101, t he decimal appearing on the VF display would be -. Solution: I f t he input was OlOl,,, 7.47 in Fig. 7-24, t he decimal appearing on the V F display would be 5. Refer to Fig. 7-24. If the BCD input was 1000, the decimal appearing on the VF display would be -and segments (plates) would be activated (HIGH). Solution: If the input in Fig. 7-24 was 1000,,,, (plates) would be activated. t he V F display would show decimal 8 a nd all the segments 164 7.48 R efer to Fig. 7-24. If the (lamp test) input is activated or goes segments of the seven-segment V F display would light. Solution: If the 7.49 [CHAP. 7 C ODE CONVERSION (HIGH, LOW), all input in Fig. 7-24 was activated with a LOW, all segments of the V F display would light. R efer to Fig. 7-25a. When connecting power to this 4000 series CMOS IC, t he positive of t he power supply is connected to the ( V D U , V ss)pin, while the negative is connected to the ( VDD, ss)pin. V ~ Solution: On 4000 series CMOS ICs (see the 4511 i n Fig. 7-25a), the V DDpin is connected to the positive, while the Vss pin is connected to the negative of the power supply. Supplementary Problems 7.50 In a calculator, a(n) ( a ) (decoder, encoder) would translate from decimal to binary while a(n) (decoder, encoder) would translate from binary to the decimal output. Ans. ( a ) encoder ( b ) decoder 7.51 I t is characteristic that a(n) Ans. encoder 7.52 Refer to Fig. 7-26. This encoder has active (HIGH, LOW) inputs and active (HIGH, LOW) outputs. A m. T he 74148 encoder has active LOW inputs and active LOW outputs, as shown by the small bubbles at the inputs and outputs of the logic symbol in Fig. 7-26. (decoder, encoder) has only one active input at any given time. Inputs - 0 1 Priority encoder A , O Octal input 4 2 43 4 4 - & 2s 1s -5 -' *,I (74148) -7 b Binary outputs 1 2 3 4 outputs 5 6 7 A, A, A0 H X X L H H H H H H X L H H H H H H H L H H H H H H H H L L L L H H H H H L L H H L L H H H L H L H L H L H HHHHH XXXXX XXXXX XXXXX XXXXL XXXLH XXLHH XLHHH LHHHH H = H IGH. L = L OW, X (U) (b) Logic symbol = irrelevant ( h ) Simplified t ruth table Fig. 7-26 T he 74148 octal-to-binary priority encoder 7.53 (HIGH, LOW), the output would be Refer to Fig. 7-26. If input 7 were activated with a ,A,= , and A , = ( HIGH, LOW). Ans. If input 7 were activated with a LOW on the 74148 encoder, the outputs would be A , = LOW, A , = LOW. and A , = LOW. A ,= 1 U CHAP. 71 165 C ODE CONVERSION 7.54 , A, R efer to Fig. 7-26. If all inputs are HIGH, the outputs will be ‘4, = ( HIGH, LOW). Ans. If all inputs to the 74148 encoder are HIGH, the outputs will be all HIGH. = , and A,, = 7.55 Refer to Fig. 7-26. If input 3 is activated, the outputs will be A 2-A , = ( c ) ( HIGH,LOW). Ans. ( a ) H IGH ( b ) LOW ( c ) LOW , A, = ( b ) , and 7.56 List the binary output indicator reading (3 bits) for each of the input pulses shown i n Fig. 7-27. Ans. pulse a = 000 pulse c = 100 pulse e = 101 pulse g = 011 pulse i = 110 pulse b = 010 pulse d = 111 pulse f = 010 pulse h = 001 pulse j = 111 (a) o utput indicators Priority encoder 0 o p+Jqo j i h g 3 0]1--+--0 f e d c b a Fig. 7-27 Encoder pulse-train problem 7.57 Refer to Fig. 7-28. T he 7443 decoder has active (HIGH, LOW) inputs and active (HIGH, LOW) outputs. Register to View Answerhe 7443 decoder has active HIGH inputs and active LOW outputs, based on the logic symbol and truth table in Fig. 7-28. 7.58 R efer to Fig. 7-28, With an input of 0110, t he ( a ) (decimal number) output of the 7443 decoder is activated with a ( b ) ( HIGH, LOW). A m. ( a ) 3 ( h ) LOW 7.59 Refer to Fig. 7-28. T he invalid input 1111 generates all decoder. Ans. I s ( OS, I s) at the outputs of t he 7443 7.60 R efer to Fig. 7-28. T he 7443 IC is a decoder that translates from (decimals, hexadecimals). Ans. ( a ) XS3 ( b ) decimals (a) 7.61 Refer to Fig. 7-28. When the outputs of t he 7443 decoder are deactivated, they are at logical (0, 1). Ans. 1 ( HIGH) (BCD, XS3) code to (6) 166 [CHAP. 7 C ODE CONVERSION I o b- 3 !E - ID A xs3 input XS3-todecimal B decoder 1 -of-10 decimal output c (7443) 9 ( b) Truth table ( a ) Logic s ymbol Fig. 7-28 T he 7443 XS3-to-decimal decoder List the decimal o utput indicator activated for each pulse going into the 7443 decoder shown in Fig. 7-29. Ans. pulse a = 6 pulse d = 9 pulse h = 3 pulse b = 4 pulse i = 5 pulse e = 0 pulse c = all outputs deactivated pulse f = 8 pulse j = all outputs deactivated (invalid XS3 input) pulse g = 1 (invalid XS3 input) 76 .2 Output indicators ‘O Otl ‘ 1 10 (7443) j i h g f e d c b 0O a Fig. 7-29 D ecoder pulse-train problem 7.63 Battery and solar-powered equipment most commonly use Ans. LCD 7.64 If a n LED emits light, a liquid-crystal display is said to Ans. control (LCD, LED) displays. (control, generate) light. CHAP. 71 167 C ODE CONVERSION 76 .5 What is the main disadvantage of liquid-crystal displays? A m. Slow switching speeds or the need for ambient light. 76 .6 R efer to Fig. 7-15. O n an LCD, only segments that are driven by (in-phase, out-of-phase) square-wave signals are activated and visible on the display. Ans. out-of-phase 76 .7 LCDs that show (black, frosty white) segments on field-effect liquid-crystal displays. Ans. black 7.68 ii silvery background are referred to as (liquid-crystal, VF) displays. Square-wave signals are required when driving liquid-crystal Ans. 7.69 The liquid-crystal sandwiched between glass plates on an LCD is called 77 .0 Refer to Fig. 7-17a. T he decoder and LCD driver are 77 .1 Refer to Fig. 7-17a. The LCD driver section consists of seven A ns. XOR 7.72 Refer to Fig. 7-30. What is t he decimal reading on the LCD for each input pulse ( a through d ) . Ans. pulse ( I = 0 pulse h = 9 pulse (I = 3 pulse d = 6 7.73 Refer to Fig. 7-30. For input pulse c only, which drive lines to the LCD have out-of-phase signals appearing o n them? Ans. Out-of-phase signals are activated on segments a , b , c , d , and g . (CMOS, TTL) devices. Inputs 11 OOll[O- A m. nematic A ns. CMOS (AND, X OR) gates. U --t- - I S. A 1m 1 - --ilooo fluid. b- BCD-tosevensegment latch/ decoder/ driver B ' 8sD C (74HC4543) dcba BI f GND Ph f- - d Common 100 Hz 77 .4 A - Refer to Fig. 7-30. For input pulse b only, which drive lines to the LCD have in-phase signals appearing on them? Ans. Segment e is deactivated with an in-phase signal (decimal 9 appears). 168 C ODE CONVERSION [CHAP. 7 7.75 A V F display has parts comparable to a 7.76 T he plates of a VF display are coated with a (barium oxide, zinc chloride) fluorescent material that glows when bombarded by electrons. Ans. barium oxide 7.77 Refer to Fig. 7-31. List the plates (anodes) that are activated on this seven-segment VF display. Ans. Activated plates = P b, P,, Pf, nd Pg a ov Ans. triode (diode, triode) vacuum tube. + 12v+12v ov ov + 12v+12v Fig. 7-31 V F display problem 7.78 Refer to Fig. 7-31. What decimal number would be shown on the seven-segment VF display? 7.79 Refer to Fig. 7-22b. Why are there five separate control grids in this commercial VF display? Ans. Each figure has a control grid so digits (or colon) can be turned on/off individually. The control grids are commonly used when multiplexing a display. 78 .0 Vacuum fluorescent displays are widely used in (automobiles, solar-powered equipment) because of voltage compatibility, long life, low cost, and good reliability. Ans. automobiles 7.81 Refer to Fig. 7-23. In the VF display, wires labeled X a re called the Ans. cathodes, filaments, or heaters 7.82 Refer to Fig. 7-23. In the VF display, the shaped segments labeled 2 are called the Ans. plates or anodes 78 .3 Refer to Fig. 7-32. List the decimal number shown on the VF display during each pulse a through d . Ans. pulse a = 8 pulse b = 9 pulse c = 5 pulse d = 2 7.84 R efer to Fig. 7-32. During pulse a only, what is the logic level at each output ( a through g ) of the 4511 IC? Ans. All outputs ( a through g ) a re HIGH or activated (decimal 8 is displayed). Ans. 4 . . CHAP. 71 CODE CONVERSION 169 Fig. 7-32 Decoder/driver pulse-train problem 7.85 Refer to Fig. 7-32. During pulse c only, what is the logic level at each output ( a through g ) of the 4511 IC? A ns. Decimal 5 is displayed. pulse a = HIGH output pulse b = LOW output pulse c = HIGH output pulse d = H IGH output pulse e = LOW output pulse f = H IGH output pulse g = H IGH output Chapter 8 Binary Arithmetic and Arithmetic Circuits 8-1 INTRODUCTION T he general public thinks of digital devices as fast and accurate calculating machines. The calculator and digital computer are probably the reason for that. Arithmetic circuits are common in many digital systems. It will be found that rather simple combinational logic circuits (several gates connected) will add, subtract, multiply, and divide. This chapter will cover binary arithmetic and the way it is performed by logic circuits. 8-2 BINARY ADDITION Adding binary numbers is a very simple task. The rules (addition tables) for binary addition using two bits are shown in Fig. 8-1. T he first three rules are obvious. Rule 4 says that, in binary, 1 + 1 = 10 (decimal 2). T he 1 in the sum must be carried to the next column as in regular decimal addition. S um O+O=O Rule 1 Rule2 Rule3 Rule 4 + Carry out 0+1=1 1+ 0 = 1 1 1 = 0 a nd carry 1 = 10 symbol means add + Fig. 8-1 R ules for binary addition Two sample binary addition problems are shown below: carries 1 +o ( sum) 1 00 10 10 4 +2 6 + ( decimal) ( sum) 1 4 14 11 .1 II I1 II I( I ; ; 0;; 1 ; ; 0 ; ; 11; 1 1000 '[ 5 +3 8 (decimal) It is now possible to design a gating circuit that will perform addition. Looking at the left two columns of Fig. 8-1 reminds one of a two-variable truth table. The binary rules are reproduced in truth table form in Fig. 8-2. T he inputs to be added are given the letters A and B . T he sum output is often I nputs outputs Carry 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 1 A+BJ c CO Fig. 8-2 Half adder truth table 170 CHAP. 81 171 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS given the summation symbol (E). T he carry-out output column is often just represented with the CO symbol. The truth table i n Fig. 8-2 is that of a h alf adder circuit. A block diagram for a half adder might be drawn as in Fig. 8 -3a. Note the two inputs A and B on the symbol in Fig. 8 -3a. T he outputs are IabeIed C (sum) and CO (carry out). It is common to label the half adder with HA as shown on the block symbol. ^---rr z B CO ( h ) Logic d iagram ( a) Block s ymbol Fig. 8-3 Half a dder Looking at the sum (C) o utput column of the truth table in Fig. 8-2, note that it takes an XOR function to produce the C output. The carry-out column will use an AND function. A complete logic circuit for the half adder with two inputs ( A and B ) and two outputs (C and C O )is shown in Fig. 8-3b. Composed only of gates ( XOR and A ND), t he half adder is classified as a combinational logic circuit. Consider the binary addition problem in Fig. 8 -4a. T he I s column is 1 + I , and it follows rule 4 in Fig. 8 -1. T he sum is 0 with a carry of 1 to the 2s column. The 2s column must now be added. In the 2s column we have 1 + 1 + 1. This is a new situation. It equals binary 11 (decimal 3). T he 1 is placed below the 2s column i n t he sum position. A 1 is carried to the 4s column. The single 1 at the top of the 4s column is added to the OS with a result of 1, which is written in the s um position. The result is a sum of 110. carry carry I Rule 5 ( U) S imple binary addition problem A + B + C arry in 1 +1+ 1 sum = Co ut arry I 1 and carry 1 = 11 (b) A dditional binary addition rule Fig. 8-4 Rule 5 for binary addition is formally written in Fig. 8 -4h. Note t he t hree inputs ( A , B , and carry in). The outputs are the usual sum and carry out. Rule 5 suggests that a half adder will not work if a carry-in situation arises. Half adders will add only two inputs ( A and B ) , a s in the I s column of an addition problem. When the 2s column or the 4 s column is added, a new circuit is needed. The new circuit is called a full a dder. A block diagram of a full adder is shown in Fig. 8 -5a. T he full adder circuit has three inputs which are added. The inputs shown in the block diagram in Fig. 8-5 a re A , B , and C in (carry in). The outputs from the full adder are the customary C (sum) and CO (carry out). Note the use of the letters FA to symbolize f ull a dder in the block diagram. To repeat, t he half adder is used in only the I s place when larger binary numbers are added. Full adders are used for adding all other columns (2s, 4 s, 8s, and so forth). A full adder circuit can be constructed from half adders and an OR g ate, A full adder circuit is diagrammed in Fig. 8 -91. T he half adder becomes a basic building block in constructing other adders. A t ruth table for the full adder is detailed in Fig. 8-5c. 172 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS A Inputs A o utputs B B C O x A Cin B x - A HA CO ( b) Wired from half adders and OR gate (c) T ruth table Fig. 8-5 Full adder SOLVED PROBLEMS Solve the following binary addition problems: (a) 100 + 11 (b) 1010 + 110 (c) 1001 + 101 Solution: Refer to Figs. 8-1 and 8-2. The sums in the problems are as follows: ( a ) 111, ( b ) 10000, ( c ) 1110. 8.2 Find the binary sums in,the following problems: (a) 1110 11 + (b) 1011 + 111 ( c) 1111 + 111 Solution: Refer to Figs. 8-1 and 8-2. The binary sums in the problems are as follows: ( a ) 10001, ( b ) 10010, ( c ) 10110. x CO - HA B ( a ) Block symbol 8.1 [CHAP. 8 C O C HAP. 81 8.3 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS A half adder circuit has input(s) and 173 output(s). Solution: A half adder circuit has 2 inputs and 2 outputs. 8.4 A full adder circuit has input($ and output(s). Solution: A full adder circuit has 3 inputs and 2 outputs. 8.5 Draw a block diagram of a half adder and label the inputs and outputs. Solution: See Fig. 8 -3u. 8.6 Draw a block diagram of a full adder and label the inputs and outputs. Solution: See Fig. 8-52. 8.7 A half adder circuit is constructed from what two logic gates? Soiution: A half adder circuit is constructed from a 2-input XOR gate and a 2-input AND gate. 8.8 A full adder circuit can be constructed by using two (AND, OR) gate. (FAs, HAS) and a 2-input Solution: A full adder circuit can be constructed by using two HAS and a 2-input OR gate. 8.9 An HA circuit is used to add the bits in the problem. (Is, 2s) column of a binary addition Solution: A n HA adds the 1s column in a binary addition problem. 8.10 Draw the logic diagram of a full a dder using AND, XOK, a nd OR gates. Solution: See Fig. 8-6. Fig. 8-6 Logic diagram of a full adder 174 8.11 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS [CHAP. 8 List the HA sum o utputs for each set of i nput pulses shown in Fig. 8-7. f e d c b a Fig. 8-7 Half adder pulse-train problem Solution: Based on the truth table in Fig. 8-2, the s um o utputs from the half adder in Fig. 8-7 are as follows: pulse a = 1 pulse c = 0 pulse e = 0 pulse b = 0 pulse d = 0 pulse f = 1 81 .2 List the half adder carry-out o utputs for each set of i nput pulses shown in Fig. 8-7. Solution: Based on the truth table in Fig. 8-2 the carry-out outputs from the half adder in Fig. 8-7 a re as follows: pulse a = 0 pulse c = 1 pulse e = 1 pulse b = 0 pulse d = 0 pulse f = 0 8.13 List the full adder sum o utputs for e ach set of i nput pulses shown in Fig. 8-8. h g f e d c b a Fig. 8-8 Full adder pulse-train problem Solution: R efer to Figs. 8-1 and 8-4b. T he sum outputs from the FA shown in Fig. 8-8 a re as follows: pulse e = 0 pulse g = 1 pulse c = 1 pulse a = 0 pulse b = 0 pulse d = 1 pulse f = 0 pulse h = 1 8.14 List the FA carry-out o utputs for each set of i nput pulses shown in Fig. 8-8. Solution: Refer to Figs. 8-1 and 8-4b. T he CO o utputs from the full adder shown in Fig. 8-8 a re as follows: pulse a = 1 pulse e = 1 pulse g = 0 pulse c = 0 pulse b = 0 pulse d = 0 pulse f = 1 pulse h = 1 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS CHAP. 81 175 8-3 BINARY SUBTRACTION Half subtractors and full subtractors will be explained in this section. The rules for the binary subtraction of two bits are given in Fig. 8-9. The top number in a subtraction problem is called the rninuend. T he bottom number is called the subtrahend, and the answer is called the difference. R ule 1 in Fig. 8-9 is obvious. Rule 2 (Fig. 8-9) concerns 1 being subtracted from the smaller number 0. In Fig. 8-10, note that, in the 1s column of the binary number, 1 is subtracted from 0. A 1 must be borrowed from the binary 2s column, leaving a 0 in that column. Now the subtrahend 1 is subtracted from the minuend 10 (decimal 2). This leaves a difference of 1 in the 1s column. The binary 2s column uses rule 1 (0 - 0) and is equal to 0. Therefore, rule 2 is 0 - 1 = 1 with a borrow of 1. Rules 3 and 4 a re also rather obvious. Rule 1 Rule 2 Rule 3 Rule 4 Minuend 0 0 1 1 Subtrahend 0 1 0 1 Difference 0 1 - - Borrow out and borrow 1 1 0 Fig. 8-9 Rules For binary subtraction borrow Minuend Subtrahend Difference 2 1 -1 /io-’lo 1 1 -0 0 -- Fig. 8-10 Binary subtraction problem showing a borrow T he subtraction rules given in Fig. 8-9 look somewhat like a truth table. These rules have been reproduced in truth table form in Fig. 8-11. Consider the difference ( D i ) o utput in the truth table. Note that this output represents the XOR function. The logic function for the difference output in a subtractor is the same as that for the sum output in a half adder circuit. Now consider the borrow ( B o ) column in the truth table. The logic function for this column can be represented by the Boolean expression A . B = Y . It can be implemented by using an inverter and a 2-input AND gate. I Inputs Minuend A Subtrahend B 0 0 o utputs Difference Borrow 0 0 0 0 1 1 1 0 0 0 Di Bo 1 1 1 A-B I 1 Fig. 8-11 Half subtractor truth table T he truth table in Fig. 8-11 represents a logic circuit called a half subtractor. T he Boolean expression for the difference output is A @ B = Di. T he Boolean expression for the borrow ( B o ) o utput is B = B o. A half subtractor would be wired from logic gates as shown in Fig. 8-12a. I nput x. 176 Inpi:\ A is t he minucnd a nd / I is the suhtrahcnd. T h e / A o utput is t he ditlcrci1cc; / I0 is t hc horro\\. ..\ s impliticd hltxck di;igr;im f o r ;I half suhtr;rctor is i n Fig. S -12h. C o m p i ~ r chc half w h t r ; ~ c t o r t logic ~ l i ; ~ g r ;i~ r 1:ip. S-1 2tr \ \it11 tlic. h di ;idcler 111 Fig. S-.%. 'I'hc w i l y n ~i d ifkrcncc in the logic circuits is t hat the half suhtractcrr hiis o11c aJdc11 i nvcrtcr a t the .,I i nput ot t he AND giltc. Consider the suhtr;~ctionprohlcm in k'ig. S-13. Sc\er;11horrous ;1rc- c *.vitlc-nt i i i t hi\ p rotdciii. If \ i i s uhtractor circuits arc u \cd f o r t h e six h i n a n p lace\. the txwotv\ n iwt he c on\idcrcd. .A h alt s uhtractor may he u scd tor thc Is pl;rcc. F'ull \ iihtr;~ctc~rs must h e i ~ \ c di n the 2 s. 4s. Ss. I h . a nd 3 3 c olumns o f t his p rohlcm. A bt c d iagram of ;I t ull s uhtractor (1:s) i.; i n 1;ig. S-l 4u. T he input\ ;1rc .4 ( minucnd). / I lx k ( suhtr:~hcnd).and H iri ( horroh input). 'l'hc outputs ;1rc 11; ( ditlcrcncc) ;ind /Io [ b orron output ). ' l'hc Bo a nd HUi l incs arc conncctcd from suhtr;tctor to s uhtractor t o kccp t rack o f t he horrcm\. [c) I .opc diagram Fig. 8-14 Full s ubtractor 177 B INARY ARITHMETIC AND ARITHMETIC CIRCUITS CHAP. 81 T he diagram in Fig. 8-146 shows how to wire two half subtractors (HS) and an OR gate together to form a full subtractor (FS) circuit. Note that the wiring pattern is similar to that used for adders. Finally, Fig. 8-14c shows how gates could be wired to form a full subtractor circuit. Remember that full subtractors must be used to subtract all columns except the 1s column in binary subtraction. The truth table for the full subtractor is in Fig. 8-15. T he inputs are labeled as minuend ( A ) , subtrahend ( B ) , and borrow in ( Bin). T he outputs are the customary difference ( D i ) and borrow out ( Bo). i Inputs Minuend Subtrahend (B) (4 Line o utputs Borrow in ( Bin) Difference Borrow out ( Bo) 0 0 1 1 1 1 1 0 1 0 0 0 1 I A - I B - Bin 0 0 1 Di Bo Fig. 8-15 Truth table for the full subtractor T he binary subtraction problem in Fig. 8-16 will aid understanding of the full subtractor truth table. Follow a s this problem is s olved, using only the truth tables in Figs. 8-11 and 8 -I5. Look a t the I s column of the problem in Fig. 8-16. T he 1s place uses a half subtractor. Find this situation in the truth table in Fig. 8-11. You find that line 3 of the half subtractor truth table gives an output of 1 for Ri (difference) and 0 f or borrow out ( Bo). This is recorded below the I s column in Fig. 8-16. A -B DI 64s 1 -0 1 32s 1 16s 1 0 1 1 0 8s 4s 2s IS 0 1 1 1 0 1 0 0 0 1 0 1 117 - 28 89 Fig. 8-16 Solving a binary subtraction probleni using truth tables Consider the 2s column in Fig. 8-16. T he 2s column uses a full subtractor. On the full subtractor truth tabIe, look for the situation where A = 0, B = 0 , and Bin = 0. This is line 1 in Fig. 8-15. According to the truth table, both outputs ( D i and B o) a re 0. This is recorded below the 2s column in Fig. 8-16. Next consider the 4s column in Fig. 8-16. The inputs to this full subtractor will be A = 1, B = 1, and Bin =: 0. Looking at the input side of the truth table in Fig. 8-15, it appears that line 7 shows this situation. The outputs ( Di and B o) a re both 0 according to the: truth table and are written as such on Fig. 8-16 under the 4s column. 178 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS [CHAP. 8 Look a t the 8s column in Fig. 8-16. The inputs to the full subtractor will be A = 0, B = 1, a nd Bin = 0. Line 3 of the truth table (Fig. 8-15) shows this situation. The outputs ( D i a nd B o ) in line 3 a re both 1s and are recorded in the 8s column in Fig. 8-16. The 16s column in Fig. 8-16 has inputs of A = 1, B = 1, and Bin = 1. This corresponds with line 8 in the truth table. Line 8 g enerates an output of Di = 1 a nd B o = 1. T hese 1s are recorded under the 16s column in the problem. The 32s column has inputs of A = 1, B = 0, and Bin = 1. This corresponds to line 6 in the truth table in Fig. 8-15. Line 6 generates outputs of Di = 0 and Bo = 0. T hese 0s a re recorded in the 32s column of the problem. Finally consider the 64s column in Fig. 8-16. The inputs to the full subtractor are A = 1, B = 0, a nd Bin = 0. This input combination is shown in line 5 in the truth table. Line 5 g enerates an output of Di = 1 and Bo = 0. Figure 8-16 illustrates how binary 11100 is subtracted from binary 1110101 using truth tables. The borrows are shown below the problem. This procedure is quite cumbersome for humans, but electronic circuits can accurately perform this subtraction in microseconds. SOLVED PROBLEMS 8.15 Solve the following binary subtraction problems: (a> - 110 100 (b) 1111 - 1010 (c) 10110 (d) - 1100 10001 - 110 (e) IIOOOI - 111 Solution: By a procedure similar to that illustrated i n Fig. 8-13, the differences for the problems are found to be as follows: ( a ) 010, ( b ) 101, ( c ) 1010, ( d ) 1011, ( e ) 101010. 8.16 Draw a block diagram of a half subtractor and label inputs and outputs. Solution: See Fig. 8-12b. 8.17 Draw a block diagram of a full subtractor and label inputs and outputs. Solution: See Fig. 8-14a. 8.18 Draw the logic diagram of a half subtractor. Use X OR and A ND gates plus an inverter. Label inputs and outputs. Solution: See Fig. 8-12a. 8.19 W hen half adders and subtractors are compared, it is found that the half subtractor logic circuit contains one extra logic element which is an (AND, inverter, OR). Solution: A H S contains one inverter more than an HA logic circuit. 8.20 List the difference ( D i ) o utputs from the half subtractor shown in Fig. 8-17. CHAP. 81 BINARY ARITHMETIC AND A RITHMETlC CIRCUITS f e d c b a 179 Bo A -- B Fig. 8-17 Half subtractor pulse-train problem Solution: Refer to t,,e truth table in Fig. 8-11. The D outputs from the HS (Fig. 8-17) are as follows: i pulse e = 0 pulse c = 0 pulse a = 1 pulse d = 1 pulse f = 1 pulse b = 0 8.21 List the borrow-out ( B o ) o utputs from the half subtractor shown in Fig. 8-17. Solution: Refer to the truth table in Fig. 8-11. The Bo outputs from the HS (Fig. 8-17) are as follows: pulse a = 1 pulse c = 0 pulse e = 0 pulse b = 0 pulse d = 0 pulse f = 1 8.22 List the difference (Di) utputs from the full subtractor shown in Fig. 8-18. o h g f e d c b a Fig. 8-18 Full subtractor pulse-train problem Solution: Refer to the truth table in Fig. 8-15. The D outputs of the FS (Fig. 8-18) are as follows: i pulse g = 0 pulse a = 0 pulse e = 1 pulse c = 1 pulse b = 1 pulse d = 0 pulse f = 0 pulse h = 1 82 .3 List the borrow-out ( B o ) o utputs from the f ull subtractor shown in Fig. 8-18. Solution: Refer to the truth table in Fig. 8-15. The Bo outputs from the FS (Fig. 8-18) are as follows: pulse a = 0 pulse c = 0 pulse e = 1 pulse g = 1 pulse b = 1 pulse d = 0 pulse f = 0 pulse h = 1 8.24 When 2-bit numbers are subtracted, an (FS, HS) is used for the 2s column. (FS, HS) is used for the I s column and an Solution: In binary subtraction, an HS is used for the 1s column and an FS is used for the 2s column. 180 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS [CHAP. 8 8-4 PARALLEL ADDERS AND SUBTRACTORS Binary addition can be accomplished in two different ways. Either parallel o r serial adders can be used. A serial adder operates in much the same way as addition by hand. It first adds the Is column, then the 2s column plus the carry, then the 4s column plus the carry, and so forth. Serial addition takes a fair amount of time when long binary numbers are added. Parallel addition, however, is very fast. In parallel addition, all the binary words (a word is a group of bits of a given length, such as 4, 8, o r 16) t o be added are applied to the inputs and the sum is almost immediate. Serial adders are simpler but slower. Parallel adders are faster, but they have more complicated logic circuits. A 4-bit parallel adder is shown in Fig. 8-19. A single half adder (HA) and three full adder (FA) circuits are used. Note that the top H A adds the 1s column ( A , and B l). T he 2s column uses a full adder. The 2s F A adds the A , and B , plus the carry from the 1s a dder. Note that the carry line runs from the CO of the 1s a dder to the Cin of the 2s a dder. The 4s and 8s a dders also are full adders. The sum (C) o utput of each adder is connected to a sum indicator at the lower right in Fig. 8-19. T he C O of the 8s F A is an overflow and forms the 16s place in the sum. Addition problem A4 A A A , 32 + B B B B, 432 A B - HA 1s z CO carry Cin L I : r A4 B 4 Sum Fig. 8-19 A 4-bit parallel adder Suppose the task were to add binary 1111 t o 1111 with the parallel adder shown in Fig. 8-19. As soon as these numbers were applied to the eight inputs on the left, the output of 11110 (decimal 30) would appear on the output sum indicators. This parallel adder is limited to four input bits. More full adders could be attached to the circuit for the 16s place, 32s place, and so forth. As with addition, subtraction can be done serially or by parallel subtractors. Figure 8-20 is a diagram of a familiar-looking 4-bit parallel subtractor. Its wiring is quite similar to that of t he 4-bit parallel adder that was just studied. The two 4-bit numbers are shown in the problem section at the upper left. Note that B , B , B , B , (subtrahend) is subtracted from A , A , A , A , (minuend). The CHAP. 81 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS 181 Subtraction problem A, A, A, A, (minuend) - B4 B3 B2 B , (subtrahend) * Difference Fig. 8-20 A 4-bit parallel subtractor difference between these numbers will appear on the difference output indicators at the lower right in Fig. 8-20. T he 1s column in Fig. 8-20 uses a half subtractor (HS). T he 2s, 4s, and 8s columns use full i subtractors (FS). Each of the D outputs of the subtractors is connected to an output indicator to show the difference. The borrow lines connect the Bo o utput of o ne subtractor to the Bin input of t he next most significant bit. The borrow lines keep track of t he many borrows in binary subtraction. If greater than 4-bit numbers were to be subtracted, more full subtractors would be added to the circuit. FSs would be added in the pattern shown in Fig. 8-20. This parallel subtractor acts on the inputs and gives the difference almost immediately. Word A 4-bit E l parallel 2, adder Word B Cout Inputs Carry input - * (7483) Typical Sum Fig. 8-21 Logic symbol for a commercial 7483 4-bit parallel-adder IC 182 B INARY ARITHMETIC AND A RITHMETIC CIRCUITS [CHAP. 8 By comparing the 4-bit parallel adder with the subtractor, it can be seen that the circuits are very similar (see Figs. 8-19 and 8-20). As a practical matter, full adders are purchased in IC form rather than being wired from logic gates. In fact, several more complicated adders and arithmetic logic units (ALUs) a re available in IC form. Typically, an adder unit is shown as a block symbol like the one in Fig. 8-21. This logic symbol is actually the diagram for a commercial 7483 4-bit f ull adder IC. I t could also be the symbol for t he 4-bit parallel adder shown in Fig. 8-19 if t he carry input ( Cin) were left off t he symbol. The A , and B , inputs are the LSB inputs. The A , and R , connections are the MSB inputs. It is typical to GND the Cin (carry input) when not connected to a preceding parallel adder. SOLVED PROBLEMS 8.25 R efer to Fig. 8-19. The top adder (1s HA) will add the (LSBs, MSBs). Solution: T he top adder shown in Fig. 8-19 will add the LSBs (least significant bits). 8.26 Refer to Fig. 8-20. The 8s full subtractor subtract will the (LSBs, MSBs). Solution: T he 8s FS shown in Fig. 8-20 will subtract the MSBs (most significant bits). 8.27 R efer to Fig. 8-19. If A , = 1 and B , = 1, then the carry line between the I s and 2s adders will be _ ___ ( HIGH, LOW). Solution: According to line 4 in the truth table in Fig. 8-2, with A , a nd B , equal to 1, the carry line between t he 1s and 2s adders shown in Fig. 8-19 will be H IGH, indicating a carry. 8.28 Draw a diagram of a 6-bit parallel adder using one HA and five FAs. Solution: S ee Fig. 8-22. 8.29 When the 6-bit unit in Prob. 8.28 adds 111111 and 111111, the sum is a binary equals in decimal. , which Solution: W hen the 6-bit unit in Prob. 8.28 a dds binary 111111 and 111111, the sum is binary 1111110 by a procedure similar to that illustrated in Fig. 8-4a. T he sum (11111 10) is then converted to its decimal equivalent of 126 by means of t he procedure shown in Fig. 1-2. 8.30 R efer to Fig. 8-19. When 1100 and 0011 are added, which carry lines will be HIGH? Solution: When 1100 and 0011 are added with the adder shown in Fig. 8-19, no carry lines are HIGH because n o carries occur in this addition problern. 8.31 Refer to Fig. 8-19. If all eight inputs to the parallel adder are HIGH, the binary output will be , which equals in decimal. CHAP. 81 183 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS Inputs 7. cin r, z I 1 1 1 Sum Fig. 8-22 A 6-bit parallel adder Solution: If all inputs to t he parallel adder shown in Fig. 8-19 are HIGH, t he binary output (sum) will be 1111, + 1111, = 11110, (sum) The s um 11110, is equal to a decimal 30 according to the procedure shown in Fig. 1-2. 8.32 Refer to Fig. 8-20. The (bottom, top) subtractor is subtracting the least significant bits. Solution: T he top subtractor is subtracting the LSBs in the problem in Fig. 8-20. 8.33 When 0011 is subtracted from 1101 in Fig. 8-20, the borrow line between the subtractor a nd t he (2s, 4s, 8s) subtractor is HIGH. (Is, 2s, 4s) Solution: W hen 0011 is subtracted from 1101 in Fig. 8-20, t he borrow line between the 2s a nd 4s s ubtractors is HIGH. T his is shown by noting the borrow between the 4s a nd 2s places in the binary subtraction problem / lfl 1lofl1 -0011 1 0 1 0 184 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS 8.34 o [CHAP. 8 List the binary sum at the output indicator for each input pulse to the 4-bit parallel adder shown in Fig. 8-23. n m l k j i h g f e d c b a E3 , E4 CO 1 output indicators Fig. 8-23 Parallel-adder pulse-train problem Solution: Refer to the procedure in Fig. 8 -4a. The binary sums for the pulses shown in Fig. 8-23 are as follows: pulse i = 0011 + 0010 = 00101 pulse a = 0101 + 0101 = 01010 pulse b = 0010 + 1010 = 01100 pulse j = 1101 + 1111 = 11100 pulse k = 1110 + 1001 = 10111 pulse c = 1000 + 1100 = 10100 pulse 1 = 0001 + 0110 = 00111 pulse d = 0110 + 0011 = 01001 pulse e = 0001 + 0100 = 00101 pulse rn = 0010 + 1001 = 01011 pulse f = 0011 + 1011 = 01110 pulse n = 1001 + 0111 = 10000 pulse g = 1111 + 0111 = 10110 pulse o = 1111 + 1111 = 11110 pulse h = 1000 + 1101 = 10101 8-5 USING FULL ADDERS A 4-bit parallel adder using three full adders and one half adder was studied in Fig. 8-19. To standardize circuitry and to do more complicated arithmetic, a somewhat different 4-bit adder is used. This new 4-bit adder is diagrammed in Fig. 8-24. Note that four full adders are used in this revised circuit. To make the 1s F A operate like a half adder, the Cin input to the FA is grounded (LOW). T he revised circuit shown in Fig. 8-24 will operate exactly like the older version shown in Fig. 8-19. The full adder truth table in Fig. 8-25 has been rearranged somewhat to help show that the full adder can be converted to a half adder by holding the Cin input LOW. Consider the upper half of the full adder truth table in Fig. 8-25. N ote that Cin = 0 for each line of the unshaded section of the truth table. The B , A , E, and CO columns now correspond exactly with the half adder truth table in Fig. 8-2. T he 4-bit full adder shown in Fig. 8-24 is a block diagram of the 7483 full adder IC introduced in Fig. 8-21. Four-bit full adder ICs can be connected to form 8-, 12-, 16-, or even 32-bit parallel adders. A n 8-bit parallel adder is featured in Fig. 8-26. Note the Cin input to t he top 7483 IC is grounded (LOW). As in Fig. 8-24, this LOW a t Cin converts the 1s full adder to a half adder. The CO o utput of CHAP. 81 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS Binary addition problem + B4 B3 B2 B l z Cin A 3 Cin 4 FA A, z Sum output Fig. 8-24 Parallel adder using four full adders Fig. 8-25 Full a dder t ruth table 185 186 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS [CHAP. 8 Binary addition problem A 8' -+ "% B 8 B7 B 6 B 5 B4 B 3 B 2 B l A2 =4 A3 -- I Sum o utput Fig. 8-26 %bit parallel adder t he top 7483 IC is connected to the Cin input of t he bottom unit. This handles carries from the 8s to the 16s places. Other carries are handled internally in the 7483 parallel adder JCs. SOLVED PROBLEMS 8.35 Draw a diagram of an 8-bit parallel adder by using eight FAs. Solution: See Fig. 8-27. 8.36 R efer to Fig. 8-24. The 1s F A is converted to function as a by grounding the Cin input. Solution: The 1s FA in Fig. 8-24 is c onverted to a half adder by g rounding the Cin i nput. 8.37 R efer to Fig. 8-24. The conductors leading f rom t he CO of one FA to the Cin of the next FA are known as lines. CHAP. 81 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS 187 1 c Cin I z 1 Cin - Cin -I: J Cin M SB 1 28s Fig. 8-27 8-bit parallel adder circuit Solution: i Conductors leading from CO to C n (Fig. 8-24) are called carry lines. These lines pass carries from one FA to the next. 8.38 Refer to Fig. 8-24. When 0001 and 0001 a re added, the carry line between the 1s and 2s FAs is (HIGH, LOW). Solution: Binary addition problem: 0001 + 0001 = 0010 When 0001 and 0001 a re added (Fig. 8-24), a carry occurs between the 1s and 2s place and that carry line will be HIGH. 8.39 Refer to Fig. 8-24. Which carry lines are HIGH when binary 0111 and 0101 a re added? 188 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS [CHAP. 8 Solution: See Fig. 8-28. When 0111 and 0101 a re added in the device diagrammed in Fig. 8-24, three carry lines will be HIGH. They are the carry lines between: 1. 1s F A and 2s F A 2. 2s F A and 4s FA 3. 4s F A and 8s F A 1 ly 1 : : Oil il il +oi1;0;1 * , I I , I , , @ 1 L1 LO L O Fig. 8-28 Binary addition problem 8.40 T he block diagram in Fig. adder IC. (8-19, 8-24) most accurately describes the 7483 4-bit parallel Solution: T he block diagram in Fig. 8-24 describes the 7483 adder IC. 8.41 R efer to Fig. 8-26. What is the sum when the binary numbers 10011000 and 10101111 are added? Solution: See Fig. 8-29. 111 + 1001 loo0 10101111 10100Olll Sum Fig. 8-29 Binary addition problem 8-6 USING ADDERS FOR SUBTRACTION With minor changes, parallel adders can be used to perform binary subtraction. The 4-bit parallel adder shown in Fig. 8-24 can be modified slightly to form a subtractor circuit. A 4-bit parallel subtractor circuit is diagrammed in Fig. 8-30. Note that four full adders (FAs) a re used. Note also that data entering each full adder’s B input is inverted. Finally, note that the Cin input to the 1s F A (top full adder shown in Fig. 8-30) is held HIGH. The 4-bit parallel subtractor circuit shown in Fig. 8-30 will subtract the subtrahend ( B , B , B , B ) from the minuend ( A A A A 1. T he theory of operation of the circuit shown in Fig. 8-30 is based on a special mathematical technique outlined in Fig. 8-31. T he problem given in Fig. 8-31 is to subtract binary 0111 from 1110. The problem is solved across the top by using traditional decimal and binary subtraction. The three steps below detail how the subtraction problem would be solved by using adders and a 2s complement subtrahend. CHAP. 81 189 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS Binary subtraction A 4 A 3 A 2 A1 Minuend - B4 i pSJ J s J@ J2 4( s Difference Fig. 8-30 4-bit subtractor using full adders Follow the steps in Fig. 8-31 when solving the sample problem. Step 1 . Change the subtrahend to its 2s complement form.Only the subtrahend must be converted to its 2s complement equivalent. First the binary number 0111 is changed to its I s complement form (lOOO), and then 1 is added to form the 2s complement (1000 + 1 = 1001). S tep 2. A dd the minuend to the 2s complement subtrahend. T he original minuend is added to the 2s complement subtrahend to get a temporary result (1110 + 1001 = 10111 in this examp 1e). Step 3. Discard the overjlow. T he MSB is discarded, and the remaining 4 bits are equal to the binary difference. In this example the difference is binary 0111. T he reason why the circuit shown in Fig. 8-30 will work as a subtractor can now be explained. The four inverters change the binary subtrahend to its I s complement form (each 1 is changed to 0 and each 0 t o 1). T he HIGH a t the Cin input to the 1s F A is the same as adding 1 t o the subtrahend. The minuend and 2s complement subtrahend are added. The CO terminal of t he 8s F A is t he overjlow o utput. The CO o utput which discards the overflow is not displayed. + 190 [CHAP. 8 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS Decimal Problem: Binary 14 -7 __ 7 1110 Minuend 0111 Subtrahend -__01 1 1 Difference - ( a) Traditional decimal and binary subtraction - Step 0 C hange subtrahend t o 2s complement form. Binary Is complement Form 0111 1000 2s complement Add 1 1001 Step 0 A dd minuend to 2s complement subtrahend. 1 + 1110 Minuend 1001 2s complement subtrahend 10111 Step 0 Discard overflow. The difference is 01 11 in this example. 1110 Minuend 1001 2s complement subtrahend _ ____ @ 01 11 Difference + Discard overflow / ( h) Special technique subtraction using 2s complement subtrahend and addition Fig. 8-31 If the 4-bit parallel adder and subtractor circuits from Figs. 8-24 and 8-30 are compared, they are seen to be almost identical. These circuits can be combined to form an adder/subtractor circuit. Such a circuit is diagrammed in Fig. 8-32. The 4-bit parallel adder/subtractor circuit shown in Fig. 8-32 has an additional input called the mode control. If the mode control input is LOW (logical O), t he four X OK gates have no effect on the data at the B inputs (data passes through the X ORs and is not inverted). The Cin input to the 1s F A is held LOW, which makes the FA function as a half adder. A 4-bit sum will appear at the output indicators at the lower right. When the mode control of the adder/subtractor circuit shown in Fig. 8-32 is HIGH (logical I), t he four XOR gates act as inverters. The subtrahend ( B,B,B,B,) is inverted. The Cin input to the 1s F A is HIGH which is like adding + 1 t o the 1s complement subtrahend. The difference will appear at the lower right in Fig. 8-32 in binary form. SOLVED PROBLEMS 8.42 List three modifications that must be made to convert the 4-bit adder shown in Fig. 8-24 to a 4-bit parallel subtractor. Solution: See Fig. 8-30 for the solution. The modifications to the adder shown i n Fig. 8-24 a re (1) adding four inverters, (2) connecting Cin input of the 1s F A to H IGH, and (3) leaving the CO o utput from the 8s FA disconnected. 8.43 R efer to Fig. 8-32. The X OR gates act as inverters when the mode control is . Solution: T he XOR gates in Fig. 8-32 act as inverters when the mode control is HIGH (subtract mode). 191 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS CHAP. 81 Addition/sub traction A4 A3 A2 A 1 Cin I z: L AB 1 l L J B Mode control Subtract = 1 Add = 0 4 w Sum or difference Fig. 8-32 4-bit adder/subtractor circuit 8.44 Refer to Fig. 8-32. This circuit acts as a 4-bit parallel LOW. when the mode control input is Solution: T he circuit shown in Fig. 8-32 acts as a 4-bit parallel adder when the mode control input is LOW. 8.45 Use t he special technique shown in Fig. 8-31 to subtract binary 0110 from 1111. Solution: S ee Fig. 8-33. 8.46 Draw a diagram of a 4-bit parallel subtractor circuit by using a 7483 4-bit parallel adder IC and four inverters. Solution: See Fig. 8-34. 8.47 Refer to Fig. 8-30. When binary 0101 is subtracted from 1100, the difference is Solution: W hen binary 0101 is subtracted f rom 1100, t he difference is 011 1 (decimal 12 - 5 = 7 ). . 192 B INARY ARITHMETIC AND A RITHMETIC CIRCUITS Step 0 Binary - 1s complement Form 0110 1001 [CHAP. 8 2s complement Add 1 _ __) 1010 11 1111 + 1010 ___-11001 + 1 1 1 1 Minuend 1010 2s complement subtrahend 1001 Discard overflow Difference Fig. 8-33 Special technique for subtraction +5 A1 LSB Bll>o- 4 Bl A2 A3 B3 A4 A4 84 B4 ::E B2 B3 MSB B2 4-bit parallel a dder A2 A 3- I nputs v =3 I ( 7483) CO Difference A4A3A2A1 - B4 B 3 B 2 B l Fig. 8-34 4-bit parallel subtractor circuit P AP Refer tn Fio 8-?n T i c t t he R i nniitc tn t h e fniir F As w hen 0101 i subtracted from 1100. s Solution: The 1s c omplement of the subtrahend will appear at the B i nputs to the FAs shown in Fig. 8-30. If t he subtrahend equals 0101, the I s complement of t he subtrahend will be 1010. 8.49 R efer t o Fig. 8-30. When 0101 is subtracted from 1100, which carry lines will be HIGH? Solution: The FAs add 1100 (minuend) to 1011 (2s complement subtrahend), which means a carry occurs only a t CO of t he 8s F A. All t he carry lines in Fig. 8-30 will be LOW in this operation. CHAP. 81 193 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS 8-7 2s COMPLEMENT ADDITION AND SUBTRACTION T he 2s complement method of representing numbers is widely used in microprocessors. Until now, the numbers added or subtracted were positive numbers. However, microprocessors must add and subtract both positive and negative numbers. Using 2s complement numbers makes adding and subtracting signed numbers possible. A review of 2s complement numbers and their use in representing positive and negative values is given in Sec. 1-4. Addition or subtraction problem A8 A , A , A5A 4 A A A 1 B5 B4 B3 B2 B , ] 2s complement numbers U -I. B6 Mode c ontrol Subtract = I Add = 0 Cin ' L A c FA I O @@L Sign bit 2s c omplement sum or difference Fig. 8-35 8-bit parallel adder/subtractor circuit 194 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS [CHAP. 8 A circuit for adding and subtracting signed numbers in 2s complement notation is diagrammed in Fig. 8-35. This is an 8-bit parallel adder/subtractor that will add or subtract signed numbers. All inputs and outputs are in 2s complement form. Note that the 8-bit 2s complement adder/subtractor shown i n Fig. 8-35 is an extension of t he 4-bit adder/subtractor shown in Fig. 8-32. I f t he mode control shown in Fig. 8-35 is LOW, t he circuit adds. However, if t he mode control is HIGH, t he circuit performs as an 8-bit parallel subtractor. Four examples of adding 2s complement numbers are shown in Fig. 8-36. Two positive numbers are shown added in Fig. 8-36a. 2s complement addition looks exactly like binary addition when positive numbers are being added. The MSB is 0 in all three 2s complement numbers in Fig. 8-36a; therefore, all of them are positive. Note that the rules of binary addition are used. 11 ( + 27) +( 10) + + + 37io 1 0001 1011 2s complement augend 0000 1010 2s complement addend 0010 0107 2s complement sum (a) Adding two positive numbers 11111 111 ( - 1) + +(-3) _ ___ 1 11 1 11 1 1 2s complement augend 1 111 1101 2 scomplementaddend ,JB 1111 1100 -410 J 2s complement sum Discard (h) Adding two negative numbers + 11 1 ( + 20) ( - 50) _ _____ -3010 (c) 0001 0100 2s complement augend +_ _1_ _ 11~0_ 2s complement addend 1 00 _ 1 _ 11 10 0010 2s complement sum Adding a smaller positive to a larger negative number 111 ( + 40) + ( - 13) + 0010 loo0 2s complement augend 11110011 2s complement addend 2s complement sum d Discard ( d) Adding a larger positive to a smaller negative number Fig. 8-36 2s complement addition T he second example of 2s complement addition is detailed in Fig. 8-36b. Two negative numbers are being added. The MSB of a negative 2s complement number is a 1. In this example the 2s complement 11111111 is added to 11111101 to get 111111100. The overflow (MSB) of t he temporary sum is discarded, leaving a 2s complement sum of 11111100, Discarding the overflow is d one automatically in a digital system because the register used in this example is only 8 bits wide. A third example of 2s complement addition is given in Fig. 8-36c. A positive number is added to a larger negative number (OOOlOlOO + 11001110). The s um is 11100010, or a -30 in decimal. The fourth CHAP. 81 BINARY ARITHMETIC A ND ARITHMETIC CIRCUITS 195 example adds a positive number to a smaller negative number. When 00101000 is added to 11110011, t he result is 10001101 1. T he overflow (MSB) is discarded, leaving the sum of 0001101 1 . Four examples of 2s complement subtraction are shown in Fig. 8-37. Two positive numbers are subtracted in Fig. 8-37a. T he + 41 is converted to its 2s complement form (00101001), and then it is 2s complemented again to get a subtrahend of 11010111. T he minuend and subtrahend are then added t o get 1 00100010. T he overflow ( MSB) is discarded, leaving a 2s complement difference of 00100010, o r + 34 in decimal. ( + 75) - ( + 41) 0010 1001 Form 2 s complement b and add a ,) + 0100 1011 Minuend 1101 0111 Subtrahend 00100010 2s complement difference _-__. Discard ( a ) Subtracting two positive numbers 11 ( - 80) - (-30) Form 2 s complement 11100010 + and add 1011 o000 Minuend Oool 1110 Subtrahend 1100 1110 2s complement difference ( b ) Subtracting two negative numbers ( + 24) - (-20) + 44m 1 1110 1100 Form 2 s complement b and add o0o11000 Minuend + o0o10100 Subtrahend _ ______ 0010 1100 2s complement difference i c) Subtracting a negative from a positive number 11 Form 2 s complement and add + 1100 0100 Minuend Subtrahend 2s complement difference + 1 1 1 1 O001 iB 101 1 0101 / rc Discard Subtracting a positive from a negative number Fig. 8-37 2s complement subtraction T he second example of 2s complement subtraction is detailed in Fig. 8-37b. Two negative numbers are subtracted. The minuend ( - 8 0) is converted to its 2s complement form (10110000). T he subtrahend ( - 3 0 ) is 2s complemented twice to get first 11100010 and finally 00011110. T he 2s complement difference is 11001 110 ( - 50) when the minuend and subtrahend are a dded. T he third example of 2s complement subtraction is explained in Fig. 8-37c. A -20 is subtracted from a + 24. T he - 20 is 2s complemented twice to get the temporary 11101100 and the final subtrahend of 00010100. T he subtrahend (OOOlOlOO) is then added to t he minuend (00011000) t o get the 2s complement difference of 00101 100, o r + 44 in decimal. The final example of 2s complement subtraction is given i n Fig. 8-37d. A + 15 is subtracted from - 60. T he minuend ( - 60) is converted to its 2s complement form (1 1000100). T he subtrahend ( + 15) is 2s complemented twice to get the temporary 00001111 and the final subtrahend of 11110001. T he minuend ( 1 1000100) and subtrahend (1 1110001) a re added to get 1 10110101. The overflow (MSB) is discarded, leaving a 2s complement difference of 10110101, or - 75 in decimal. 196 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS [CHAP. 8 All the sample problems can be tested by using the 8-bit parallel adder/subtractor shown in Fig. 8-35. R emember that both the inputs to and outputs from the adder/subtractor circuit shown in Fig. 8-35 must be in 2s complement notation. SOLVED PROBLEMS 8.50 Why are 2s complement numbers used in digital systems? Solution: 2s complement numbers are used to represent signed numbers. 8.51 R efer to Fig. 8-35. This circuit can add or subtract numbers. Solution: The circuit shown in Fig. 8-35 can add or subtract signed numbers in 2s complement notation. B2 -IdB2 A4 A4 ( 7483) I 2s c omplement inputs A5 Gr ( 7483) MSB B Mode control Subtract = 1 A dd = 0 8 p B 4 cot Sign bit 2s c omplement s um or d ifference Fig. 8-38 8-bit adder/subtractor circuit 8.52 Draw a diagram o f an 8 -bit parallcl a ddcr/subtrnctor by using two 7483 ICs and cight XOK gatcs. Usc i;igs. 8 -34 a nd 8 -35 a \ :I g uide. Solution: S ec Fig. X -38. 8.53 Kefcr t o Fig. 8 -35. Thc numhcrs input i nto thc addcr/subtractor must be in what code? Solution: The number\ inpiit i nto thc ddtlcr/\iibtractor 5 h w n i n b ig. 8 -35 mu\[ bc i n 2s coniplemcnt notation. 8.S Kcfer t o Fig. 8 -35. W hat d o inputs A , and II, rcprcscnt'! Solution: Inputs A , m d ! I, 111 I -ip. S-35 rcpruwnt t hu !.igns of t hc nunibcrr. I f t he pviitivc: i f thc \ipii h it i \ I . tlic iiuiiilxr i 5 i icx;rtivc. 8.55 A dd + 83 a nd + 17 h y sign bit IS 0 , t he number i s using 2 s coniplement r iunihcr5. IJsc t hc prtxcdurc s hown in F ig. 8 -36. Solution: Scc Fig. X -3q. (+U) +( + 17) +1010 I + 2s complement augend 2s complement addend 0110 0100 2s complement 5uni Fig. 8-39 Solution to 8.56 II 0101 001 I O001 OOOI 25 complcmcnt a ddition problem Add + 1 1 0 iind - 13 by w i n g 25 c omplcnicnt nunibcrk. I:sc thc p rtnxiurc illustrated i n I - i g 8-30. Solution: Sec F ig. WO. 8.57 Subtract + I 0 from t M by using 2 s coniplcnicnt numhcrs. U w t he procedure illustrated i n Fig. 8 -37. S o h t ion: Scc Fig. S -41. I98 H INARY ARITHMETIC A X D ARITt IMETIC CIRCC!ITS ( +U) - ( + 26) I 2 s c omplement ' +38,0 2 1 c omplement Oool a ndadd '+ @ , J M inuend I I1001 10 S ubtrahcnd oOlO~Ol1O 2s c omplcmcnt diffcrcncc 0100oooO Disc;i;tI Fig. 8 41 S olution t o 8.58 3 c omplcrncnt subtraction prohlcm S ubtract - 23 f roni - 53 by usirig 2 s c oniplcnicnt n unihcrs. IJsc r hc prcwctlurc illrr\trawd i n 1--1g. x-37. Solution: S CC F ig. 8 -42, II Ill (-53) ( - 2 3) - 3010 2 scnmplerncnt ' 1 1 10 1001 2 s c omplcmcnt and add + I I 0 0 1 0 1 1 h finucnd OOO1 011 I S ubtrahend I 1 10 0010 2s c omplcmcnt difference Fig. 8-42 S olution to 3 c ornplcmcnt subtraction prohlcm Supplementary Problems 8.60 8.61 Givc thc I cttcr symbol for the f ollowing inputs to a n d output5 f r o i r i ;I I i;ilf ;ttltlcr (IIA): ( a1 t op i nput. ( h ) b ottom input. ( c ) s um output. ( d 1 c a r n o utput. Ans. ( a ) t op i nput - A ( h ) b ottom input = H ( c.) sun1 o utpiit - L (cf) u r p o utput G ivc thc l cttcr symbol for the f ollowing input\ to a n d outputs from ;i f ull a tldcr ( FI\): ( a ) carry i nput. ( h ) top d a t a input. ( c ) h ottom d ata i nput. ( ( 1 ) sun1 output. o utput. Airs. ( a ) carry i nput = ('in ( c ) b ottom d a t a input R ( c ) c arp o utput ' . C I J ( h ) t op d ata i nput A ( ( 1 ) s um output 2: *A - (c) = ('o carn i 8.62 D r a w a logic d iagram of a n H A c ircuit using gatch. 1,;ihcl t h c inputs iind ouiputs. Anc. Scc Fig. 8 -Zh. 8.63 Draw :i logic diagram o f a n FA c ircuit b) u sing X OR a n d N A S D gatcs o nly. 1;rhcl t hc input5 iind A m. S cc F ig. 8-43. i outputs. U s c Fig. 8-6 a s ; g uide. 199 BINARY ARITHMETIC AND ARITHMETIC CIRCUITS CHAP. 81 Fig. 8-43 Full adder logic diagram using XOR a nd N AND g ates 8.64 An HA will add two variables, and an F A will add 8.65 List the full adder C o utputs for each set of input pulses shown in Fig. 8-44. A ns. pulse a = 1 pulse c = 1 pulse e = 0 pulse g = 1 pulse i = 0 pulse b = 0 pulse d = 1 pulse f = 1 pulse h = 0 pulse j = 0 j i h g f e d c b Register to View Answerhree input variables. a Fig. 8-44 Full adder pulse-train problem 8.66 8.67 List the full adder CO o utputs for each set of i nput pulses shown in Fig. 8 -44. A ns. pulse a = 1 pulse c = 0 pulse e = 0 pulse g = 0 pulse i = 1 pulse b = 1 pulse d = 0 pulse f = 1 pulse I ! = 1 pulse j = 0 Solve the following binary subtraction problems: (a) 11011 -01110 A ns. ( a ) 1101 (b) 11100 -01110 ( b ) 1110 (c) ( c) 1111 11001 - 01010 ( d ) 0111 (d) 10000 - 01001 (e) 10111 - 10001 ( e ) 0110 8.68 Give the names of the following inputs to and outputs from a half subtractor: (a) A, ( b ) B, ( c ) Di, ( d ) B o. A m. ( a ) A = m inuend input ( c) D = d ifference output i ( 6) B = s ubtrahend input ( d ) B o = b orrow output 8.69 Give the letter symbols for the following inputs to and outputs from the FS: ( a ) borrow input, ( b ) m inuend input, ( c) s ubtrahend input, ( d ) difference output, ( e ) borrow output. A ns. ( a ) borrow input = Bin ( c) s ubtrahend input = B ( e) borrow output = B o ( b ) m inuend input = A ( d ) d ifference output = D i 200 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS [CHAP. 8 8.70 R efer to Fig. 8-19. T he A , and B , inputs are from the problem. Ans. 2s 8.71 R efer to Fig. 8-20. T he A , and B , inputs are from the Ans. 4s problem. 8.72 Refer to Fig. 8-20. If all inputs to the 4s FS are 1, the output from this FS will be D i = and Bo= . Am. When all inputs to the 4s FS shown in Fig. 8-20 a re HIGH, the outputs will be Di = 1 and Bo = 1 . This is based on line 8 of the FS truth table in Fig. 8-15. 8.73 R efer to Fig. 8-45. T he outputs from the 1s HS are Di = (c) (Is, 2s, 4s, 8s) column of the addition ( Is, 2s, 4s, 8s) column of t he subtraction (a) and Bo = (b) according to line in the truth table in Fig. 8-11. Problem 100 1 - 00 1 1 I Bin Di I Bin Di Difference Fig. 8-45 Parallel-subtractor circuit problem 8.74 Refer to Fig. 8-45. T he inputs to the 2s FS are A = ,B= , and Bin = with outputs of Di = and Bo = according to line in the truth table in Fig. 8-15. Ans. The inputs to t he 2s FS (Fig. 8-45) a re A = 0, B = 1, and Bin = 0 with outputs of Di = 1 and Bo = 1 according to line 3 in Fig. 8-15. 8.75 ,B= , and Bin = -with Refer to Fig. 8-45. T he inputs to the 4s FS are A = outputs of D = i and Bo = according to line in the truth table in Fig. 8-15. Register to View Answerhe inputs to the 4s FS (Fig. 8-45) a re A = 0, B = 0, andBin = 1 with outputs of Di = 1 and Bo = 1 according to line 2 in Fig. 8-15. CHAP. 81 201 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS 8.76 -, B = , and Bin = with R efer to Fig. 8-45. The inputs to the 8s FS are A = i and B o = according to line in the truth table in Fig. 8-15. outputs of D = Register to View Answerhe inputs to the 8s FS in Fig. 8-45 are A = 1, B = 0, and Bin = 1 with outputs of D i = 0 and Bo = 0 according to line 6 in Fig. 8-15. 8.77 Refer to Fig. 8-45. The difference showing on the indicators is a binary . 8.78 Refer to Fig. 8-45. This unit is a Ans. 4-bit parallel subtractor (adder, subtractor). 8.79 List the binary differences at the output indicators of the 4-bit parallel subtractor circuit shown in Fig. 8-46. Ans. The differences for the pulses shown in Fig. 8-46 are as follows: pulse c = 0100 pulse g = 0001 pulse i = 0011 pulse e = 001 1 pulse a = 0010 pulse 6 = 1000 pulse d = 1001 pulse f = 0011 pulse h = 0111 pulse j = 1101 -bit (parallel, serial) A m. 0110, L Minuend . Subtrahend I I I Difference output indicators Fig. 8-46 Parallel-subtractor pulse-train problem HS(s) and FSs. 8.80 Refer to Fig. 8-46. The subtractor probably contains Ans. ( a ) one ( 6 ) three 8.81 Refer to Fig. 8-46. The subtractor circuit is classified as a circuit. Ans. combinational 8.82 Refer to Fig. 8-24. What is t he effect of grounding the 1s full a dder Cin input? Ans. Grounding the 1s FA Cin input shown i n Fig. 8-24 has the effect of converting the 1s full a dder to a half adder. 8.83 T he 7483 TTL I C is described as a 4-bit Ans. parallel 8.84 Refer to Fig. 8-26. What is the sum when the binary numbers 11101010 and 01001110 are added? Ans. sum = 100111000 (a) (b) (combinational, sequential) logic (parallel, serial) adder DIP integrated circuit. 202 BINARY ARITHMETIC AND A RITHMETIC CIRCUITS [CHAP. 8 8.85 Refer to Fig. 8-26. What is the highest sum that could be generated by the 8-bit parallel adder? Ans. 1 1111111 + 1 1111111 = 1 11111110, (255 + 255 = 5 10,,). 8.86 Refer to Fig. 8-32. The XOR gates act like H IGH. Ans. inverters 8.87 Refer to Fig. 8-32. This circuit acts as a 4-bit parallel Ans. subtractor 8.88 Draw a diagram of an 8-bit parallel adder/subtractor using eight FAs and eight XOR gates. Ans. See Fig. 8-47. (AND gates, inverters) when the mode control is when the mode control input is HIGH. A ddition o r subtraction p roblem I' I C in + B6 A7 B7 Mode control Subtract = 1 Add = 0 -: I A FA ~ - @@@@@@(hJ@ Sum or difference Fig. 8-47 8-bit parallel adder/subtractor circuit CHAP.81 8.89 B INARY ARITHMETIC AND A RITHMETIC CIRCUITS 203 R efer to Fig. 8-35. The output from the adder/subtractor is in what code? 2s complement notation Am. 8.90 R efer to Fig. 8-35. Why does this adder/subtractor circuit specify the use of 2s complement numbers? Ans. 2s complement notation is one method of representing signed numbers in digital circuits. 8.91 R efer to Fig. 8-35. The MSB in the result (sum or difference) is t he Ans. sign (0 = positive or 1 = negative) 8.92 bit. A dd + 18 to - 55 by using 2s complement numbers. Use the procedure shown in Fig. 8-36. Ans. S ee Fig. 8-48. ( + 18) +( - 55) -3710 + 0o010010 2s complement augend 1100 1001 2s complement addend 1101 1011 2s Complement sum Fig. 8-48 Solution to 2s complement addition problem 8.93 Subtract - 14 from +47 by using 2s complement numbers. Use the procedure shown in Fig. 8-37. Ans. S ee Fig. 8-49. ( + 47) -(- 14) _ ___ + 6LO -1111 0010 1 I1 + 0010 1111 Minuend oo00 1110 Subtrahend 001 1 1101 2s complement difference _ _ _ _ I _ Fig. 8-49 Solution to 2s complement subtraction problem Chapter 9 Flip-Flops and Other Multivibrators 9 -1 INTRODUCTION Logic circuits are classified in two broad categories. The groups of gates described thus far‘have been wired as combinational logic circuits. In this chapter a valuable type of circuit will be introduced: the sequential logic circuit. T he basic building block of combinational logic is the logic gate. The basic building block of the sequential logic circuit is the flip-flop circuit. Sequential logic circuits are extremely valuable because of their m emory characteristic. Several types of flip-flops will be detailed in this chapter. Flip-flops are also called “latches,” “bistable multivibrators,” or “binaries.” The term “flip-flop” will be used in this book. Useful flip-flops can be wired from logic gates, such as NAND gates, or bought in IC form. Flip-flops are interconnected to form sequential logic circuits for data storage, timing, counting, and sequencing. Besides the bistable multivibrator (flip-flop), two o ther types of multivibrators (MVs) a re introduced in this chapter. The astable multivibrator is also called a free-running M V. T he astable MV produces a continuous series of square-wave pulses and is commonly used as a clock in a digital system. The monostable multiuibrator is also called a one-shot M V in that i t produces a single pulse when triggered by an external source. 9-2 RS FLIP-FLOP T he most basic flip-flop is called the RS flip-flop. A block logic symbol for the RS flip-flop is shown in Fig. 9-1. T he logic symbol shows two inputs, labeled set ( S) and reset ( R ) ,on the left. The RS flip-flop in this symbol has active LOW inputs, shown as small bubbles at the S and R inputs. Unlike logic gates, flip-flops have two complementary outputs. The outputs are typically labeled Q a nd (say “not Q o r Q not”). The Q o utput is considered the “normal” output and is t he one most used. The other output ( 12) is simply the complement of output Q, and it is referred to as the complementary output. Under normal conditions these outputs are always complementary. Hence, if Q = 1, t hen = 0; o r if Q = 0, then = 1. a Reset R f Complementary Fig. 9-1 Logic symbol for RS flip-flop T he RS flip-flop can be constructed from logic gates. A n RS flip-flop is shown wired from two NAND gates in Fig. 9 -2a. Note the characteristic feedback from the output of one NAND gate into the input of the other gate. As with logic gates, a truth table defines the operation of the flip-flop. Line 1 of the truth table in Fig. 9 -2b is called the prohibited state in that it drives both outputs to 1, o r HIGH. This condition is not used on the RS flip-flop. Line 2 of the truth table shows the set condition of t he flip-flop. Here a LOW, or logical 0, activates the set ( S ) input. That sets the normal Q o utput to HIGH, or 1, as shown in the truth table. This set condition works out if t he NAND circuit shown in Fig. 9 -2a is analyzed. A 0 a t gate 1 generates a 1 a t output Q . This 1 is fed back to gate 2. Gate 2 now has two 1s applied to its inputs, which forces the output to 0. O utput is therefore 0, or LOW. Line 3 in Fig. 9 -2b is the reset condition. The LOW, or 0, activates the reset input. This clears (or resets) the normal Q o utput to 0. T he fourth line of the table shows the disabled, or h old, condition of the R S 204 205 FLIP-FLOPS AND OTHER MULTIVIBRATORS C HAP. 91 Mode of operation Q Inputs Prohibited Set Reset Hold S--o 00 S 0 outputs QQ R 1 1 1 10 11 1 0 01 no change (6) T ruth table ( a) Wired using N AND gates Fig. 9-2 RS flip-flop flip-flop. The outputs remain a s they were before the hold condition existed. There is no change in the outputs from their previous states. Note that, when the truth table in Fig. 9-2b refers to the ser condition, it means setting output Q t o 1. Likewise, the reset condition means resetting (clearing) output Q t o 0 . T he operating conditions i therefore refer to the normal output. Note that the complementary output ( 0)s exactly the opposite. Because of its typical function of holding data temporarily, the RS flip-flop is often called the RS latch. RS latches can be wired from gates or purchased in IC form. Think of the RS flip-flop as a memory device that will hold a single bit of data. SOLVED PROBLEMS 9.1 Refer to Fig. 9-1. This RS flip-flop has active (HIGH, LOW) inputs. Solution: As indicated by the small bubbles at the inputs of t he logic symbol in Fig. 9-1, t he RS flip-flop has active LOW inputs. 9.2 If the normal output of the RS flip-flop is HIGH, then output Q = (0, 1 ). Solution: If t he normal output of the RS flip-flop is HIGH, then output Q = 1 a nd 9.3 Activating the reset input with a Q t o a logical ( 0, 1). (HIGH, LOW) effectively - ( 0,l) and Q = 0 = 0. (clears, sets) output Solution: Activating the reset input with a LOW clears output Q t o 0. 9.4 List the binary o utputs at the normal output ( Q) of t he RS flip-flop shown in Fig. 9-3. j i h g f e d c b a +-PI-? Fig. 9-3 RS flip-flop pulse-train problem 206 Solution: The binary outputs at output Q shown in Fig. 9-3 are as follows: pulse j pulse g = 1 pulse d = 0 pulse a = 1 pulse h = 1 pulse b = 1 pulse e = 0 pulse i = 1 (prohibited state) pulse c = 0 pulse f = 0 9.5 List the binary o utputs at output =0 of the RS flip-flop shown in Fig. 9-3. Solution: (Fig. 9-3) are as follows: The binary outputs at output pulse d = 1 pulse g = 0 pulse a = 0 pulse e = 1 pulse h = 0 pulse b = 0 pulse i = 1 (prohibited state) pulse f = 1 pulse c = 1 9.6 [CHAP. 9 FLIP-FLOPS AND OTHER MULTIVIBRATORS pulse j = 1 List the mode of operation of t he RS flip-flop for each input pulse shown in Fig. 9-3. Solution: The modes pulse a = set pulse b = hold pulse c = reset of operation of the pulse d = hold pulse e = reset pulse f = hold RS flip-flop (Fig. 9-3) are as follows: pulse g = set pulse j = reset pulse h = hold pulse i = prohibited 9-3 CLOCKED RS FLIP-FLOP T he basic R S latch is an asynchronous device. I t does n ot o perate in step with a clock or timing device. When an input (such as the set input) is activated, the normal output is immediately activated just as in combinational logic circuits. Gating circuits and RS latches operate asynchronously. The clocked R Sflip-flop adds a valuable synchronous feature to the RS latch. The clocked R S flip-flop operates in step with the clock o r timing device. I n o ther words, it o perates synchronously. A logic symbol for the clocked R S flip-flop is shown in Fig. 9-4. It has the set ( S ) and reset ( R ) inputs and the added clock (CLK) input. The clocked R S flip-flop has the customary normal output ( Q ) and complementary output (Q). Set I nputs Clock- Reset-R FF Q O utputs CLK 0- Fig. 9-4 Logic symbol for clocked RS flip-flop T he clocked R S flip-flop can be implemented with NAND gates. Figure 9-5a illustrates two NAND gates being added to the RS latch (flip-flop) to form the clocked RS flip-flop. NAND gates 3 and 4 add the clocked feature to the RS latch. Note that just gates 1 and 2 form the RS latch, or flip-flop. Note also that, because of the inverting effect of gates 3 and 4, the set ( S) and reset ( R ) inputs are now active HIGH inputs. The clock (CLK) input triggers the flip-flop (enables the flip-flop) when the clock pulse goes HIGH. The clocked RS flip-flop is said to be a level-triggered device. Anytime the clock pulse is HIGH, the information at the data inputs ( R and S ) will be transferred to the outputs. It should be emphasized that the S and R inputs are active during the entire time the clock pulse level is HIGH. The HIGH of the clock pulse may be thought of as an enabling pulse. FLI P-FLOPS A N D OTI 1ER MULTI V 1B RAT0R S 207 Fig. 9-5 C lwkcd RS flip-flop T he truth table i n Fig. 9-56 details the opcration of thc clockcd RS flip-flop. Thc hold modc of operation is described i n linc 1 of thc truth tablc. When a clock pulsc arrives at the CLK input ( with 0s a t thc S and R inputs), thc outputs (10 r roi c.lrurip. T he outputs stay the same as they wcrc bcforc thc clock pulse. This modc might also bc dcscribcd as the disahktcl condition of the flip-flop. Line 2 is thc rcsct mode. The normal output ( Q ) will bc clcarcd or reset to 0 when a HIGH activates thc R input and a clock pulse arrives at the CLK input. I t will tw: notcd that just placing R = 1 a nd S = 0 docs not immcdiatcly r c x t the flip-flop. The flip-flop waits u ntil the clock pulsc goes from LOW to HIGH,a nd then thc flip-flop resets. This u nit operates synchronously, or in s tcp with t h e clock. Line 3 of the truth tablc describes the set condition of the flip-flop. A H IGH activatcs the S input (with R = 0 and a H IGH clock pulsc), sctting thc Q output to 1. Line 4 o f thc t ruth tahlc is a prohibited combination (all inputs 1 ) a nd is not used because i t drives b oth outputs HIGH. Warefornu, or riming diagranrs, a rc widely used and are quite u seful for working w ith flip-flops and scqucntial logic circuits. Figure 9-6 i s i timing diagram for the clocked R S flip-flop. The top three l lincs rcprcscnt thc binary signals at thc clock, set, and rcsct inputs. O nly a single output ((2) is shown across the bottom. Beginning at the Icft. clock pulsc 1 arrives but has no effect on Q because inputs S and R a rc in the hold mode. Output Q therefore stays at 0. At p oint a o n the timing diagram, the set input is activated t o a HIGH. After a timc at point 6. output Q is sct to 1 . Notc that thc flip-flop waited u ntil clock pulsc 2 started t o go f rom LOW to HIGH before output Q was s ct. Pulsc 3 scnscs the inputs ( R and S ) i n the hold modc, and thcrcforc the output does not change. At p oint c the rcsct input is activatcd with a €iIGIi. A short time latcr at p oint d, output Q is cleared. or reset to 0. Again t his happens on the LOW-to-HIGH transition of the clock pulsc. Point c senses the sct input activated, which sets output Q to 1 a t point f o n thc timing diagram. Input S i s deactivated and R is activated before pulse 6, which causes output @ t o go t o I,OW, o r t o the reset condition. Pulse 7 shows that output Q follows inputs S and R the entire timc thc clock is HIGH. At p oint g on thc timing diagram i n Fig. 9-6, thc sct input (S)goes HIGH and the Q output follows by going HIGH. Input S then g w s LOW. Next the rcsct input ( R ) is activated by a H IGH at p oint h . T hat causes Fig. 9-6 Wavcform diagram for clocked RS flip-flop 208 FLIP-FLOPS A ND O THER MULTIVIBRATORS [CHAP. 9 o utput Q t o reset, or go LOW. Input R t hen returns to LOW, and finally clock pulse 7 e nds with a HIGH-to-LOW transition. During clock pulse 7, t he output was set t o HIGH and then reset t o LOW. N ote that between pulses 5 and 6 it appears that both inputs S and R a re at 1. T he condition of inputs R and S b oth being HIGH would normally be considered the prohibited state for the flip-flop. In this case it is acceptable for both R and S to be HIGH because the clock pulse is LOW and the flip-flop is not activated. SOLVED PROBLEMS 9.7 R efer to Fig. 9-4. T he reset and set inputs on the clocked RS flip-flop are said to be active ( HIGH, LOW) inputs. Solution: T he R and S inputs are active HIGH inputs on the clocked RS flip-flop shown in Fig. 9-4. 9.8 A flip-flop that operates in step with the clock is said to operate synchronously). (asynchronously, Solution: A flip-flop that operates in step with the clock operates synchronously. 9.9 T he RS latch operates (asynchronously, synchronously). Solution: T he RS latch operates asynchronously. 9.10 T he clocked RS flip-flop operates (asynchronously, synchronously). Solution: T he clocked RS flip-flop operates synchronously. 9.11 Draw the logic symbol of a clocked R S flip-flop by using NAND gates. Solution: See Fig. 9-5a. 9.12 List the binary o utput at clock pulses. Solution: T he binary outputs at follows: pulse 3 = 0 pulse 1 = 1 pulse 2 = 0 pulse 4 = 1 9.13 for the clocked RS flip-flop shown in Fig. 9-6 during the input in this flip-flop are the opposite of those at the Q o utput. They are as pulse 5 = 0 pulse 6 = 1 pulse 7 = 1 , then 0, and then 1 List the binary o utput at Q for the flip-flop of Fig. 9-7 during the eight clock pulses. CHAP. 91 FLIP-FLOPS AND OTHER MULTIVIBRATORS 209 Fig. 9-7 Clocked RS flip-flop pulse-train problem Solution: T he binary outputs at Q for the clocked R S flip-flop of Fig. 9-7 are as follows: pulse g = 1 pulse e = 0 pulse a = 1 pulse c = 1 pulse f = 1 (prohibited condition) pulse h = 1 pulse b = 1 pulse d = 0 9.14 List the mode of operation of the flip-flop of Fig. 9-7 during the eight clock pulses (use terms: hold, reset, set, prohibited). Solution: The operational modes for the clocked RS flip-flop of Fig. 9-7 are as follows: pulse g = set pulse e = hold pulse c = set pulse a = set pulse f = prohibited pulse h = hold pulse b = hold pulse d = reset 9.15 Refer to Fig. 9-6. T he clocked RS flip-flop is level-triggered, which means the unit is enabled during the entire (HIGH, LOW) portion of the clock pulse. Solution: The flip-flop of Fig. 9-6 is level-triggered, which means it is enabled during the entire HIGH portion of the clock pulse. 9-4 D FLIP-FLOP T he logic symbol for a common type of flip-flop is shown in Fig. 9-8. T he D flip-flop has only a o utputs are shown on the single d ata input ( D ) and a clock input (CLK). T he customary Q and right side of the symbol. The D flip-flop is often called a delay flip-flop. This name accurately describes the unit's operation. Whatever the input at the data ( D ) point, it is deluyed from getting to the normal output ( Q ) b y one clock pulse. D ata is transferred to the output on the LOW-to-HIGH transition of the clock pulse. a Inputs Clock outputs Fig. 9-8 Logic symbol for D flip-flop The clocked RS flip-flop can be converted to a D flip-flop by adding an inverter. That conversion is shown in the diagram in Fig. 9 -9u. Note that the R input to the clocked RS flip-flop has been inverted. 210 Data’al fr FLIP-FLOPS A ND O THER MULTIVIBRATORS [CHAP. 9 Preset (set) Clock CLK F F Clock (7474) Q Clear (reset) ( a ) D flip-flop wired from clocked R S flip-flop ( h ) Logic s ymbol for 7474 D flip-flop with asynchronous inputs Fig. 9-9 A commercial D flip-flop is shown in Fig. 9-9b. T he D flip-flop in Fig. 9-9b is a TTL device described by the manufacturers as a 7474 IC. The logic symbol for the 7474 D flip-flop shows the regular D and CLK inputs. Those inputs are called the synchronous inputs, for they operate in step with the clock. The extra two inputs are the asynchronous inputs, and they operate just as in the RS flip-flop discussed previously. The asynchronous inputs are labeled preset ( P E ) a nd clear (CLR). The preset ( P R ) input can be activated by a LOW, a s shown by the small bubble on the logic symbol. When the preset ( P R ) is activated, i t sets the flip-flop. I n o ther words, i t places a 1 at the normal output ( Q,. It presets Q t o 1 . T he clear (CLR) input can be activated by a LOW, as shown by the small bubble on the logic symbol. When the clear (CLR) input to the D flip-flop is activated, the Q o utput is reset, or cleared to 0. T he asynchronous inputs o rwride the synchronous inputs on this D flip-flop. A t ruth table for the 7474 D flip-flop is in Fig. 9-10. T he modes of operation are given on the left and the truth table on the right. The first three lines are for asynchronous operation (preset and clear inputs). Line 1 shows the preset ( P R )input activated with a LOW. That sets the Q o utput to 1. Note the X’s under the synchronous inputs (CLK and D ) . T he X’s mean that these inputs are irrelevant because the asynchronous inputs override them. Line 2 shows the clear ( CLR) input activated with a LOW. This results in output Q being reset, or cleared to 0. Line 3 shows the prohibited asynchronous input (both PR and CLR at 0). T he synchronous inputs ( D and CLK) will operate when both asynchronous inputs are disabled ( P R = 1 , CLR = 1 ). Line 4 shows a 1 a t the data ( D ) input and a rising clock pulse (shown with the upward arrow). The 1 a t input D is transferred t o o utput Q on the clock pulse. Line 5 shows a 0 a t the data ( D ) input being transferred to output Q on the LOW-to-HIGH clock transition. Inputs Asynchronous Mode of outputs Synchronous operation PR CLR CLK D Asynchronous set Asynchronous reset Prohibited Set Reset 0 1 1 1 1 X X X T 1 X 0 1 0 0 1 x X Q Q 1 0 1 1 0 1 o 1 1 1 0 0 Fig. 9-10 Truth table f or 7474 D flip-flop CHAP. 91 21 1 FLIP-FLOPS AND OTHER M ULTIVIBRATORS Only the bottom two lines of the truth table in Fig. 9-10 are needed if t he D flip-flop does not have the asynchronous inputs. D flip-flops are widely used in data storage. Because of this use, it is sometimes also called a data flip-flop. Look at the D flip-flop symbols shown in Figs. 9-8 and 9-96. Note that the clock (CLK) input in Fig. 9-9b has a small > inside the symbol, meaning that this is an edge-triggered device. This edge-triggered flip-fop transfers data from input D t o output Q on the LOW-to-HIGH transition of the clock pulse. In edge triggering, it is t he change of the clock from LOW to HIGH (or H to L) that transfers data. Once the clock pulse is HIGH on the edge-triggered flip-flop, a change in input D will have no effect on the outputs. Figures 9-8 and 9-9a show a D flip-flop that is leuel-triggered (as opposed to edge-triggered). The absence of t he small > inside t he symbol at the clock input indicates a level-triggered device. On a level-triggered flip-flop, a certain voltage level will cause the data at input D to be transferred to output Q. T he problem with the level-triggered device is that the output will follow the input if t he input changes while the clock pulse is HIGH. Level triggering, or clocking, can be a problem if input data changes while t h e clock is HIGH. SOLVED PROBLEMS 9.16 What two other names are given to the D flip-flop? Solution: T he D flip-flop is also called the d elay a nd the d ata flip-flop. 9.17 Draw a logic diagram of a clocked R S flip-flop and inverter wired as a D flip-flop. Solution: S ee Fig. 9 -9a. 9.18 Draw the logic symbol for a D flip-flop. Label inputs as D , CLK, P R , and CLR. Label outputs as Q and Q. Solution: S ee Fig. 9-9b. 9.19 T he data bit at the D input of the 7474 D flip-flop is transferred to output the (H-to-L, L-to-H) transition of t he clock pulse. (Q, e)on Solution: The data at the D input of a D flip-flop is t ransferred to output Q on the L-to-H transition of t he clock pulse. 9.20 Refer to Fig. 9-10. An X in the truth table stands for an (extra, irrelevant) input. Solution: An X i n the truth table stands for an irrelevant input. An X input can be either 0 o r 1 and has no effect on the output. 9.21 List the binary outputs at the complementary output each of the clock pulses. (e)of the D flip-flop of Fig. 9-11 after 212 FLIP-FLOPS AND O THER MULTIVIBRATORS 0 1 1 0 1 1 1 0 1 0 1 I 1 O 0 I h g f d e 0 1 1 [CHAP. 9 b 1 1 1 - 1 CLK ( 7474)Q CkR ? 1 Fig. 9-11 D flip-flop pulse-train problem Solution: Refer to the truth table in Fig. 9-10. The binary outputs at of the D flip-flop (Fig. 9-11) are as follows: pulse a = 0 pulse e = 0 pulse g = 0 pulse c = 0 pulse h = 1 (prohibited state) pulse b = 1 pulse d = 1 pulse f = 1 9.22 R efer to Fig. 9-11. Which input has control of t he flip-flop during pulse a ? Solution: T he preset (PI?)nput is activated during pulse a and overrides all other inputs. It sets the Q output i t o 1. 9.23 Refer to Fig. 9-11. Just before pulse 6, o utput Q is (HIGH, LOW); during pulse 6, o utput Q is (HIGH, LOW); on the H-to-L clock-pulse transition, output Q is ( HIGH, LOW). Solution: Just before pulse b, output Q is HIGH; during pulse b , output Q is LOW; on the H-to-L clock-pulse transition, output Q is LOW. 9-5 J K FLIP-FLOP T he logic symbol for a J K flip-flop is shown in Fig. 9-12. This device might be considered the universal flip-flop; other types can be made from it. The logic symbol shown in Fig. 9-12 has three synchronous inputs ( J , K , and CLK). The J a nd K inputs are data inputs, and the clock input transfers data from the inputs to the outputs. The logic symbol shown in Fig. 9-12 also has the customary normal output ( Q ) and complementary output (D). Inputs Clock outputs K Fig. 9-12 Logic symbol for J K flip-flop A t ruth table for the JK flip-flop is in Fig. 9-13. The modes of operation are given on the left and the truth table is on the right. Line 1 of the truth table shows the hold, or disabled, condition. Note that both data inputs ( J and K ) a re LOW. The reset, or clear, condition of t he flip-flop is shown in 213 FLIP-FLOPS AND OTHER MULTIVIBRATORS CHAP. 91 Inputs Outputs operation Hold Reset Set Toggle n o n n n o change 0 1 1 0 opposite state 0 1 O 1 0 n l 1 Fig. 9-13 Truth table for pulse-triggered J K flip-flop line 2 of the truth table. When J = 0 and K = 1 and a clock pulse arrives at the CLK input, the flip-flop is reset ( Q = 0). Line 3 shows the set condition of the JK flip-flop. When J = 1, K = 0 , and a clock pulse is present, output Q is set to 1. Line 4 illustrates a very useful condition of the J K flip-flop that is called the toggle position. When both inputs J and K a re HIGH, the output will go to the opposite state when a pulse arrives at the CLK input. With repeated clock pulses, the Q o utput might go LOW, HIGH, LOW, HIGH, LOW, and so forth. This LOW-HIGH-LOW-HIGH idea is called toggling. T he term “toggling” comes from the ON-OFF nature of a toggle switch. Note in the truth table in Fig. 9-13 t hat an entire clock pulse is shown under the clock (CLK) input heading. Many J K flip-flops are pulse-triggered. I t takes the entire pulse to transfer data from the input to the outputs of the flip-flop. With the clock input in the truth table, it is evident that the JK flip-flop is a synchronous flip-flop. The J K is considered the universal flip-flop. Figure 9 -14a shows how a JK flip-flop and an inverter would be wired to form a D flip-flop. Note the single D input at the far left and the clock input. This wired D flip-flop would trigger on the HIGH-to-LOW transition of the clock pulse, as shown by the bubble at the CLK input. D G - J FF Q’ +-K H IGH J Clock a> CLK Clock Q- ( a ) Wiring the J K flip-flop as a D flip-flop F F Q -CLK --K Clock d ( b ) Wiring the J K flip-flop as a T flip-flop ( c ) Logic symbol for a Tflip-flop Fig. 9-14 A useful toggle flip-flop (T-type flip-flop) is shown wired in Fig. 9-14b. A JK flip-flop is shown being used in its toggle mode. Note that the J and K inputs are simply tied to a HIGH, and the clock is fed into the CLK input. As t he repeated clock pulses feed into the CLK input, the outputs will simply toggle. The toggle operation is widely used in sequential logic circuits. Because of its wide use, a special symbol is sometimes used for the toggle (T-type) flip-flop. Figure 9-14c shows the logic symbol for the toggle flip-flop. The single input (labeled T ) is the clock input. The Customary Q and outputs are shown on the right of the symbol. The T flip-flop has only the toggle mode of operation. One commercial J K flip-flop is detailed in Fig. 9-15. This is described by the manufacturer as a 7476 TTL dual J Kflip-flop. A pin diagram of the 7476 IC is reproduced in Fig. 9-15a. Note that the IC contains two s eparate J K flip-flops. Each flip-flop has asynchronous preset ( P R ) and clear (CLR) inputs. The synchronous inputs are shown as J , K , and CLK (.clock). The customary normal ( Q ) and 214 FLIP-FLOPS AND OTHER MULTIVIBRATORS 1 I 1 G ND 2K KQQ ICK 1PR 1 1J CLR [CHAP. 9 2Q 2 2J Q Vcc 2CLK2PR 2 CLR ( a ) Pin diagram ( Reprinted b y permission of Texas Instruments, Inc.) Mode of operation outputs PR CLR Asynchronous set Asynchronous clear Prohibited 0 0 1 1 1 1 1 1 1 1 K Q Q x x x x x x x x x 1 0 0 1 1 0 0 Hold Reset Set Toggle J 1 1 CLK X = irrelevant n n n n o o 1 1 0 1 0 1 1 no change 0 1 1 0 opposite state n= positive clock pulse ( h ) Mode-select t ruth table Fig. 9-15 The 7476 JK flip-flop IC complementary ( 0) o utputs are available. Pins 5 and 13 a re the + 5-V ( V,,) and GND power connections on this IC. A t ruth table for the 7476 JK flip-flop is shown in Fig. 9-15b. T he top three lines detail the operation of t he asynchronous inputs preset ( P R ) and clear (CLR). Line 3 of t he truth table shows the prohibited state of the asynchronous inputs. Lines 4 through 7 detail the conditions of the synchronous inputs for the hold, reset, set, and toggle modes of the 7476 JK flip-flop. The manufacturer describes the 7476 as a master-slave J Kflzp-flop using positive-pulse triggering. The data at the outputs changes on the H-to-L transition of the clock pulse, as symbolized by the small bubble and > symbol at the CLK input on t he flip-flop logic diagram in Fig. 9-1%. Most commercial JK flip-flops have asynchronous input features (such as PR and CLR). Most JK flip-flops are pulse-triggered devices like the 7476 IC, but they can also be purchased as edgetriggered units. Flip-flops are the fundamental building blocks of sequential logic circuits. Therefore, IC manufacturers produce a variety of flip-flops using both the ?TL and C MOS technologies. Typical TTL flip-flops are the 7476 JK flip-flop with preset and clear, 7474 dual positive-edge-triggered D flip-flop with preset and clear, and the 7475 4-bit bistable latch. Typical CMOS flip-flops include the 4724 8-bit addressable latch, 40175 quad D flip-flop, and the 74C76 J K flip-flop with preset and clear. CHAP. 91 FLIP-FLOPS AND OTHER MULTIVIBRATORS 215 SOLVED PROBLEMS 9.24 Draw the logic symbol for a JK flip-flop with pulse triggering. Label inputs as J, K , a nd CLK. Label outputs as Q and D. Solution: See Fig. 9-12. 9.25 List the four synchronous modes of operation of t he J K flip-flop. Solution: T he synchronous modes of operation for the JK flip-flop are hold, reset, set, and toggle. 9.26 When the output of a flip-flop goes LOW, H IGH, LOW, .HIGH on repeated clock pulses, it is in what mode of operation? Solution: If a flip-flop’s output alternates states (LOW, HIGH, LOW) o n repeated clock pulses, i t is in the toggle mode. 9.27 List the binary o utput at output Q of t he JK flip-flop of Fig. 9-16 after each of t he eight clock pulses. Fig. 9-16 JK flip-flop pulse-train problem Solution: Refer to the truth table in Fig. 9-13. Based on t he truth table, the binary output (at (2) (Fig. 9-16) after each clock pulse is as follows: pulse e = 0 pulse g = 0 pulse a = 1 pulse c = 1 pulse b = 1 pulse d = 0 pulse f = 1 pulse h = 1 9.28 List the mode of operation of the JK flip-flop during each of t he eight clock pulses shown in Fig. 9-16. Solution: Refer to the mode-select truth table i n Fig. 9-13. Based on the table, the mode of the JK flip-flop during each clock pulse shown i n Fig. 9-16 is as follows: pulse e = hold pulse c = hold pulse g = toggle pulse a = set pulse b = hold pulse d = reset pulse f = toggle pulse h = toggle 9.29 List the asynchronous inputs to the 7476 J K flip-flop. Solution: The asynchronous inputs to the 7476 JK flip-flop are preset ( PR) nd clear (CLR). a 216 9.30 FLIP-FLOPS AND O THER MULTIVIBRATORS T he asynchronous inputs to the 7476 JK flip-flop have active [CHAP. 9 (HIGH, LOW) inputs. Solution: T he asynchronous inputs to the 7476 J K flip-flop have active LOW inputs. 9.31 Both asynchronous inputs to the 7476 IC must be (HIGH, LOW); the J and K inputs must be (HIGH, LOW); and a clock pulse must be present for the flip-flop to toggle. Solution: Both asynchronous inputs to the 7476 IC must be HIGH; the J and K inputs must be HIGH, and a clock pulse must be present for the flip-flop to toggle. 9.32 0 List the mode of operation of the 7476 JK flip-flop during each of the seven clock pulses shown in Fig. 9-17. 0 1 1 1 1 1 Ql-? Fig. 9-17 Solution: Refer to the mode-select truth table i n Fig. 9-15b. Based on the table, the mode of t he J K flip-flop during each clock pulse shown in Fig. 9-17 is as follows: pulse a = asynchronous set pulse b = toggle pulse c = toggle pulse d = asynchronous clear (reset) pulse e = set pulse f = hold pulse g = reset 9.33 R efer to Fig. 9-17. List the binary o utput at Q of the JK flip-flop after each of the seven clock pulses. Solution: Refer to the truth table in Fig. 9-1%. Based on t he table, the binary output (at Q ) after each clock pulse is as follows: pulse a = 1 pulse b = 0 pulse c = 1 pulse d = 0 pulse e = 1 pulse f = 1 pulse g = 0 CHAP. 91 FLIP-FLOPS AND OTHER MULTIVIBRATORS 217 9-6 TRIGGERING OF FLIP-FLOPS Most complicated digital equipment operates as a synchronous sequential system. This suggests that a master clock signal is sent to all parts of the system to coordinate system operation. A typical clock pulse train is shown in Fig. 9-18. Remember that the horizontal distance on the waveform is time and the vertical distance is voltage. T he clock pulses shown in the figure are for a TTL device because of the + 5-V and GND voltages. Other digital circuits use clocks, but the voltages might be different. Positive (leading) Negative (trailing) a J 3 4 Fig. 9-18 Clock pulses S tart at the left of t he waveform in Fig. 9-18. The voltage is at first LOW, or at GND. That is also called a logical 0. Pulse a shows the leading edge (also called the positive edge) of the waveform going from GND voltage to + 5 V . This edge of the waveform may also be called the LOW-to-HIGH (L-to-H) edge of t he waveform. On the right side of pulse a , t he waveform drops from + 5 V t o GND voltage. This edge is called the HIGH-to-LOW (H-to-L) edge of the clock pulse. It is also called the negatiue-going edge or the trailing edge of t he clock pulse. Some flip-flops transfer data from input to output on the positive (leading) edge of t he clock pulse. These flip-flops are referred to as positive-edge-triggered flip-flops. A n example of such a flip-flop is shown in Fig. 9-19. The clock input is shown by the middle waveform. The top waveform shows the Q o utput when the positive-edge-triggered flip-flop is in its toggle mode. Note that each leading edge (positive-going edge) of the clock toggles the flip-flop. Positiveedge-t riggered FF N e ga t i \ eedge-t riggered FF Fig. 9-19 Triggering of positive- and negative-edge flip-flops O ther flip-flops are classed as negatiue-edge-triggered flip-flops. T he operation of a negative-edgetriggered flip-flop is shown by the bottom two waveforms in Fig. 9-19. The middle waveform is the clock input. The bottom waveform is the Q o utput when the flip-flop is in its toggle mode. Note that this flip-flop toggles to its opposite state only on the trailing edge (negative-going edge) of the clock pulse. It is important to note the difference in timing of the positive- and negative-edge-triggered flip-flops shown in Fig. 9-19. The timing difference is of great importance in some applications. Many JK flip-flops are pulse-triggered units. These pulse-triggered devices are master-slave JK flip-flops. A master-slave JK flip-flop is actually several gates and flip-flops wired together to use the entire clock pulse to transfer data from input to output. In Fig. 9-18, pulse c will be used to help explain how pulse triggering works with a master-slave JK flip-flop. The following events happen, 218 [CHAP.9 FLIP-FLOPSA N D O T H E R MULTIVIBRATORS during the pulsc-triggering scqucncc, at thc numbcrcd points in Fig. 9-18: 1. Thc input and output of thc flip-flop arc isolated. 2. Data is entered f rom t he J and K inputs, but it is n ot transfcrrcd t o thc output. 3. The J and K inputs are disabled. 4. Previously entcrcd data from J and K is transfcrrcd to thc output. Notc that thc data actually appcars at thc outputs at point 4 (trailing cdgc) of thc wavcform in Fig. 9-18. T hc logic symbol for a pulsc-triggcred flipflop has a small bubble attached to !he clock (CLK) input (scc Fig. Y-15a) to s how that t he actual transfcr of data to the output takes place on the H-to-L transition of t he clock pulsc. Thc wavcforms in Fig. 9-20 will aid undcrstanding of the opcration of the mastcr-slave JK flip-flop and pulse triggcring. Start at thc left of thc wavcform diagram. The top thrcc waveforms are the synchronous inputs J , K. and C1.K. The top linc describes t he modc of opcration during thc clock pulse. Thc bottom linc is the rcsultant output of the JK flip-flop at output Q. Fig. 9-20 Waveform diagram for a mastcr-slavc JK flipflop L ook at clock (CLK) pulsc 1 shown in Fig. 9-20. B oth J and K inputs arc LOW. This is the hold condition. and s thc Q output stays at 0. as i t was beforc pulse 1. L ook at clock (CLK) pulse 2. Inputs o J and K arc in thc s et mode ( I = 1. K = 0). On the trailing edge of pulsc 2. output Q gcxs to a logical I . or HIGH. Pulsc 3 sccs the inputs i n the rcsct modc ( I = 0. K = 1). O n thc trailing cdgc of clock pulse 3. output Q is rcsct. or cleared to 0. Pulsc 4 sccs thc inputs in the toggle modc ( J 1, K = 1). On t hc trailing edge of clock pulse 4. output Q toggles to a logical 1. o r HIGH. Pulse 5 sees t he inputs i n thc toggle m cdc again. On the trailing edge of pulx 5 . output Q togglcs to a logical 0 o r LOW. Pulsc 6 (Fig. 9-20) will show an unusual charactcristic of thc mastcr-slavc J K Hip-flop. Notc that, on the leading edgc of clock pulse 6. input K = 1 and I = 0. When clock pulsc 6 is HIGH, input K goes from 1 to 0 while J gcxs from Q to I t o 0. O the trailing edge o f clock pulse 6. both inputs ( J and n K ) arc LOW. Howcvcr. as strangc as i t may sccm. t hc flip-flop still toggles to a HIGH. The master-slave JK flip-flop remetnbers any or all HIGH inpiits while the clock pulse is HIGH. During pulse 6, both input 1 and K were HIGH for a short time when the clock input w as HIGH. T h e flip-flop thercforc rcgardcd t his a s thc togglc condition. and K in the hold mode Next refer to clock pulse 7 (Fig. 9-20). Pulsc 7 sccs inputs ( I = 0, K = 0). Output Q remains i n its prcscnt state (stays at 1). Pulsc 8 sccs input K at 1 for a short timc and input J at U. Thc flip-flop intcrprcts this as thc rcsct modc. Output Q therefore re%& output @ to 0 on thc trailing edge of clock pulse 8. Rcfcr to clock pulse 9 (Fig. 9-20). T he mastcr-slave JK flip-flop secs both 1 and K inputs at a I D W o n the positive edge o f clock pulse 9. When t hc pulse is HIGH. input K goes HIGH for a short limc and thcn i nput I gocs HIGH for a short timc. Inputs J and K arc nor HIGH at the same timc, - .' CHAP. 91 FLIP-FLOPS AND OTHER MULTIVIBRATORS 219 however. On the trailing edge of clock pulse 9, both inputs ( J and K ) a re LOW. T he flip-flop interprets this as the toggle mode. Output Q changes states and goes from a 0 t o a 1. I t should be noted that not all J K flip-flops are of the master-slave type. Some JK flip-flops are edge-triggered. Manufacturers’ data manuals will specify if t he flip-flop is edge-triggered or pulsetriggered. SOLVED PROBLEMS 9.34 Flip-flops are classified as either edge-triggered or -triggered units. Solution: Flip-flops are classified as either edge-triggered or pulse-triggered units. 9.35 A positive-edge-triggered flip-flop transfers data from input to output on the trailing) edge of the clock pulse. (leading, Solution: A positive-edge-triggered flip-flop transfers data from input to output on the leading edge of t he clock pulse. 9.36 A negative-edge-triggered flip-flop transfers data from input to output on the (H-to-L, L-to-H) transition of the clock pulse. Solution: A negative-edge-triggered flip-flop transfers data from input to output on the ,H-to-L transition of the clock pulse. 9.37 T he master-slave JK flip-flop is an example of a (positive-edge-, pulse-) triggered unit. Solution: T he master-slave J K flip-flop is an example of a pulse-triggered unit. 9.38 Refer to Fig. 9-20. List the binary o utput (at 0 ) after each of the nine clock pulses. Solution: T he output is always the complement of the Q output on a flip-flop. Therefore the binary outputs (at 0 )in Fig. 9-20 after each clock pulse are as follows: pulse 1 = 1 pulse 3 = 1 pulse 5 = 1 pulse 7 = 0 pulse 9 = 0 pulse 6 = 0 pulse 4 = 0 pulse 2 = 0 pulse 8 = 1 9.39 List the binary o utput (at Q ) of t he master-slave J K flip-flop of Fig. 9-21 after each of t he eight clock pulses. Solution: Refer to the truth table i n Fig. 9-13. According to this table, the binary output (at Q ) of t he master-slave JK flip-flop (Fig. 9-21) after each clock pulse is as follows: pulse e = 0 pulse g = 0 pulse c = 1 pulse a = 1 pulse h = 0 pulse d = 0 pulse f = 1 pulse h = 1 220 9.40 F LIP-FLOPS A ND OTHER MULTIVIBRATORS [CHAP. 9 List the mode of operation for the master-slave J K flip-flop of Fig. 9-21 for each clock pulse. Fig. 9-21 JK flip-flop pulse-train problem Solution: Refer to the mode-select truth table in Fig. 9-13. According to the table, the modes of o peration for t he master-slave J K flip-flop (Fig. 9-21) for each clock pulse are as follows: pulse g = reset pulse c = toggle pulse a = s et pulse e = hold pulse b = r eset pulse d = toggle pulse f = toggle pulse h = toggle 9.41 Refer to Fig. 9-21. Assume the JK flip-flop is a negative-edge-triggered unit. List the binary o utput (at Q ) of t he edge-triggered flip-flop after each of the eight clock pulses. Solution: R efer to the truth table in Fig. 9-13, but remember that this is a negative-edge-triggered JK flip-flop (it triggers on the H-to-L transition of t he clock pulse). The binary output (at Q ) for the negative-cdgctriggered J K flip-flop after each clock pulse is as follows: pulse a = 1 pulse c = 1 pulse g = 0 pulse e = 0 pulse b = 0 pulse d = 0 pulse f = 0 pulse h = 1 9-7 ASTABLE MULTMBRATORS-CLOCKS Introduction A multivibrator ( MV) is a pulse generator circuit which produces a rectangular-wave output. Multivibrators are classified as astable, bistable, o r monostable. An astable M V is also called a free-running multiribrator. T he astable M V generates a continuous flow of pulses as depicted in Fig. 9 -22a. A bistable multivibrator is also called a f lip-pop. T he bistable M V is always in o ne of two stable states (set or reset). The basic idea of a bistable M V is diagrammed in Fig. 9 -22b, where the input pulse triggers a change in output from LOW to H IGH. A monostable MV is also called a one-shot multivibrator. When the one-shot is triggered, as shown in Fig. 9 -22c, t he M V generates a single short pulse. Astable Multivibrator T he versatile 555 Timer IC can be used to implement an astable, bistable, or monostable multivibrator. The 5 55 timer is shown wired as a free-running (astable) multivibrator in Fig. 9 -23a. If FLIP-FLOPS AND OTHER MULTIVIBRATORS CHAP. 91 22 1 Fig. 9-22 b oth resistors ( R A a nd R H ) 4.7 k (kilohms) and C = 180 p F, t he output will be a string of T TL = a level pulses at a frequency of 1 Hz. T he output frequency of the M V shown in Fig. 9-23a can be increased by decreasing t he value of t he resistors and/or capacitor. For example, if the resistors ( R A a nd R B )= 330 f a nd C = 0.1 p F, l t hen the output frequency will rise to about 10 kHz. t5 v I 1s RA 1 14 555 Rb 6 c 3 7 t imer IC -2 T TL output 0.. RA = RB = 4.7 k!L? C = 1 00pF RA = R B = 3 3 0 5 2 C = 0.1 pF (a) I o utput x 1 Hz o utput x 10 k Hz 5 55 timer IC wired as an astable M V i Tl Top View output Reset ( h ) 5 55 timer D IP I C 4 iyharge Threshold C ontrol Voltage ( c) 5 55 timer pin diagram Fig. 9-23 222 FLIP-FLOPS AND OTHER MULTIVIBRATORS [CHAP. 9 T he 555 timer is commonly sold in an 8-pin DIP IC like that pictured in Fig. 9-23b. T he pin functions for the 555 timer IC are shown in Fig. 9-23c. A nother astable multivibrator circuit is shown in Fig. 9-24. This free-running MV uses two CMOS inverters from the 4069 hex inverter IC. Note the use of a 10-V dc power source, which is common (but not standard) in CMOS circuits. The frequency of the output is about 10 kHz. The output frequency can be varied by changing the value(s) of the resistors and capacitor in the circuit. Another astable multivibrator circuit using CMOS inverters is diagrammed in Fig. 9-25. This free-running MV contains a crystal-controlled oscillator (4049a and 4 049b) with inverters (4049c and 4 049d) used to square up the waveform. The output frequency is controlled by the natural frequency of the crystal, which is 100 kHz in this circuit. The frequency is very stable. The square-wave output is at CMOS voltage levels (about 10 V p-p). 680 I1 +10 v 2 100-kHz 10-v p-p o utput + JlJlJl-0.. Fig. 9-25 Crystal-controlled astable MV Astable multivibrators are often called clocks when they are used in digital systems. A system clock is used in all synchronous digital and microprocessor-based systems. Some important characteristics of a clock in a digital system are frequency, clock cycle time, frequency stability, voltage stability, and shape of the waveform. The clock cycle time is calculated by using the formula 1 T= - f where T = time, s f = frequency, Hz Clocks require square-wave pulses with fast rise times and fast fall times. 223 F LIP-FLOPS AND OTHER MULTIVIBRATORS CHAP. 91 SOLVED PROBLEMS 9.42 List three classes of multivibrators. Solution: Multivibrators are classified as astable, bistablc, or monostable. 9.43 A nother name for an astable multivibrator is . Solution: An astable MV is also called a f rec-running multivibrator. 9.44 A nother name for a bistable multivibrator is . Solution: A bistablc MV is also called a flip-flop. 9.45 A nother name for a monostable multivibrator is . Solution: A monostable MV is also called a one-shot multivibrator. 9.46 Increasing the value of both resistors and the capacitor i n t he MV circuit shown in Fig. 9 -23a will (decrease, increase) the output frequency. Solution: Increasing t he value of the resistors and capacitor in t he free-running M V of Fig. 9-23a will decrease the output frequency. 9.47 Pin number is next to t he dot on the 8-pin DIP IC shown i n Fig. 9-236. Solution: Pin 1 is located next to the dot on top of the &pin DIP 1C o f Fig. 9-23h. 9.48 T he clock pulses from the MV shown in Fig. 9-23a (are, are not) compatible with T TL. Solution: The clock pulses from the 5 55 timcr shown in Fig. 9 -23a a re at TTL voltage levels. ( LOW = 0 V a nd H IGH = about +4.S V.) 9.49 T he 4069 inverters used in the MV shown i n Fig. 9-24 are (CMOS, TTL) ICs. Solution: T he 4069 is a CMOS hex inverter IC. 9.50 T he astable MV shown in Fig. (9-24, 9-25) would have the greatest frequency stability. Solution: The free-running MV shown in Fig. 9-25 would have great frequency stability. The oscillator’s frequency is crystal-controlled. 224 9.51 F LIP-FLOPS A ND OTHER MULTIVIBRATORS [CHAP. 9 T he output from the crystal-controlled free-running MV shown in Fig. 9-25 is compatible with (CMOS, T TL) circuit. a Solution: T h e 10-V o utput from the MV shown in Fig. 9-25 m eans i t is compatible with a CMOS circuit. TTL v oltage levels must r ange from 0 t o + 5.5 V only. 9.52 T he clock cycle time for the MV shown in Fig. 9-25 is S. Solution: T he formula is T = l /f, so T = 1/100,000 9-25 is 0.00001 s, or 10 ,us. = 0.00001. T he clock cycle time for the M V shown in Fig. 9-8 MONOSTABLE MULTIVIBRATORS T he o ne-shot o r m onostable multir?ibrator generates an output pulse of fixed duration each time its input is triggered. The basic idea of the monostable MV is shown graphically in Fig. 9-22c. The input trigger may be an entire pulse, an L-to-H transition of the clock, or an H-to-L transition of the trigger pulse depending on the one-shot. The output pulse may be either a positive or a negative pulse. The designer can adjust the time duration of t he o utput pulse by using different resistor-capacitor combinations. The adaptable 555 timer IC is shown wired as a one-shot M V in Fig. 9-26. A short negative input pulse causes the longer positive output pulse. The time duration t of the output pulse is calculated by using the formula t = l .lR,C where R A is equal to the value of the resistor i n ohms, C is equal to the value of t he capacitor in farads, and t is equal to the time duration of the output pulse i n seconds. By calculating the output pulse time duration t for the one-shot shown in Fig. 9-26, we have t = 1.1 x 10,000 x 0.0001 = 1.1 s T he calculated time duration t of the output pulse for the one-shot MV shown in Fig. 9-26 is 1.1 s. T he one-shot M V shown in Fig. 9-26 is nonretriggerable. This means that when the one-shot's output is HIGH, it will disregard any input pulse. Retriggerable monostable MVs also are available. +5 v + l output t imer I nput U n Trigger l oo lJF ii" T Fig. 9-26 555 t imer IC w ired as a m onostable MV FLIP-FLOPS AND O THER MULTIVIBRATORS CHAP. 91 225 In Fig. 9-27 the TTL 74121 one-shot IC is shown being used to generate single TTL level pulses when a mechanical switch is pressed. Many digital trainers used in technical education and design work use circuits of this type to generate single clock pulses. Both positive and negative clock pulses are available from the normal ( Q) a nd complementary o utputs of t he 74121 one-shot IC. (e) +5 v d = 100 kS2: 4 L l+l I nput L +'2p I I 0.01 pF s wl outputs one-shot - GND Q 1 1 i Fig. 9-27 74121 I C w ired to g enerate single clock pulses T he duration of the output pulse can be adjusted by varying the values of the resistor R a nd capacitor C. To calculate the time duration of the output pulse, use the formula t = 0 .7RC where R e quals the value of the resistor in ohms, C e quals the value of the capacitor in farads, and t is t he duration of the output pulse in seconds. By calculating the duration of t he output pulse in the one-shot circuit in Fig. 9-27, we have t = 0 .7 X 15,000 X 0.000001 = 0.0105 s T he calculated time duration t for the output pulse from the one-shot shown in Fig. 9-27 is 0.0105 s, o r about 10 ms. A pin diagram and truth table for the 74121 one-shot IC a re reproduced in Fig. 9-28. Note that the 74121 one-shot has three separate trigger inputs (XI,X 2 ,a nd B ). Typically, only a single input H = HIGH voltage level L = LOW voltage level X = d on't care t = LOW-to-HIGH transition .1 = HIGH-to-LOW transition ( h ) T ruth table ( Courtesy of' S ignetics C orporation) Fig. 9-28 226 F LIP-FLOPS A ND O THER MULTIVIBRATORS [CHAP. 9 x, would be used at a time. In the application shown in Fig. 9-27, input ( pin 3 ) serves as the trigger input. This matches the situation in line 6 of t he truth table (Fig. 9-286). Inputs and B a re HIGH, a nd trigger input reacts to a H IGH-to-LOW transition of t he trigger pulse. Monostable multivibrators are useful, for timing applications when precision is n ot critical. One-shots are also used to introduce delays in digital systems. SOLVED PROBLEMS 9.53 ---.A - multivibrator is also r eferred to as a o ne-shot. Solution: A m onostable MV is also called a o ne-shot. 9.54 T he one-shot circuit shown in Fig. 9-26 g enerates a when triggered by a negative input pulse. (negative, positive) output pulse Solution: T he one-shot shown i n Fig. 9-26 g enerates a positivc output pulse when triggered by a negative input pulse. 9.55 W hat is the calculated time duration t of t he output pulse from the one-shot shown in Fig. 9-26 if R A = 9.1 kSZ a nd C = 10 p F? Solution: T he formula is t = 1.1R AC; then t = 1 .1 x 9 100 x 0.0000 1 T he calculated time duration of the output pulsc from thc one-shot would be 0.1 s. 9.56 An ( H-to-L, L-to-H) transition of t he trigger pulse shown in Fig. 9-27 causes the one-shot to generate an output pulse. l_l_ Solution: In Fig. 9-27, it is the HIGH-to-L,OW transition of t he trigger pulse that causes the one-shot to g enerate an output pulse. 9.57 I n Fig. 9-27, w hat will be the time duration of t he output pulse if R = 30 k R a nd C = 100 p F ? Solution: T he formula is t = 0 .7RC SO t = 0.7 x 30,000 x 0.0001 T he time duration of t he output pulse from the 74121 IC will be 2.1 s. 9.58 Pressing the switch SW1 shown in Fig. 9-27 activates the trigger input and generates a (negative, positive) pulse from the complementary < Q)o utput. Solution: Pressing SWl in Fig. 9-27 triggers the 74121 one-shot and generates a negative pulsc from the complementary ( 0) utput. Also s ee truth table in Fig. 9-28h. o 227 FLIP-FLOPS AND OTHER MULTIVIBRATORS CHAP. 93 Supplementary Problems ( HIGH, LOW). Ans. HIGH 9.59 If it is said that “the flip-flop is set,” then output Q is 9.60 A(n) (clocked RS, R S ) flip-flop is an example of a synchronously operated device. Ans. clocked RS 9.61 A(n) 9.62 Combinational logic circuits and the RS latch operate Ans. asynchronously 9.63 T he normal output of a flip-flop is the 9.64 List the binary output (at Q )of the RS latch shown in Fig. 9-29 for each of the eight pulses. Ans. pulse a = 0 pulse c = 1 pulse e = 1 pulse g = 1 pulse b = 0 pulse d = 0 pulse f = 1 (prohibited) pulse h = 1 . A ns. RS ( D , R S ) flip-flop does nor have a clock input. (asynchronously, synchronously). - ( Q, output. Q) 0 h . 0 0 1 0 1 1 g f e d c b Ans. Q a Fig. 9-29 RS flip-flop pulse-train problem 9.65 List the mode of operation of the RS flip-flop shown in Fig. 9-29 for each of the eight pulses. pulse a = reset pulse c = set pulse e = set pulse g = set pulse f = prohibited condition pulse h = hold pulse b = hold pulse d = reset A m. a 9.66 for the clocked RS flip-flop shown in Fig. 9-7 for each of the eight clock List the binary output at pulses. Ans. pulse a = 0 pulse c = 0 pulse e = 1 pulse g = 0 pulse b = 0 pulse d = 1 pulse . f= 1 pulse h = 0 9.67 Refer to Fig. 9-30. T he clocked RS flip-flop is triggered by the Ans. leading clock pulse. 0 0 0 0 Fig. 9-30 Clocked RS flip-flop pulse-train problem (leading, trailing) edge of t he 228 9.68 F LIP-FLOPS AND O THER MULTIVIBRATORS [CHAP. 9 List the binary o utput (at Q ) of the clocked RS flip-flop shown in Fig. 9-30 for each of the six clock pulses. Ans. pulse a = 1 pulse c = 0 pulse e = 1 ( prohibited condition) pulse d = 1 pulse ,f 1 pulse b = 0 - 9.69 List the mode of o peration for the clocked Ans. pulse a = set pulse h = r eset pulse c = hold ( S a nd R a re both 0 on leading edge) 9.70 List the binary o utput (at Q ) for the 0 flip-flop shown in Fig. 9-1 1 a fter each o f t he eight clock pulses. Ans. pulse a = 1 pulse c = 1 pulse e = 1 pulsc g = 1 pulse f = 0 pulsc h = 1 ( prohibited condition) pulse b = 0 pulse d = 0 9.71 Refer to Fig. 9-11. Which input has control of t he flip-flop during pulse e ? Register to View Answerhe preset ( P S ) input is activated during pulse e and overrides all other inputs. It sets the Q o utput to 1. 9.72 R efer to Fig. 9-11. Which input has control of t he flip-flop during pulse f ? Register to View Answerhe clear (CLR) input is activated during pulsc f and overrides all other inputs. It resets thc Q o utput to 0 . 9.73 A delay flip-flop is also called a 9.74 On a D flip-flop, the data bit at input D is delayed (Q, Ans. I ; Q output 9.75 A T-type flip-flop is also called a 9.76 Draw a logic diagram showing how to wire a J K flip-flop as a T flip-flop. 9.77 Draw a logic diagram showing how to wire a J K flip-flop and an inverter as a D flip-flop. Ans. See Fig. 9 -14a. 9.78 List the binary o utput (at Q ) fo the J K flip-flop shown i n Fig. 9-16 a fter each of t he eight clock pulses. Ans. pulse a = 0 pulse c = 0 pulsc r = 1 pulse g = 1 pulse b = 0 pulse d = 1 pulsc f = 0 pulse h = 0 9.79 R efer to Fig. 9-16. The (asynchronous, synchronous) inputs to the J K flip-flop are shown being used on this unit. A m. T he J , K , and CLK inputs are synchronous inputs. 9.80 Refer to Fig. 9-17. Which input has control of the J K flip-flop during pulse U ? Ans. PR ( Preset input activated with LOW sets output Q t o 1 .) 9.81 R efer to Fig. 9-17. Which input has control of the J K flip-flop during pulse d ? Register to View AnswerLR (Clear input activated with LOW resets output Q to 0 .) 9.82 R efer to Fig. 9-17. List the binary o utput at t he seven clock pulses. Ans. pulse a = 0 pulse b = 1 pulse c = 0 pulse d = 1 pulse e = 0 pulse f = 0 pulse g 1 RS flip-flop shown in Fig. 9-30 as each pulse triggers the unit. pulse d = set pulse e = prohibited condition pulse f = set ( S = I , R = 0 on the leading edge) ( D , T)-type flip-flop. e). ; = A m. D ( 0, I , 2, 3, 4) clock pulse(s) from getting to (toggle. truth-table) flip-flop. A m. 0 (complementary output) of the A ns. toggle See Fig. 9 -14h. J K flip-flop afrer each o f CHAP. 91 229 FLIP-FLOPS A ND O THER MULTIVIBRATORS 9.83 A negative-edge-triggered flip-flop transfers data from input to outputs on the Ans. trailing edge of the clock pulse. (leading, trailing) 9.84 A positive-edge-triggered flip-flop transfers data from input to outputs on the transition of the clock pulse. A ns. L-to-H (H-to-L, L-to-H) 9.85 Refer to Fig. 9-21. List the binary o utput (at Q ) of the master-slave JK flip-flop a fter each of the eight clock pulses. A ns. pulse a = 0 pulse c = 0 pulse e = 1 pulse g = ‘I pulse b = 1 pulse d = 1 pulse f = 0 pulse h = 0 9.86 Refer to Fig. 9-21. List the mode of operation of the n egatice-ed~e-tri~~ered flip-flop for each of the JK clock pulses. A m. pulse a = s et pulse c = toggle pulse e = hold pulse g = reset pulse d = toggle pulse b = reset pulse f = hold ( J and K = 0 pulse h = toggle during H-to-L pulse) 9.87 A flip-flop is also r eferred to as a(n) 9.88 A free-running clock is also referred to as a(n) 9.89 One-shots are also called 9.90 The main advantage of a crystal-controlled clock is its 9.91 I f a free-running MV has a clock cycle time of 0.000001 s, the frequency of t he clock is Rns. 1 MHz 9.92 The output of the astable MV shown i n Fig. 9-25 A ns. is not (voltage is too high.) . mu1tivibrator. Ans. bistable multivibrator. Ans. astable Ans. monostable multivibrators stability. Ans. frequency (is, is not) TTL-compatible. . Chapter 10 Counters 10-1 INTRODUCTION Counters are important digital electronic circuits. They are sequential logic circuits because timing is obviously important and because they need a memory characteristic. Digital counters have the following important characteristics: 1. 2. 3. 4. Maximum number of counts (modulus of counter) U p or down count Asynchronous or synchronous operation Free-running or self-stopping As with other sequential circuits, flip-flops are used to construct counters. Counters are extremely useful in digital systems. Counters can be used to count events such as a number of clock pulses in a given time (measuring frequency). They can be used to divide frequency and store data as in a digital clock, and they can also be used in sequential addressing and in some arithmetic circuits. 10-2 RIPPLE COUNTERS Digital counters will count only in binary or in binary codes. Figure 10-1 shows the counting sequence in binary from 0000 t o 1111 (0 to 15 in decimal). A digital counter that would count from binary 0000 t o 1111 a s shown in t he table might be called a modulo-16 counter. T he modulus of a counter is the number of counts the counter goes through. The term “modulo” is sometimes shortened to “mod.” This counter might thus be called a mod-I6 counter. Binary count D ecimal count 0 1 2 3 4 5 6 . 8 s 4s 2s 1s D ecimal c ount DCBA 0 0 0 0 0 0 0 0 0 0 0 1 1 1 00 01 10 1 0 0 1 Binary count 8 9 10 11 12 13 14 1 0 1 0 8 s 4s 2 s 1s DCBA 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Fig. 10-1 C ounting sequence for a 4-bit counter A logic diagram of a mod-16 counter using J K flip-flops is shown in Fig. 10-2. First note that the J a nd K d ata inputs of the flip-flops are tied to logical 1. This means that each flip-flop is in its toggle mode. Each clock pulse will then cause the flip-flop to toggle to its opposite state. Note also that the Q o utput of FF1 (flip-flop 1) is connected directly to the clock (CLK) input to the next unit (FF2), and so forth. Output indicators (lamps or LEDs), shown at the upper right, monitor the binary output of t he counter. Indicator A is the LSB (least significant bit), D is t he MSB. 230 I 1 I 1 1 f 7 t * 1 I 232 COUNTERS [CHAP. 10 Look at the dashed line after pulse 4 t o the HIGH waveform at Q of FF3. Note that quite a lot of time passes before FF3 finally toggles to its HIGH state. That is because FF1 toggles, which in turn toggles FF2, which in turn toggles FF3. All that takes time. This type of counter is called a ripple counter. T he triggering from flip-flop to flip-flop in effect ripples through the counter. The counter is also referred to as an asynchronous counter because not all flip-flops toggle exactly in step with the clock pulse. Look at the remainder of the waveform shown in Fig. 10-3 to make sure you understand its operation. Note particularly that, on pulse 16, the H-to-L transition toggles FF1. T he output of FF1 goes from HIGH to LOW. F F2 is toggled by FF1. The output of FF2 goes from HIGH to LOW. F F3 is toggled by FF2, and so forth. Note that all the flip-flops toggle in turn and go from their HIGH t o their LOW states. The binary count is then back to 0000. T he counter does not stop at its maximum count; it continues counting as long as the clock pulses are fed into the CLK input of FF1. Count carefully the- number of HIGH pulses under the first 16 clock pulses (in the FF1 output line, Fig. 10-3). You will find eight pulses. Sixteen pulses go into FF1, and only eight pulses come out. This flip-flop is therefore a frequency divider. 16 divided by 8 equals 2. F F1 may thus also be considered a divide-by-2 counter. Count the HIGH o utput pulses at FF2. For 16 clock pulses, only four pulses appear at the output of FF2 (16 divided by 4 equals 4). O utput Q of FF2 may be considered a divide-by-4 counter. It is found that the output of FF3 is a divide-by-8 counter. The output of FF4 is a divide-by-16 counter. On some devices, such as digital clocks, dividing frequency is a very important job for counters. The waveform confirms that a counter is a sequential logic device. The memory characteristic also is important; for the flip-flop must “remember” how many clock pulses have arrived at the CLK input. The ripple counter is the simplest type of counter. Its shortcoming is the time Zag as one flip-flop triggers the next, and so forth. SOLVED PROBLEMS 10.1 A ripple counter is a(n) (asynchronous, synchronous) device. Solution: The ripple counter is an asynchronous device because not all flip-flops trigger exactly in step with the clock pulse. 10.2 A counter that counts from 0 t o 7 is called a mod- counter. Solution: A counter that counts from 0 to 7 is called a mod-8 counter. 10.3 Draw a logic diagram of a mod-8 ripple counter using three JK flip-flops. Solution: See Fig. 10-4. 1 J 1- FF 1 Clock input -----O>CLK 1-K c Q, 1- 41 +> 1-K J FF2 CLK Q- 41 1- J 01 FF3 CLK I-K Fig. 10-4 A 3-bit ripple counter output CHAP. 101 233 COUNTERS 10.4 List the sequence of binary counts that the counter in Prob. 10-3 would go through. Solution: The mod-8 counter would count in binary as follows: 000,001,010,011,100,101,110,111, and then back to 000, and so forth. 10.5 I t is customary to designate FF1 in a counter as the (LSB, MSB) counter. Solution: Customarily, FF1 is the LSB counter. 10.6 Refer to Fig. 10-5. What is t he binary count after pulse 2? Fig. 10-5 Timing diagram for a mod-8 ripple counter Solution: The binary count after pulse 2 is 010. 10.7 Refer to Fig. 10-5. The output of FF1 will go HIGH again on the trailing edge of clock pulse --. Solution: FF1 will go H IGH again on the trailing edge of clock pulse 5. 10.8 R efer to Fig. 10-5. The output of FF2 will go HIGH again on the edge of clock pulse 6. (leading, tra Solution: FF2 will go HIGH again on the trailing edge of clock pulse 6, 10.9 R efer to Fig. 10-5. T he output of FF3 will go LOW again on the H-to-L edge of clock pulse Solution: FF3 will go LOW again on the H-to-L edge of clock pulse 8. 10.10 R efer to Fig. 10-5. T he binary count after clock pulse 8 will be Solution: T he binary count after clock pulse 8 will be 000. . 234 [ CHAP. 1 0 COUNTERS 10-3 PARALLEL COUNTERS T he asynchronous ripple counter has the limitation of the time lag in triggering all the flip-flops. To c ure this problem, parallel counters c an be used. The logic diagram for a 3-bit parallel counter is shown in Fig. 10-6a. N ote that all C LK i nputs are tied directly to the input clock. They are wired i n parallel. N ote also that J K flip-flops are used. F Fl is the 1 s place counter and is always in the toggle mode. FF2 h as its J a nd K i nputs tied to the output of FF1 a nd will be in the hold or toggle mode. The o utputs of F F1 and FF2 are fed into an A ND g ate. The AND gate controls the mode of o peration of FF3. W hen the A ND g ate is activated by Is a t A a nd B , FF3 will be in its toggle mode. With the AND g ate deactivated, FF3 will be in its hold mode. FF2 is the 2s place counter and FF3 t he 4s place counter. Clock input 1 ( a) Logic d iagram Deci m a1 c ount B inary c ount -4s 2s Is CBA 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ( b ) Counting sequence Fig. 10-6 A 3-bit parallel c ounter T he counting sequence for this 3-bit parallel counter is shown in Fig. 10-66. N ote that this is a modulo-8 (mod-8) counter. The counter will start counting at binary 000 a nd count up to 1 1 1. I t will then recycle back to 000 t o start the count again. The waveform (timing diagram) for the parallel mod-8 counter is drawn in Fig. 10-7. T he top line represents the clock (CLK) i nputs to all three flip-flops. The outputs (at Q ) of t he flip-flops are shown in the middle three lines. The bottom line gives the indicated binary count. Consider pulse 1, Fig. 10-7. Pulse 1 arrives at each of t he three flip-flops. FF1 toggles from LOW to HIGH. FF2 a nd FF3 d o not toggle because they are in the hold mode ( J a nd K = 0). T he binary count is now 001. CHAP. 103 COUNTERS 235 Fig. 10-7 Timing diagram for a 3-bit parallel counter Look at pulse 2, Fig. 10-7. Pulse 2 arrives at all the flip-flops, FF1 a nd FF2 toggle because they are in the toggle mode ( J a nd K = 1). FF1 goes from HIGH to LOW while FF2 goes from LOW to HIGH. FF3 is still in the hold mode, and so it does not toggle. The count is now 010. Pulse 3 arrives at all the flip-flops at the same time. Only FF1 toggles. FF2 and FF3 are in the hold mode because J a nd K = 0. T he binary count is now 011. Consider pulse 4, Fig. 10-7. Note that the AND gate is activated just before the clock pulse goes from HIGH to LOW. The AND gate will put FF3 in the toggle mode ( J a nd K = 1). O n the H-to-L transition of clock pulse 4, all flip-flops toggle. FF1 a nd FF2 go from HIGH to LOW. FF3 toggles from LOW to HIGH. The binary count is now 100. N ote the dashed line below the trailing edge of clock pulse 4. Hardly any time lag is evident from FF1 t o FF3 b ecause all the flip-flops are clocked at exactly the same time. That is the advantage of t he parallel-type counter. Parallel counters are also called synchronous counters b ecause all flip-flops trigger exactly in time with the clock. Parallel counters are more complicated (see the added lines and the AND gate), but they are used when the time lag problem with a ripple counter would cause problems. Look over the rest of the waveform in Fig. 10-7. Understand that each flip-flop is clocked on e ach clock pulse. FF1 always toggles. FF2 and FF3 may be in either the toggle or the hold mode. SOLVED PROBLEMS 10.11 R efer to Fig. 10-7. When the clock pulse 5 is HIGH, FF1 is in its toggle mode, FF2 in its (hold, toggle) mode, and FF3 in its (hold, toggle) mode. . Solution: W hen pulse 5 is HIGH, F F1 is in its toggle mode, FF2 in its hold mode, and FF3 in its hold mode. 10.12 R efer to Fig. 10-7. On the trailing edge of clock pulse 6, which flip-flop(s) toggle? Solution: O n the trailing edge of clock pulse 6 (Fig. 10-7), both FF1 a nd FF2 toggle. 10.13 R efer to Fig. 10-7. When clock pulse 8 is HIGH, which flip-flops are in the toggle mode? Solution: W hen clock pulse 8 (Fig. 10-7) is H IGH, all three flip-flops are in the toggle mode. 10.14 R efer to Fig. 10-7. What is the binary count after clock pulse 8? Solution: T he binary count after clock pulse 8 (Fig. 10-7) is 000. 236 COUNTERS [CHAP. 10 10.15 All flip-flops in the counter shown in Fig. 10-7 o perate in step with the clock. The counter is t herefore referred to as a(n) (asynchronous, synchronous) counter. Solution: T he c ounter shown in Fig. 10-7 is r eferred to as a s ynchronous counter. 10-4 OTHER COUNTERS S uppose a modulo-6 ripple counter were needed. What would i t look like? The first step in constructing a mod-6 ripple counter is to list the counting sequence shown in Fig. 1 0-8a. T he counting sequence for the mod-6 counter is from 000 t o 101. N ote that a 3-bit counter is needed with a 4s c ounter ( C ) , a 2s counter ( B ) , a nd a 1s c ounter ( A ) . As shown in Fig. 1 0-8a, t he 3-bit counter normally counts from 000 t o 111. T he last two c ounts o n t he chart (110 and 111) must be omitted. 1 Clock i nput Recycle (reset) ( a ) C ounting sequence 1 o utput CLR Reset ( 6) Logic-symbol diagram Fig. 10-8 Mod-6 r ipple counter T he trick to this mod-6 design problem is t o look a t the binary count i mmediatdy after the highest count of thc counter. I n this case, it is 110. F eed the 110 into a logic circuit that will produce a c lear, o r reset, pulse. The clear pulse goes back to an asynchronous clear input on e ach JK flip-flop, thus clearing, or resetting, the counter to 000. T he logic circuit needed to clear or reset the JK flip-flops back to 0 is shown in Fig. 10-8b. T he 2-input NAND gate will do the job when the outputs of FF2 and FF3 a re fed into it. Note from the counting table in Fig. 10-8a t hat the first time both C a nd B a re 1 is i mmediately a fter t he highest count. Thus when t he counter tries to go to 110, it will immediately be cleared or reset to 000. The mod-6 counter shown in Fig. 10-8b is a r ipple counter that is just reset or c leared two counts before its normal maximum count of 111 . T he NAND gate does the job of resetting the JK flip-flops to 0 by activating the CLR inputs. Waveforms for the mod-6 ripple counter are diagrammed in Fig. 10-9. T he clock (CLK) i nput to FF1 is shown across the top. The middle three lines show the state of t he Q o utputs. The bottom line gives the binary count. The mod-6 counter represented in the diagram in Fig. 10-9 o perates as a normal ripple counter until pulse 6. The binary count before pulse 6 is 101, the maximum count for this unit. On the H-to-L transition of clock pulse 6, FF1 toggles from HIGH to LOW. F Fl's H-to-L transition triggers FF2, which toggles from LOW t o HIGH. At point a , Fig. 10-9, both outputs of FF2 and FF3 a re at 1. These two I s a re applied to the NAND gate (see Fig. 10-8b). The NAND gate is activated, producing a 0. T he 0 activates the asynchronous CLR input to ail the flip-flops, resetting them all to 0. The resetting, or clearing to 000, is shown at point b , Fig. 10-9. T he small pulse at point a , Fig. 10-9, is so s hort that CHAP. 101 237 COUNTERS Fig. 10-9 Timing diagram for a mod-6 ripple counter it does not even light the output indicators. The counter is free to count upward normally again from binary 000. Look at the trailing edge of pulse 6 (Fig. 10-9) again. Again note the lag between the time pulse 6 goes from HIGH t o LOW a nd the time FF2 a nd FF3 finally are reset to 0 a t point b . E ngineers refer to this lag time as the propagation time, and it is based on the propagation delay of t he flip-flop and gate being used. The propagation delay for a typical TTL flip-flop is very short-from 5 t o 30 n s (nanoseconds). Some logic families have much longer propagation delays. A decade counter is probably the most widely used counter. It could also be described as a rnodulo-10 counter. Figure 10-10a is a d iagram of a mod-10 ripple counter. Four JK flip-flops plus a NAND gate are used to wire the decade counter. The unit counts just like the mod-16 counter up to ohob D 1J Clock input -> FF 1 CLK 1K Q-I 1J Q-' FF2 CLK -> 1K CLR CLR FF3 > CLK -4 1K CLR p p Y Q+' 1J Q-' 1J -> C inary B B o utput FF4 CLK 1K CLR p Reset 1, (a) Logic diagram for ripple-type decade counter I outputs Inputs c Decade counter ( b ) Simplified logic symbol for decade counter Fig. 10-10 238 [CHAP. 10 COUNTERS 1001. Binary 1001 is the maximum count of this unit. When the count tries to advance to 1010, the two I s ( D = 1 and B = 1) a re fed into the NAND gate. The NAND gate is activated, resetting the display to 0000. A general logic symbol is sometimes used for a counter when bought in IC form. The logic symbol shown in Fig. 10-10b might be substituted for the decade counter diagram in Fig. 10-IOa. A clear (or reset) input has been added to the decade counter in Fig. 10-lob. This clear input does not appear on t he decade counter shown in Fig. 10-10a. A logical 0 activates the reset and clears the output to 0000. I t was mentioned that some counters count downward. Figure 10-11 is a diagram of such a down counter. This unit is a 3-bit ripple down counter. The binary count would be 111,110, 101,100, 011,010,001,000, followed by a recycle to 111, and so forth. Note in Fig. 10-11a that the ripple down counter is very similar to the up counter. The “trigger line” from FF1 to FF2 goes from the output to the clock input instead of from the Q o utput to the clock. Otherwise, the up counter and down . I FF2 Clock input crrq.:.. I ( a ) Logic diagram i 1J Clock input --c> FF 1 CLK 1K Q-’ 1J ,- > -O // FF2 CLK output FF3 * KCLK Q Q-llJ / Q I -a> FF3 CLK Q- 6 Fig. 10-11 A 3-bit ripple down counter &A C B Binary output A CHAP. 101 239 COUNTERS counter are wired in the same way. Note also that each JK flip-flop is in its toggle mode ( J and K equal 1). The waveform in Fig. 10-116 aids in the understanding of the operation of the down counter. The top line is the CLK input to FF1. The bottom line is the binaiy count. Note that the binary count a re shown for both FF1 and FF2. Output Q is shown starts at 111 on the left. Two outputs ((2 and for FF3. The outputs attached to the binary indicators are shown with shading on the timing diagram. Consider pulse 1 (Fig. 10-116). All flip-flops are set. The binary output on the indicators is 1 11. O n the H-to-I, transition of pulse 1, FF1 toggles. Output Q goes from HIGH to LOW goes from LOW to HIGH). The binary count is now 110. Look at pulse 2 (Fig. 10-116). On the H-to-L transition of the clock pulse, FF1 toggles. This causes output (2 to go from LOW t o H IGH. Output goes from HIGH to LOW, thereby causing FF2 to toggle. FF2 toggles, and output Q goes from HIGH to LOW goes from LOW to HIGH). The binary count is now 101. Consider pulse 3, Fig. 10-116. Pulse 3 triggers FF1. O utput Q of FFl goes LOW while goes HIGH. The binary output is now 100. Look a t pulse 4 (Fig. 10-1lb). Pulse 4 triggers FFI. FF1 is set, and output goes from HIGH to goes from HIGH to LOW. T hat i n turn LOW. That causes FF2 to toggle. FF2 is set, and output causes FF3 to toggle and reset. The binary output after pulse 4 is t hen 011. Look over the rest of the waveform. Particularly note the light vertical lines that show the triggering of the next flip-flop. Remember that the Q o utputs connect to the output indicators but the outputs of FF1 and FF2 trigger the next flip-flop. a) (e (a e SOLVED PROBLEMS 10.16 A decade counter has counts and therefore is also called a modulo- counter. Solution: A d ecade counter has 10 c ounts and is called a modulo-10 counter. 10.17 T he maximum binary count for a 3-bit counter is - (binary number). Solution: T he maximum binary count for a 3-bit counter is binary 111. (reset, set) 10.18 Refer to Fig. 10-86. The job of the NAND gate in this mod-6 counter is to the flip-flops to (binary number) after the counter’s maximum number of (binary number). Solution: T he job of t he NAND g ate shown in Fig. 10-8h is to reset the flip-flops to 000 a fter the counter’s maximum number of binary 101. 10.19 Refer to Fig. 10-9. Which flip-flop(s) toggle on the H-to-L transition of clock pulse 4? Solution: All three flip-flops toggle on the H-to-L transition of clock pulse 4 (Fig. 10-9). 10.20 R efer to Fig. 10-3. The time lag after clock pulse 4 shown with the dashed line is caused by t he delay of t he flip-flops. Solution: The time lag shown by t he dashed line after pulse 4 (Fig. 10-3) is caused by t he propagation delay of t he flip-flops. 240 COUNTERS [CHAP. 10 10.21 R efer to Fig. 10-9. Why is the pulse at point a very short? Solution: The pulse at point a, Fig. 10-9, is very short because, as i t goes HIGH, both FF2 and FF3 are set, which causes the NAND gate (see Fig. 10-8b) to reset all three flip-flops. 10.22 Refer to Fig. 10-11a and b. List the next ten binary counts after 010 on this counter. Solution: The next ten binary counts after 010 on the 3-bit down counter of Fig. 10-11 are as follows: 001,000,111,110,101,100,011,010,001,000. 10.23 R efer to Fig. 10-lla. This is a mod- (ripple, synchronous) down counter. Solution: This is a mod-8 ripple down counter. 10.24 List the binary counting sequence of a mod-9 up counter. Solution: The binary counting sequence of a mod-9 up counter is as follows: 0000,0001,0010,0011,0100,0101, 0110,0111,1000. 10.25 Refer to Fig. 10-10a. If this unit were converted to a mod-9 counter, the two inputs to the NAND gate would be ( D, , B , A ) and C ( D , C, B , A ) . Solution: If the unit shown i n Fig. 10-10a were converted to a mod-9 counter, the two inputs to the NAND gate would be A and D ,so all flip-flops would be reset immediately upon hitting the binary 1001 count. 10.26 R efer to Fig. 10-11a. List two wiring changes that will convert this 3-bit down counter to an up counter. Solution: The down counter shown in Fig. 10-lla can be converted to an up counter by making the changes shown in Fig. 10-llc: 1. Move the wire coming from Q of FF1 to output Q of FF1. of FF2 to output Q of FF2. 2. Move the wire coming from - 10.27 R efer to Fig. 10-llb. The clock input triggers FF1; the ( Q , Q ) o utput of FF1 triggers FF2; and the ( Q , G ) o utput of FF2 triggers FF3 in this ripple counter. Solution: The clock triggers FF1; the Q output of FF1 triggers FF2; and the t he ripple counter shown in Fig. 10-llb. output of FF2 triggers FF3 in 10-5 l T L IC COUNTERS Counters can be constructed from individual flip-flops and gates or be purchased from manufacturers in IC form. Several typical general-purpose TTL counter ICs will be detailed in this section. 241 COUNTERS CHAP. 101 T he 74192 IC is described by the manufacturers as a T TL synchronous BCD u p/down counter. A block symbol of the 74192 IC decade counter is shown in Fig. 10-12. Note the use of dual clock (CLK) inputs. If t he count-up clock input is pulsed, the counter will count upward from 0000 t o 1001 (0 t o 9 in decimal). If the count-down clock input is pulsed, the counter will count downward from 1001 to 0000 (9 to 0 in decimal). The counter toggles on the L-to-H transition of the clock pulse. inputs Data Inputs { =; A BCD up/downQDh QB Load-dataCount -up >CLK Count-down > CLK Clear- QA Borrow (74192) Carry Fig. 10-12 The 74192 synchronous BCD up/ciown counter IC T he asynchronous clear input to the 74192 counter shown in Fig. 10-12 is activated by a HIGH. When activated, the clear input resets all Q o utputs to LOW (0000). T he clear input overrides all other inputs. The 74192 counter can be preset to any number by activating the load-data input with a LOW. With a LOW at the load-data input, the data at the data inputs will be asynchronously transferred to the BCD o utput ( A = Q A,B = QB, C = Q,, D = Q,). T he BCD outputs shown in Fig. 10-12 <Q,,Q,,Q,,Q,) a re the normal outputs from the four flip-flops in the 74192 IC. The carry output is used when cascading several counters together. Figure 10-13 shows two 74192 ICs cascaded to form an up counter that will count from BCD 0000 0000 t o 1001 1001 (0 t o 99 in decimal). Note that the carry output of the 1s up counter is connected directly to the count-up clock input of the 10s up counter. For a cascaded down counter (99 to 0 in decimal), the borrow output of the 1s counter is connected directly into the count-down input of the 10s counter. The count-down input on the 1s counter then becomes the clock input. UP counter QA (1s) > CLK 1 QB QC QC BCD (74192) CountUP counter (10s) Q c . I Q B 1 0 Load Q A Q Clear (74192) Fig. 10-13 Cascading two 74192 ICs to form a 0--99 BCD up counter 242 COUNTERS [CHAP. 10 A manufacturer’s timing diagram for the 74192 decade counter is shown in Fig. 10-14. Shown from left to right are typical clear, load (preset), count-up, and count-down sequences. The manufacturer’s waveforms give much information on the operation of an IC. C arry Borrow I I 11 I I 1I 101 I 1 I 1 71 C lear I Preset Sequence: ( 1) Clear outputs to zero. (2) L oad (preset) to B CD seven. ( 3) C ount up to eight, nine, carry, zero, one, and two. (4) C ount down to o ne, zero, borrow, nine, eight, and seven. Notes: ( a) Clear overrides load, data, and count inputs. ( b ) W hen counting up, count-down input m ust be H IGH ; when counting down, count-up input must be H IGH. Fig. 10-14 M anufacturer’s timing diagrarn for thc 74192 d ecade counter I C (Courtesy o j National Semiconductor C orp.) A second counter in 1C form is detailed i n Fig. 10-15. A block diagram of the TTL 7493 4-bit binary counter is shown in Fig. 10-15a. Note the use of four J K flip-flops each in the toggle mode. a Inputs D , and p, re clock inputs. Note that normal output Q of the left-hand flip-flop, Fig. 10-150, is not connected to the clock input of the second FF. To form a 4-bit mod-16 ripple counter, s an external connection must be made from Q,, to @, (pin 12 to p in 1, Fig. 10-156), with Go erving as the counter clock input. The 7493 IC has two reset inputs ( M R , and M R,) a s shown in Fig. 10-15a. A mode select table for the reset inputs is in Fig. 10-15c. U nder normal use, t he reset inputs of the 7493 IC must not be left disconnected (floating). The reset pins float HIGH, which places the IC in the reset mode. While in t he reset mode, the 7493 IC cannot count. The reset inputs are asynchronous and override both clocks. CHAP. 101 243 C OUNTERS -ia,CP, C P, MRlE MR2 1 )C 3N 1 )o 2Q a DQ3 NC (4 vcc (5 NC lo> G ND B Q, E _S, Q 2 NC ( 7 ( b ) Pin diagram H = H IGH voltage level L = L OW voltage level (c) M ode select table I 8 9 10 11 12 13 14 15 O utput Q o is connected to o utput H H H H H H H H L L L L H H H H L L H H L L H H L H L H L H L H e,. ( d ) Counting sequence for 4-bit counter Fig. 10-15 7493 4-bit binary counter IC T he table in Fig. 10-1% shows the binary counting sequence for the 7493 IC wired as a mod-16 ripple counter. In Fig. 10-15b, note the unusual power connections <Vcc= pin 5 a nd GND = pin 10) o n the 7493 counter IC. SOLVED PROBLEMS 10.28 T he 74192 IC is a a nd down). (binary, decade) counter that will count (down, up, both up Solution: The 74192 IC is a d ecade counter that will count both up and down depending o n which clock input is used. 244 [CHAP. 10 COUNTERS 10.29 List the BCD o utputs for the 74192 IC counter after each of t he input clock pulses shown in Fig. 10-16. BCD output indicators Carry 0 (74192) Inputs Fig. 10-16 Up/down counter pulse-train problem Solution: Refer to the waveforms i n Fig. 10-14. The BCD outputs for the 74192 IC counter shown i n Fig. 10-16 are: pulse i = 0000 (count down) pulse a = 0000 (clear input overrides all inputs) pulse b = 0001 (count-up input pulsed) pulse j = 1001 (count-down counter cycles to pulse c = 0010 (count up) BCD 1001) pulse d = 0101 (load input activated with a pulse k = 1000 (count-down input pulsed) LOW; t he 0101 a t the data inputs pulse 1 = 0111 (count down) pulse m = 1000 (count-up input pulsed) is loaded into the counter) pulse e = 0100 (count-down input pulsed) pulse n = 1001 (count up) pulse f = 0011 (count down) pulse o = 0000 (clear input overrides all o ther pulse g = 0010 (count down) inputs) pulse h = 0001 (count down) 10.30 T he counters are said to be (cascaded, paralleled) when the carry output of o ne 74192 IC counter is fed into the clock input of the next IC. Solution: When the carry output of one 74192 IC is fed into the CLK input of the next IC, the counters are said to be cascaded. 10.31 T he 7493 IC is a (ripple-, synchronous-) type counter. Solution: T he 7493 IC is a ripple-type counter. 10.32 T he reset inputs ( M R , and M R,) on the 7493 IC are active (HIGH, LOW) inputs. Solution: See mode table in Fig. 10-15c. The 7493 IC has active HIGH reset inputs. 10.33 List the binary output from the 7493 counter 1C after each input clock pulse shown in Fig. 10-17. 245 C OUNTERS CHAP. 103 +5 Inputs Binary o utput v Is Q3 0 1 7493 M R C ounter Q1 QO Fig. 10-17 C ounter pulse-train problem S o htion: Refer to Fig. 10-15 for assistance. The binary outputs from the are a s follows: pulse pulse d = 001 1 (count up) pulse U = 0000 ( reset) pulse pulse c = 0100 (count up) pulse h = 0001 (count up) pulse pulse c = O O I O (count up) pulse f = 0101 (count up) 10.34 T he 7493 counter IC shown in Fig. 10-17 is in the pulse a . 7493 counter IC shown in Fig. 10-17 g = 01 10 (count up) h = 01 11 (count up) i -- 1000 (count up) mode of operation during clock Solution: The 7493 IC shown in Fig. 10-17 is i n t he reset mode during clock pulse a . 10.35 T he 7493 counter IC shown i n Fig. 10-17 is in the pulse b. mode of operation during clock Solution: T he 7493 IC shown i n Fig. 10-17 is i n the count mode during clock pulst: b. 10-6 CMOS IC COUNTERS A variety of counters are available from IC m anufacturers using the CMOS technology. Two representative CMOS c ounter integrated circuits are featured in this section. The first is a simple ripple counter and the second a more sophisticated presettable synchronous up/down counter. Manufacturer's data on the first CMOS counter is reproduced in Fig. 10-18. A logic diagram (called a function diagram by the manufacturer) is shown in Fig. 10-18a for the CMOS 74HC393 d u d 4-bit binary ripple counter IC. A m ore detailed logic diagram of e ach 4-bit ripple counter is shown in Fig. 10-18c. N ote the use of f our T flip-flops. The clock inputs (1- and 2D)a re edge-triggered on t he HIGH-to-LOW transition of the clock pulse as indicated in the pin description table in Fig. 10-18h. The master reset pins (1MR and 2 M R ) o n the 74HC393 counter are active HIGH inputs. The flip-flop outputs of t he counter are labeled as Q,, t o Q 3 with Q ,, being the LSB while Q 3 holds the MSB of t he 4-bit binary number. The 74HC393 dual 4-bit binary counter is packaged in a 14-pin DIP I C which is illustrated in Fig. 10-18d. T he 74HC393 counter requires a 5 -V d c power supply. 246 I COUNTERS - [ CHAP. 10 PIN NO. SYMBOL NAME AND FUNCTION 1, 13 2, 12 3, 475, 6, 11, 10, 9, 8 7 1 lcp, 2 c p clock inputs (HIGH-to-LOW, edge-triggered) asynchronous master reset inputs (active HIGH) flip-flop outputs GND g round (0 V) positive supply voltage IMR, 2MR lQ, to l Q3. 2Q0 to 2Q3 14 vcc (b) 1cp 1MR 1Qn CP IQ, 393 lQ2 MR IQ3 Qn Q, Q2 Q3 GND Fig. 10-18 CMOS d ual 4-bit binary counter IC (74HC393) ( a ) F unction diagram. ( b ) Pin descriptions. ( c ) D etailed logic diagram. ( d ) Pin diagram. (Courtesy of Signetics Corporation) T he second featured CMOS counter is the 74HC193 presettable synchronous 4-bit u p / down counter I C. Details of t he 74HC193 counter are shown in t he manufacturer’s data in Fig. 10-19. A function diagram, table of pin descriptions, and pin diagram for the 74HC193 counter are shown in Fig. 10-19a, b , and c. T he 74HC193 counter has two edge-triggered clock inputs ( CPU and CP,) which operate on the LOW-to-HIGH transition of the clock pulse. One clock input is used when counting up (CP,,) while the other is for counting down (CP,). When using the count up ( C P U )input for implementing an up counter, the count down (CP,) pin must be tied to HIGH o r + 5 V. A t ruth table detailing the operating modes of the 74HC193 CMOS counter is in Fig. 10-19d. T he reset mode asynchronously clears the outputs ( Q3, Q 2 , Q ,, and Q,,) t o binary 0000. T he reset pin ( M R ) is an active HIGH input which overrides all other inputs (such as the load, count, and data inputs). The reset ( M R ) input is activated with a HIGH briefly on the left side of the waveform diagram in Fig. 10-19e when it cleais all flip-flops to 0. T he parallel load inputs on the 74HC193 counter IC include the four data pins ( D o to D 3 ) and the parallel load pin ( E).he parallel load T inputs are for presetting the counter to any given 4-bit count. A preset sequence is shown near the left activated with a LOW. During the parallel load in the waveform diagram in Fig. 10-19e w ith t he operation, binary information from the data inputs ( D 3 , D ,, D , , and D o ) is asynchronously transferred to the outputs ( Q 3 , Q 2 , Q ,, and Q,,). In this example (Fig. 10-19e), binary 1101 is being loaded into the counter. The reset ( M R ) input must be LOW during the parallel load operation. Typical count-up and count-down sequences are also shown on the waveform diagram in Fig. 10-19e. During the count-up and count-down sequences, the operation of the carry ( E,,) borrow ( E,) and C HAP. 103 247 C OUNTERS P IN DESCRIPTION I 1 PINNO. S YMBOL NAM N - E Autputs - D FIIN('TI<)N flip-flop o c ount d o w n clock i n p i i t * count u p cluck i n p u t * ground I I ) V J a synchionou\ parallel Iodd i n p u t (active i O W ) t erniin;il count u p ( carry) output ( active L O W ) t crrnin;il count d o w n ( h o r r t i u ) output (active L OW) a synchvonou\ mabter r o e ( lnput ( d ~ t i v e 1 1 G 1 1 ~ 1 d ata inputs p osltlvf' supply v ultagc ' L OW-to-IIIGH. edgc t riggered *-K ',.,= <'PI * * K , ,- a t t erminal cuunt u p (llHl1HJ c.P,> at t erminal c ount d o w n (1.i.I.L) 11 1. X T = = = I l l G H v oltage level I .0W v oltage level d on't c are 1.OW-to l 11GH c lock t r a i i v t i o n (4 Fig. 10-19 CMOS p rcsettable 4-bit synchronous up/down counter 1C (74HC193) ( a ) Function diagram. ( b ) Pin descriptions. ( c ) Pin diagram. ( d ) T ruth table. (e) Typical clear, preset, and count sequence. (Courtesy o f Signetrc, Corporation) 248 C OUNTERS [CHAP. 10 o utputs can be noted. These carry and borrow outputs are used when cascading counters (producing 8-, 12-, or 16-bit devices) as either up or down counters. Note that the carry and borrow outputs a nd g enerate a negative pulse for either a carry or a borrow. The 74HC193 counter is housed in a 16-pin DIP and operates on a 5-V d c power supply. (w, z D) SOLVED PROBLEMS (one, two, four) 4-bit binary 10.36 R efer to Fig. 10-18. The 74HC393 IC contains (ripple, synchronous) counters in a single DIP package. Solution: T he 74HC393 IC contains two 4-bit binary ripple counters. (edge, level)- 10.37 R efer to Fig. 10-18. The clock inputs to the 74HC393 counters are triggered on the (H-to-L, L-to-H) edge of the clock pulse. Solution: See Fig. 10-18b. The clock inputs to the 74HC393 counters are edge-triggered on the H-to-L edge of the clock pulse. 10.38 Refer to Fig. 10-18. Each counter in the 74HC393 IC contains flip-flops. (three D , four T ) Solution: See Fig. 10-18c. Each counter in the 74HC393 IC contains four T flip-flops. 10.39 R efer to Fig. 10-18. The reset pins to the counter in the 74HC393 are active LOW) inputs. (HIGH, Solution: See Fig. 10-18h. The reset pins (1MR and 2 M R ) on the 74HC393 counter are active HIGH inputs. 10.40 R efer to Fig. 10-18. The normal counting sequence of a 4-bit counter (74HC393) would be from 0000 through in binary. Solution: Normal counting sequence for the 4-bit counter (74HC393) would be from 0000, through 111l ,, and with continued clock pulses, the count would recycle back to 0000, 0001, etc. 10.41 Draw the 4-bit binary counter wired to operate as a decade (mod-10) counter. Use a 74HC393 4-bit counter and a 2-input AND gate. Solution: One method of converting a 4-bit binary counter into a decade counter using the 74HC393 IC is shown in Fig. 10-20. 249 C OUNTERS CHAP. 101 vcc - --m Clock input uc c) Counter L?3 0 Q2 - e, e o c> C P dt 4 (74HC393) MR I( GND - Fig. 10-20 A decade (mod-10) counter circuit 10.42 T he 74HC193 IC is described as a(n) up/down counter manufactured using (4,8)-bit presettable (ripple, synchronous) (CMOS, 7TL) technology. Solution: T he 74HC193 IC is described as a CMOS presettable 4-bit synchronous up/down counter. 10.43 Refer to Fig. 10-19. Why does the 74HC193 counter have two clock inputs? Solution: T he 74HC193 counter has CPU (count up) and CP, (count down) clock inputs. The CPU pin is used if t he design calls for an up counter or the CP, input is used when developing a down counter. The two clock inputs make the 74HC193 counter a more versatile IC. 10.44 Refer to Fig. 10-19. The (parallel load, reset) pin is an asynchronous active HIGH input that causes the output of the 74HC193 counter to be cleared to 0000 when activated. Solution: The reset ( M R ) pin is an asynchronous active HIGH input that causes the output of t he 74HC193 counter to b e cleared to 0000 when activated. 10.45 Draw a mod-6 counter that has a counting sequence of 001,010,011,100,101,110,001,010, etc. This is the type of counter that might be used to simulate the roll of a die in a dice game. Use the 74HC193 IC and a 3-input NAND. Solution: See Fig. 10-21. 250 COUNTERS [CHAP. 10 0 0 inputs 0 1 +5 v mClock Fig. 10-21 A mod-6 counter circuit (counts 1 to 6) 0 1 - +5 - c PL 0 D3 1 Inputs 1 4-5 v vcc C ounter Q3 Q2 D2 1 Binary output v 0 1 ' Qi Do 4 Q" ~> PD C (74HC193) > CPU MR GND - 1 Fig. 10-22 Counter pulse-train problem CHAP. 101 25 1 COUNTERS 10.46 Refer to Fig. 10-22. The 74HC193 IC is wired as a modcircuit. (number) counter in this Solution: T he 74HC193 I C is wired as a mod-10 (decade) counter in the circuit in Fig. 10-22. 10.47 Refer to Fig. 10-22. List the mode of operation during each pulse a t o f . (Use answers parallel load, count up, or count down.) Solution: pulse a = parallel load pulse b to f = count up 10.48 R efer to Fig. 10-22. List the binary output for the 74HC193 counter after each pulse a t o f. Solution: T he binary output of the decade counter in Fig. 10-22 after each pulse is as follows: pulse a = 01 11 (parallel load to 01 11) pulse b = 1000 pulse c = 1001 pulse d = 0000 (reset to 0000) pulse e = 0001 pulse f = 0010 10-7 FREQUENCY DMSION: THE DIGITAL CLOCK T he idea of using a counter for frequency division was introduced in Sec. 10-2. It was mentioned that, for the 4-bit counter shown in Fig. 10-2, the A o utput could be considered a divide-by-2 output because it divides the clock input frequency in half. Likewise, B (Fig. 10-2) can serve as a divide-by-4 output, C is a divide-by-8 output, and D is a divide-by-16 frequency division output. One digital system that makes extensive use of counters is diagrammed in Fig. 10-23. The digital clock uses counters as frequency diriders in the lower section. ‘The counters shown in Fig. 10-23 are also used as count accumulators. T he count accumulator’s job is to count the input pulses and serve as a temporary memory while passing the current time through the decoders onto the time displays. The block diagram in Fig. 10-23 represents a 6-digit 24-h digital clock. The input to the frequency dividers shown in Fig. 10-23 is a 60-Hz square wave. The divide-by-60 blocks could be constructed by using a divide-by-6 counter feeding a divide-by-10 counter. A block diagram of such an arrangement is in Fig. 10-24a. The divide-by-6 counter on the left divides the 60 Hz to 10 Hz. T he divide-by-10 counter on the right divides the 10 Hz to 1 Hz, or 1 pulse per second. The divide-by-60 block is shown implemented by using 7493 ICs in Fig. 10-24b. The divide-by-10 counter shown in Fig. 10-24b is implemented by first making an external connection from (Io o B ,. his makes the 7493 IC a 4-bit binary counter. Second, the IC must be t T converted to a decade or mod-10 counter. This is accomplished by resetting the counter outputs to 0 when binary 1010 first appears. The resetting is done by using the HIGH outputs from Q 3 and Q , tied back to the two reset inputs on the 7493 IC. T he divide-by-6 counter shown in Fig. 10-24b is wired like the unit diagrammed earlier in Fig. 10-8. T he first flip-flop inside the 7493 IC package is not used, so B , becomes the clock input to the divide-by-6 counter. The 0 to 59 count accumulators in the block diagram of the digital clock shown in Fig. 10-23 are actually two counters. A block diagram showing more detail of the seconds count accumulator/ decoder/display section is sketched in Fig. 10-25. A decade (mod-10) counter is needed to accumulate 252 C OUNTERS [CHAP. 10 Fig. 10-23 Block diagram of a digital clock ( Roger L . T okheim, Digital Electronics, 3d e d., McGruw-Hill, New Y ork, 1 990) 00 OJUUUUL 1 Hz 60 Hz t5 v ( a) Block d iagram - output 15 I nput + b y 10 60 H z 2 3 M R l ( 7493) MR2 TG1 1 GND IC ( h ) Wiring d iagram using 7403 c ounters Fig. 10-24 Divide-by-60 c ounter QI ,9 12 G- 1 Hz COUNTERS CHAP. 101 253 Fig. 10-25 D etailed block diagram of t he seconds count accumulator of t he digital clock t he I s of seconds. This decade counter is driven directly from the output of the first divide-by-60 frequency divider. As t he decade counter sequences from 9 back to 0, it generates a “carry pulse” which is sent to the mod-6 10s of seconds counter. The decoder/drivers serve to decode the BCD t o seven-segment display output. The minutes and hours count accumulators shown in Fig. 10-23 a re connected similarly to the seconds accumulator. The minutes count accumulator would consist of a d ecade and mod-6 counter (like the seconds accumulator). However, the hours count accumulator would consist of a d ecade and a mod-3 counter (or mod-2 counter for a 12-h clock). SOLVED PROBLEMS 10.49 T he divide-by-60 block of t he digital clock shown in Fig. 10-23 could be constructed by using two . Solution: S ee Fig. 10-24. The divide-by-60 block shown in Fig. 10-23 could be wired by using two counters. 10.50 T he 0 t o 59 count accumulator of t he digital clock shown in Fig. 10-23 could be constructed by using . Solution: S ee Fig. 10-25. T he 0 t o 59 c ount accumulator shown in Fig. 10-23 could be wired by using two counters. 254 COUNTERS [CHAP. 10 10.51 Draw a diagram of decade and mod-6 counters wired to form t he count accumulator shown in Fig. 10-25. Use two 7493 ICs. Solution: See Fig. 10-26. r -4 w Q3 Q 2 Q i Q3 Q2 Q i Qo Decade c ounter ( 7493) Mod-6 c ount er ( 7493) Fig. 10-26 Wiring of a 0 t o 59 count accumulator circuit 10.52 Draw a diagram of t he divide-by-60 frequency divider shown in Fig. 10-23. Use two 7493 ICs. Solution: See Fig. 10-24b. a, used as the clock input of the divide-by-6 counter, whereas the pin 10.53 Why is the 7493 IC’s decade counter uses the Dopin as the clock input? Solution: Refer to Fig. 10-15a. The divide-by-6 counter uses only the three JK flip-flops shown on the right in Fig. 10-15a and uses the pin as the clock input. The decade counter uses all four flip-flops in the 7493 IC and uses the Gopin as the clock input. a, Supplementary Problems 10.54 A counter that counts from 0 to 4 is called a mod- 10.55 Draw a logic diagram of a 5-bit ripple up counter using five JK flip-flops. counter. Ans. 5 I 1 +I* Clock input Am. See Fig. 10-27. -> J FF3 CLK Q- 1K Fig. 10-27 A 5-bit ripple up counter I d CHAP. 101 255 COUNTERS 10.56 T he maximum binary count of a 5-bit counter is decimals. Ans. ( a ) 11111 ( 6 ) 31 10.57 In a 4-bit counter, FF4 is usually designated as the Ans. MSB (most significant bit) 10.58 (binary number), which equals 10.59 Refer to Fig. 10-3. On the trailing edge of clock pulse 15, which flip-flop(s) toggle? Ans. Only FF1 toggles. 10.60 (6) Refer to Fig. 10-3. On the H-to-L transition of clock pulse 8, how many flip-flops toggle? Ans. All four Refer to Fig. 10-3. With clock pulse 16 HIGH, what is the state of each flip-flop? Ans. All four flip-flops are set ( Q outputs are HIGH). (a) (LS13, MSB) counter. 10.61 Refer to Fig. 10-3. After the trailing edge of clock pulse 16, the binary count is and all four flip-flops are (6) ( reset,set). in Ans. ( a ) 0000 (b) r (binary number) (a) e s r 10.62 Refer to Fig. 10-3. Which flip-flop affects FF4 and makes it toggle? Ans. O utput Q of FF3 is connected to the CLK input of FF4 and makes i t toggle when the pulse goes from HIGH to LOW. 10.63 Refer to Fig. 10-5. What is the binary count after pulse 4? 10.64 R efer to Fig. 10-5. T he output Q of FF2 will go HIGH again on the trailing edge of clock pulse (5, 6). Ans. 6 10.65 R efer to Fig. 10-5. The output of FF1 will go HIGH on the 5. Ans. trailing 10.66 Refer to Fig. 10-5. After clock pulse 7, FF1 is (reset, set), FF2 is (reset, set). Ans. All the flip-flops are set ( Q = 1). 10.67 Refer to Fig. 10-5. Which flip-flop(s) toggle on the H-to-L transition of clock pulse 7? Ans. Only FF1 toggles. 10.68 Refer to Fig. 10-5. T he binary count after clock pulse 9 will be 10.69 The 10.70 Refer to Fig. 10-7. The fact that all flip-flops toggle at exactly the same time (see dashed line) means this timing diagram is for a(n) (asynchronous, synchronous') counter. Ans. synchronous Ans. 100 (leading, trailing) edge of clock pulse . (reset, set), and FF3 is Ans. 001 (parallel, ripple) counter is an example of a synchronous device. Ans. parallel 10.71 Refer to Fig. 10-7. When clock pulse 6 is H IGH, FF1 is in its toggle mode, FF2 in its toggle) mode, and FF3 in its (h) (hold, toggle) mode. Ans. ( a ) toggle (parallel, ripple) counter is the more complicated device. (a) ( b ) hold (hold, 10.72 The 10.73 The basic building block for combinational logic circuits is the gate. The basic building block for . Ans. flip-flop sequential logic circuits is the Ans. parallel 256 10.74 C OUNTERS [CHAP. 10 R efer to Fig. 10-28. The clear (or reset) input on the counter is activated by a (HIGH, LOW). Ans. The clear input on the counter shown in Fig. 10-28 is activated by a LOW, or logical 0. This is symbolized by the small bubble at the clear input. Binary o utput Clock I I I 1 I I 1 I 0 I -,+ C ounter CLK QD Qc QB Clear 4 (Reset) CLR QA Fig. 10-28 C ounter pulse-train problem 10.75 List the binary output after each of t he clock pulses for the decade up counter shown in Fig. 10-28. Ans. pulse a = 0000 pulse c = 0010 pulse e = 0100 pulse g = 0110 pulse i = 1000 pulse b = 0001 pulse d = 0011 pulse f = 0101 pulse h = 0111 pulse j = 1001 10.76 Assume the counter shown in Fig. 10-28 is a mod-16 down counter. List the binary output after each clock pulse. Ans. pulse a = 0000 pulse c = 1110 pulse e = 1100 pulse g = 1010 pulse i = 1000 pulse b = 1111 pulse d = 1101 pulse f = 1011 pulse h = 1001 pulse j = 0111 10.77 Draw a logic diagram of a mod-12 ripple up counter by using four JK flip-flops (with clear inputs) and a Ans. See Fig. 10-29. 2-input NAND gate. 1 Clock input 1 11 J -C> Q--( FF2 CLK 1 K CLR t,J -11 1 K ’CLR , J FF4 ‘ w>CLK Q -I Binary o utput 1 K CLR P Fig. 10-29 Mod-12 ripple up counter Reset CHAP. 101 257 COUNTERS 10.78 Draw a logic diagram for a divide-by-5 ripple counter by using three JK flip-flops (with clear inputs) and a Am. See Fig. 10-30. 2-input NAND gate. Show clock input and only the divide-by5 output. 1J Clock input , FF 1 CLK Q- 1 J FF2 ‘t--a> C LK 1 K CLR Q n Divide-by-5 o utput 1 K CLR Reset Fig. 10-30 Divide-by-5 ripple counter 10.79 Refer to Fig. 10-31. The clear (CLR) input to the 74192 counter IC is an active input. Ans. H IGH u.mJ+-’ Down r7-r 1 CLK CLR (74192) (HIGH, LOW) D - Borrow - *Carry Fig. 10-31 Counter pulse-train problem 10.80 List the BCD outputs of the 74192 IC counter after each of the input clock pulses shown in Fig. 10-31. Ans. pulse a = 0000 (clear) pulse f = 0100 pulse j = 1000 pulse k = 0000 (clear) pulse g = 0101 pulse b = 1001 pulse 1 = 0001 pulse h = 0110 pulse c = 1000 pulse rn = 0010 pulse i = 01 11 pulse d = 0111 pulse e = 0011 (load) 10.81 Refer to Fig. 10-32. List the binary Ans. pulse a = 000 (reset) pulse b = 001 (count up) pulse c = 010 (count up) outputs of the 7493 counter pulse d = 011 (count up) pulse e = 100 (count up) pulse f = 101 (count up) IC after each clock pulse. pulse g = 110 (count up) pulse h = 111 (count up) pulse i = 000 (count up) 258 COUNTERS Clock [CHAP. 10 G>CPl vcc 7 493 Q3 - Q2- Fig. 10-32 Counter pulse-train problem 10.82 T he 7493 IC detailed in Fig. 10-32 is wired as a mod- 10.83 T he 7493 IC shown in Fig. 10-32 is in the Ans. reset (or clear) 10.84 Ans. mod-8 mode of operation during clock pulse a . Refer to Fig. 10-18. The 74HC393 IC is described by the manufacturer as a CMOS dual 4-bit binary) counter. Ans. 4-bit binary 10.85 R efer to Fig. 10-18. The 74HC393 IC is a 10.86 up counter. (ripple, synchronous) counter. Refer to Fig. 10-33. T he 74HC393 IC is wired as a modAns. 8 (decade, Ans. ripple (decimal number) counter in this circuit. Binary output vcc Counter Clock input m- 123 1 22 - c> C P Ql Qo . Fig. 10-33 . Ans. 0111 10.87 Refer to Fig. 10-33. T he circuit counts from a low of binary 0000 t o a high of 10.88 Refer to Fig. 10-19. On the 74HC193 IC, if both the reset ( M R ) and parallel load ( E) ins are activated p at the same time, the input will override all others. Ans. reset ( M R ) 259 COUNTERS CHAP. 101 10.89 Refer to Fig. 10-34. What is the mode of operation for the 74HC193 counter during clock pulse a? Ans. parallel load 10.90 Refer to Fig. 10-34. What is the mode of operation for the 74HC193 counter during clock pulse b? Ans. count down 10.91 Refer to Fig. 10-34. What is the mode of operation for the 74HC193 counter during clock pulse f ? Ans. reset (or clear) Inputs 1 0 +5 - Binary output v I Q3 1 D2 0 Dl t D3 1 I 1 vcc Q2 Counter Qi 1 Fig. 10-34 10.92 Refer to Fig. 10-34. List the binary output after each of the clock pulses for the 74HC193 counter circuit. Ans. pulse a = 1101 pulse h = 1100 pulse c = 1011 pulse d = 1010 pulse e = 1001 pulse f = 0000 10.93 Refer to Fig. 10-2. If the frequency of the clock input were 1 MHz, the frequency at output A of FF1 . Ans. 500 kHz, or 0.5 MHz would be 10.94 Refer to Fig. 10-2. If the frequency of t he clock input were 1 MHz, the frequency at output C of FF3 would be . Ans. 125 kHz 10.95 Refer to Fig. 10-23. Digital devices called Ans. counters, or counter ICs digital clock. are used to implement the divide-by-60 circuits in this 10.96 Refer to Fig. 10-23. Digital devices called Ans. counters, or counter ICs digital clock. are used to implement the count accumulators in this 10.97 Refer to Fig. 10-24a. If the input frequency on t he left were 600 kHz, the output frequency would be . Ans. 10 kHz. Chapter 11 §hift Registers 11-1 INTRODUCTION T he s hift register is one of the most widely used functional devices in digital systems. The simple pocket calculator illustrates the shift register’s characteristics. To e nter the number 246 o n t he calculator, the 2 key is depressed and released. A 2 is displayed. Next the 4 key is depressed and released. A 24 is displayed. Finally, the 6 key is depressed and released. The number 246 is displayed. On a typical calculator, the 2 is first shown on the right of the display. When the 4 key is depressed, the 2 is shifted to the left to make room for the 4. The numbers are progressively shifted to the left on the display. This register operates as a shift-left register. Besides the shifting characteristic, t he calculator also exhibits a memory characteristic. T he proper calculator key (such as 2) is depressed and released, b ut the number still shows on the display. The register “remembers” which key was pressed. This temporary memory characteristic is vital in many digit a1 circuits. Shift registers are classed as sequential logic circuits, and as such they are constructed from flip-flops. Shift registers are used as temporary memories and for shifting data to the left or right. Shift registers are also used for changing serial to parallel data or parallel to serial data. One method of identifVing shift registers is by how data is loaded into a nd read from t he storage units. Figure 11-1is a register 8 bits wide. The registers in Fig. 11-1 a re classified as: 1. 2. 3. 4. Serial-in serial-out (Fig. 1 1-la) Serial-in parallel-out (Fig. 1 1-lb) Parallel-in serial-out (Fig. 1 1 - l c ) Parallel-in parallel-out (Fig. 1 1-ld) T he diagrams in Fig. 11-1i llustrate the idea of each type of register. Fig. 11-1 Types of shift r egisters 260 CHAP. 111 SHIFT REGISTERS 26 1 11-2 S E W - L O A D SHIFT REGISTER A simple 4-bit shift register is illustrated in Fig. 11-2. Note the use of four D flip-flops. Data bits (OS a nd 1s) a re fed into the D i nput of FF1. T his input is labeled as the serial-data input. The clear input will reset all four flip-flops to 0 when activated by a LOW. A pulse at the clock input will shift the data from the serial-data input to position A ( Q of FF1). The indicators ( A ,B , C, D ) across the top of Fig. 11-2 show the contents of each flip-flop or the contents of the register. This register can be classified as a serial-in parallel-out unit if data is read from the parallel outputs ( A ,B , C, 0 )across the top (Fig. 11-2). Pa r;i I I e 1-d ;t a o utput I n d ica t o r s I Serialdata I nputs Clear Clock - I - A Fig. 11-2 Logic diagram of a 4-bit serial-load shift-right register Assume all the flip-flops shown in Fig. 11-2 a re reset ( Q = 0). T he output is then 0000. Place the clear input at 1. Place a 1 a t the data input. Pulse the clock input o nce. T he outputs will then read 1000 ( A = 1, B = 0, C = 0, D = 0). Place a 0 a t the data input. Pulse the clock input a second time. The output now reads 0100. After a third pulse, the output reads 0010. A fter a fourth pulse, the output reads 0001. The binary word 0001 has been loaded into the register one bit at a time. This is called serial loading. N ote that, on each clock pulse, the register shifts data to the right. This register could then be called a serial-load shift-right register. As with other sequential logic circuits, waveforms (timing diagrams) are an aid to understanding circuit operation. Figure 11-3 illustrates the operation of the 4-bit serial-load shift-right register. The Fig. 11-3 T iming diagram for a 4-bit serial-load shift-right register 262 SHIFT REGISTERS [CHAP. 11 t hree inputs (serial-data, clear, and clock) to the register are shown across the top. The parallel outputs are shown in the middle-four lines. Note that the outputs are taken from the normal output ( Q ) of each flip-flop. The bottom line describes several functions of the shift register. Consider the initial conditions of all the flip-flops shown in Fig. 11-3. All are set. At point a on the clear-input waveform, all the flip-flops are reset to 0000. T he clear input operates asynchronously and overrides all other inputs. Note that the clear input is a n active-LOW input. At point b o n the serial-data input, a HIGH is placed on the D input to FF1. On the leading edge of clock pulse 1, the HIGH is transferred to output Q of FFI. The output now reads 1000. Clock pulse 2 transfers a 0 t o output Q of FFl. At the same time, the 1 at input D t o FF2 is transferred to output Q of this flip-flop. The output is now 0100. Clock pulse 3 transfers a 0 t o the output of FF1. The 1 at input D of FF3 is transferred to the output of this flip-flop. The output of the register is now 0010. Clock pulse 4 transfers a 0 t o the output of FF1. The 1 at input D of FF4 is transferred to the output of this flip-flop. The output of the register is now 0001. It took four clock pulses (pulses 1 through 4, Fig. 11-3) to serially load the 4-bit word 0001 into the register. Consider clock pulse 5 (Fig. 11-3). Just before pulse 5 , t he register contents are 0001. Clock pulse 5 adds a new 0 a t the left (at Q of FFl), and the 1 on the right is shifted out of the register and is lost. The result is that the register contents are 0000 after clock pulse 5. Consider clock pulses 6 through 9 (Fig. 11-3). T hese four pulses are used to serially load the binary word 1001 into the register. At point c t he serial-data input is placed at 1. On the L-to-H transition of clock pulse 6, this 1 is transferred from the D input of FF1 to its Q output. After pulse 6 t he register reads 1000. The serial-data input is r eturned to 0 at point d . Clock pulses 7 and 8 shift the 1 t o the right. After clock pulse 8, t he register reads 0010. T he serial data input is placed at 1 a t point e . O n the leading edge of clock pulse 9, this 1 is placed at output Q of FF1 and the other data is shifted one place to the right. The register contents after clock pulse 9 a re 1001. It took four clock pulses (6 through 9) t o serially load 1001 into the register. Consider clock pulses 10 through 12 (Fig. 11-3). The serial-data input remains at 1 during these pulses. Before pulse 10 t he register contents are 1001. On each pulse, a 1 is added to output Q of FF1 and the other 1s are shifted to the right. After clock pulse 12, t he register contents are 1111. If output D of FF4 in Fig. 11-2 is considered the only output, this storage unit could be classified as a serial-in serial-out shift register. SOLVED PROBLEMS 11.1 T he 4-bit shift register described in this section uses flip-flops. (decimal number) Solution: T he 4-bit register uses four D flip-flops. 11.2 T he flip-flops shown in Fig. 11-2 a re (leading-, trailing-) edge triggered. Solution: T he flip-flops shown in Fig. 11-2 are leading-edge triggered. 11.3 I n Fig. 11-2, the shift-right operation means to shift data from (FF1, FF4). Solution: By definition, shift right means to shift data from FF1 to FF4 in Fig. 11-2. (FF1, FF4) to ( D, ) T 263 SHIFT REGISTERS C HAP. 111 11.4 Refer to Fig. 11-2. Clear is an active- (HIGH, LOW) input. Solution: Clear is an active-LOW input in Fig. 11-2, as shown by the bubbles on the CLR inputs of each D flip-flop. 11.5 Refer to Fig. 11-3. T he clear is a(n) (asynchronous, synchronous) input. Solution: T he clear is an asynchronous input to the register (Fig. 11-.3). 11.6 Refer to Fig. 11-4. List the states of the output indicators of t he shift register after each clock pulse (bit A on left, bit D o n right). Serial- D Q Q +D FF2 > CLK CLK 1 1 & - Clear - --> FF3 CLK n I I FF4 >CLK I n A Solution: T he output states of the register shown in Fig. 11-4 are as follows: pulse a = 0000 pulse b = 1000 pulse c = 0100 pulse d = 1010 pulse e = 0000 Clear mode resets all FFs to 0. Shift-right mode moves bits one position to the right on leading edge of clock pulse. Note that the 1 at the D input to FF1 is shifted to the (2 o utput of F Fl. Shift-right mode moves bits one position to the right. Note that the 0 a t the D input to FF1 is shifted to the Q o utput of FFl. Shift-right mode moves bits one position to the right. Note that the 1 at D input to FF1 is shifted to the Q o utput of FF1. Temporarily the output goes to 0101 on leading edge of t he clock pulse. Then the clear input is activated, resetting all FFs to 0. pulse f = 1000 pulse g = 1100 pulse h = 1110 pulse i = 0111 pulse j = 0011 Shift-right mode moves bits one position to the right. Shift-right mode moves bits one position to the right. Note that a 1 is being shifted into the leftmost position from input D of FF1. Shift-right mode moves bits one position to the right. Shift-right mode. Note the 0 being loaded into the left position from input D of FF1. Shift-right mode. Note the 0 being loaded into the left position. 264 [CHAP. 11 S HIFT REGISTERS 11.7 R efer to Fig. 11-4. This is a (parallel-, serial-) load shift- (left, right) register. Solution: T he device shown in Fig. 11-4 is a serial-load shift-right register. 11.8 R efer to Fig. 11-4. After clearing, it takes register. clock pulse(s) to load a 4-bit word into this Solution: I t takes four clock pulses to serially load the register shown in Fig. 11-4. 11.9 R efer to Fig. 11-4. The CLK inputs to the flip-flops are wired in therefore all shifts take place at the same time. (parallel, series), and Solution: T he CLK inputs to the flip-flops shown in Fig. 11-4 a re wired in parallel. 11-3 PARALLEL-LOAD SHIFT REGISTER T he disadvantage of t he serial-load shift register is that it takes many clock pulses to load the unit. A parallel-load shift register loads all bits of information immediately. One simple 4-bit parallel-load shift register is diagrammed in Fig. 11-5. Note the use of JK flip-flops with both CLR and PS inputs. The inputs at the left are the clear, clock, and four parallel-data (parallel-load) inputs. The clock connects each CLK input in parallel. The clear connects each CLR input in parallel. The P S input for each flip-flop is brought out for parallel-data loading. The output indicators across the top of Fig. 11-5 show the state of output (2 of each flip-flop. Note the wiring of the J K flip-flops. Especially note the two feedback lines running from the Q of F F4 back to the J of FF1 and from the of FF4 back to the K of FF1. T hese are recirculating lines, and they save the data that would normally be lost out the ,right end of t he register. It is said that the data will recirculate through the register. Parallel-data output indicators Paralleldata (load) [ Q D A 1 1 A -JpsQr FF 1 ----O>CLK Inputs Q ! , JpsQ. FF2 4) LK C 6 3 A 0 1 Q I +> K CLRQ u - JPSQ’ FF3 CLK KCLRQ 9 Q I I n b - KCLRQ A& 1 n J ps Q 5 FF4 d>CLK * KCLRQ 0 J Clock Clear A A Fig. 11-5 Logic diagram of a 4-bit parallel-load recirculating shift-right register N ote from the JK flip-flop logic symbols in Fig. 11-5 t hat the PS and CLR inputs are active-LOW inputs. They are also asynchronous and override all other inputs. Assume that these JK flip-flops are pulse-triggered units. CHAP. 111 S HIFT REGISTERS 265 A waveform diagram for the parallel-load recirculating shift-right register is shown in Fig. 11-6. The top four lines on the diagram are the parallel-data inputs, or load inputs. These are normally HIGH and are placed LOW only when loading. The clear and clock inputs are shown near the center of the diagram. Fig. 11-6 Timing diagram for a 4-bit parallel-load recirculating shift-right register T he four shaded waveforms in Fig. 11-6 are the outputs at Q of each JK flip-flop. Across the bottom of the diagram are functions being performed by the register. Consider the outputs on the left side of Fig. 11-6. The outputs are 1111 before point a on the clear waveform. At point a , t he outputs are immediately reset to 0000. T he clear input is asynchronous and therefore needs no clock pulse to reset the register. At point b t he A and B parallel-data inputs are activated. Being asynchronous inputs, the outputs of FF1 and FF2 go HIGH immediately. At point c , t he A and B parallel-data inputs are deactivated. The register is now loaded with 1100. On the trailing edge of clock pulse 1, the two 1s shift one position to the right. The result is 0110 after clock pulse 1. A nother right shift takes place on the trailing edge of clock pulse 2. The result after pulse 2 at the outputs of the JK flip-flops is 0011. Consider clock pulse 3, shown in Fig. 11-6. The output was 0011 before pulse 3. O n the trailing edge of pulse 3, a right shift takes place. The 1 a t Q of FF4 would normally be lost, but because of the recirculating lines (see Fig. 11-5) it is shifted back around to Q of FF1. T he result is that the register contents are 1001 after clock pulse 3. Likewise, clock pulse 4 shifts the register one place to the right. The 1 a t Q of FF4 is shifted to Q of FF1. T he results are that, after pulse 4, the register contains 1100. This is the same data that was loaded in the register prior to clock pulse 1. It took four pulses to recirculate the data to its original position. Consider point d on the clear waveform in Fig. 11-6. It is an asynchronous input; therefore, as soon as it goes LOW, all flip-flops are reset. Clock pulse 5 has no effect because the clear input overrides the clock. 266 [CHAP. 11 S HIFT REGISTERS Consider point e on the parallel-load waveform in Fig. 11-6. For a very short time, parallel-data input D is activated and then deactivated. It loads 0001 into the register. Clock pulse 6 recirculates the 1 a t output Q of FF4 to FF1. After pulse 6, t he register contains 1000. Pulses 7, 8, and 9 shift the single 1 to the right three places. After the four pulses (6 through 9), t he data is the same as t he original: 0001. A careful look at Figs. 11-5 and 11-6 will show that the J K flip-flops are always operating in either the set o r reset modes. Before pulse 6 (Fig. 11-6), the Q o utputs are 0001. However, remember that the complementary 0 o utputs are at the same instant 1110. On the trailing edge of clock pulse 6, FF1 goes from the reset to the set condition because it has inputs of J = 1 and K = 0. FF2 has inputs of J = 0 and K = 1 and therefore stays in the reset condition. FF3 has inputs of J = 0 and K = 1 and therefore stays in the reset condition. FF4 has inputs of J = 0 and K = 1 . FF4 changes state and goes from the set to the reset condition. The circuit shown in Fig. 11-5 is but one of many parallel-load shift registers. Because these registers are somewhat complicated, they are often purchased i n I C form. The shift register shown in Fig. 11-5 might also be called a ring counter if a single 1 is loaded into the register. If a continuous series of pulses arrives at the clock input, the lone HIGH o utput will sequence in a “ring” in t he register. Each output ( A , R , C, and 0 ) can then be turned on (HIGH = o n) in sequence as the ring counter shifts. SOLVED PROBLEMS 11.10 Refer to Fig. 11-5. The parallel-load recirculating register uses four with asynchronous and ( D , J K ) flip-flops inputs. Solution: The register shown in Fig. 11-5 uses four J K flip-flops w ith asynchronous clcar ( CLR) and preset ( P S ) inputs. 11.11 Refer to Fig. 11-5. The asynchronous inputs ( P S and CLR) to the J K flip-flops have active- (HIGH, LOW) inputs. Solution: T he asynchronous inputs to the flip-flops shown in Fig. 11-5 have active-LOW inputs. 11.12 Refer to Fig. 11-5. This register is a shift- output Q of (FF1, FF4) to (left, right) device because it shifts data from (FF1, FF4). Solution: T he register shown in Fig. 11-5 is a shift-right device because it shifts data from FF1 to FF4. 11.13 Refer to Fig. 11-5. It takes clock pulse(s) to load a 4-bit number in this shift register. Solution: It takes zero clock pulses to load the register shown i n Fig. 11-5. T he PS (parallel-load) inputs are asynchronous and therefore do not need a clock pulse to load the register. 11.14 R efer to Fig. 11-5. The JK flip-flops are always in either the this register. or the mode in Solution: T he JK flip-flops are always i n either the reset or set mode in the register shown in Fig. 11-5. CHAP. 111 267 S HIFT REGISTERS 11.15 T he JK flip-flop is in its set mode when input J = Solution: T he JK flip-flop is in its set mode when J = 1 and K 11.16 T he JK flip-flop is in its reset mode when input J Solution: The JK flip-flop is i n its reset mode when J =0 (0, 1) and input K = (0, 1). (0, 1) and input K . = (0, 1). = 0. = and K = 1. 11.17 List the state of t he output indicators after each clock pulse on the shift-right register shown in Fig. 11-7. Solution: T he outputs of the register shown in Fig. 11-7 after each clock pulse are as follows: = 000 pulse a pulse b = 010 pulse c = 001 pulse d pulse f = 000 Clear mode resets all FFs to 0. Parallel-load mode sets outputs to 100. On trailing edge of pulse, register shifts right one position to 010. Shift-right mode shifts bits one position to the right. The 0 a t C is recirculated back to A . Shift-right mode shifts bits one position to the right. The 1 at C is recirculated back to A . Shift-right mode shifts bits one position to the right. = 100 pulse e = 010 pulse g = 101 pulse h = 110 pulse i = 011 pulse j = 111 Clear mode resets all FFs to 0. Temporarily the parallelload inputs B and C load 011 into the register. On the trailing edge of the clock pulse, the shift-right mode causes the bits to shift right one position. The 1 at C is recirculated to position A . Shift-right mode. The 1 a t C is recirculated back to A . Shift-right mode. Parallel-load mode loads all FFs with a 1. Output indicators 1 1 p J p J Parallel1 d ata (load) 1 L I 1 -t - pT JT B I d , -JPSQ FF I -+> CLK -> r K CLR Q , LClock 1 A 0 1 'Iear JPSQ FF2 C LK -KcLRQ. L L h D = 0 * 5 +> ~ , J "QF F3 C LK ~KCLRQ~ 0 - are pulse triggered A J K flip-flops Fig. 11-7 Parallel-load shift-register pulse-train problem 268 S HIFT REGISTERS [CHAP. 11 11.18 R efer to Fig. 11-7. What is the mode of operation of each flip-flop while clock pulse c is HIGH? Solution: T he modes of operation of the flip-flops while clock pulse c is HIGH (Fig. 11-7) a re as follows: FF1 mode = reset ( J K = 1) FF2 mode = reset ( J = 0 , K = 1) = 0, FF3 mode = set ( J = 1 , K = 0 ) 11.19 R efer to Fig. 11-7. What is the mode of operation of each flip-flop when pulse j is HIGH? Solution: All flip-flops are being asynchronously preset by the active parallel-data inputs. All flip-flops are in t he set mode ( J = 1, K = 0). 11.20 R efer to Fig. 11-7. This digital device is a shift- -bit (nonrecirculating, recirculating) (left, right) register. Solution: T he digital device shown in Fig. 11-7 is a 3-bit, recirculating shift-right register. 11-4 TTL SHIFI' REGISTERS Integrated-circuit manufacturers market many shift registers. The one that has been selected for description is a universal shift register. A block logic symbol for the commercial TTL 74194 4-bit universal shift register is shown in Fig. 11-8. The 74194 register has 10 inputs and 4 outputs. The outputs a re connected to the normal ((2) o utputs of each flip-flop inside the IC. Consider the inputs on the 74194 register shown in Fig. 11-8. The parallel-load inputs ( A , B , C, D ) a re the top four inputs. The next two inputs are for feeding data into the register serially ( one bit at a ) time). The shift-right serial input ( D S R feeds bits into position A (Q,) as the register is shifted to the right. The shift-left serial input ( D s L )feeds bits into position D ( Q u ) a s the register is shifted to the left. The clock input (CLK) triggers the four flip-flops on the L-to-H transition of the clock pulse. When activated with a LOW, the clear (CLR) input resets each flip-flop to 0. T he mode controls O utput i ndicators Parallelload I nputs Shift-right serial input 7R DS Shift-left (74194) serial i nput CLK Clock CLRS, S, >DSL Q 1) -2 !- controls ( s ,I Fig. 11-8 Logic symbol for the 74194 universal shift-register IC 269 SHIFT REGISTERS CHAP. 1 11 instruct the register through a gating network to shift right, shift left, parallel-load, or hold (do nothing). Of course, the 74194, which is a TTL IC, has a + 5 V and GND power-supply connection. The power-supply connections are not usually shown on the logic symbol. A mode-select-function table for the 74194 shift register is shown in Fig. 11-9. The operating modes for the shift register are listed in the left section of the table. The operating modes are reset, hold, shift-left, shift-right, and parallel-load. I Operating mode Reset (clear) I I Inputs x L (x XIX x XIL o utputs L L L Hold (do nothing) Shift- left Shift-right ~~ ~ Parallel-load H = HIGH voltage level h = HIGH voltage level one setup time prior to the L-to-H clock transition L = LOW voltage level 1 = LOW voltage level one setup time prior to the L-to-H clock transition d ,(q,) = (Lowercase letters indicate the state of the referenced input [or output] one setup time prior to the L-to-H clock transition.) X = don’t care t = L-to-H clock transition * The H-to-L transition of the S o and S , inputs o n the 74194 should only take place while C K is HIGH for conventional operation. Fig. 11-9 Mode select/function table for the 74194 universal shift-register IC Consider the reset (clear) mode of the shift register shown in Fig. 11-9. When the CLR input is LOW, i t overrides all other inputs (all other inputs are X on t he table) and clears the outputs to 0000 (shown as LLLL in table). Note that the outputs are identified with a Q o instead of Q A , Q l for Q B , and so forth. Identification of inputs and outputs does vary from manufacturer to manufacturer. The remaining four modes of operation shown in Fig. 11-9 a re controlled by the mode controls (So and S ,). When both mode controls are LOW (So= 0, S , = 0), t he shift register is in the hold mode and will do nothing. The table shows that the outputs (at Q o through Q 3 )a re displayed, however. Consider the shift-left line in Fig. 11-9. The two mode controls are set properly ( So = 0, S , = l), and data is fed into t he shift-left serial input ( D s L ) . Note that the 1s and OS at the shift-left serial input are transferred to the Q 3 ( D ) osition as the register shifts one place to the left. The shift takes p place on the L-to-H transition of the clock pulse, as shown by the arrow pointing upward on the table. Look at the shift-right line in Fig. 11-9. The mode controls are set ( S o = 1, S , = 0). D ata is placed at the shift-right serial input ( D S R ) . n the L-to-H transition of t he clock pulse, the bit at input D SRis O transferred to the Q o ( A ) o utput as the register shifts one place to the right. The final operating mode for the universal shift register is shown o n t he bottom line in Fig. 11-9. To parallel load (also called broadside l oad) t he 74194 register, set the two mode controls (So= 1, S , = 1). On the L-to-H transition of t he clock pulse, the data at the parallel-load inputs will be 270 SHIFT REGISTERS [CHAP. 11 transferred to the appropriate outputs. Note that the parallel-load inputs are not asynchronous as they were on the previous parallel-load register. The parallel-load operation takes place in step with a single clock pulse. The 74194 register is indeed universal. Data can be loaded either serially or in parallel. Data can be read out in parallel or in serial form [output from one point such as Q D ( Q,)].T he register can hold (or do nothing) on command. The register can shift right or shift left. This 4-bit register is but one of many units manufactured in IC form. A few other TTL shift registers include the 7494 4-bit and 7496 5-bit shift registers. Also listed in data manuals are the 74164 8-bit serial-in, parallel-out and 74165 8-bit serial/parallel-in, serial-out shift registers. Other shift registers are available from chip manufacturers in the various T TL subfamilies such as the 74LS395A 4-bit cascadeable shift register with 3-state outputs. SOLVED PROBLEMS 1 . 1 List the five modes of operation of the 74194 shift register. 12 Solution: The five modes of operation of the 74194 register are as follows: ( a ) reset (clear) ( c) shift-left ( e ) parallel-load ( b ) hold ( d ) shift-right 11.22 R efer to Fig. 11-9. The single asynchronous input on the 74194 register that overrides all other inputs is the input. Solution: T he clear is the only asynchronous input on the 74194 register. 11.23 R efer to Fig. 11-9. What effect does a clock pulse have when the 74194 register is in the hold mode? Solution: T he 74194 register does nothing on a clock pulse when it is in the hold mode. 11.24 R efer to Fig. 11-9. It takes clock pulse(s) to parallel load four bits in the 74194 register. Solution: I t takes one clock pulse to parallel load the 74194 shift register. 1 . 5 T he 74194 input labeled D , would be used when So = 12 , (0, 1) and S , = (0, 1). Solution: T he D , input (shift-right serial input) would be used during the shift-right mode, and therefore , So = 1 a nd S, = 0. 11.26 T he 74194 register uses (positive-edge, pulse) triggering. Solution: T he 74194 register uses positive-edge triggering. 11.27 List the operating mode of the shift register (74194) for each of the pulses shown in Fig. 11-10. Solution: Refer to the S, and So columns of the mode-select table in Fig. 11-9. The operating mode of the register for each pulse shown in Fig. 11-10 is as follows: pulse j = shift-left pulse g = shift-right pulse d = shift-left pulse a = reset (clear) pulse h = reset (clear) pulse e = shift-left pulse b = parallel-load pulse f = shift-right pulse i = hold pulse c = shift-left 271 S HIFT REGISTERS C HAP. 111 Output indicators 0 Parallel loads -. T -A 0 --I --1 I 0 1 1 0 I QA 0 0 I Qc L 1 l - 1 Clear T - QB Right Ds~ serial input' 1 0 0 D LLL 1 1 Shift register B T - (74 194) -L S , Mode controls 1 Fig. 11-10 Shift-register pulse-train problem 11.28 List the state of t he output indicators after each pulse for the 74194 shift register shown Fig. 11-10. In Solution: T he output indicators read as follows for the register shown i n Fig. 11-10 ( A on left, D on right): pulse a = 0000 Reset mode which clears all outputs to 0. pulse 6 = 0011 Parallel-load mode which loads four parallel-load inputs into register. pulse c = 03 10 Shift-left mode moves bits one position to the left. Note that a 0 is being serially loaded into position D from the left serial input. pulse d = 1100 Shift-left mode moves bits one position to the left. Note that a 0 is being serially loaded into position D from the left serial input. pulse e = 1000 Shift-left mode moves bits one position to the left. Note that a 0 is being serially loaded into position D from the left serial input. pulse f = 1100 pulse g = 0110 pulse h = 0000 pulse i = 0000 pulse j = 0001 Shift-right mode moves bits one position to the right. Note that a 1 is being serially loaded into position A from the right serial input. Shift-right mode moves bits one position to the right. Note that a 0 is being serially loaded into position A from the right serial input. The clear input overrides all other inputs and resets all outputs to 0. Hold mode commands the register to do nothing. Shift-left mode moves bits one position to the left. Note that a 1 is being serially loaded into position D from the left serial input. 11-5 CMOS SHIFT REGISTERS A wide variety of CMOS shift registers are available from chip manufacturers. The 7#HC16# 8-bit serial-in parallel-out shift-register IC is featured in this section. Information from the manufacturer's data manual is reproduced in Fig. 11-11, 272 [CHAP. 11 SHIFT R EGISTERS 4, Dsb (U) Q4 Q3 12 13 Q7 Q5 Q2 MR Q6 Qi 9 Q7 QO 8 vcc m GND CP Simplified logic symbol Q.; D 1 ( b) Pin diagram Q. D Q D = Q. : D Q, D = Q D : Q D = D OS b 4 CP --c CP FFl CP MR + Ru -c CP .-c CP 4 CP FF2 I FF4 Ru - FF3 RI, RU I 1 1 1 Q, QO --c CP FF6 FF7 RD Y Y 4 CP 4 CP FF5 RD RD I 1 A 1 Y 1 Q, Qz 0 . 4 Qs Q6 ( c ) Detailed logic diagram - Inputs outputs MR CP 03, Ds, QO Q l-Q7 reset (clear) L X X X L L-L t 1 T 1 1 h T h h L L L H q O-q6 shift H H H H Operating modes T 1 h ~~~-~ H = H IGH voltage level h = H IGH voltage level one setup time prior to t he LOW-to-HIGH clock transition L = LOW voltage level 1 = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition q = lowercase letters indicate the state of the referenced input one setup time prior to the LOW-to-HIGH clock transiton t = LOW-to-HIGH clock transition ( d ) Truth table Fig. 11-11 T h e 74HC164 shift register I C q o-q6 q o-q6 q0-6 Q- CHAP. 113 273 SHIFT REGISTERS The 74HC164 CMOS I C is an 8-bit edge-triggered shift register that permits only serial data input. Eight parallel outputs are available ( Qo to Q 7 ) from each of t he eight internal flip-flops (Fig. 11-llc). The clock input ( C P ) t o the 74HC164 is edge-triggered and shifts data on the LOW-to-HIGH transition of the clock pulse. Data is e ntered one bit at a time (serially) through one of two d ata inputs ( Dsa o r D rh).T he simplified logic diagram in Fig. 11-1l a shows that the data inputs (Dsa and D sb)a re ANDed together. This means that one input can be used as an active-HIGH data enable input while serial data is fed into the second data input. If no data enable input is required, both data inputs (Ds, and D sb)a re tied together and used as a single serial data input. I n Fig. 11-llc, each clock pulse will pin on shift data one position to the right (from Q, to Q 7) in the shift register. The master reset the 74HC164 IC is an active-LOW input which resets all eight flip-flops and clears the outputs to 0. T he master reset is an asynchronous input that overrides all other inputs. The 74HC164 shift register is packaged in a 14-pin DIP IC, shown in Fig. 11-llb. A t ruth table detailing the operating modes of the 74HC164 IC is reproduced in Fig. 11-lld. The 74HC164 IC operates on a 5-V d c power supply. Manufacturers produce a variety of CMOS shift registers. If you a re wiring shift registers using D flip-flops, the 4076 and 40174 ICs are available. The 4014 8-stage static shift-register IC is a serial-in parallel-out device. The 4031 64-stage static shift register is a serial-in serial-out unit. The 4035 4-bit shift register is a parallel-in parallel-out storage unit, The 4034 &bit static shift register is a universal 3-state bidirectional parallel/serial-input/output unit which can input from and output to bus lines. Many other shift registers are also available in the 74HC and 74HCT series of CMOS ICs. (m) (m) SOLVED PROBLEMS 11.29 R efer to Fig. 11-11. The activated with a LOW. Solution: T he active-LOW master reset 11.30 T he master reset input. Solution: T he reset input to the 74HC164 shift register overrides all others when (m) to the 74HC164 shift register overrides all others. input (m)pin on the 74HC164 IC is a(n) (asynchronous, synchronous) (m) in on the 74HC164 IC is an asynchronous input. p (edge, pulse)-triggered 11.31 R efer to Fig. 11-11,T he clock input (CP) o the 74HC164 IC is t and shifts data on the (H-to-L, L-to-H) transition of the clock pulse. Solution: The clock input ( C P ) to the 74HC164 IC is edge-triggered and shifts data o n t he L-to-H transition of the clock pulse. 11.32 T he 74HC164 is an 8-bit (parallel, serial)-in parallel-out shift register. Solution: T he 74HC164 is an 8-bit serial-in parallel-out shift register. 11.33 Refer to Fig. 11-11.Why does the 74HC164 IC have two serial data inputs (see Dsa and D sb)? 274 S HIFT REGISTERS [CHAP. 11 Solution: T he 74HC164 IC has two ANDed serial data inputs ( Dsa and D sb).Two serial data inputs allow one t o be used as an active-HIGH serial data enable input to turn the data input on and off. 11.34 R efer to Fig. 11-12. The 74HC164 shift register is in the operation during clock pulse a . (reset, shift) mode of Solution: input is activated with a LOW during pulse a so t he shift register is in the The master reset reset mode. Remember that the reset ( M R ) input overrides all others. (m) 11.35 R efer to Fig. 11-12. The 74HC164 IC is in t he clock pulse b . (reset, shift) mode of operation during Solution: Reset ( M R ) is deactivated so t he 74HC164 IC shifts right one position loading a 1 bit from the data input ( Dsb)into the Q , position. The results after pulse h a re 10000000. 11.36 R efer to Fig. 11-12. The serial-in data inputs are pulse c. (activated, deactivated) during clock Solution: See Fig. 11-12. The top input to the serial data AND gate is LOW during clock pulse c, which deactivates the entire serial data input. 11.37 List the state of the output indicators after each clock pulse for the 74HC164 shift register shown in Fig. 11-12. Solution: T he output indicators read as follows for the shift register shown in Fig. 11-12 ( Q , on left, right): pulse a = 0000 0000 Reset mode pulse b = 1000 0000 Shift right-serial load a 1 into Q, pulse c = 0100 0000 Shift right-serial load a 0 into Q, pulse d = 0010 0000 Shift right-serial input disabled pulse e = 0001 0000 Shift right-serial input disabled Shift right-serial input disabled pulse f = 0000 1000 Shift right-serial input disabled pulse g = 0000 0100 Shift right-serial input disabled pulse h = 0000 0010 Shift right-serial input disabled pulse i = 0000 0001 Shift right-serial input disabled pulse j = 0000 0000 Data enable I 1 +5 Q7 v I Fig. 11-12 Shift-register pulse-train problem IIIIIIII on 275 SHIFT REGISTERS CHAP. 111 Suppl ementary ProbIems 11.38 Draw the logic diagram for a 5-bit serial-load shift-right register. Use five D flip-flops. Label inputs as clock, clear, and serial-data. Label outputs as A , B , C , D , and E . Ans. See Fig. 11-13. FF 1 CLK -> Inputs I CLR 1 Clear F F2 FF3 >CLK > CLK CLR Y - I -> CLR 1 F F4 CLK FF5 > CLK CLR P CLR P ? Fig. 11-13 Logic diagram for a 5-bit serial-load shift-right register 11.39 It takes clock pulse(s) to load a 5-bit serial-load shift register. 11.40 Refer to Fig. 11-14. The data input is a ( c ) (left, right) register. Ans. ( (a) a Ans. five (parallel, serial) data input to this m ( 6) 3 ( c ) right ( 6 ) -bit shift- Output indicators D FF 1 > CLK Q QQQ 1-D -> F F2 CLK CLR CLR y Q 1.D -> FF3 CLK QJ CLR 9 Fig. 11-14 Serial-load shift-register pulse-train problem 11.41 List the output after each clock pulse for the shift register shown in Fig. 11-14 ( A on left, C on right). A m. pulse a = 000 pulse c = 010 pulse e = 010 pulse g = 110 pulse d = 101 pulse f = 100 pulse h = 011 pulse b = 100 11.42 R efer to Fig. 11-14. List the two synchronous inputs on this register. 11.43 Refer to Fig. 11-14. It takes 11.44 R efer to Fig. 11-7. This 3-bit parallel-load shift register uses ( a ) ( D , J K ) flip-flops and is a (nonrecirculating, recirculating) unit. A m. ( a ) JK @)recirculating Register to View Answerata (serial), clock clock pulse(s) to load this register with 011. A m. t hree (6) 276 S HIFT REGISTERS [CHAP. 11 11.45 Refer to Fig. 11-7. What is the mode of operation of each J K flip-flop while clock pulse d is H IGH? A ns. FF1 mode = set ( J = 1 , K = 0) FF2 mode = reset ( 1= 0, K = 1) FF3 mode = reset ( J = 0, K = 1 ) 11.46 Refer to Fig. 11-7. The active state for the clear input is 11.47 R efer to Fig. 11-7.The output indicators on this register read A when pulse g is HIGH. Ans. ( a ) 0 ( b ) 1 ( c ) 1 11.48 R efer to Fig. 11-7, What is the mode of operation of each J K flip-flop while clock pulse h is HIGH? A ns. FF1 mode = set ( J = 1 , K = 0 ) FF2 mode = set ( J = 1, K = 0) FF3 mode = reset ( J = 0, K = 1) 11.49 Refer to Fig. 11-7. The two lines w ith arrows going back from FF3 to FFl arc called Ans. recirculating (recirculating, reset) lines. 11.50 Refer to Fig. 11-7. The J K flip-flops arc triggered on the ( a ) ( HIGH, LOW)-toLOW) transition of the clock pulse. Ans. ( a ) HIGH ( h ) L O W 11.51 Refer to Fig. 12-7. List the outputs of the transition of the clock). A ns. pulse a = 000 pulse d = 001 pulse b = 100 pulse e = 100 pulse c = 010 pulse .f‘=000 11.52 (0, 1). ,B (a) = 1 = (6) , and C = (6) (c) ( HIGH, register while each clock pulse is H IGH (just before the H-to-L pulse g = 01 1 pulse h = 101 pulse i = 110 pulse j = 11 1 Refer to Fig. 11-15. The clock input triggers the shift register on the ( a ) (HIGH, LOW) transition of the clock pulse. Ans. ( a ) LOW HH -G I 1 0 Ans. (b) O utput indicators Parallel loads 0 ( HIGH, LOW)-to- A ~ B C D Universal shift register QA 0 0 I 0 1 Right ’ LOW serial i nput D.w + s, QL3 QC Mode controls Fig. 11-15 Universal shift-register pulse-train problem 11.53 Refer to Fig. 11-15. The clear connection to the 74194 register is an active A ns. LOW and overrides all others. (HIGH, LOW) input CHAP. 111 277 SHIFT REGISTERS 11.54 List the operating mode of the 74194 shift register for each clock pulse shown in Fig. 11-15. Ans. pulse a = parallel-load pulse d = parallel-load pulse g = shift-right pulse h = shift-left pulse b = shift-right pulse e = hold pulse f = shift-right pulse c = shift-right 11.55 List the states of the output indicators of the register shown in Fig. 11-15 while each clock pulse is HIGH. Ans. pulse U = 1111 pulse c = 0011 pulse e = 0110 pulse g = 0001 pulse b = 0111 pulse d = 0110 pulse f = 0011 pulse h = 0010 11.56 R efer to Fig. 11-15. Just before clock pulse d , t he output indicators read . Why? Ans. Because of the clear pulse, the output indicators read 0000 just before clock pulse d (Fig. 11-15). 11.57 R efer to Fig. 11-15. During pulse a , this register is set up for Ans. parallel 11.58 A nother term for parallel loading is 11.59 A shift register is classified as a 11.60 T he storage unit shown in Fig. 11-4 might be classified as a serial-in A ns. parallel 11.61 R efer to Fig. 11-5. T he recirculating shift register might also be called a 11.62 R efer to Fig. 11-16. Which part of the figure illustrates the idea of a serial-in parallel-out register? Ans. p art b loading. (parallel, serial) loading. A m. broadside (combinational, sequential) logic circuit. Ans. sequential -out register. counter. A ns. Fig. 11-16 Types of registers 11.63 R efer to Fig. 11-16. Which part of the figure illustrates the idea of a parallel-in serial-out register? Ans. part c 11.64 T he 74HC164 IC is best represented by which type of register pictured in Fig. 11-16? Register to View Answer(serial-in parallel-out) ring 278 11.65 S HIFT REGISTERS R efer to Fig. 11-12. This shift register is an example of a (m) [CHAP. 11 (CMOS, TI'L) IC. pin on t he 74HC164 is an active11.66 R efer to Fig. 11-12. The master reset and overrides all others. Ans. LOW 11.67 Refer to Fig. 11-12. The data enable ( OS,)input is an activeexample. Ans. H IGH 11.68 Ans. CMOS (HIGH, LOW) input (HIGH, LOW) input in this Refer to Fig. 11-12. Assuming the data enable ( OS,>nput is HIGH the entire time (pulses a to i), list the i states of t he output indicators for the shift register after each clock pulse ( Q , on left, Q7 o n right). Ans. Assuming D,, input = H IGH, then pulse a = 0000 0000 pulse b = 1000 0000 pulse c = 0100 0o00 pulse d = 1010 0000 pulse e = 0101 0000 pulse f = 1010 1000 pulse g = 1101 0100 pulse h = 0110 1010 pulse i = 0011 0101 pulse j = 1001 1010 Chapter 12 Microcomputer Memory 12-1 INTRODUCTION I n a new electronic product, designers must choose to use either analog or digital devices. If the unit must input, process, or output alphanumeric data, the choice is clearly digital. Also, if the unit has any type of memory or stored program, the choice is clearly digital. Digital circuitry is becoming more popular, but most complex electronic systems contain both analog and digital devices. Microcomputer memory is one example of the application of d ata storage devices called memory. A simplified microcomputer system is shown in Fig. 12-1. T he keyboard is the input device, while the output device is the video monitor. The central processing unit (CPU) controls the operation of t he microcomputer system and processes data. The internal memory of a typical microcomputer system is composed of t hree types of s emiconductor memory. T he nonL1olatile semiconductor memory is shown in Fig. 12-1 a s ROM ( read-only memory) a nd NVRAM ( nomlolatile R A M ) . T he uolatile semiconductor memory is shown as R AM ( random-access memory). Fig. 12-1 D ata and most programs are commonly stored on m agnetic bulk storage devices such as floppy d isks o r hard disks. T he disk drive is the unit that reads from or writes to either the floppy disk or t he hard disk. Strictly speaking, each device, such as the keyboard, video monitor, disk drive, and CPU, h as smaller memory devices. These memory devices usually take the form of registers and latches, but they can contain smaller ROM and RAM semiconductor memory devices. 279 280 MICROCOMPUTER MEMORY [CHAP. 12 T he RAM and ROM storage devices come as ICs and are typically mounted on printed-circuit boards as depicted in Fig. 12-1. It is usual to have at least one ROM and many RAM ICs in a microcomputer. 12-2 RANDOM-ACCESS MEMORY (RAM) Semiconductor memories are classified as volatile and nonvolatile. A volatile memory is one that loses its data when power is turned off. The R AM ( random-access memory) is a volatile semiconductor memory widely used in modern microcomputers to hold data and programs temporarily. The RAM is also described as a r ead/write memory. Storing data in a RAM is called the write operation o r writing. Detecting or recalling data from RAM is called the read operation or reading. When data is read from memory, the contents of R AM are not destroyed. Consider the table in Fig. 12-2. This is a representation of the inside of a 64-bit memory. The 64 squares (mostly blank) represent the 64 memory cells inside the 64-bit memory. The memory is organized into 16 groups of 4 bits each. Each 4-bit group is called a word. This memory is said to be organized as a 16 X 4 memory. I t contains 16 words of 4 bits each. The representation of the 64-bit memory shown in Fig. 12-2 is a programmer’s view of this unit. Electronically it is organized somewhat differently. W ord 5 Word 6 Fig. 12-2 Organization of a 64-bit memory Consider the memory shown in Fig. 12-2 to be a RAM. If the RAM (read/write memory) were in the write mode, d ata (such as 1101) could be written into the memory as shown after word 5. T he write process is similar to writing on a scratch pad. If the RAM were in the read mode, d ata (such as 1101) could be read from the memory. The process is similar to reading the 1101 from word location 5 in Fig. 12-2. A R AM memory of this type is sometimes called a scratch-pad memory. Reading word 5 (1101) does not destroy the contents of t he memory; it is said that the read process is nondestructive. T he memory in Fig. 12-2 is a random-access memory because one can skip down to word 5 o r any other word with ease. CHAP. 121 281 MICROCOMPUTER MEMORY A logic diagram of a simple R A M IC is drawn in Fig. 12-3a. 'The 74F189 TTL RAM IC is a 64-bit read/write random-access memory. The 74F189 IC is from the newer Fairchild advanced Schottky TT'L, FAST, a subfamily that exhibits a combination of performance and efficiency unapproached by any other T TL family. Its internal organization is similar to that shown in Fig. 12-2. It has 16 words, each of which is 4 bits long for a total of 64 memory locations. Inverted data output indicators + 5v Address inputs Input controls c I Chip select 3:: Write enable L = write, H = read 8s A3 c - cs - OWE '3 - Data inputs 64 bit RAM A2 r D3 D2 Di (74F189) D O + 0 ' G ND (U) Operating mode Write Read Store (inhibit) CS L L H Logic symbol Inputs WE L H X Condition of outputs High impedance Complement of stored data High impedance ( b ) Operating modes Fig. 12-3 74F189 64-bit static RAM T he modes of operation for the 74F189 R AM IC a re detailed in Fig. 12-3b. The first line of t he chart illustrates the write mode. Note from Fig. 12-3b that both control inputs and E) re LOW. a During the write operation, the 4 input data bits ( D,, D,, D,, D o ) a re written into the memory word location specified by the address inputs. For instance, to write 1101 into word location 5 as shown in Fig. 12-2, the data inputs must be D , = 1, D,= 1, D ,= 0, and D o = 1 and the address inputs must be A , = 0, A , = 1, A , = 0, A , = 1. Next, the write enable input (WE) must be LOW. Finally, the chip ( a 282 M ICROCOMPUTER MEMORY +5 Address inputs v 1/01 - iA4 ( a ) Logic diagram R ow select Memory array 6 4 r ows 6 4 c olumns U Column 1 / 0 circuits ( h) Block diagram (Courtesy of’ Intel Corporation) Fig. 12-4 M OS s tatic R AM (1024 X 3 ) [CHAP. 12 CHAP. 121 MICROCOMPUTER MEMORY 283 (a) select input must go LOW. Memory address location 5 (word 5) now contains the data 1101. I t will be noted that the outputs of the 74F189 R AM remain in their high impedance state during the write operation. The second line of t he table in Fig. 12-3b shows the read mode for the 74F189 RAM. The input LOW- nd E = IGH. The contents of t he memory location a-- H controls must be set so t hat addressed will appear at the outputs ( 03,,, 0,,0,) in complementary form. Note the invert bubbles 0 at the outputs o n t he logic symbol in Fig. 12-3a. For example, to read the contents of word 5 (address must be activated with a LOW and the location 5 ) in the memory in Fig. 12-2, t he chip select write enable (-1 must be deactivated with a HIGH. The address inputs must be A , = 0, A , = 1, A , = 0, A , = 1. T he outputs indicate 0010, which is the complement of the true data 1101 located at address location 5 in the RAM. It should be understood that the read operation does not destroy the stored data in memory location 5 but outputs an inverted copy of t hat data. The bottom line in the table in Fig. 12-3b illustrates the store o r inhibit mode. When the chip select input is deactivated with a HIGH, the outputs go to a high impedance state (they float) and the read and write operations are inhibited. It can be said that the memory is “storing” data. The 74F189 I C is an example of a static RAM. A static RAM can be fabricated using either bipolar or MOS technology. The static RAM uses flip-flops (or similar circuits) as memory cells and holds its data as long as power is supplied to the chip. Large-capacity temporary storage units are usually dynamic R AMs. A dynamic RAM’S memory cell is based on a n MOS device that stores a charge (much like a small capacitor). The difficulty with dynamic RAMs (DRAMS) is that all memory cells must be refreshed every few milliseconds to retain data. The 2114 static RAM is a popular MOS memory IC. It will store 4096 bits, which are organized into 1024 words of 4 bits each. A logic diagram of the 2114 R AM is in Fig. 1 2-4a. Note that the 2114 R AM has 10 address lines which can access 1024 (2”) words. It has the familiar chip select and control inputs, 1 /01, 1 /02, 1 /03, and I/O, a re inputs when the RAM is in the write enable (E) write mode and outputs when the IC is in the read mode. The 2114 R AM is powered by a + 5-V power supply. A block diagram of the 2114 R AM is shown in Fig. 12-4b. Note especially the three-state buffers used to isolate the data bus from the input/output (I/O) pins. Note that the address lines also are buffered. The 2114 R AM comes in 18-pin DIP I C form. Microprocessor-based systems (such as microcomputers) typically store and transfer data in 8-bit groups called words. Two 2114 RAMs are connected in Fig. 12-5 t o form a RAM memory of 1024 words each 8 bits wide. This is referred to as 1 K of memory in most microcomputers, that is, 1024 bytes (8-bit groups) of memory. Note that the left 2114 R AM furnishes the least significant 4 bits of a a= (a) (a) (a) Fig. 12-5 Combining two 1 K X 4 RAMs to f orm a 1K X 8 RAM 284 MICROCOMPUTER MEMORY [CHAP. 12 word and the right 2114 RAM furnishes the 4 most significant bits. The 2114 RAM has the proper buffering to interface with the system address bus and data bus. Often-mentioned characteristics of RAMs a re size (in bits) and organization (words X bits per word). For the 2114 RAM this would be 4096 bits, or 1024 X 4. For the 74F189 RAM this would be 64 bits, or 16 X 4. A second characteristic might be the technology used to fabricate the chip. This would be N MOS ( N-channel metal oxide semiconductor) for the 2114 RAM. T he 74F189 uses the new Fairchild advanced Schottky TTL technology. A third characteristic might be the type of output. Both the 2114 and 74F189 RAMs have three-state outputs. A fourth characteristic might be the access time (speed) of the memory chip. The access time is the time it takes to locate and read data from a RAM. T he access time of the 2114 RAM may be from 50 t o 450 ns, depending on which version you specify. The access time of the 74F189 RAM is only about 10 ns. The 74F189 is said to be a faster memory. Faster memories are more expensive than their slower counterparts. A fifth characteristic might be the type of memory: either static (SRAM) o r dynamic (DRAM). Both the 2114 and 74F189 ICs a re static RAMs. T he packaging and power supply voltage are two o ther common specifications for RAMs. T he 2114 RAM is packaged in an 18-pin DIP. T he 74F189 IC is housed in either a 16-pin D IP o r in a 16-pin LCC (leadless chip carrier) package. Both the 2114 and 74F189 RAMs o perate on a 5-V dc power supply. SOLVED PROBLEMS 12.1 T he letters R OM s tand for - in digital electronics. Solution: T he letters ROM stand for read-only memory. 12.2 T he letters RAM literally stand for memory. - memory, but in practice they designate a Solution: T he letters RAM literally stand for random-access memory, but in practice they designate a read/write memory. 12.3 T he R OM is (nonvolatile, volatile), whereas the RAM is a memory. Solution: T he ROM is nonvolatile, whereas the RAM is a volatile memory. 12.4 T he the (read, write) process in a RAM consists of putting data into the memory, whereas (read, write) process consists of revealing the stored contents of a memory location. Solution: The write process in a RAM consists of putting data into the memory, whereas the read process consists of revealing the stored contents of a memory location. 12.5 T he (RAM, ROM) is easily erased. Solution: T he RAM is easily erased. 12.6 A 32 X 8 memory would contain bits. words, each bits long, for a total capacity of Solution: A 32 X 8 memory would contain 32 words, each 8 bits long, for a total capacity of 256 bits. C HAP. 121 12.7 285 MICROCOMPUTER MEMORY List the mode of operation of the 74F189 R AM for each input pulse shown in Fig. 12-6. Solution: inputs in the memory control the operation of the RAM. The modes of operation T he % a nd ! ? for t he RAM in Fig. 12-6 are as follows: pulses a to i = write pulse j = s tored (inhibit read and write) pulse k = r ead pulse 1 = r ead - l +5 k j i h g f e d c b Output indicators v )O@@ a 0 1 1 0 1 0 Fig. 12-6 Static R AM pulse-train problem 12.8 List the memory contents of word Iocations 0 through 8 after pulse I , Fig. 12-6. Solution: T he memory contents of t he 74F189 RAM (Fig. 12-6) after pulse 1 a re as follows: word 0 = 0001 word 1 = 0010 word 2 = 0011 word 3 = 0100 word 4 = 0101 word 5 = 0110 word 6 = 0111 word 7 = 1000 word 8 = 1001 Written into memory tion 0 during pulse a Written into memory tion l d uring pulse b Written into memory tion 2 during pulse c W ritten into memory tion 3 during pulse d Written into memory tion 4 during pulse e Written into memory tion 5 during pulse f W ritten into memory tion 6 during pulse g W ritten into memory tion 7 during pulse h Written into memory tion 8 during pulse i localocalocalocalocalocalocalocaloca- 286 12.9 MICROCOMPUTER MEMORY [CHAP. 12 What is the state of the output indicators during input pulse k in Fig. 12-6? Solution: O utput indicators read 1001 during pulse k which is a copy of t he contents of memory location 8. 12.10 W hat is the state of the output indicators during input pulse 2 in Fig. 12-6? Solution: O utput indicators read 1000 during pulse 1 which is a copy of the contents of memory location 7. 12.11 T he access time for the faster chip. (2114, 74F189) RAM is shorter, and therefore it is considered a Solution: T he access time for the 74F189 R AM is shorter. 12.12 Each memory cell of this static R AM is similar to a (capacitor, flip-flop). Solution: Each memory cell in a static R AM is similar to a flip-flop. 12.13 S ee Fig. 12-4. The 10 address lines entering the 2114 RAM can address words. different Solution: T he 10 address lines on the 2114 shown in Fig. 12-4 can address a total of 1024 (2l") words in R AM. 12.14 What is meant when a microcomputer is said to have 16K of memory? Solution: A computer said to have 16K of memory has a 16384-byte memory. Such a memory would have a total capacity of 131 072 bits (16384 X 8 = 131 072). 12.15 R efer to Fig. 12-5. Why can the 1 / 0 pins of the RAMs be connected directly to the data bus? Solution: T he 2114 R AMs shown in Fig. 12-5 have three-state buffered 1 / 0 terminals. 12.16 T he time it takes to locate and read data from a RAM is called the time. (access, interface) Solution: T he time it takes to locate and read data from a R AM is called the access time. 12.17 T he 2114 IC shown in Fig. 12-4 is a (dynamic, static) RAM. Solution: T he 2114 IC shown in Fig. 12-4 is a static R AM. 12-3 READ-ONLY MEMORY (ROM) Microcomputers must store permanent information in the form of a system or monitor program, typically in a read-on2y memory ( R O M ) . T he ROM is programmed by the manufacturer to the user's specifications. Smaller ROMs can be used to solve combinational logic problems (to implement truth tables). CHAP. 121 287 MICROCOMPUTER MEMORY ROMs are classified as nonvolatile storage devices because they do not lose their data when power is turned off. T he read-only memory is also referred to as the m ask-programmed R OM. T he ROM is used only in high-volume production applications because the initial set-up costs are high. Varieties of programmable read-only memories (PROMS) might be used for low-volume applications. Consider the problem of converting from decimal to Gray code (see Sec. 2 -3). T he truth table for this problem is in Fig. 1 2-7a. This conversion could be made by using a simple diode ROM circuit such as the one shown in Fig. 1 2-76. If the rotary switch has selected the decimal 2 position, what will the ROM output indicators display? The outputs ( D ,C, B , A ) will indicate LLHH or 0 021. T he D and C outputs are connected directly to ground through the resistor and read LOW. The B and A outputs are connected to + 5 V through two forward-biased diodes, and the output voltage will read about + 2-3 V, which is a logical HIGH. +5 v i nput 97 I t 1.5 I'i, O utput output O utput indicators, Gray code ( a) T ruth table ( b ) Diode R OM Fig. 12-7 Decimal-to-Gray code conversion Note that the pattern of diodes in the diode ROM matrix (Fig. 1 2-76) is similar to the pattern of 1s in the truth table (Fig. 1 2-7a). T he circuit in Fig. 1 2-7b is considered a ROM that is permanently programmed as a decimal-to-Gray code decoder. Each new position of the rotary switch will give the correct Gray code output as defined in the truth table. In a memory, such as the one shown in Fig. 1 2-7, each position of t he rotary switch is referred to as an address. A slight refinement in the diode ROM is shown in Fig. 12-8. Figure 1 2-8a is the truth table for a binary-to-Gray code converter. The diode ROM circuit shown in Fig. 1 2-86 has an added 1-of-10 288 [CHAP. 12 MICROCOMPUTER MEMORY I Binary 1 8 s 4s 2s 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1s 0 1 0 1 0 1 0 1 0 1 I 1 Gray code D C B A 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 (a) Truth table +5 v Input li 0101 8s 4s 2s .It O utput indicators, Gray code ( b ) Diode ROM decoder Fig. 12-8 Binary-to-Gray code conversion 289 MICROCOMPUTER MEMORY CHAP. 121 NC A12 A7 A6 A4 241 A9 231 A l l A3 g Sl/Sl A2 21( A10 A5 A1 A0 Q1 Q2 Q3 vss r ( a) Pin diagram (Reprinted by permission of Texas Instruments) Address inputs Chip enable/power down inputs Chip select 7:; ROM 3 2KX8 Q2 Q3 A4 Q4 -4 Q5 Q6 A7 A9 A10 All A12 A 13 MSB Q7 Q8 UMS47256) E or S 2 S1 ( b) Logic diagram Fig. 12-9 TMS47256 32K X 8 ROM -I - -I MSB f 1 Data Outputs 290 MICROCOMPUTER M EMORY [CHAP. 12 decoder (TTL 7442 IC) and inverters used to activate only one o fthe 10 rows in the diode ROM. The example in Fig. 12-86 shows a binary input of 0101 (decimal 5 ). This activates output 5 of the 7442 with a LOW; and that drives the inverter, which outputs a HIGH. The HIGH forward-biases the three diodes connected to the row 5 line. The outputs will be LHHH or 01 11. This is also specified in the truth table. The primitive diode ROMs have many disadvantages. Their logic levels are marginal, and they have very limited drive capability. They do not have the input and output buffering that is needed to work with systems that contain data and address busses. Practical mask-programmable ROMs are available from many manufacturers. They can range from very small units to quite large capacity ROMs. Some of these commercial ROMs can be purchased in familiar DIP form. ROMs are manufactured using TTL, CMOS, NMOS, PMOS, and GaAs (gallium arsenide) process technologies. The GaAs technology yields very fast digital ICs. Currently ROMs using either NMOS or CMOS seem to be very popular. As an example, one very small unit is the Harris 82HM141C 512 x 8 NMOS ROM with an access time of under 70 ns. A similar unit, the very fast 14GM048 GaAs ROM is manufactured by Tri Quint Semiconductor and has access time of less than 1.5 ns. One large unit is the Sharp LH5316000 2M X 16 CMOS ROM, with an access time of less than 200 ns. ROMs are used to hold permanent data and programs. Computer system programs, look-up tables, decoders, and character generators are but a few uses of the ROM. They can also be used for solving combinational logic problems. General-purpose microcomputers contain a larger proportion of RAM for their internal memory. Dedicated computers allocate more addresses to ROM and usually contain only smaller amounts of RAM. According to one recent listing, more than 300 different commercial ROMs are available. As an example, a pin diagram of a commercial TMS47256 ROM is shown in Fig. 12-9a. A logic diagram for the ROM is illustrated in Fig. 12-9b. The TMS47256 is an NMOS 262 144-bit read-only memory organized as 32768 words of &bit length. From a practical point, this is called a 32K X 8 ROM, or in most microprocessor-based systems this would be 32K of ROM (32K bytes of ROM). While a 28-pin DIP IC is pictured in Fig. 12-9a, the ROM is also available in a 32-lead plastic leaded chip carrier package designed for surface mount applications. The TMS47256 is compatible with most TTL and CMOS logic devices. The access time for the TMS47256 ROM is less than 200 ns. The TMS47256 ROM has 15 address inputs ( A o to A ,,), which can address 32768 (215) ords. w The A , input is the LSB of the address, while A , , is the MSB. Pin 22 (see Fig. 12-9a) can be programmed during mask fabrication by the manufacturer as either active-HIGH or active-LOW chip-select input. Pin 20 can be programmed during mask fabrication to be a chip-enabZe/power-down input ( E o r E ) o r a secondary chip-select pin (S2 or E).Each option can be either active-LOW or active-HIGH. When the chip-enable/power-down pin is inactive, the chip is put in t he standby mode. The standby mode reduces the power consumption. The eight outputs ( Q , t o Q 8 ) a re in the three-state high-impedance state when disabled. To read data from a given address, both the chip select (pin 22) and the chip-enable/power-down (pin 20) control inputs must be enabled. When both controls are enabled, the 8-bit output word from a given address can be read from the outputs. Output Q , is considered the LSB , while Q 8 is the MSB. A 5-V d c power supply is used with + 5 V connected to the Vcc (pin 28) and the negative (ground) connected to Vss (pin 14). A computer program is typically referred to as software. When a computer program is stored permanently in a ROM, it is commonly called firmware because of t he difficulty of making changes in the code. SOLVED PROBLEMS 12.18 A ( RAM, ROM) is classified as a nonvolatile storage device. Solution: A R OM is classified as a nonvolatile storage device because it does not lose its data when power is turned off. CHAP. 121 12.19 A - 29 1 MICROCOMPUTER MEMORY ( RAM, R OM) is programmed by the computer operator. Solution: A R A M is programmed by the computer operator. 12.20 R efer to Fig. 12-86. What is the function of the diode R OM? Solution: The function of the ROM shown i n Fig. 12-86 is as a simple binary-to-Gray code converter. 12.21 Refer to Fig. 12-86. List the state of the output for each binary input from 0000 t o 1001. Solution: See the Gray code output for each binary count in Fig. 12-8a. 12.22 Refer to Fig. 12-86. When the binary input is 0001, o utput 1 is activated and the output of its inverter goes (HIGH, LOW), thereby forward-biasing a diode in the ( A , B , C , 0 )column. Solution: Binary 0001 activates output 1, Fig. 12-86. This causes the inverter output to go H IGH, which forward-biases the single diode in the A column. The ROM output reads 0001. 12.23 R efer to Fig. 12-10. List the state of t he ROM outputs during each pulse. Solution: The ROM outputs during each pulse are as follows: pulse e = 1001 (address = 6 ) pulse a = 0011 (address = 0) pulse b = 01 10 (address = 3) pulsef = 0100 (address = 1) pulse g = 1011 (address = 8) pulse c = 1100 (address = 9) pulse d = 1010 (address = 7) 12.24 T he TMS47256 RAM shown in Fig. 12-9 can address wide. pulse h = 0101 (address = 2) pulse i = 01 11 (address = 4) pulse j = 1000 (address = 5 ) words. Each word is -bits Solution: T he TMS47256 R A M can address 32768 (32K) words each 8-bits wide. 12.25 T he TMS47256 IC is a (field, mask)-programmable read-only memory. Solution: The TMS47256 IC is a mask-programmable ROM which is programmed by the manufacturer to the user’s specifications. 12.26 T he TMS47256 ROM has bytes of memory. (number) address lines which can address (16, 32)K Solution: See Fig. 12-9b. T he TMS47256 ROM has 15 address lines ( A o t o A 14)which can address 32K bytes of memory. 12.27 With the chip-enable/power-down pin of the TMS47256 ROM chip goes into the standby mode, which reduces power consumption. (disabled, enabled), the +5 7 0 1 j 0 i I 1 0 1 1 0 h Binary inputs 1- 0 11 1 g 1 101 1 1 0 f e d v 110 / 0 1 n 0 b A ' -+ 1 o I Fig. 12-10 ROM pulse-train problem 292 CHAP. 121 MICROCOMPUTER MEMORY 293 Solution: With the chip-enable/power-down input (pin 20) disabled, the chip goes into the standby mode, which reduces power consumption. 12.28 Refer to F ig. 12-9. Which two control inputs to the TMS47256 ROM must be enabled for stored data to be read from the outputs? Solution: Both the chip-select (pin 22) a nd chip-enable/power-down (pin 20) control inputs must be enabled for stored date to be read from the outputs. 12-4 PROGRAMMABLE READ-ONLY MEMORY Mask-programmable ROMs are programmed by the manufacturer by using photographic masks to expose the silicon die. M ask-programmable R OMs have long development times, and their initial costs are high. They are usually referred to simply as ROMs. Field p rogrammable R OMs ( P R O M S ) also are available. They shorten development time and lower costs. It is also much easier to correct program errors and update products when PROMs can be programmed (burned) by the local developer. The regular PROM can be programmed only once like a ROM, but its advantage is that it can be made in limited quantities and can be programmed in the local lab or shop. A variation of t he PROM is an erasable PROM ( EPROM). T he EPROM is programmed or burned at the local level by using a P ROM burner. If t he EPROM must be reused or reprogrammed, a special quartz window on the top of the IC is used. Ultraviolet (UV) light is directed at the EPROM chip under the window for about an hour. The UV light erases the EPROM by setting all the memory cells to a logical 1. T he EPROM can then be reprogrammed. Figure 12-11 illustrates a typical 24-pin EPROM DIP IC. Note the rectangular EPROM chip visible through the quartz window on top of the IC. These units may sometimes be called UV-erasable PROMs. Fig. 12-11 U V e rasable PROM A third variation of the PROM is an electrically erasable PROM, also referred to as an EEPROM or E2PROM. Because an EEPROM can be erased electrically, it is possible to erase and reprogram it while it remains on the circuit board. This is not possible with the PROM or the UV-erasable PROM. The EEPROM can also reprogram parts of the code on the chip 1 byte at a time. A fourth variation of the PROM is the f lash E PROM. T he flash EPROM is very similar to the EEPROM in that it can be reprogrammed while on the circuit board. The flash EPROM is different M ICROCOMPUTER MEMORY 294 G ood fuse means stored logical 1 Binary i nput b *’ 0 1-of-4 row d ecoder 2 3 (a) Before programming (all logical Is) Blown fuse means stored logical 0 Binary i nput ’I b. 2s 1-of-4 row decoder (6) After programming (selected addresses changed to O S) Fig. 12-12 Diode P ROM [CHAP. 12 CHAP. 121 295 MICROCOMPUTER MEMORY from the EEPROM in that the entire chip is erased and then reprogrammed. The advantages of the flash EPROM over the older EEPROM is it has a simpler storage unit so more bits can be stored on a single chip. Also flash EPROMs can be erased and reprogrammed much faster than EEPROMs. The disadvantages of the flash EPROM are that 12 o r 12.75 V a re required for reprogramming and that a single byte cannot be reprogrammed as on an EEPROM. The basic idea of a programmable R OM ( PROM) is illustrated in Fig. 12-12a. This is a simple 16-bit (4 x 4) PROM. It is similar to the diode ROM studied in the preceding section. Note that each of the memory cells contains a diode and a good fuse. That means that each of the memory cells i n Fig. 12-12a contains a logical 1, which is how the PROM might look beforeprogramming. T he PROM shown in Fig. 12-12b has been programmed with seven OS. T o program or burn the P ROM, tiny fuses must be blown as shown i n Fig. 12-12b. A blown fuse in this case disconnects the diode and means that a logical 0 is permanently stored in the memory cell. Because of the permanent nature of burning a PROM, the unit cannot be reprogrammed. A P ROM of the type shown in Fig. 12-12 can be programmed only once. A popular EPROM family is the 27XX series. It is available from many manufacturers such as Intel and Advanced Micro Devices. A short summary of some models in the 27XX series is shown in Fig. 12-13. Note that all models are organized with byte-wide (8-bit-wide) outputs. Many versions of each of these basic numbers are available. Examples are low-power CMOS units, EPROMs with different access times, and even pin-compatible PROMS, EEPKOMs, and ROMs. E PROM 27XX Organization 2708 2716 2732 2764 27128 27256 27512 1 024 x 2 048 x 4 096 x 8 192 x 1 6384 x 32 768 x 65 536 x 8 8 8 8 8 8 8 Number of bits 8 192 16 384 32 768 65 536 1 3 1 072 262 144 524 288 Fig. 12-13 Selected members of the 277XX series EPROM family A sample IC from the 27XX series EPROM family is shown in Fig. 12-14. T he pin diagram in Fig. 12-14a is for the 2732.4 32K ( 4K X 8) Ultrauiolet Erasable P ROM. T he 2732A E PROM has 1 2 address pins ( A , - - A l l ) which can access the 4096 (212) byte-wide words in the memory. The 2732A E PROM uses a 5-V power supply and can be erased by using ultraviolet ( UV) light. The chip enable input inputs seen on other memory chips. I t is activated with a LOW. is like the chip select p The ?%!?/Vpfi, in serves a dual purpose; it has one purpose during reading and another during writing. Under normal use the EPROM is being read. A LOW at the output enable pin during a memory read activates the three-state output buffers driving the data bus of t he computer system. The eight output pins on the 2732 E PROM are labeled 0 , - 0,. T he block diagram in Fig. 12-14b shows the organization of the 2732A E PROM IC. When the 2732A E PROM is erased, all memory cells are returned to logical 1. D ata is introduced by changing selected memory cells to 0s. T he 2732A is in the programming mode (writing into EPROM) when the dual-purpose input is at 21 V. During programming (writing), the input data is applied to the data output pins (0, - 0,).T he word to be programmed into the EPROM is addressed by using the 12 address lines. A very short (less than 55 ms) T T L level LOW pulse is then applied to the @ input. (m) (a) ( m) m/V,, 296 MICROCOMPUTER MEMORY A7C 1 A6C [CHAP. 12 24 I V c c 2 23 3 A s 22 3 A , ASC3 A4C4 A3C5 21 2 20 A2C6 A l C7 2732A 4 1 3 OEf v pp - AoC 8 ooc 16 3 0 , 9 GND 0 w 193AI0 18 2 C E 17 2 0 , Data outputs vcc o-----.) - OEl v pp CE I Program O E and C Elogic Y decoder GND A o-All address inputs Pin Names 1 3 X decoder -I ' O Q-07 c---7 --A- Output buffers I Y-gating 11 3 2 768-bit cell matrix I I Chip enable (a) Pin diagram ( h ) Block diagram Fig. 12-14 The 2732A 32K U V erasable PROM (Courtesy of Intel Corporation) EPROM erasing and programming is handled by special equipment called PROM burners. After erasing and reprogramming, it is common to cover the EPROM window (see Fig. 12-11) with an opaque sticker. The sticker protects the chip from UV light from fluorescent lights and sunlight. The EPROM can be erased by direct sunlight in about one week or room level fluorescent lighting i n a bout three years. One of the disadvantages of the typical RAM is that it is volatile. When power is turned off, all data is lost. To solve this problem, nonvolatile static RAMs have been developed. Currently nonvolatile read/write memories are implemented by (1) using a CMOS SRAM with battery backup or (2) using a newer semiconductor NVSRAM (nonvolatile static RAM). Static RAMs have both read and write capabilities but are volatile memories. One straightforward solution to the volatility problem is to furnish a battery backup for the S U M . CMOS RAMs are used with battery backup because they consume little power. A long-life battery (such as a lithium battery) is used to back up data on the normally volatile CMOS SRAM when the power fails. During normal operation the regular dc power supply provides power for the SRAM. When power is turned off, a special circuit senses the drop in voltage and switches the SRAM to its standby battery power. Backup batteries have life expectancies of about 10 years. A newer product called a nonvolatile R AM has become available. The nonvolatile RAM is commonly referred to as a N VRAM, NOKUAM, o r N V S R A M . T he NVRAM has the advantage of having both read and write capabilities but does not have the disadvantage of being a volatile memory or having a battery backup. A logic diagram of a commercial NVSRAM is shown in Fig. 12-15a. T he names of the pins are given in the chart in Fig. 12-156. Notice from the logic diagram that the NVSRAM has two parallel memory arrays. The front memory array is a normal static RAM, while the back is an EEPROM. Each SRAM storage location has a parallel EEPROM memory cell. During normal operation the SRAM array is written into and read from just like with any SRAM. When the dc power supply voltage drops, a circuit automatically senses the drop in dc supply voltage and performs the store operation, and all 297 MICROCOMPUTER MEMORY CHAP. 121 A3 A4 A5 Static RAM array 256 X 256 A7 43 A9 A12 DQo Store,’ recall control DQi DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 L I 1 ( a ) Logic diagram [ &-Al2 I Addressinputs i 7 Write enable 0120-0127 Data in/out Chip enable [ i Output enable Nonvolatile enable vcc Power (+ 5 V) Ground ( b) Pin names Fig. 12-15 STKlOC68 CMOS n onvolatile SRAM (Cou:rtesyof Sirntek Corporation) d ata on the volatile SRAM array is stored in the nonvolatile EiEPROM array. This store operation is shown with an arrow pointing from the SRAM to the EEPROM on the logic diagram in Fig. 12-15a. \With t h e nnuipr n i T t h e E E P R n M arrgw ixrithin t h e N V C R A M h nldc a d iinliratp nf t h e l a c t d sta i n t h e SRAM array. When power to the chip is t urned on, the N VSRAM automatically performs the recall operation shown with an arrow pointing from the EEPROM to t he SRAM in Fig. 12-15a. T he recall operation copies all the data from the EEPROM array in the NVSRAM to the SRAM array. 298 M ICROCOMPUTER MEMORY [CHAP. 12 T he NVSRAM detailed in Fig. 12-15a is for an STK10C68 CMOS NVSRAM produced by Simtek. The STK10C68 NVSRAM is organized as an 8 K X 8 memory. The STK10C68 NVSRAM uses 13 address lines ( A , t o A 1 2 t o access the 8192 (213) words, each 8 bits wide. The access time of the ) STK10C68 NVSRAM is about 25 ns. The SRAM can be read from or written to an unlimited number of times, while independent nonvolatile data resides in the EEPROM array. Data can be transferred from the SRAM to the EEPROM array (store operation), or from the EEPROM to t he SRAM array (recall operation), using the pin. The STK10C68 NVSRAM can handle more than 10000 s tore-to-EEPROM operations and an unlimited number of recall-from-EEPROM operations. The STK10C68 operates on a 5-V d c power supply. The STK10C68 is packaged in a variety of standard 28-pin packages. SOLVED PROBLEMS 12.29 T he letters PROM stand for . Solution: T he letters PROM stand for programmable read-only memory. 12.30 T he letters EPROM stand for . Solution: T he letters EPROM stand for erasable programmable read-only memory. 12.31 T he letters NVRAM stand for . Solution: T he letters NVRAM stand for nonvolatile random-access memory (nonvolatile RAM). 12.32 A P ROM can be programmed (many times, only once). Solution: A P ROM can be programmed only once. 12.33 R efer to Fig. 12-12b. A blown fuse in this PROM means that memory cell stores a logical (0,1). Solution: A blown fuse in the PROM in Fig. 12-126 means that memory cell is storing a logical 0. 12.34 R efer to Fig. 12-12b. List the outputs from the PROM for the binary inputs of 00, 01, 10, and 11. Solution: The outputs from the PROM in Fig. 12-126 for each address are as follows: address 10 output = 1110 (row 2) a ddress 00 o utput = 1001 (row 0) a ddress 01 output = 0111 (row 1) address 11 output = 1000 (row 3) 12.35 R efer to Fig. 12-11. What is the purpose of t he window in the EPROM? Solution: A s trong ultraviolet (UV) light directed through the window of the IC in Fig. 12-11 will erase the E PROM chip. CHAP. 121 299 MICROCOMPUTER MEMORY 12.36 What is the advantage of an EPROM over a PROM? Solution: T he EPROM can be erased and used over, whereas the PROM can be programmed only once. 12.37 T he 2732A 1C shown in Fig. 12-14 is a(n) (EPROM, R AM) memory unit. Solution: T he 2732A IC shown in Fig. 12-14 is an EPROM memory unit. 12.38 R efer to Fig. 12-11. Why would an opaque sticker be placed over the window of t he EPROM after programming? Solution: A n o paque sticker is commonly placed over the window of an EPROM (see Fig. 12-11) to keep sunlight and fluorescent light from erasing the memory unit. 12.39 R efer to Fig. 12-14. What is the purpose of t he m/V,, input pin on the 2732A E PROM? Solution: T he = /I$, pin on the 273214 EPROM shown in Fig. 12-14 has a dual purpose. In t he read mode, the @ pin is the output enable to turn on the three-state buffers so they can drive the data bus. In the program mode, the I /pp pin is held at 21 V, which allows writing into the EPROM through the 0,-0, pins. 12.40 T he letters SRAM stand for . Solution: T he letters SRAM stand for static RAM, or static random-access memory. 12.41 T he letters NVSRAM stand for . Solution: T he letters NVSRAM stand for nonvolatile static random-access memory. 12.42 What two methods are currently used to form nonvolatile static RAMS? Solution: Currently nonvolatile SRAM memories are produced by (1) using a CMOS SRAM with battery b ackup and (2) using a NVSRAM (see Fig. 12-15a). (carbon-zinc, 12.43 SRAMs with battery backup generally use a long-life battery such as a lithium) battery to supply standby power when the dc power supply is turned off. Solution: SRAMs with battery backup commonly use lithium batteries to supply standby power when the dc power supply is off. 12.44 T he NVSRAM in Fig. 12-15 might also be called a NVRAM or (DRAM, NOVRAM). Solution: T he NVSRAM in Fig. 12-15 might also be called a NVRAM or NOVRAM. M ICROCOMPUTER MEMORY 300 12.45 T he NVSRAM contains both a static RAM and a nonvolatile [CHAP. 12 (EEPROM, ROM) of t he same size. Solution: See Fig. 12-15a. The NVSRAM contains both a static RAM and a nonvolatile EEPROM of t he same size. 12.46 R efer to Fig. 12-15. As power is turned off, t he STK10C68 NVSRAM automatically (recalls, stores) the data on the SRAM to the EEPROM. Solution: As power is turned off, t he STKlOC68 NVSRAM automatically stores (copies) the data on the SRAM t o the EEPROM. 12.47 R efer to Fig. 12-15. As power is first turned on, the STK10C68 NVSRAM automatically (recalls, stores) the data from the EEPROM to the SRAM. Solution: As power is first turned on, the STKlOC68 NVSRAM automatically recalls (copies) data from t he E EPROM to the SRAM. 12.48 R efer to Fig. 12-15. What is the purpose of the eight D Q pins on the STK10C68 NVSRAM? Solution: The D Q pins serve as eight parallel data outputs during memory read operations or d ata inputs during a memory write operation. 12-5 MICROCOMPUTER BULK STORAGE Program and data storage in a computer system is sometimes classified as either internal or external. I n a microcomputer, the internal storage devices are semiconductor RAM, ROM (or EPROM), and various registers. Currently the most common form of external storage for microcomputers is the magnetic disk. Magnetic disks are subdivided into hard or floppy disks. The most common form of magnetic disk used with microcomputers is the floppy d isk. Typical types of memory devices used in microcomputers are summarized in Fig. 12-1. External storage is also referred to as bulk storage. D ata is stored on floppy disks in much the same way it is on magnetic tapes. The disk drive unit reads and writes on the floppy disk. This is like the play and record functions of a t ape recorder. Reading from a disk has an advantage over reading from a tape because the disk is a random-access instead of a sequential-access device. The disk drive can access any point on the floppy disk in a very short time. In contrast, access to information on a tape is very slow. Floppy disks, or diskettes, come in several sizes. Those most commonly used with microcomputers are the 5.25-in and the newer 3.5-in sizes. There is also an 8-in version of the floppy disk available. A diagram of a typical 5.25-in floppy disk is shown in Fig. 12-16a. The thin, circular, plastic floppy is permanently enclosed in a plastic jacket. The plastic disk is coated with a magnetic material, iron oxide or barium ferrite. Several holes are cut in both sides of t he jacket. These are illustrated in Fig. 12-16a. The round center hole in the jacket provides access to the center area of t he disk. The hub of the disk drive clamps on this area to spin the disk at a constant speed (300 o r 360 rpm). The larger hole in the jacket near the bottom of t he disk shown in Fig. 12-16a exposes part of the disk to the read/write head of t he disk drive. The read/write head touches the spinning floppy disk to store data on the disk (to write) or retrieve data from it (to read). The small round hole cut in the jacket and disk is used as CHAP. 121 301 MICROCOMPUTER MEMORY ( a) Features of the disk Inside track (track 34) ( b ) Location of invisible tracks on disk (c) Location of invisible sectors on disk Fig. 12-16 A 5.25-in floppy disk .ck 302 MICROCOMPUTER MEMORY [CHAP. 12 a n index hole by disk drives on a few computers. If covered, the write-protect notch on the 5.25-in floppy disk prevents data from being written to the disk. When the write-protect notch is open, as in Fig. 12-16a, the disk drive can both write to and read from the disk. Floppy disks are organized in tracks and sectors. Figure 12-16b shows how one microcomputer manufacturer formats the 5.25-in floppy disk. The disk is organized into 35 circular tracks numbered from 00 t o 34 (00 t o 22 in hexadecimal). Each track is divided into 16 sectors, which are shown in Fig. 12-16c. Each sector has 35 short tracks, as shown near the bottom of Fig. 12-16c. By using this format, each short track can hold 256 eight-bit words, or 256 bytes. When formatted as shown in Fig. 12-16c, a floppy disk can hold about 140K bytes of d ata. That is about 1 million bits of d ata on a single 5.25-in floppy disk. It should be noted that there is no standard method of formatting floppy disks. Many microcomputer manufacturers format their disks to hold much more data. That includes reading and writing on both sides of the disk. The floppy disk is a random-access bulk storage memory device which is widely used with home, school, and office microcomputers. Care must be taken when handling floppy disks. Do not touch the magnetic disk itself, and do not press hard when writing on the plastic jacket (5.25-in and %in). A felt-tip pen is recommended for labeling floppy disks. Magnetic fields and high temperatures also can harm data stored on floppy disks. Because of t he danger of surface abrasion, keep disks in a clean area and protect the thin magnetic coating from scratches. A diagram of t he 3.5-in floppy disk is shown in Fig. 12-17. The case is made of rigid plastic for maximum protection of the floppy disk housed inside. The drawing of t he 3.5-in disk in Fig. 12-17 is a Fig. 12-17 A 3.5-in floppy disk CHAP. 121 MICROCOMPUTER MEMORY 303 view from the underside of the storage unit. The center of the plastic case is cut out (on the bottom only), revealing a metal drive hub which is connected to the floppy disk. A sliding metal cover is shown in Fig. 12-17 moved to the right, revealing a rectangular cutout in the rigid plastic case exposing the floppy disk. The floppy disk is accessible from both the bottom and top sides of the disk so t he disk drive read/write heads can retrieve/store data on both sides. When released, the sliding metal cover, which is spring-loaded, snaps back to the left (in Fig. 12-17) to protect the surface of the floppy disk. A write-protect notch is shown at the lower right of the 3.5-in disk in Fig. 12-17. If the write-protect hole is closed by sliding the built-in cover upward (as shown in Fig. 12-17), the disk drive can both write to and read from the disk. This is sometimes called the unlocked position. If the hole is open (slide cover downward in Fig. 12-17), the disk drive can only read from the disk. This is sometimes called the locked position. A n index hole is cut in the metal hub for timing purposes. The 3.5-in disk shown in Fig. 12-17 is a newer development, compared to the 5.25-in and 8-in floppy disks. Precision disk drives commonly access 80 tracks on both sides of the disk. Common formats on the 3.5-in disk allow it to store either 400K, 720K, or 800K bytes. Available with suitable disk drives, high-density 3.5-in disks (FDHD-floppy disk high density) have storage capacity of 1.44M bytes. Most modern microcomputers come with at least one disk drive used to read from and write to 3.5-in floppy disks. Another bulk storage method that is very popular on microcomputers, as well as large computer systems, is the hard disk, a rigid metal disk coated with magnetic material. These disks may be arranged as shown in Fig. 12-18. Notice that read/write heads float just above the surface of the spinning hard disks. The motor spins the hard disk at about 3000 rpm, which is about 10 times faster than the rotation of a floppy disk. The drive units are very precise, and the hard disk may be permanently mounted with the air filtered to keep out unwanted dust and smoke which can hamper operation. Removable hard disks, such as the 5.25-in cartridge drive, are also available. Currently 20M-, 40M-, and 80M-byte hard drives are common on home, school, and small business microcomputers. Larger-capacity units are also widely used in business. Two advantages of hard disks over floppy disks are (1) they store many times more information and (2) they can access information faster. Fig. 12-18 H ard disk drive mechanism H ard disk drives are sometimes called Winchester drives. Microcomputers with hard drives are very common and typically also have a floppy disk drive attached to the system so t he data and programs on the hard drive can be backed up for use in the event of hard disk failure. Still another bulk storage method that shows great promise is the optical disk. T he optical disk is a relative of the laser videodisk. Optical disks are available in three types: (1) read-only, (2) write-once 304 MICROCOMPUTER MEMORY [CHAP. 12 read-many (WORM), and (3) read/write. The read-only disk (optical ROM) is good for prerecorded information like an encyclopedia. The WORM optical disk can be written to once and then read from many times. Read/write optical disks have large storage capacities and are similar in function to a hard disk. The technology used for writing and reading with the optical disk is different from the magnetic hard disk. The magneto-optical disk drive uses a laser in conjunction with a coil of wire to erase, write to, and read from the metal-coated disk. A popular magneto-optical disk has a storage capacity of 128M bytes on a removable 3.5-in optical disk. These optical disks look much like the 3.5-in floppy disk except they are thicker and contain an optical disk. These removable disks a re sometimes called rewritable magneto-optical disks. A 5.25-in magneto-optical disk drive is also available with removable cartridges with a storage capacity of 650M bytes. Because the magneto-optical disk can be removed from the disk drive, it is a suitable medium for backup storage or for transferring large amounts of data or programs from one machine to another. One of the least expensive methods for storing vast amounts of data for backup is to use magnetic tape. Some drives are available that use inexpensive digital audio tape (DAT); however, access to data on tape is very slow. SOLVED PROBLEMS 12.49 R efer to Fig. 12-1. Which device(s) on the microcomputer shown could be classified as internal storage? Solution: Both the semiconductor RAM, ROM, and NVRAM on the microcomputer shown in Fig. 12-1 could both be classified as internal storage. The floppy disk is external storage. 12.50 W hat two types of magnetic disks are used on microcomputers? Solution: Both hard and floppy disks are used on microcomputers for external bulk storage of data and programs. 12.51 T he magnetic disk is a (random-, sequential-) access device. Solution: T he magnetic disk is a random-access device, which means it can find data in a very short time. 12.52 W hat are three sizes of floppy disks? Solution: Floppy disks come in the 3 . 5 , 5 .25, and 8-in sizes. 12.53 A typical disk drive spins the floppy disk at a constant speed of (300, 3000) rpm. Solution: A disk drive spins the floppy disk at a constant speed of 300 rpm (one manufacturer's specification). H ard disks might spin at 3000 rpm. 12.54 T o store data on a floppy disk is called . Solution: To store data o n a floppy disk is called writing (write operation). CHAP. 121 MICROCOMPUTER MEMORY 305 12.55 Briefly, how is data organized on a floppy disk? Solution: Data is organized in tracks and sectors. See Fig. 12-16b and c for more detail on the format used by o ne microcomputer manufacturer. 12.56 Refer to Fig. 12-16c. By using this format, a floppy disk can hold about informat ion. bytes of Solution: By using the format shown in Fig. 12-16c, a floppy disk can hold about 140K (16 x 256 x 35 = 143360 bytes) of information. 12.57 List some precautions that must be observed when 5.25-in floppy disks are handled. Solution: The following are some precautions when floppy disks are handled: 1. Do not touch the magnetic disk itself. 2. Mark the disk lightly or with felt-tip pens when labeling. 3. Keep the disk away from strong magnetic fields. 4. Keep the disk away from high temperatures. 5 . Keep the disk clean. 6. Protect the disk from scratches or surface abrasion. 7. Do not bend or fold the disk. 12.58 What advantage does a hard disk drive have over a floppy disk? Solution: T he hard drive has a much greater storage capacity and a quicker access time. 12.59 T he WORM optical disk can be written to many times. (once, about 10000 times) and read from Solution: T he W ORM (write-once read-many) optical disk can be written to once and read from many times. 12.60 T he (magnetic hard disk, magneto-optical disk) drive uses a laser in conjunction with a coil of wire to erase, write to, and read from the disk. Solution: The magneto-optical disk drive uses a laser in conjunction with a coil of wire to erase, write to, and read from the optical disk. 12.61 T he popular removable 3.5-in rewritable magneto-optical disk has a capacity of about (400K, 128M) bytes and is commonly used for backup storage or for transferring large amounts of data from one machine to another. Solution: T he popular removable 3.5-in rewritable magneto-optical disk has a capacity of about 128M bytes. 306 MICROCOMPUTER MEMORY [CHAP. 12 Supplementary Problems 12.62 Refer to Fig. 12-1. List the five types of memory used by this microcomputer system. Ans. RAM, ROM, NVRAM, floppy disk, and hard disk 12.63 Refer to Fig. 12-1. Which type of memory in this system is volatile? Ans. RAM (read/write memory) 12.64 Refer to Fig. 12-1. What three types of storage devices are semiconductor memories in this system? Ans. RAM, ROM, and NVRAM 12.65 Refer to Fig. 12-1. T he medium for storing data on the Ans. floppy disk 12.66 A read/write memory could be a (floppy disk, RAM) is magnetic. (RAM, ROM). Ans. RAM 12.67 Refer to Fig. 12-1. This semiconductor memory has the read/write capabilities of a RAM with the Ans. NVRAM nonvolatile characteristics of a ROM. 12.68 T he RAM is a ( a ) (nonvolatile, volatile) memory that t he power. Ans. ( a ) volatile ( 6 ) can 12.69 T he 12.71 A 256 X 4 memory would contain ( a ) words, each bits. Ans. ( a ) 256 ( b ) 4 ( c ) 1024 12.72 Entering data in a RAM is the ( lK, 8K) of memory, (b) (read, write) operation. Ans. static Ans. 1K (1024 bytes) bits long, for a total capacity of (c) Ans. write (read, write) mode of operation of a RAM means revealing the contents of a memory Ans. read 12.73 T he location. (RAM, ROM) can be repeatedly programmed by the user. 12.75 A ROM is a 12.76 A Ans. (can, cannot) be erased by turning off (dynamic, static) RAM uses a memory cell similar to a flip-flop. 12.70 Refer to Fig. 12-5. The system is said to have 12.74 A (b) (permanent, temporary) memory. Ans. RAM Ans. permanent (RAM, ROM) is programmed by the manufacturer to the user’s specifications. R OM 12.77 Refer to Fig. 12-7b. What is the function of this simple diode ROM? Ans. decimal-to-Gray code decoder 12.78 R efer to Fig. 12-7b. List the state of the outputs for each decimal input (0-9). Ans. See the table in Fig. 12-7a. 12.79 Refer to Fig. 12-7b. Which diode(s) are forward-biased when the input switch is at decimal 2? Ans. two diodes in columns A and B in row 2 i n Fig. 12-7b. 12.80 Larger-capacity ROMs (such as 512K X 8 ROMs) use manufacture. A m. CMOS 12.81 A 131 072 X 8 R OM would have a total capacity of (bipolar, CMOS) technology in their bits Ans. 1 048576 C HAP. 121 307 MICROCOMPUTER MEMORY 12.82 A 65 536 x 8 R OM would need (8, 16) a ddress line pins on the IC. 1 6 (216 = 65 536) Ans. 12.83 What is a computer program called when it is permanently stored in a ROM? A ns. firmware 12.84 In a general-purpose microcomputer, a greater proportion of internal memory is probably allocated to (RAM, ROM). Ans. R AM 12.85 In a dedicated computer, a greater proportion of internal memory is probably allocated to (RAM, ROM). Ans. R OM 12.86 The letters EEPROM stand for . A ns. electrically erasable programmable read-only memory . 12.87 A mask-programmable read-only memory is commonly called a(n) 12.88 Refer to Fig. 12-12. This is an example of a(n) (EPROM, PROM). A ns. R OM A ns. P ROM 12.89 Refer to Fig. 12-12b. A good fuse (see row 0, column D ) in the PROM means that the memory cell stores (0, 1). Ans. 1 a logical 12.90 R efer to Fig. 12-11. This IC is a(n) (EPROM, ROM). A ns. E PROM (ultraviolet-erasable PROM) 12.91 An E PROM is considered a (nonvolatile, volatile) memory device. A ns. nonvolatile 12.92 The abbreviation E2PROM stands for . A ns. electrically erasable programmable read-only memory (same as EEPROM) 12.93 EPROMs are programmed in the (factory, local lab). A ns. P ROM burner 12.94 What is t he equipment that is used to program EPROMs called? 12.95 The letters SRAM stand for . local lab Register to View Answerns. static random-access memory (static RAM) when dealing with semiconductor memories. 12.96 T he letters RWM stand for Ans. read/write memory (same as RAM) . 12.97 A R WM is more commonly referred to as a(n) 12.98 Magnetic Ans. R AM (disks, tapes) are random-access devices and have a short access time. 12.99 To retrieve data from a floppy disk is called . A ns. disks A ns. reading Ans. 12.100 “ Winchester” is another name for what magnetic storage device? h ard disk drive 12.101 T he 74F189 RAM IC is from the newer subfamily that exhibits an outstanding combination of Ans. Fairchild advanced Schottky TTL, FAST performance and efficiency. 12.102 A short access time for a RAM, ROM, or PROM means it is Ans. faster (A faster chip can be used in higher-frequency circuits.) 12.103 Semiconductor memory ICs manufactured using the Ans. G aAs (gallium arsenide) fastest chips. (faster, slower). (CMOS, GaAs) process technology are the 12.104 R efer to Fig. 12-9. The TMS47256 32K X 8 R OM IC would have A ns. 15 ( A o t o A , , ) , 8 ( Q , t o Q 8 ) data outputs. ~ a ddress inputs and 308 MICROCOMPUTER MEMORY 12.105 T he flash EPROM is very similar to the 12.106 T he letters NVSRAM stands for (EEPROM, NOVRAM). [ CHAP. 12 Register to View AnswerEPROM . Ans. nonvolatile static random-access memory, or nonvolatile static RAM 12.107 Refer to Fig. 12-15. The STK10C68 NVSRAM has 64K bits of memory organized with each -bits wide. Ans. 8K (8192 words), 8 12.108 Refer to Fig. 12-15. The STK10C68 IC is considered a words (nonvolatile, volatile) memory unit. Ans. nonvolatile (does not lose data on loss of power) 12.109 Refer to Fig. 12-17. Disk drives that use the 3.5-in floppy disk most often read from and write to (both sides, one side) of the memory disk. Ans. both 12.110 R efer to Fig. 12-17. The 3.5-in floppy disk is write-protected and can only be read from when the hole in the write-protect slot is (closed, open). Ans. open (This is the opposite of the 5.25-in disk i n Fig. 12-16a.) 12.111 T he (floppy, hard) disk has the advantage over the other in that i t can store more data and can access the information faster. Ans. hard 12.112 T he 3.5-in (magnetic floppy, rewritable magneto-optical) disk has a storage capacity of about 128M bytes and uses a laser diode and coil of wire for erasing, reading, and writing. Ans. rewritable magneto-optical Chapter 13 Other Devices and Techniques 13-1 INTRODUCTION In examining manufacturers’ TTL, CMOS, and memory data manuals, you would find several types of ICs t hat have not been investigated in the first 12 c hapters of this book. This will be a “catchall” chapter to include devices and techniques that do not fit neatly into other chapters but are topics that are included in many of t he standard textbooks in the field. Included will be multiplexers/data selectors and multiplexing, demultiplexers, an introduction to digital data transmission, latches and three-state buffers, programmable logic devices, magnitude comparators, and Schmitt trigger devices. 13-2 DATA SELECTOR/ MULTIPLEXERS A data selector is the electronic version of a one-way rotary switch. Figure 13-1 shows a single-pole, eight-position rotary switch on the left. The eight inputs ( 0-7) a re shown on the left, and a single output on the right is labeled Y.A d ata selector is shown on the right. The data at input 2 (a logical 1) is being transferred through the contacts of the rotary switch. Similarly, the data at input 2 (a logical 1) is being transferred through the circuitry of the data selector on the right. The data position is selected by mechanically turning the rotor on the rotary switch. The data position is selected in the data selector by placing the proper binary number on the data-select inputs ( C , B , A ) . T he data selector permits data to flow only from input to output, whereas the rotary switch allows data to flow in both directions. A d ata selector can be thought of as being similar to a one-way rotary switch. Inputs Inputs 0 I output 5 o utput & 3 4/0 7 Y \ : 1 1 1 o$ + I ‘I 0 Electronic data selector Mechanical data selector Fig. 13-1 Comparison of a rotary switch and a data selector A commercial data selector is shown in block-diagram form in Fig. 1 3-2a. This T T L IC is identified as a 74150 16-input data selector /multiplexer by t he manufacturers. Note the 16 d ata inputs at the top left. The 74150 has a single inverted output labeled W . F our data-select inputs ( D, , B , A ) C a re identified at the lower left in Fig. 1 3-2a. A LOW a t the strobe input will enable the data selector and can be thought of as a main on-off switch. 309 310 OTHER DEVICES AND TECHNIQUES Data inputs I [CHAP. 13 Inputs o utput Strobe Select selector/ multiplexer D output j: L L L L L L L L H H H H H H H H 9 10 It 12 13 Enable input (74150) Strobe select inputs D L L L L H H H H L L L L H H H H H L L L L L L L L L L L L L L L L L H L H L H L H L H L H L H L H H E0 El E2 E3 E4 - E5 - E6 E7 - E8 - E9 E 10 El 1 E 12 E13 E 14 E15 Data-select 1 0 11 12 13 E5 E4 E 3 E2 E E0 l 9 1 4 IIIIIll 7 L L H H L L H H L L H H L L H H - Data inputs IE6 W S A ( b ) Truth table (Courtesy of T exas Instruments, Inc.) ( a) Block logic symbol Vcc ‘ 8 B xxxx I 14 IS C 15’ A B S DI W C YI 0 Strobe W D GND Out- DataData inputs put select ( c ) Pin diagram (Courtesy of Texas Instruments, Inc.) 6 5 4 3 2 1 Fig. 13-2 The TTL 74150 data selector/multiplexer IC Consider the 74150 data selector truth table in Fig. 13-2b. Line 1 shows the strobe (enable) input HIGH, which disables the entire unit. Line 2 shows all the data-select inputs LOW as well as t he strobe input being LOW. This enables the information at data input 0 to be transferred to output W . T he data at output W will appear in its inverted form, as symbolized by the in the output column of the truth table. As t he binary count increases (0001, 0010, 0011, and so f orth) down the truth table, each data input in turn is connected to output W of the data selector. The 74150 IC is packaged in a 24-pin package. The pin diagram for this IC is shown in Fig. 13-2c. Besides the 21 inputs and one output shown on the block diagram, the pin diagram also identifies the power connections (Vcc and GND). Being a T T L IC, t he 74150 requires a 5-V power supply. Note the use of the term “data selector/muZtzpZexer” to identify the 74150 IC. A 74150 digital multiplexer can be used to transmit a 16-bit parallel word into serial form. This is accomplished by 311 OTHER DEVICES AND TECHNIQUES CHAP. 131 connecting a counter to the data-select inputs and counting from 0000 t o 1111. T he 16-bit parallel word at the data inputs (0-15) is then transferred to the output in serial form (one at a time). The 74150 data selector/multiplexer can also be used to solve difficult combinational logic problems. Consider the truth table o n t he left in Fig. 13-3. The simplified Boolean expression for this truth table is CO + A BCE + z B C B + A B C D + A B c D + x B C D + ABCD = Y . Many ICs would be needed to implement this complicated expression by using AND-OR logic or NAND combinational logic circuits. The data selector is an easy method of solving this otherwise difficult problem. 2s Inputs o utput DCBA Y Line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 0 0 Data inputs 1 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 v 0 i ' 4 5 16-input data selector 6 7 '8 output W -9 10 11 Y 12 13 14 I5 (74150) Strobe Enable a A 13 c D Fig. 13-3 Using the 74150 d ata selector to solve a combinational logic problem A combinational Iogic problem is posed by the truth table in Fig. 13-3. A 16-input data selector is being used to solve the problem. The 16 data inputs (0-15) to the 74150 I C have logic levels corresponding to the output column of the truth table. Line 1 in the truth table has an input of binary 0000 (decimal 0) and an output of 1. T he 1 is then applied to the 0 d ata input of the data selector. Line 2 in the truth table has an input of binary 0001 (decimal 1) and an output of 0. T he 0 is t hen applied to the 1 input of t he data selector. The input logic levels ( D , C, B , A ) from the truth table are applied to the data-select inputs of t he 74150 d ata selector. The enable input of the 74150 IC is placed at 0, and the unit solves the logic problem in the truth table. Note that, because of t he inverted output of the 74150 data selector, an inverter is shown added at the right in Fig. 13-3. The data selector solution to this combinational logic problem was a quick and easy one-package solution. 312 O THER DEVICES A ND T ECHNIQUES [CHAP. 13 SOLVED PROBLEMS 13.1 A data selector is also called a . Solution: A d ata selector is also called a multiplexer. 13.2 A data selector is comparable to a mechanical switch. Solution: A data selector is comparable to a mechanical one-way rotary switch. 13.3 Refer to Fig. 13-2. If the data selects on the 74150 IC equal D = 1, C = 0, B = 1, A = 1 and if the chip is enabled by a (HIGH, LOW) at the strobe input, (inverted, normal) data will be transferred from data input (decimal number) to output W . Solution: Based on t he truth table in Fig. 13-2, if t he data selects on the 74150 IC equal 1011 (HLHH in truth table) and if the chip is enabled by a LOW a t the strobe input, inverted data will be transferred from data input 11 to output W . 13.4 Refer to Fig. 13-2. A HIGH at the strobe input of the 74150 IC will the data selector. (disable, enable) Solution: A H IGH at the strobe input of the 74150 IC will disable the data selector. 13.5 Refer to Fig. 13-3. If the data-select inputs equal D be (HIGH, LOW). = 1, C = 0, B = 1, A = 0, the output Y will Solution: If the data-select inputs equal 1010, output Y of the data selector shown in Fig. 13-3 will be HIGH. 13.6 Often the single-packagemethod of solving a combinational logic problem involves using (a data selector, N AND logic). Solution: Often the single-package method of solving a combinational logic problem involves using a data selector. 13.7 Draw a block diagram of a 74150 data selector being used to solve the logic problem described by the Boolean expression z CD + Z BCD + A BCD + A B B + A BCD = Y . Solution: See Fig. 13-4. The procedure is to first prepare from the Boolean expression a truth table similar to that in Fig. 13-3. Each 0 and 1 in the output column of the truth table will be placed o n the corresponding data input of the data selector. An inverter is placed at output W of t he 74150 data selector to read out noninverted data at Y . CHAP. 131 313 OTHER DEVICES AND TECHNIQUES Data inputs ABCD 0 1 0 0 0 0 0 'I . 0 ABCD ABCD A BCD A BCD 1 1 0 0 0 0 0 1 1 Enable Dataselect inputs 2 3 4 5 6 7 8 9 16-input data selector output W . 10 * II I2 13 14 I5 (74150) Strobe A B c [*?I I " I Fig. 13-4 Solution of a combinational logic problem by using a 74150 data selector 13-3 MULTIPLEXlNG DISPLAYS Many electronic systems use alphanumeric displays. In fact, alphanumeric displays are a first clue that an electronic system contains at least some digital circuitry. A simple 0 t o 99 counter system with a digital readout is diagrammed in Fig. 13-5. T he 0 t o 99 counter system is used to illustrate the idea of display multiplexing. T he counters are driven by a low-frequency clock ( 1 Hz). T he outputs from the two decade counters are alternately fed through the I MUX I - 100 H z nnMiuL LOW = Is count HIGH = 10s count I x Decoder Ucounter Fig. 13-5 Block diagram of 0 to 99 counter using multiplexed displays CHAP. 131 315 OTHER DEVICES AND TECHNIQUES multiplexer (MUX), decoded, and applied to both seven-segment LED displays. The multiplex clock (MUX clock) generates a higher-frequency signal (100 Hz). This signal alternately lights the 1s count on the display at the right or the 10s count on the seven-segment LED display at the left. The block diagram in Fig. 13-5 suggests that the 1s count is passed through the multiplexer and decoded and the 1s display is activated when the MUX clock signal is LOW. When the MUX clock signal goes HIGH, the 10s count is passed through the multiplexer and decoded and the 10s display is activated. In effect, the seven-segment displays are alternately tu.rned on and off about 100 times per second. The human eye interprets that as both seven-segment LED displays being lit continuously. In this example, multiplexing reduces display power consurnption and reduces the need for an extra decoder. Multiplexing is widely used with displays to save power. There is less need to multiplex LCD-type displays because they already consume very little power. For this and other reasons, LCD displays are often driven directly and not multiplexed. The logic diagram in Fig. 13-6 is an implementation of the 0 to 99 counter using T T L ICs. All of t he ICs used were examined in some detail earlier in the book except the multiplexer. The 74157 T TL 2-line-to-1-line multiplexer serves the purpose of alternately switching either the 1s count or the 10s count onto the input of the decoder. Note that, when the select line of the 74157 MUX is LOW, the A d ata (BCD from 1s counter) is passed to the decoder. At the same time, the 7404 inverter’s output is HIGH, which allows the 1s seven-segment display to light. The 10s display is turned off when the MUX clock is LOW because the anode is grounded. When the select line to the 74157 M UX in Fig. 13-6 goes HIGH, the B d ata is passed to the decoder. At the same instant, the anode of the 10s seven-segment display is HIGH, which allows it to light. The 1s display is turned off during this time because its anode is grounded by the LOW from the output of the inverter. The 1 50-0 resistors limit the current through the display LEDs to a safe level. The circuit shown in Fig. 13-6 will actually operate. To demonstrate that’the displays are being multiplexed, substitute a 150-kfl resistor for R , in the MUX clock circuit. This will slow down the MUX clock so you can see the action of the multiplexer as t he displays flash alternately on and off. SOLVED PROBLEMS 13.8 Refer to Fig. 13-5. When the MUX clock signal is HIGH, the the (left, right) seven-segment LED display. (Is, 10s) count is lit on Solution: When the MUX signal shown in Fig. 13-5 is HIGH the 10s count is lit on the left LED display. 13.9 Why are displays multiplexed? Solution: Multiplexing of LED displays reduces power consumption and simplifies wiring. 13.10 Refer to Fig. 13-6. Technically, are 60th seven-segment displays ever lit at the same time? Solution: Technically, both seven-segment displays shown in Fig. 13-6 are never lit at the same time. To the human eye they both appear to be continuously l it because they are flashing at 100 Hz. 13.11 Refer to Fig. 13-6. What effect would reducing the MUX clock frequency to 5 Hz have on the appearance of the displays? Solution: If the frequency of the MUX clock shown in Fig. 13-6 were reduced to 5 Hz, the eye would see the multiplexing action as a flashing of the displays. 316 O THER DEVICES AND TECHNIQUES [CHAP. 13 input to the 74157 MUX determines if the I s 13.12 Refer to Fig. 13-6. The logic level on the o r the 10s count will be passed on to the decoder. Solution: The logic level of the select input to the 74157 M UX in Fig. 13-6 determines if the 1s or 10s count will be passed on to the decoder. 13.13 Refer to Fig. 13-6. If the M UX clock is LOW, t he 1s count is passed through the decoder to which seven-segment display(s)? Solution: When the MUX clock shown in Fig. 13-6 is LOW, the 1s count is passed through the decoder to-both displays. However, only the 1s display lights because only its anode is HIGH. 13.14 Refer to Fig. 13-6. What is the job of the 7404 inverter? Solution: The inverter shown i n Fig. 13-6 activates the anodes of the displays alternately. A HIGH at the anode will activate the display. 13-4 DEMULTIPLEXERS T he operation of a demultiplexer ( DEMUX) is illustrated in Fig. 13-7. The demultiplexer reverses the operation of t he multiplexer (see Fig. 13-1). T he single-pole, eight-position rotary switch at the left in Fig. 13-7 shows the fundamental idea of t he demultiplexer. Notice that the demultiplexer has a single input and eight outputs. The data at the input can be distributed to one of eight outputs by the mechanical wiper arm on the rotary.switch at the left. In the example in Fig. 13-7, the HIGH a t the input is routed to output 2 by the rotary switch. Inputs outputs outputs Demultiplexer HIGH Input x- HIGH (jl= 3 7 0 1 oc Mechanical data selector 7 Electronic data s:lector Fig. 13-7 Comparison of a rotary switch and a demultiplexer (data distributor) A logic symbol for a simplified electronic demultiplexer is drawn at the right in Fig. 13-7. Note the single data input with eight outputs. The demultiplexer also has three data-select inputs (address inputs) for choosing which output is selected. In the example in Fig. 13-7, the HIGH a t the input appears at output 2 of the electronic demultiplexer because 010, (2 in decimal) is applied to the data-select inputs. The demultiplexer is also called a decoder and sometimes a d ata distributor. T he electronic demultiplexer in Fig. 13-7 only allows data to flow from input to output, whereas the rotary switch permits data to flow in both directions. A d ata distributor, or demultiplexer, can be thought of as being similar to a one-way rotary switch. 317 OTHER DEVICES AND TECHNIQUES CHAP. 131 outputs 3 Dataselect inputs ( a ) Logic symbol Function Table Inputs outputs G1 G 2 D C B A 0 1 2 3 4 5 6 7 8 9 L L L L L L L L L L L L L L L L L H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H HH HH HH HH HH HH HH HH HH LH HL HH HH HH HH HH HH HH HH L L L L L L L L L L L L L L L L H L H L L L L L L L L H H H H H H H H xxxx xxxx xxxx 101112131415 H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H = High Level, L = Low Level, X = Don’t Care ( b ) Function table (Courtesy of National Semiconductor Corporation ) Fig. 13-8 T he 74LS154 decoder/dernultiplexer IC H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L H H H 318 O THER DEVICES AND TECHNIQUES [CHAP. 13 A commercial demultiplexer is shown in Fig. 13-8. The T T L unit detailed in Fig. 13-8 is described by the manufacturer as a 74LS154 4-line to 16-line decoder/demultiplexer IC. T he logic diagram in Fig. 13-8a describes the 74LS154 demultiplexer. The 74LS154 has 16 outputs (0 t o 15) with 4 data-select inputs ( D t o A ). T he outputs are all active LOW pins, which means they are normally and which HIGH and one is pulled LOW when activated. The 74LS154 has two data inputs are NORed together to generate the single d ata input. The two d ata inputs are both active-LOW inputs. The 74LS154 demultiplexer is sometimes described as a 2-of-16decoder. T he 74LS154 is a member of the T T L low-power Schottky family. The 74LS154 is a fast decoder with a propagation delay of less than 30 ns. A t ruth table (or function table) for the 74LS154 decoder/demultiplexer IC is reproduced in Fig. 13-8b. Note that both the data inputs and must be LOW before 1 of t he 16 outputs is activated. The data-select inputs can be thought of as address inputs because of the use of the demultiplexer as a memory decoder. For instance, i t might be used to select (or address) 1 of 16 RAM chips. Both T T L and CMOS versions of demultiplexers/decoders are available. Common units include 1-of-4, 1-of-8, 1-of-10, and 1-of-16 decoders/demultiplexers. (a a ) (a m) SOLVED PROBLEMS 13.15 A (demultiplexer, shift register) reverses the action of a multiplexer. Solution: T he demultiplexer reverses the action of the multiplexer (compare Figs. 13-1 and 13-7). 13.16 T he demultiplexer on the right in Fig. 13-7 could also be referred to as a 1-of-16) decoder. (1-of-8, Solution: The demultiplexer on the right in Fig. 13-7 distributes data from a single input to one of eight outputs. It is therefore commonly called a I-of-8 decoder. 13.17 Demultiplexers are commonly called data (decoders, gates). (distributors, multivibrators) or Solution: Demultiplexers are commonly called data distributors or decoders. 13.18 T he 74LS154 demultiplexer is a LOW) data inputs and active- (1-of-8, 1-of-16) decoder with active(HIGH, LOW) outputs. (HIGH, Solution: See Fig. 13-8. The 74LS154 demultiplexer is a 1-of-16 decoder with active-LOW data inputs and active-LOW outputs. 13.19 R efer to Fig. 13-8. Both data inputs and G2 must be selected output on the 74LS154 demultiplexer IC. Solution: See Fig. 13-8b. Both data inputs (HIGH, LOW) to activate the (and m)must be LOW to activate the selected output. z 13.20 Which output of t he 74LS154 demultiplexer will be activated if while the data-select inputs are all HIGH. and G2 a re both LOW CHAP. 131 319 OTHER DEVICES AND TECHNIQUES Solution: and are LOW and all the See Fig. 13-8. Output 15 will be activated (LOW) when data inputs data-select inputs are HIGH. The address at the data-select inputs is l lll,, which is decimal 15. (m m) a 13.21 Which output of the 74LS154 demultiplexer will be activated if and while the data-select inputs are D = LOW, C = LOW, B = H IGH, and A Solution: See Fig. 13-8. Output 3 will be activated (LOW) when data inputs address at the data-select inputs is 0011, (decimal 3). = are both LOW H IGH? (a E )are LOW and the and 13-5 LATCHES AND THREE-STATE BUFFERS Consider the simple digital system shown in Fig. 13-9a. When 7 is pressed on the keyboard, a decimal 7 appears on the display. However, when the key is released, the 7 disappears from the output display. To solve this problem, a 4-bit latch has been added to the system in Fig. 13-9b so that, when the key is pressed and released, the decimal number will remain lit on the seven-segment display. It can be said that the number 7 is latched on the display. The latch could also be referred to as a buger memory. Fig. 13-9 Block diagram of simple digital systems A simple latch manufactured in IC form is detailed in Fig. 13-10. This is the TTL 7475 4-bit transparent latch IC. A logic diagram for the 7475 latch is shown in Fig. 13-10a with its truth table detailed in Fig. 1 3-lob. T he 7475 IC has four data inputs which accept parallel data. The data at D o - D , pass through the 7475 to both normal and complementary outputs when the data-enable inputs are HIGH. With the data-enable inputs HIGH the latch is said to be transparent in that any change in data at the data inputs is immediately passed to the data outputs. When the data-enables are activated with a LOW, data is latched (or held) at the outputs. When latched, changes at the data inputs do not cause any changes at the outputs. 320 OTHER DEVICES AND TECHNIQUES D ata inputs for D o a nd D , l atches {- Data inputs for D 2 a nd D 3 l atches {- N ormal and c omplementary outputs for D o a nd D , l atches Q O 4-bit latch Qi 7 475) 1 = d ata enable 0 = l atch enable E, 1 [CHAP. 13 N ormal and complementary outputs for D2 and D , l atches Q3 ‘ 2-3 ( a) L ogc d iagram Q O Q O D O QI Dl Ql ‘2-3 E 04 vcc GND - D2 Q2 D3 Q2 Q3 Q3 - ( b) T ruth table (c) P in diagram Fig. 13-10 7475 4-bit latch T he 7475 latch comes in a standard DIP IC. The pin diagram for the 7475 IC is drawn in Fig. 13-1Oc. 7475 latch is considered a parallel-in parallel-out register. Microprocessor-based systems (such as microcomputers) use a two-way data bus to transfer data back and forth between devices. The block diagram in Fig. 13-11 shows a simple microprocessor-based system using a 4-bit bidirectional data bus. For a data bus to work properly, each device must be isolated from t he bus, by using a three-state buffer. A familiar keyboard input is shown with an added three-state buffer to disconnect the latched data from the data bus for all but a very short time when the microprocessor sends a LOW read signal. When the buffer’s control input C is activated, the latched data drives the data bus lines either HIGH or LOW depending on the data present. The microprocessor then latches this data off the data bus and deactivates the buffer (control C back to HIGH). The three-state buffer shown in block form in Fig. 13-11 might be implemented using the T T L 74125 quad three-state buffer I C. A logic symbol for a single noninverting buger is drawn in Fig. 13-12a. A pin diagram of t he 74125 I C is in Fig. 1 3-126, and a truth table is in Fig. 13-12c. When the control input is LOW, data is passed through the buffer with no inversion. When the control input goes HIGH, the output of the buffer goes to the high-impedance state. This is like creating an open between input A and output Y in Fig. 13-12a. O utput Y t hen floats to the voltage level of the data bus line to which it is connected. C HAP. 131 OTHER DEVICES AND TECHNIQUES 321 Fig. 13-11 Buffers used to isolate devices from a data bus Three-state buffers are commonly built into devices designed to interface with a microcomputer bus. Figure 13-11 shows the buffer as part of the microprocessor and RAM (random-access memory or read/write memory). Many devices called peripheral interface adapters ( PIAS) hich contain latches, w buffers, registers, and control lines are available. These special ICs are available for each specific microprocessor and take care of the input/output needs of the system. A variety of latches are available in both T T L and CMOS. Latches commonly come in 4- or 8-bit D flip-flop versions. Some latches have three-state outputs. Many buffer ICs are available using either T T L or CMOS technology. T T L buffers come with totem-pole, open-collector, or three-state outputs. Buffers may be of the inverting or noninverting types. Many buffers, such as the 74125 in Fig. 13-12, allow data to pass through the unit only in one direction. A variation of the buffer is the bus transceiuer which allows two-way flow to or from a bus. The buffers identified as part of the microprocessor and RAM in Fig. 13-11 are really two-way buffers or bus transceivers. 322 [CHAP. 13 O THER DEVICES AND TECHNIQUES Control I nputs output (noninverted) Data (a) Logic symbol of a three-state buffer 1 c 1A 4c 1Y 4A 4Y -+ Inputs L L H L H X Output L H (Z) ,pc -3 (c) T ruth table ( b) Pin diagram Fig. 13-12 74125 quad three-state buffer IC SOLVED PROBLEMS 13.22 R efer to Fig. 13-9a. Why does the output show decimal 7 only when the key is pressed on t he keyboard and not when it is released? Solution: The system shown in Fig. 13-9a does not contain a latch to hold the data at the inputs to the decoder. To latch data, the system must be modified to the one shown in Fig. 13-96. 13.23 R efer to Fig. 13-13. The 7475 IC has active (HIGH, LOW) enable inputs. Solution: The bubbles at the enable inputs to the 7475 IC shown in Fig. 13-13 mean these are active LOW inputs. 13.24 R efer to Fig. 13-13. List the mode of operation of t he 7475 latch for each time period. Solution: time period time period time period time period t, t, t, t, = d ata enabled latched = data latched = d ata enabled = d ata time period t , = data enabled time period t , = data latched time period t , = d ata latched CHAP. 131 t7 ‘6 1 0 0 0 323 OTHER DEVICES AND TECHNIQUES 1 t5 t4 t3 t2 1 0 0 1 I 0 0 0 c1 0 0 0 0 0 1 (Time) \ iD ata nputs ------ /- 4-2 Q3 D1 4-bit latch D, D3 (7475) Q2 Q, QO I Eo-1 Fig. 13-13 Latch pulse-train problem 13.25 Refer to Fig. 13-13. List the 4-bit binary output at the indicators of the 7475 IC for each time period. Solution: time period time period time period time period t , = 0001 (data t = 0001 (data t , = 0001 (data t , = 1000 (data enabled) latched) latched) enabled) time period t , = 0111 (data enabled) time period t , = 01 11 (data latched) time period t , = 0111 (data latched) 13.26 Each device connected to a data bus (such as the one shown in Fig. 13-11) must be isolated . from the bus by a Solution: Devices on a data bus are isolated from the bus by using a three-state buffer. This buffer is often built into the peripheral interface adapter or memory ICs. A two-way buffer is called a bus transceiver. 13.27 Refer to Fig. 13-11. If the 9 were pressed on the keyboard, what might be the sequence of events for the microprocessor to read this number? Solution: Refer to Fig. 13-11. Closing the 9 key causes binary 1001 to be latched and the microprocessor interrupted (signaled that keyboard is sending data). The microprocessor completes its current task and sends a LOW read signal to the three-state buffer. Data (binary 1001) flows through the buffer onto the data bus. The microprocessor latches this data off the data bus and disables the read signal (read output back to HIGH). The outputs of t he three-state buffer return to their high-impedance state. 13.28 R efer to Fig. 13-11. If t he latched data is binary 1001 and the control C input to t he buffer is HIGH, t hen the outputs of the three-state buffer are at what logic levels? Solution: T he HJGH on the control C pin of the three-state buffer places the outputs of t he buffers in a high-impedance state. That means the buffer outputs will float to whatever logic levels exist o n the data bus. 324 O THER DEVICES AND TECHNIQUES 13.29 R efer to Fig. 13-12. T he 74125 I C contains four buffers. [CHAP. 13 (inverting, noninverting) three-state Solution: R efer to Fig. 13-12. T he 74125 I C contains four noninverting three-state buffers. 13.30 Refer to Fig. 13-11. What might be the difference between the keyboard buffers compared to the buffers in the RAM? Solution: T he buffers between the keyboard and the data bus pass information in only one direction (onto the data bus). However, the RAM buffers must be able to send data to and accept data from the data bus. 13-6 DIGITAL DATA TRANSMISSION Digital data transmission is t he process of sending information from o ne part of a system to another. Sometimes the locations are close, and sometimes they are many miles apart. Either parallel or serial data transmission can be used. Serial data transmission is more useful when sending information long distances. Figure 13-14a illustrates the idea of parallel data transmission. This is typical inside microprocessor-based systems where entire groups of bits (called w ords) a re transferred at the same time. In Fig. 13-14a eight lines are needed to transmit the parallel data. A parallel system is used when speed is important. The disadvantage of parallel transmission is the cost of providing many registers, latches, and conductors for the many bits of data. The data bus shown in Fig. 13-11 is another example of parallel data transmission inside a microcomputer. In the case of the bus system, data can flow in both directions and additional buffering for each device connected to the bus is required. Figure 13-14b illustrates the idea of serial data transmission. T here is only one transmission line, and data is sent serially (one bit at a time) over the line. One format for sending asynchronous data serially is shown in Fig. 13-14b. A 7-bit ASCII code (see ASCII code in Fig. 2 -11) can be sent by using this serial format. The line is normally HIGH, as shown on the left of the waveform. The LOW start bit signals the start of a word. The data bits are transmitted one at a time with the LSB ( D o )first. After the 7 data bits ( D o- D 6), a parity bit for error detection is transmitted. Finally, two H IGH stop 1 n De.;ice U (a) I Device 2 I Parallel data transmissions ( h ) Serial data transmissions Fig. 13-14 Digital data transmission methods CHAP. 131 O THER DEVICES AND TECHNIQIJES 325 bits indicating that the character is complete are sent. These 1 1 bits transmit one ASCII character representing a letter, number, or control code. Note that both devices 1 and 2 in the parallel transmission system in Fig. 13-14a would require parallel-in parallel-out type registers. In the serial data transmission system shown in Fig. 13-14b , device 1 would require a parallel-in serial-out register. Device 2 in Fig. 13-14b would require a serial-in parallel-out storage unit to reassemble the data back into parallel format. Manufacturers produce specialized complex ICs that perform the task of serial data transmission. One such device is the universal asynchronous receiver-transmitter , o r U ART. T he UART takes care of the parallel-to-serial and serial-to-parallel conversions for the transmitter and receiver. A typical UART is the A Y-5-1013 by General Instrument. Other complex ICs that handle serial data transmission are the Motorola 6850 asynchronous communication interface adapter ( ACL4) and the Intel 8251 unir;ersal synchronous-asynchronous receiver-transmitter ( USART). Serial data transmissions can be either asynchronous or synchronous. Asynchronous formats need start and stop bits (see Fig. 1 3-146). T here are also several synchronous serial protocols. Two of them are IBM’s binary synchronous protocol ( BISYNC) and IBM’s synchronous data link control ( SDLC). T he speed at which serial data is transmitted is referred to as, the baud rate. As a n example, look at Fig. 13-14b. It takes 1 1 bits to send a single character. If 10 characters per second are transmitted, then 110 bits are sent per second. The r ate of data transfer will then be 110 baud (110 bits per second). Confusion sometimes occurs if baud rate is compared with data bits transmitted per second. In the above example, the 10 words transmitted per second contain only 70 d ata bits. Therefore, 110 baud equals only 70 d ata bits per second. Many microcomputer owners use parallel and serial data transmission when interfacing with peripheral equipment. They may use either parallel or serial interfaces for their printers. They may use m odems (modulator-demodulators) for sending and receiving data over phone lines. Some serial interface devices used with home computers send and receive data at speeds of 9600 baud. SOLVED PROBLEMS 13.31 Digital data can be transmitted in either parallel or form. Solution: Digital data can be transmitted in either parallel or serial form. 13.32 (parallel, serial) data transmission is the process of transferring whole data words at the same time. Solution: Parallel data transmission is the process of transferring whole data words at the same time. 13.33 Refer to Fig. 13-14a. Device 1 must be a -in-- -out type register. Solution: Device 1 (Fig. 1 3-14a) must be a parallel-in parallel-out register. 13.34 Refer to Fig. 13-146. Device 2 must be a -in -out register. Solution: Device 2 (Fig. 1 3-14b) must be a serial-in parallel-out device. O THER DEVICES AND TECHNIQUES [CHAP. 13 13.35 R efer to Fig. 13-11. T he data bus system is an example of transmission. (parallel, serial) data 326 Solution: A data bus system is an example of parallel data transmission. Bus systems are widely used i n microprocessor-based equipment, including microcomputers. 13.36 R efer to the waveform in Fig. 13-14b. T he 11 bits transmit one character representing a letter, number, or control code. (ASCII, Basic) Solution: T he 11 bits shown i n Fig. 13-14b serially transmit one ASCII character. 13.37 List at least one complex IC t hat can handle the task of serial data transmission. Solution: Several complex ICs used for serial data transmission are available from manufacturers. Three of these specialized ICs are the universal asynchronous receiver-transmitter (UART), the asynchronous communication interface adapter (ACIA), and the universal synchronous-asynchronous receiver-transmi tter (USART). 13.38 A (modem, parallel-in parallel-out register) is the complex device used to send and receive serial data over telephone lines. Solution: A modem (modulator-demodulator) is the device used to send and receive data over phone lines. 13-7 PROGRAMMABLE LOGIC ARRAYS A programmable logic array ( P U ) is an IC t hat can be programmed to execute a complex logic function. They are commonly used to implement combinational logic, but some PLAs can be used to implement sequential logic designs. The PLA is a one-package solution to many logic problems that may have many inputs and multiple outputs. Programmable logic arrays are closely related to PROMS and are programmed much like a PROM. A PLA may also be called a programmable logic device ( PLD). Both PLA and PLD seem to be generic terms used for these programmable logic units. One popular programmable logic device is the PAL,@ (programmable array logic), available from several manufacturers. Using PLDs cuts cost because fewer ICs a re used to implement a logic circuit. PLDs a re faster than using many SSI gate ICs o n a printed circuit board. Software tools are available for programming the PLDs, making it easy to add changes in the prototype designs. Other advantages of the PLDs a re the lower cost of inventory because they are somewhat generic components and the moderate cost of upgrades and modifications. The PLD is a very reliable component. Proprietary logic designs can be hidden from competitors by using the security fuse provided by the manufacturer. A logic diagram for a simple PLA device is shown in Fig. 13-15a. Note that this unit has only two inputs and a single output. A typical commercial product may have 12 inputs and 10 outputs, as is the case for the PAL12LlOA IC. I n Fig. 13-15a n ote the AND-OR p attern of logic gates which can implement any minterm (sum of products) Boolean expression. The simplified PLA in Fig. 13-15a has intact fuses (fusible links) used for programming the AND gates. The OR gate is not programmed in this unit. The PLA in Fig. 13-15a shows the device as it comes from the manufacturer-with all fuses intact. The PLA in Fig. 13-15a needs to be programmed by burning open selected fuses. PAL@Registered Trademark of Advanced Micro Devices, Inc. 327 OTHER DEVICES AND T E C ~ N I ~ ~ E S A Fuses used for mming the AND gates B Y (U) Fuses intact (as from manufacturer) Input A Burn~d-open fuses ( b) Selected fuses burned open to solve logic problems [CHAP. 13 328 A B X \# \# \# \# \# \# \# \# \# 0\ \# 0\ \# 0\ /\ \# Y ( a ) All fuses intact Burned-open fuses (no connection) output A . B + X . B= Y ( b>Selected fuses burned open to solve logic problems Fig. 13-16 Simple PLA using abbreviated notation system (fuse map) 329 OTHER DEVICES AND TECHNIQUES C HAP. 131 T he PLA in Fig 13-1% has been programmed to implement the minterm Boolean expression A - B + A. = Y . Notice that the top 4-input AND gate (gate 1) has two fusible links burned open, B leaving the A and B terms connected. Gate 1 A NDs the A and 8 terms. AND gate 2 has two burned-open fuses, leaving the A and B inputs connected. Gate 2 ANDs t he and B terms. AND gate 3 is not needed t o implement this Boolean expression. All fuses are left intact as shown in Fig. 13-15b, which means the output of A ND gate 3 will always be a logical 0. This logical 0 will have no effect on the operation of t he OR gate. The OR gate in Fig. 13-1% logically ORs the A - and B terms implementing the Boolean expression. In this simplest example, the A - B 2 . = Y m intenn B expression was implemented using a programmable logic array. Recall that the Boolean expression A * B + A. = Y describes the 2-input XOR function which could probably be implemented cheaper B using a 2-input XOR gate SSI IC. x- + Inputs "" i 1 C D I U ABCD I ' Fig. 13-17 PLA with four inputs and three outputs Ouputs YI 330 OTHER DEVICES AND TECHNIQUES [CHAP. 13 A n abbreviated notation system used with PLAs is illustrated in Fig. 13-16. Note that all AND and OR gates have only one input, while in reality each AND gate has four inputs, and the OR gate has three inputs (see Fig. 13-15a). The PLA has all fuses intact before programming. This is shown in Fig. 13-15a as a regular logic diagram. Figure 13-16a shows all fuses intact (each X represents an intact fuse) by using the abbreviated notation system. B The Boolean expression A - + A- = Y is implemented in Fig. 13-156. The same Boolean expression is implemented in Fig. 13-166 but only using the abbreviated notation system to describe the programming of the PLA. Notice in Fig. 13-166 that an X a t an intersection means an intact fuse while no X means a burned-open fuse (no connection). The abbreviated notation system is used because commercial PLAs are much larger than the simplified device drawn in Figs. 13-15 and 13-16. This notation is sometimes called a fuse m ap. A more complex PAL-type programmable logic device is illustrated in Fig. 13-17. This PLA features four inputs and three outputs. It is common for decoders to have many outputs (such as the 7442 decoder in Fig. 7-7). The programmable logic device in Fig. 13-17 is not a commercial product. Three combinational logic problems have been solved using the PLA in Fig. 13-17. First the B - D + A B - C - D + 2. - C - D = Y , is implemented using the upper B Boolean expression A. * Inputs outputs Fig. 13-18 FPLA (field-programmable logic array) w ith p rogrammable AND a nd O R arrays CHAP. 131 331 OTHER DEVICES AND TECHNIQUES group of AND-OR gates. Remember that an X on the fuse map means an intact fuse while no x means a burned-open fuse. The second Boolean expression A B - C - D + A. - C E = Y 2 is impleB mented using the middle group of AND-OR gates. Note that the bottom AND gate in the middle group is not needed. Therefore it has all eight fuses intact, which means it generates a logical 0 which -has no effect on the output of the O R gate. The third Boolean expression A - B - C - D + A . B - C - E -+ A. C - D = Y3 is implemented using the bottom group of AND-OR gates. B A n alternative PLA architecture is shown in Fig. 13-18. This PLA provides both programmable AND and O R arrays. The programmable logic devices studied before only contained programmable AND gates. This type of device is sometimes called a field-programmable logic array ( FPLA). Notice in Fig. 13-18 that each fusible link in both the AND and O R arrays is marked with an X , meaning that all the links are intact (not burned). One catalog of ICs groups programmable logic devices first by the process technology used to manufacture the units. Second, they are grouped as either one-time programmable or erasable. The erasable units can be either of the U V (ultraviolet) light type or electrically erasable. Third, they are grouped by whether the PLD has combinational logic or registered/latched outputs. Traditionally PLDs have been uscd to solve complex combinational logic problems. The registered PLDs contain both gates and flip-flops, providing the means of latching output data or of designing sequential logic circuits such as counters. The PAL10H8 is an example of a small commercial programmable logic device. The pin diagram in Fig. 13-19a shows a block diagram of the PALlOH8 programmable logic array. Notice that the block diagram shows 10 inputs and 8 o utputs along with the programmable AND array. A more detailed logic diagram of the PALlOH8 is reproduced in Fig. 13-19b. This detailed logic diagram looks much like the simple programmable logic devices studied earlier. The PALlOH8 IC is a Schottky T T L device with titanium tungsten fusible links. The PALlOH8 has a propagation delay of less than 35 ns. The PALlOH8 requires a standard 5-V dc power supply. The PALlOH8 is available in the 20-pin DIP (shown in Fig. 13-19a) or a 20-lead plastic chip carrier package for surface mounting. Part number decoding and ordering information supplied by National Semiconductor for the PAL series of programmable logic arrays is shown in Fig. 13-20. Note that the letters PAL indicate the family of devices. I n this example, the next number (10) indicates the number of inputs to the AND array. The middle letter ( H in this example) indicates the type of output. The H means the outputs are active-HIGH. The next number (8 in this example) indicates the number of outputs. The trailing * a I - ( a ) Pin and block diagram Fig. 13-19 PAL1 OH8 programmable logic device (Courtesy of National Semiconductor Corporation) 332 [CHAP. 13 O THER DEVICES AND TECHNIQUES Input line numbers Dip pin numbers Product line first fuse numbers 0 2 4 6 8 10 12 11 7 14 16 13 18 Dip pin numbers I 17 19 vc> J 20 19 18 17 16 15 -4) 14 13 12 10 012141 135 I & 8 6 7 I 9 10 1 11 14 12 13 I 15 16 17 19 ( 6 ) Logic diagram Fig. 13-19 Continued. ( Courtesy of National Semiconductor Corporation) C HAP. 131 333 O T H E R DEVICES A N D TECHNIQUES -- PAL 10 H 8 A N C Programmable array logic family Number of array inputs Output type: H = Active High L = Active Low C = Complementary R = Registered X = Exclusive-OR registered P = Programmable polarity Number of outputs Speed/power version: No Symbol = 35 ns A = 25 ns A2 = 35 ns, half power Package Type: N = 20-pin plastic DIP J = 20-pin ceramic D IP V = 20-lead plastic chip carrier Temperature range: C = commercial (0 1.0 + 75°C) M = military ( - 5 5 ito -t 125°C) Fig. 13-20 D ccoding a P AL part number (Courtesy o f N utiond Semicwzductor Corporation) l etters indicate the speed/power version, package type, and temperature range. Note t hat both commercial and military versions of t he PALlOH8 a re available. SOLVED PROBLEMS 13.39 T he letters PLA stand for when dealing with programmable logic Icls. Solution: T he letters PLA stand for programmable logic array. PLA and PLD (programmable logic device) have become generic terms for these ICs. 13.40 T he letters PAL'"' s tand for . Solution: T he letters PAL" stand for programmable array logic. 13.41 Programmable logic devices are commonly used to implement logic circuits. (combinational, fuzzy) Solution: P LDs are commonly used to implement combinational logic circuits. 13.42 T he letters FPL,A s tand for when dealing with programmable logic ICs. Solution: The l etters FPLA stand for field-programmable logic array. 13.43 PLAs a nd FPLAs a re commonly programmed by the (manufacturer, user). Solution: P LAs and FPLAs are commonly programmed in the field by t he user. , P AL@ is a registered trademark of A dvanced Micro Devices, Inc. 334 O THER DEVICES AND TECHNIQUES 13.44 T he PLA is a close relative of t he [CHAP. 13 (PROM, RAM) IC. Solution: T he PLA is a close relative of the PROM (programmable read-only memory). 13.45 Programming of most PLDs consists of burning open selected titanium tungsten the device. within Solution: Programming one-time PLDs consists of burning open selected fuses within the device. Some programmable logic devices are erasable. 13.46 What is the fundamental difference between a PAL and an FPLA? Solution: A n FPLA (see Fig. 13-18) has both programmable AND and OR gates, while a PAL (see Fig. 13-19) contains only programmable AND gates. 13.47 PLAs are organized to implement AND-OR pattern of logic gates. (maxterm, minterm) Boolean expressions using an Solution: PLAs are organized to implement minterm (sum-of-products) Boolean expressions using an AND-OR p attern of logic gates. 13.48 R efer to Fig. 13-19. The PALlOH8 IC is a programmable logic device with (number) inputs and (number) outputs with a programmable (AND, OR) array. Solution: T he PALlOH8 is a PLD w ith 10 inputs and 8 outputs with a programmable AND array. 13.49 R efer to Fig. 13-20. Explain the meaning of a programmable logic device with a part number of PAL24LlOA from National Semiconductor. Solution: Decoding the part number PAL24LlOA is as follows: PAL = programmable array logic family 24 = 24 inputs L = active-LOW outputs 10 = 10 outputs A = propagation delay of 25 ns 13.50 Using a simple fuse map like the one- pictured in Fig. 13-16a, program this PLA to implement the minterm Boolean expression A - B + A . B = Y . Solution: See Fig. 13-21. CHAP. 131 OTHER DEVICES AND TECHNIQUES 335 Inputs A- B - I A 4 Fig. 13-21 PLA fuse map solution 13-8 MAGNITUDE COMPARATOR A magnitude comparator is a device that compares two binary numbers and outputs a response such as A is equal to B ( A = B ) , A is greater than B ( A > B ) , o r A is less than B ( A < B ) . O ne commercial unit is the 74HC8.5 4-bit magnitude cornparator. A D IP pin diagram for the 74HC85 magnitude comparator is drawn in Fig. 13-22a. The 74HC85 IC has eight data-comparing inputs. Two 4-bit binary numbers (A3A2AlAo and B3B2BIBo) are entered into the data-comparing inputs. The 74HC85 IC compares the two 4-bit numbers and generates one of three active-HIGH outputs. The three outputs are either A > Bout(pin 5 is HIGH) or A = Bout(pin 6 is HIGH) or A < Bout(pin 7 is HIGH). Under normal conditions, only one of the three outputs is HIGH for any one comparison. A detailed truth table for the 74HC85 4-bit magnitude comparator is reproduced in Fig. 13-22b. The 74HC85 is a high-speed CMOS magnitude comparator having a propagation delay of about 27 ns. This 74HC85 IC can operate on a wide range of voltages, from 2 to 6 V. This CMOS unit consumes little power but can drive up to 10 LS-TTL loads. A single 74HC85 IC compares two 4-bit numbers, but it can easily be expanded to handle 8-, 12-, 16-bit, or more numbers. The cascade inputs are commonly used when expanding the word size of the magnitude comparator. Typical cascading of 74HC85 ICs is shown in Fig. 13-23. Note that the cascade inputs of IC, are permanently connected as follows: ( A > B in)= LOW, ( A < Bin)= LOW, and ( A = B in)= H IGH. The cascade inputs of IC2 are fed directly from the A > Bout, A = Bout, and A < Bouto utputs of t he previous 74HC85 (ICl). The circuit in Fig. 13-23 compares the magnitude of two 8-bit binary numbers A7A6A5A4A3A2AlAO and B7B6B5B,B3B,B,Bo. In response to the comparison, IC2 drives one of t hree outputs HIGH. As a n example in Fig. 13-23, if A, to A , equals 11111111 and B , t o Bo equals 10101010, then the A > Bouto utput from IC2 is activated and driven HIGH. In this example, all other outputs ( A = Boutand A < Bout) emain deactivated at a LOW logic r level. A simple electronic game can be designed using the 74HC85 magnitude comparator. The game is a version of “guess the number.” In the classic computer version, a random number is generated within a range, and the player tries to guess the number. The computer responds with such responses [CHAP. 13 OTHER DEVICES AND TECHNIQUES 336 B 3 A < B A = B A > B A > B A = B A < B G ND data LvJ -L-J v input Cascade inputs outputs Top view ( a ) Pin diagram Comparing inputs A 37 A3 Cascading inputs A>B B3 > B3 A3 < B3 A3 = B3 A3=B3 A3 = B , A , = B3 A3 = B3 A , = B3 A , = B3 A3 = B3 A , = B3 A3 = B3 A , = B3 o utputs X X A ,>B2 A2 < B2 A, =B, A , = B, A , = B2 A2 = B2 A , =B, A , =B, A , =B, A2 = B2 A , = B2 X X X X Al>Bl AI < B l A , =B, A, =B, A , =B, A , =B, A , =B , A , = B, A, =B, X X X X X X A0 > B, A0 < B , A , = B, A,= B, A , = B, A, = B, A , =B, A<B A=B A>B A<B A=B X X X X X X X H L H L H L H L H L L L H L H L H L H L H L H L L H L L L L L L L L L L H L L X X X X X X X H L X H L X X X X L H X H L X X X X X X L L H L L ( b ) Truth table Fig. 13-22 74HC85 4-bit magnitude comparator (Courtesy of National Semiconductor Corporation) a s “Correct,” “Too high,” or “Too low.” The player can then guess again until reaching the correct number. The player with the fewest guesses wins the game. A logic diagram of the guess-the-number game is illustrated in Fig. 13-24. To play the game, first o press switch S W,, allowing clock pulses to reach the clock input ( D) f t he 4-bit binary counter (74HC393). When the switch is released, the counter will stop at some random binary count from 0000 t o 1111. T he random count is applied to the B data-compare inputs of t he 4-bit magnitude comparator. Next the player makes a guess (from 0000 t o l l l l , ) , which is applied to the A data-compare inputs of t he comparator. The 74HC85 IC compares the magnitudes of t he guess and CHAP. 131 OTHER DEVICES AND TECHNIQUES A > B in GND vcc GND 337 A 1 = B in A <Bin A0 AI A, A2 A2 A3 A3 B O B O Bl Bl 74HC85 magnitude comparator IC, Inputs A > Bout - B2 T WO 8-bit binary words B2 A =Bout - B3 B3 A <Bout - A4 A5 A, A2 74HC85 magnitude comparator A7 A3 B4 Bo B5 Bl A ’Bout A>B B2 A = Bout A=B B3 A < Bout A<B IC2 outputs B6 B? ~~ Fig. 13-23 C ascading 74HC85 m agnitude comparator random inputs and generates a HIGH output at one output, lighting one of the LEDs. If the guess is the same as the random number, the A = Bout o utput goes HIGH, causing the green LED t o light, and the player wins. If the guess is lower than the random number, the A < Bouto utput goes HIGH, causing the yellow LED t o light. If the guess is higher than the random number, the A > Bouto utput goes HIGH, causing the red LED t o light. The person’s next guess can then be adjusted based on the information gained from the “Too high” or “Too low” outputs of the guess-the-number game. In the guess-the-number game, the three outputs of the 74HC85 generate information that is used by the player to adjust the next guess. In like manner, magnitude comparators may be used in digital equipment to generate feedback t o circuitry that can make adjustments in the input. Feedback is a critical item in automated equipment. For instance, if a physical variable (such as temperature, speed, position, time, light intensity, pressure, weight, etc.) is converted into binary form by an A /D converter, this measurement can be sent to one of the data-compare inputs of a magnitude comparator. The other data-compare inputs are set by the operator at the proper level. The outputs of t he magnitude comparator will be used to activate circuitry to drive the physical variable toward the proper level. A simple example of how a magnitude comparator might be used in a control application is shown in Fig. 13-25. I n this example the temperature in an oven is to be controlled. The temperature sensor [CHAP. 13 OTHER DEVICES AND TECHNIQUES 338 Fig. 13-24 Electronic guess-the-numbergame temperature sensor L i . Analog signal t A /D converter A Magnitude comparator A Bout ’ B If Temperature controller A t Feedback-decrease temperature Fig. 13-25 Temperature control application with magnitude comparator generating feedback C HAP. 131 339 OTHER DEVICES AND TECHNIQUES sends an analog signal to the A /D converter which generates a proportional binary signal. The binary signal enters the B data-compare inputs of a magnitude comparator. The operator sets the A data-compare inputs at the proper temperature. If t he oven temperature is too low, the A > Bout o utput of t he magnitude comparator is activated with this signal fed back to the temperature control unit. This unit causes the temperature to be increased. I f t he oven temperature is too high, the A < B,,, o utput of t he comparator is activated and is fed back to the temperature control unit. The temperature control unit would cause the temperature to be decreased in the oven. SOLVED PROBLEMS 13.51 A (magnitude, voltage) comparator is a(n) (analog, digital) device that can compare two binary numbers and output a response such as A = B , A > B , o r A < B . Solution: A m agnitude comparator is a digital device that can compare two binary numbers and output a response such as A = B , A > B , o r A < B . (4-, 8-, 16-) bit binary numbers and output one of 13.52 A single 74HC85 IC will compare two t hree responses such as . , or A < B . Solution: A single 74HC85 IC will compare two 4-bit binary numbers and output one of t hree responses such as A = B , A > B , o r A < B . 13.53 What is t he purpose of t he cascading inputs on the 74HC85 IC shown in Fig. 13-22a? Solution: T he 74HC85 ICs can be cascaded (see Fig. 13-23) to make an 8-, 12-, or 16-bit magnitude comparator. I f not cascaded, the A = Bin i nput should be tied to V,, while the A > Bin a nd A < Bin cascade inputs should be grounded. 13.54 Refer to Fig. 13-23. I f t he inputs are A , to A , output will be activated? Solution: If A , t o A , with a HIGH. = 00110011 and B , t o B , = = 00110011 and B , t o B , = 11110000, which 11110000, then the A < Bout o utput of IC, will be activated 13.55 Refer to Fig. 13-24. T he 555 timer IC is wired as a(n) tor in this game circuit. (astable, monostable) multivibra- Solution: The 5 55 t imer IC in Fig. 13-24 is wired as an astable multivibrator generating a continuous string of clock pulses. 13.56 Refer to Fig. 13-24. If t he binary counter holds the number 0101, and your guess is lOOO,, t he (correct, too high, too low). (color) LED will light, indicating your guess is Solution: If t he binary counter holds the number 0101 and your guess is 1000, t he red LED will light, indicating your guess is too high. 340 O THER DEVJCES AND TECHNIQUES [CHAP. 13 13.57 R efer to Fig. 13-25. The magnitude comparator in this control application is used to generate digital (feedback, random) signals which cause the temperature controller to turn the oven heating element either on or off. Solution: T he magnitude comparator in Fig. 13-25 is used to generate digital feedback signals which cause the t emperature controller to turn t he oven heating clement either o n o r off. 13.58 R efer to Fig. 13-25. I f t he preset temperature setting is 11110000, ( at i nput 14) a nd the (decrease, increase) temperatemperature signal is 110O111l2 (at input B ) , t hen the ture feedback line will be activated. Solution: If t he preset temperature setting is 11110000, a nd the tcmpcrature signal i s 11001111,, then thc i ncrease temperature feedback line will be activated. 13.59 R efer to Fig. 13-26. List the color of the output L ED t hat is lit for e ach time period ( t l to t s ) . 0 1 Fig. 13-26 M agnitude comparator pulse-train problem Solution: t ime t ime t ime t ime time The color of the output LED that is lit for each time period is as follows: period t , =: yellow LED l it period t , = g reen LED l it period t , = r ed LED l it period t , = yellow LED lit period t , = g reen LED l it , CHAP. 131 O THER DEVICES AND TECHNIQUES 341 13-9 SCHMITT TRIGGER DEVICES Waveforms with fast rise times and fast fall times are preferred in digital circuits. A s quare wave is an example of a good digital signal because it has almost vertical LOW-to-HIGH and HIGH-to-LOW edges. A s quare wave is said to have fast rise and fall times. A waveform, such as the sine wave in Fig. 13-27, has a slow rise time and a slow fall time. Using a sine wave to drive a normal gate, counter, or other digital device will cause unreliable operation. In Fig. 13-27 a S chmitt trigger inverter is being used to “square up” the sine wave by forming a square wave at the output. The Schmitt trigger inverter is reshaping the waveform. Schmitt trigger devices are used for “squaring up” waveforms. This process is sometimes called signal conditioning. Fig. 13-27 Schmitt trigger inverter used to “square up” waveform A voltage profile of a common 7404 inverter IC is compared with that of a 7414 Schmitt trigger inverter in Fig. 13-28. Of special interest is the switching threshold of the inverters. The switching Switching threshold (negative going) Fig. 13-28 Input switching thresholds 342 OTHER DEVICES AND TECHNIQUES [CHAP. 13 threshold is the input voltage at which the outputs of the digital device flip to their opposite state. In examining the input voltage profiles in Fig. 13-28, n ote that the switching threshold is always within the unshaded forbidden or undefined region of the device. In Fig. 13-28a you will notice that the switching threshold for the standard 7404 inverter is 1.2 V. F or the 7404 inverter, as voltage increases from 0 to about 1.1 V, t he input is considered to be LOW (output of inverter would be HIGH). As t he voltage increases closer to the threshold voltage of 1.2 V, t he output would flip to the opposite state (output of inverter to LOW). On the standard 7404 inverter, as voltage decreases from near 5 to 1.3 V, t he input is considered to be HIGH (output of inverter would remain LOW). As t he voltage continues to decrease to the threshold voltage of 1.2 V, t he output would flip to the opposite state (output of inverter to HIGH). The important idea on the standard 7404 inverter is that the threshold voltage is the same for both L-to-H and H-to-L transitions of t he input. This can cause trouble when the input signal has a slow rise time because several oscillations (H-L-H or L-H-L) can occur at the output when the threshold voltage is crossed. In Fig. 13-28b you will notice that the switching threshold for the Schmitt trigger 7414 inverter is different for the L-to-H and H-to-L transitions of the input. For the Schmitt trigger 7414 inverter, as the voltage increases from 0 to 1.6 V, t he input is considered LOW (output of inverter would be HIGH). As t he voltage increases to the threshold voltage of 1.7 V, t he output would flip to the opposite state (output of inverter would go LOW). On the Schmitt trigger 7414 inverter, as voltage decreases from near 5 t o 1 V, t he input is considered to be H IGH (output remains LOW). As t he voltage continues to decrease to the threshold voltage of 0.9 V , t he output would flip to the opposite state (output of inverter to HIGH). This difference in threshold voltage for a positive-going (L-to-H) and a negative-going (H-to-L) input signal is called hysteresis. Each input of Schmitt trigger devices has hysteresis which increases noise immunity and transforms a slowly changing input signal to a fast changing output. Note in Fig. 13-28 t hat the hysteresis s j ~ ~ 6 is lplaced in the center of t he logic symbol for those 0 digital devices that have Schmitt trigger inputs. The profiles of the output voltages are the same from both the standard 7404 and Schmitt trigger 7414 inverters. Schmitt trigger inputs are also available in CMOS. Some of these include the 4093 Q uad 2-input N AND gate Schmitt trigger, 40106 Hex Schmitt trigger inverter, and 74HC14 Hex inverting Schmitt trigger ICs. O ther T T L devices with Schmitt trigger inputs include the 74LS132 (74132) and 74LS13 NAND gate ICs. SOLVED PROBLEMS 13.60 R efer to Fig. 13-29. T he hysteresis sign in the middle of the inverter logic symbol indicates that this device has inputs. Solution: T he hysteresis sign in the inverter logic symbol indicates that this device has Schmitt trigger inputs. Fig. 13-29 S ample problem 13.61 R efer to Fig. 13-29. T he waveform on the output side of the Schmitt trigger inverter would be a (sign, square) wave. Solution: T he waveform on t he output side of the Schmitt trigger inverter would be a square wave. 343 O THER DEVICES AND TECHNIQUES CHAP. 131 (conditioner, 13.62 T he Schmitt trigger inverter in Fig. 13-29 is being used as a signal multiplexer) in this circuit. Solution: T he Schmitt trigger inverter is being used as a signal conditioner in this circuit. It “squares up” the triangular waveform to form a square wave. 13.63 W hat is hysteresis when dealing with a Schmitt trigger digital device? Solution: See Fig. 13-28b. Hysteresis is the input characteristic of a Schmitt trigger device that sets the switching threshold higher for an L-to-H input (about 1.7 V on the 7414 inverter) and lower for an H-to-L input (about 0.9 V on the 7414 inverter). This greatly improves its noise immunity and its ability to “square up” input signals w ith slow rise and fall times. Supplementary Problems 13.64 The 74150 IC is described by the manufacturer as a 16-input Ans. data-selector/multiplexer - ,/ . 13.65 T he 74150 IC can be used for changing ( a ) (parallel, serial) input data to ( b ) (parallel, serial) output data. The 74150 IC can also be used for solving -___ (combinational, sequential) logic (c) problems. Ans. ( a ) parallel ( b ) serial ( c ) combinational 13.66 Draw a block diagram of a 74150 data seiector being used to solve the logic problem described by the Boolean expression X BcD + X BCD + CD + ABCD + X BCD = Y . Ans. See Fig. 13-30. Data inputs 0- ABCB 0 I 1 0- XBCE 16-input data selector 3 14 - 0 00- XHCD 5 6 7 8 9 1 0 11 12 13 1 00- ABED I 0 0- ABCD 11 -4 00 (74150) 15 I Strobe ABCDl select Fig. 13-30 Combinational logic problem solved by using a 74150 data selector 344 [CHAP. 13 O THER DEVICES AND TECHNIQUES 13.67 Refer to Fig. 13-5. T he letters MUX on t he counter block diagram stand for Ans. multiplexer 13.68 R efer to Fig. 13-5. When the MUX clock signal is LOW, the (left, right) seven-segment LED display. Ans. Is, right 13.69 To reduce power consumption, Ans. L ED (light-emitting diode) . ( Is, 10s) count is lit on the (LCD, LED) displays are most often multiplexed. 13.70 R efer to Fig. 13-5. If the MUX clock frequency were reduced to 1 Hz, what would happen? Register to View Answerhe displays would flash on and off. The eye would see the multiplexing action. 13.71 R efer to Fig. 13-6. A display. Ans. H IGH ( HIGH, LOW) at the anode terminal would activate the seven-segment . 13.72 A demultiplexer reverses the action of a(n) Ans. multiplexer 13.73 Refer to the demultiplexer at the right in Fig. 13-7. If the data-select inputs are C = 1, B = 1, and A = 0, then output (number) is selected and a HIGH will appear at that output. Ans. 6 or 110, 13.74 Demultiplexers are also called distributors or . Register to View Answerata distributors, decoders 13.75 Refer to Fig. 13-8. Which output of the 74LS154 D EMUX is activated if G 1 and G 2 a re both LOW and Ans. output 12 or 1100, the data-select inputs are D = 1, C = 1, B = 0, and A = 0. 13.76 Refer to Fig. 13-9a. When the decimal 7 key is pressed and released, what will a ppear on the seven-segment output display? Ans. nothing (There is n o latch to hold the 7 a t the inputs of the decoder.) 13.77 T he 7475 is a TTL 4-bit IC. Ans. transparent latch 13.78 Microprocessor-based systems transfer data back and forth on a bidirectional parallel path called a . Register to View Answerata bus 13.79 A two-way buffer that will pass data to and from a data bus and serves to isolate a device from the bus is . Ans. bus transceiver or peripheral interface adapter (PIA) called a(n) 13.80 If the outputs of a three-state buffer are in their (high-impedance, transmit) state, they will float to whatever logic levels exist o n the data bus. Ans. high-impedance or high-Z 13.81 Refer to Fig. 13-11. T he interfaces between the microprocessor and bidirectional buffers sometimes called bus transceivers. Ans. RAM 13.82 T he 74125 three-state buffer will Ans. pass data through 13.83 (keyboard, RAM) are (block data, pass data through) when its control input is LOW. (Parallel, Serial) data transmission is transferring data one bit at a time over a single line. Ans. Serial 13.84 Refer to Fig. 13-14b. Device 1 must be a Ans. parallel-in serial-out 13.85 T he abbreviation UART stands for -in . Ans. -out device. universal asynchronous receiver-transmitter 13.86 Refer to Fig. 13-31. Which part of the figure illustrates the idea of a serial-in parallel-out register? Ans. part b CHAP. 131 OTHER DEVICES AND TECHNIQUES 345 Fig. 13-31 Types of registers 13.87 Refer to Fig. 13-31. Which part of the figure illustrates the idea of a parallel-in serial-out register? Ans. p art c 13.88 A data bus, such as that used within a microcomputer, forms a bidirectional path for transmitting Ans. parallel (parallel, serial) data. 13.89 Refer to Fig. 13-11. All devices interfaced with a data bus must use buffers having Ans. three-state totem-pole) outputs. 13.90 T he letters PLD stand for Ans. programmable logic device when dealing with programmable logic. 13.91 Refer to Fig. 13-15a. This PLA would be Ans. programmed fuses. (activated, programmed) by burning open selected 13.92 Refer to Fig. 13-17. An abbreviated notation system, sometimes called a was used to document the programming of this PLA. Ans. fuse 13.93 Refer to Fig. 13-18. This is a fuse map for a Ans. FPLA (field-programmable logic array) (fuse, Karnaugh) map, (FPLA, PAL). 13.94 Refer to Fig. 13-20. A programmable logic device with a part number of PAL16L8 has inputs, (number) outputs. The outputs are active (HIGH, LOW) pins. Ans. 16, 8, LOW 13.95 T he 74HC85 is a 4-bit (three-state, comparator IC. (number) Ans. magnitude 13.96 Refer to Fig. 13-26. Which color LED is lit during time period t,? Ans. red (The output A > Bout goes HIGH.) 13.97 Refer to Fig. 13-26. During time period t , , the goes HIGH. Ans. green, A = Bout (color) LED is lit because the output 13.98 When 74HC85 ICs are connected together to form 8-, 12-, 16-bit magnitude comparators, it is said that Ans. cascaded (See Fig. 13-23.) they are (cascaded, multiplied). 346 [CHAP. 13 O THER DEVICES AND TECHNIQUES 13.99 R efer to Fig. 13-24. If the 74HC393 c ounter stops at 1101, a nd the player’s guess is O lll,, t hen the (color) LED will light, which means the guess is (correct, too high, too low). Ans. yellow, too low 13.100 R efer to Fig. 13-25. If the preset temperature setting is 00011000, (at input A ) a nd the temperature (decrease, increase) temperature signal from the oven is 00011011, ( at input B ) , t hen the feedback line is activated. Register to View Answerecrease 13.101 A (sine, square) wave is said to have fast rise and fall times. 13.102 T he switching their new state. Ans. s quare (threshold, time) is the input voltage at which the outputs of an inverter flip to Register to View Answerhreshold 13.103 E ach input of a Schmitt trigger device has (ac coupling, hysteresis) which increases noise immunity and transforms a slowly changing input signal to a fast-changing output. Ans. h ysteresis 13.104 Schmitt trigger devices are commonly used for signal Register to View Answeronditioning (conditioning, multiplexing). Index Access time, 284, 286, 307 ACIA, 325-326 Active HIGH, 126-127, 164, 208, 248 Active LOW, 35, 125-127, 145, 148, 164, 204-205, 263, 273 A/D converter, 116, 131-136, 138, 338-339 Adder/subtractor, 190- 191, 193- 194, 196- 197 Address, 287 Address bus, 283 Alphanumeric codes, 24-27 Analog-to-digital converter (see A /D converter) AND gate, 29-31, 40-41, 43-44, 46, 55-56, 58, 326-335 A ND-OR gate pattern, 36-39, 44-47, 58-60, 66, 69-71, 77-99, 326, 334 Anode, 147, 158-159, 161, 168 ASCII, 24-27, 324-326 Astable multivibrator (clock), 133-134, 139, 154-158, 204, 220-224, 229, 313-315, 338-339 Asynchronous, 206, 210, 215-216, 227, 232, 263, 265-266, 273 Bistable multivibrator (flip-flop), 204, 220-221, 223, 229 Bit (binary digit), 1, 4, 14 Boolean algebra ( see Laws of Boolean algebra) Boolean expressions: for AND function, 28-30 for AND-OR gate pattern, 36-39 for NAND function, 48-50, 63 for NOR function, 50-51, 63 for NOT function, 34-36 for OR-AND gate pattern, 72-75 for OR function, 32-33 for XNOR function, 54-55, 65 for XOR function, 52-54, 64 from truth table (minterm), 37-39, 69-71 from truth table (maxterm), 72-74 simplification of, 82-103 Broadside loading, 269-270, 277 Buffer memory, 319 Buffer, three-state, 320-324, 344 Bulk storage (memory), 300-305 Bus transceivers, 321, 344 Buzzer, 129, 131 Byte, 283 Base 2 numbers (see Binary numbers) Base 8 numbers ( see Octal numbers) Base 10 numbers (see Decimal number system) Base 16 numbers ( see Hexadecimal numbers) Baud rate, 325 BCD ( see Binary-coded-decimal) BCDIC, 25 BCD-to-binary conversion, 16-17, 19, 26 BCD-to-decimal conversion, 16-17, 19, 26, 140-143 BCD-to-decimal decoder/driver, 143-146 BCD-to-seven-segment code, 147-152, 155-158 BCD-to-seven-segment decoder/driver, 147-152, 252-253 BCD-to-XS3 conversion, 20-21, 23 Binaries, 204 Binary addition, 170-174, 184-188, 194, 198-203 Binary-coded-decimal codes: 4221 BCD code, 18-20, 26 5421 BCD code, 18-20, 26 8421 BCD code, 16-20, 26 Binary numbers, 1, 4-6, 14, 16 Binary subtraction, 175-180, 188-192, 199-201 Binary-to-BCD conversion, 18-19, 26 Binary-to-decimal conversion, 1-3, 5, 12, 14 Binary-to-Gray-code conversion, 21-23, 27, 287-288, 290-291 Binary-to-hexadecimal conversion, 8, 10, 14 Bipolar technology, 104 BISYNC, 325 Calculator, 116, 140, 164 Cathode, 14.7, 158-164 Clamp diode, 130-131 Clock ( see Astable multivibrator) Clock characteristics, 222 Clock cycle time, 222-224 Clocked RS flip-flop, 206-21 1, 227-228 CMOS, 42, 105-109, 114-118, 137 CMOS integrated circuits: ADC0804 8-bit A/D converter IC, 133-136, 139 2732 32K EPROM IC, 295, 299 4002 4-input NOR gate IC, 61, 117 4012 4-input NAND gate IC, 61 4014 Shift register IC, 273 4024 7-stage binary counter IC, 115 4028 BCLI-to-decimal decoder IC, 146 4030 XOR gate IC, 61 4031 64-stage shift register IC, 273 4034 8-bit shift register IC, 273 4035 4-bit shift register IC, 273 4049 Inverted buffer IC, 121-122, 222 4050 Noninverted buffer IC, 121-122 4093 Schrnitt trigger NAND gate IC, 342 40106 Schmitt trigger inverter, 342 40175 D flip-flop IC, 2124 40192 Decade counter IC, 116 347 348 CMOS integrated circuits: ( continued) 4511 BCD-to-seven segment decoder IC, 150, 161- 164, 168- 169 4543 BCD-to-seven segment decoder IC, 150, 156-158 4724 8-bit latch IC, 214 74COO NAND gate IC, 61 74C02 NOR gate IC, 61, 107 74C04 Hex inverter IC, 42 74C08 AND gate IC, 42, 47, 137 74C30 8-input NAND gate, 61 74C32 OR gate IC, 42 74C42 BCD-to-decimal decoder IC, 146 74C48 BCD-to-seven-segment decoder IC, 150 74C76 J K flip-flop IC, 214 74C86 XOR gate IC, 61 74C192 Decade counter IC, 115-116 74HC04 Hex inverter IC, 106 74HC14 Schmitt trigger inverter IC, 342 74HC32 2-input OR gate IC, 116 74HC42 BCD-to-decimal decoder IC, 146 74HC85 Magnitude comparator IC, 335-340, 345 74HC147 Encoder IC, 142 74HC193 4-bit up/down counter IC, 246-251, 258- 259 74HC393 4-bit counter IC, 245-249,258,338-339, 345-346 74HC4511 BCD-to-seven-segment decoder IC, 150 74HC4543 BCD-to-seven-segment decoder IC, 150, 156-158, 201 74HCT34 Noninverting IC, 119-121 STK10C68 NVSRAM IC, 296-300, 308 Combinational logic circuits, 69, 102, 170, 204, 227, 255, 331 Combinational logic solutions (data selectors), 311-313, 343 Combinational logic solutions (PLAs), 326-335 Complement, 35-36 Complementary metal-oxide semiconductor ( see CMOS) Control grid (VF tube), 158-163, 168 Conversion time (A/D converter), 134, 136 Count accumulators, 25 1-253 Counters: asynchronous, 232 BCD up/down, 241 -244 cascading, 241-242, 244 characteristics of, 230 decade, 237-239, 241-244, 248-251 down (3-bit), 238-240 down (4-bit), 256 4-bit up/down, 247-251 5-bit ripple, 254-255 as frequency divider, 232, 251-254, 259 mod-2, 253 mod-3, 253 I NDEX Counters: ( continued) mod-5, 254, 257 mod-6, 236-237, 239, 249-254 mod-8, 232-233, 240, 258 mod-9, 240 mod-10, 237-238, 241-244, 25 1-253 mod-12, 256 mod-16, 230-232, 242-25 1, 255 parallel, 234-236, 255 ripple, 230-233, 236-240, 242-249, 254-255 synchronous, 235-236, 246-251, 255 CPU (central processing unit), 140 Crystal-controlled oscillator, 222-224, 229 D flip-flop, 209-212, 228, 261-263, 272 D/A converter, 116, 132-133, 135, 138 Data bus, 135, 283, 286, 320-321, 323, 326, 344-345 Data distributor ( see Demultiplexer) Data flip-flop ( see D flip-flop) Data selector, 69, 102, 309-313, 343 Data transmission, 324-326 Decimal number system, 1, 4, 14 Decimal-to-BCD conversion, 16- 17, 19 Decimal-to-BCD encoder, 140-143 Decimal-to-binary conversion, 3-6, 14 Decimal-to-Gray code converter, 287-288, 306 Decimal-to-hexadecimal conversion, 7-9, 14 Decimal-to-2s complement conversion, 10- 11, 13, 15 Decimal-to-XS3 conversion, 20-21, 23, 27 Decoder, 16,26,69,102,140,143-153,164,287-288, 316-319, 330, 344 Dedicated computer, 290 Delay flip-flop ( see D flip-flop) DeMorgan’s theorems ( see Laws of Boolean algebra) Digital clock, 232, 251-254 Digital counter ( see Counters) Digital-to-analog converter ( see D /A converter) Digital voltmeter, 134, 138 Diode ROM, 287-288, 290-292, 294-295. 306 DIP ( see Dual-in-line package) Display multiplexing, 313-316 Double inversion, 34-35, 59, 76-77 DRAM ( see Dynamic RAM) DTL (diode-transistor logic), 104 Dual-in-line package, 40, 221, 223, 293 Duty cycle, 152 Dynamic RAM, 284 Dynamic-scattering LCD, 153 EBCDIC, 24-27 ECL (emitter-coupled logic), 104 Edge-triggering, 21 1-212, 214, 217, 219, 227-228, 248, 262, 270, 273 EEPROM (electrically-erasable PROM), 293, 295, 307 349 I NDEX E PROM (erasable PROM), 293, 295, 298-299, 307 Encoder, 16, 26, 140-143, 164 Excess-3 code (see XS.3 code) Exclusive-NOR gate, 54-55, 65 Exclusive-OR gate, 52-53, 64, 68, 190-191, 193, 196- 197, 202 Extended Binary-Coded Decimal Interchange Code (see EBCDIC) Fan-out, 107-108, 137 Feedback, 265, 337-339 Field-effect LCD (see Liquid-crystal display) Field Programmable ROM (see P ROM) Filament (VF display), 159-164, 168 Firmware, 290, 307 Flash PROM, 293-294, 308 Floating inputs, 112-1 14, 117-118, 141, 145, 150, 242 Floppy disk, 279, 300--308 Fluorescent display (see Vacuum fluorescent display) FPLA (field programmable logic array), 331, 333, 345 Free-running multivibrator (see Astable mu1tivibrator) Full adder, 171-174, 180, 182-188, 193, 198-199 Full subtractor, 176- 179, 181- 182, 199-201. Fuse map, 328-329, 334-335 Fusible links, 326-335 Gallium arsenide (GaAs), 290, 307 Gate inputs and outputs inverted, 55-58 Gray code, 20-24, 27, 287-288, 291 Gray-code-to-binary conversion, 22, 24, 27 Guess-the-number game, 335-338, 345-346 Half adder, 170- 174, 180, 182- 183, 198- 1 99 Half subtractor, 175-179, 181, 200-201 Handling precautions (CMOS), 117-1 18 Handling precautions (floppy disks), 302, 305 Hard disk, 279, 303-308 Heater (see Filament) Hexadecimal numbers, 1 , 6-10, 14 Hexadecimal-to-binary conversion, 8-10, 14 Hexadecimal-to-decimal conversion, 6-7, 9 Hollerith code, 25-26 HTL (high-threshold logic), 105-106 Hysteresis, 342, 346 IC (see Integrated circuit) IC markings, 111- 114 IGFET, 104 IIL (integrated-injection logic), 105 Integrated circuit, 39 Interfacing,: A/D conversion, 131-136 D/A conversion, 131-136 ICs with switches, 125-129 ICs with output devices, 129-131 Printers, 325 TTL ancl CMOS ICs, 118-125 Interrupt (microprocessor), 134, 136 Invert bubble, 35, 48, 51 Inverter (see N OT gate) JK flip-flop, 212-219, 228-232, 236-239, 264-268 Karnaugh mapping: effect of don’t cares on, 91-93, 101-102 1oop i n g variations , 82-88 using with maxterms, 88-91, 98, 100-101 2-variable minterm, 82-83 3-variable minterm, 83-85 4-variable minterm, 85-88, 91-93, 97-98 5-variable minterm, 93-96, 102-103 K-map (see Karnaugh mapping) Latch, 128, 204-205, 319-324 Laws of Boolean algebra: AND function, 30 DeMorgan’s theorems, 75-77, 97-98 NOT function, 35 OR function, 33 LCC (leadlcss chip carrier), 284 LCD display decoders/drivers, 116 Level triggering, 206, 209, 211 Light-emitting diode (LED), 122-125, 138, 150, 166, 313-315, 338, 344 Liquid-cryslal display (LCD), 147, 152-158, 166-167 Logical HIGH, 105-106, 108, 136, 341 Logical LOW, 105-106, 108, 136, 341 Logic symbols: AND gate, 28-31, 43-44 NAND gate, 49-50, 63, 75 NAND gate (alternate), 55-56, 75, 77-79 NOR gate, 50-51, 63, 75, 79-82 NOR gate (alternate), 55-56, 75 NOT gate, 34-35 NOT gate (alternative), 34-35 O R gate, 32-34, 43-44 Schmitt trigger inverter, 342 XNOR gate, 54-55, 65 XOR gatc, 52-54, 64, 155-156, 167 LSB (least significant bit), 1 LSI (large scale integration), 104-105, 116 Magnetic bulk storage, 279, 300-305 Magneto-optical disk (see Rewritable magneto-op tical disk) 350 Magnitude comparator, 335-340, 345 Mask-programmable ROM, 287, 289-291, 293, 307 Master-slave J K flip-flop, 214, 217-219, 229 Maxterm Boolean expression, 72-75, 88-91, 96, 98, 100- 101 Memory, 204, 230, 260, 279-308 Memory cell, 205 Memory size, 283-284, 286, 290-291, 306-307 Microcontroller, 116 Microprocessor, 116, 193, 320-321 , 323 Microprocessor-based system, 10, 136, 222, 283, 290, 320-321, 344 Microprocessor register, 10-12 Minterm Boolean expression, 69-71, 82-88,91-102, 311, 326-331 Military grade IC, 111, 113 Modem, 116, 325-326 Mode of operation/truth table: Clocked RS flip-flop, 207 D flip-flop, 210 JK flip-flop, 213-214 RS flip-flop, 205 7475 4-bit latch IC, 320 7493 4-bit counter IC, 243 74125 three-state buffer, 322 74194 shift register, 269 74F189 RAM, 281 74HC85 magnitude comparator, 336 74HC154 demultiplexer, 317 74HC164 shift register, 272 74HC193 up/down counter, 247 Modulus of counter, 230 Monostable multivibrator, 204, 220-221, 223-226, 229 MOSFET, 114, 117 MOS ICs: 2114 Static RAM, 283-286 MOS technology, 104-105, 114 Motor (electric), 130-131 MSB (most significant bit), 1 MSI (medium-scale integration), 104- 105, 116- 117, 136 Multiplexer, 309-313, 343-344 Multiplexing (display), 160, 168, 344 MUX ( see multiplexer) NAND gate, 48-50, 55-64, 66-68,77-79, 110, 205-207 NAND logic, 58-60,63, 66-67, 77-79 NAND-NAND gate pattern, 58-60, 66-67, 77-79, 99 Negate, 35-36 Nematic fluid (LCD), 152, 154, 167 NMOS ICS, 105, 121, 284, 289-290 Noise immunity of IC, 106, 109, 114, 118, 342 I NDEX Nondestructive read, 280 Nonvolatile memory, 279-280, 287, 290, 296, 306 Nonvolatile RAM ( see NVRAM) Nonweighted binary codes, 20-24 NOR gate, 50-52, 55-56, 68 NOR logic, 79-82 NOR-NOR gate pattern, 79-82, 99 NOT gate, 34-36,41-42, 55-58 NOVRAM ( see NVRAM) NVRAM, 279, 296-300, 306, 308 NVSRAM ( see NVRAM) Octal numbers, 1, 14 1s complement, 189, 191-192 One-shot multivibrator ( see monostable mu1tivibrator) Op amp ( see Operational amplifier) Open-collector TTL outputs, 111, 113, 121- 122, 124, 127-128 Operational amplifier, 133, 135, 138 Optical disk, 303-305 OR-AND gate pattern, 73-75, 79-82, 96-97, 99 OR gate, 31-34,41-46, 55-57, 324-325 Oscillator, 222-223 PAL ( see PLA) Parallel adder, 180-188, 193-198, 200-203 Parallel data transmission, 324-326, 345 Parallel subtractor, 180- 183, 188-198, 200-202 Parity bit, 324 PIA (peripheral interface adapter), 344 PLA (programmable logic arrays), 69, 102, 326-335, 345 Plate ( VF display), 158-163, 168 PLCC (plastic leaded chip carrier), 290 PLD ( see PLA) PMOS ICs, 105, 290 Power consumption, 107-108, 113-114, 137 Product-of-sums ( see Maxterm Boolean expression) PROM (programmable read-only memory), 69, 102, 116, 293-300, 307, 326-334 PROM burner, 293, 296, 307 Propagation delay (speed of IC), 106, 108, 113, 115-116, 118, 137, 237, 239, 318 Pull-down resistor, 126-128 Pull-up resistor, 111, 113, 120, 124, 138 Pulse triggering, 213-215, 217-219, 264 Radix, 1 RAM (random-access memory), 116, 279-286, 306 Read-only memory ( see R OM) Read/write memory, 280, 307 Recirculate, 264, 268, 276 Register ( see shift register) I NDEX Relay, 130-131, 138 Resolution: of A/D converter, 134, 136, 138 of D/A converter, 133 Rewritable magneto-optical disk, 304-305, 308 Ring counter, 266 ROM (read-only memory), 69, 102, 279-280, 284, 286-293, 306 RS flip-flop, 138, 204-206, 227 RS latch (see RS flip-flop) RTL (resistor-transistor logic), 104 Schottky diode, 110 Scratch-pad memory, 210 SDLC, 325 Sector, 301-302, 305 Selectric code, 25 Sequential logic circuits, 204, 213, 230, 232, 255, 261, 331 Serial adder, 180 Serial data transmission, 324-326, 344 Serial load (see shift register) Seven-segment displays: fluorescent (VF), 147, 158-164, 168 gas-discharge, 147 incandescent, 147 light-emitting diode (LED), 147-152 liquid-crystal (LCD), 147, 152-158, 167 segment identification, 147-148, 156-157, 162 Shift registers: 3-bit parallel-load shift-right, 267-268, 275-276 3-bit serial-load shift-right, 261-264, 275 4-bit serial-load shift-right, 261-264 5-bit serial-load shift-right, 275 8-bit serial-in parallel-out, 271-274 characteristics of, 260, 277 parallel-load recirculating shift-right, 264-266 types, 260 universal, 268 Sign bit, 10-13, 203 Signed numbers (adding and subtracting), 193-198, 203 Sinking current, 107, 109-110, 150 Software, 290 Speed of IC ( see propagation delay) Solenoid, 130- 131 Sourcing current, 107, 109-110 SRAM (see static RAM) SSI (small-scale integration), 104-105, 116-117 Static RAM, 283, 286, 296-300, 306-307 Subtraction using adders, 184-188 Successive-approximation A/D converter, 134, 139 Sum-of-products (see Minterm Boolean expression) Summing amplifier, 132-133, 135 Switch bounce, 126-127, 129, 138 351 Switching threshold, 341-343, 346 Synchronous, 206, 208, 210, 215, 227, 235-236, 255, 275 Temperature control system, 338-340, 346 T flip-flop (see toggle flip-flop) Thermionic emission, 159 Three-state output, 111, 135-136, 284, 286, 290, 345 Timer IC (5551, 220-224, 314, 338-339 Timing diagrams (see Waveform diagrams) Toggle, 213, 215, 230, 235, 245-246, 248 Toggle flip-flop, 213, 228 Tone generator, 116 Totem-pole output, 110-111, 113 Track, 301-302, 305 Triode vacuum tube, 158-159 Truth tables: AND function, 28-31 Comparator IC (see Mode of operation/truth table) Counter ICs ( see Mode of operation/truth table) Flip-flop ICs ( see Mode of o peration/truth table) NAND function, 48-49, 63 NOR function, 50-52, 63 NOT function, 35 OR function, 31-33, 41-43 RAM I C (see Mode of operation/truth table) XNOR function, 45-55, 65 XOR function, 52-54, 64 TTL (transistor-transistor logic), 40-41, 43 TTL integrated circuits: 5400 series, 111, 113 7400 NAND gate IC, 60-62, 67, 137 7403 NAND gate IC, 126, 128-129, 138 7404 Inverter IC, 41, 112, 314, 316, 341-342 7406/7416 Inverted buffer IC, 120-122 7407/7417 0. C. buffer IC, 120-122 7408 AND gate IC, 40-41, 111-112 7410 NAND gate IC, 60-61, 67 7414 Schmitt trigger inverter IC, 341-343 7432 OR gate IC, 41-43 7442 Decoder IC, 143-146, 287-288, 290 7443 Decoder IC, 165-166 7447A Decoder/driver IC, 148-152, 314 7474 D flip-flop IC, 210-212, 214 7475 4-bit latch IC, 214, 319-320, 322-323, 344 7476 JK flip-flop IC, 213-214, 216-220 7483 4-bit adder IC, 181-182, 184, 192, 196, 201 7493 4-bit counter IC, 242-245,251-254,257-258 7494 4-bit shift register IC, 270 7496 5-bit shift register IC, 270 74121 One-shot multivibrator IC, 225-226 74125 Three-state buffer IC, 320-324, 344 74147 Encoder IC, 141-143 74148 Encoder IC, 164-165 74150 Data-selector/multiplexer IC, 309-313,343 352 TTL integrated circuits: (continued) 74157 Multiplexer IC, 314-316 74164/74165 8-bit shift register ICs, 270 74192 Up/down counter IC, 241-244, 257, 314 74194 Universal shift register IC, 268-271, 276-277 74ALS76 JK flip-flop IC, 113-114 74F189 RAM IC, 281-286, 307 74LS154 Demultiplexer IC, 316-319, 344 74LS395 4-bit shift register IC, 270 TTL subfamilies: Advanced low-power Schottky, 110-112 Advanced Schottky, 106, 110-112 FAST, 281 Low-power, 109-113 Low-power Schottky, 107, 109, 113, 123, 318 Schottky, 109-112 Standard TTL, 107, 109-113 TTL voltage levels, 105-106, 108, 136 2s complement addition, 193-197, 203 2s complement numbers, 10-13, 15, 188-198, 203 2s complement-to-decimal conversion, 11-13, 15 2s complement subtraction, 193-198, 203 UART, 116, 325-326, 344 ULSI (ultra-large-scale integration), 104 Unipolar technology, 104 Universal gate, 49, 58-60, 77-82 I NDEX USART, 325-326 UV erasable PROM (see E PROM) Vacuum fluorescent display, 147, 158-164, 168-169 VLSI (very-large-scale integration), 104- 105, 116 Volatile memory, 279-280, 284, 296, 306 Waveform diagrams: defining terms, 217 for clocked RS flip-flop, 207 for decade counter, 242 for 4-bit parallel-load recirculating register, 265 for 4-bit serial-load shift-right register, 261 for 4-bit up/down counter, 247 for master-slave J K flip-flop, 218 for mod-6 ripple counter, 237 for mod-8 down counter, 238 for mod-8 parallel counter, 235 for mod-16 ripple counter, 231 for negative-edge-triggered flip-flop, 217 for positive-edge-triggered flip-flop, 217 Weighted binary codes, 16-20 Winchester (hard disk), 303, 307 Word (binary), 280, 283, 324 XNOR (see Exclusive-NOR gate) XOR (see Exclusive-OR gate) XS3 code, 20-21, 23, 26 XS3-to-decimal conversion, 21, 23, 27

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National Institute of Technology, Calicut - ECE - 209
2007 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This publication is protected by Copyright and written permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or tra
National Institute of Technology, Calicut - CS - 101
HACKING INTO COMPUTER SYSTEMSA Beginners GuideGuides of the Beginner's Series:So you want to be a harmless hacker?Hacking Windows 95!Hacking into Windows 95 (and a little bit of NT lore)!Hacking from Windows 3.x, 95 and NTHow to Get a *Good* Shell
National Institute of Technology, Calicut - CS - 101
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National Institute of Technology, Calicut - CS - 101
(WKLFDO +DFNLQJStudent Guide Copyright 2000 Internet Security Systems, Inc.All rights reserved.This product and related documentation are protected by copyright and distributionunder licensing restricting their use, copy, and distribution. No part of
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GOOGLEHACKS2ndnEditio ailrs GmCoveTMTips &amp; Tools for Smarter SearchingTara Calishain &amp; Rael DornfestWith a new foreword byCraig Silverstein, Director of Technology, Google,ch07.copy.11281 Page 354 Wednesday, December 15, 2004 1:07 PMHACK#84
National Institute of Technology, Calicut - CS - 101
STEAL THIS BOOKBy Abbie HoffmanDedicated to Jerry Lefcourt, Lawyer and BrotherLibrary of Congress number 72-157115 (stolen from Library of Congress)copyright 1971 PIRATE EDITIONSTABLE OF DISCONTENTSINTRODUCTIONAIDING AND ABETTINGSURVIVE!1. FREE F
National Institute of Technology, Calicut - CS - 101
How to hack Windows XP Admin Passwords the easy way by Estyle, Jaoibhand Azrael.-This hack will only work if the person that owns the machinehas no intelligence. This is how it works:When you or anyone installs Windows XP for the first time yourasked
National Institute of Technology, Calicut - CS - 101
www.GetPedia.comPARRT PA T PARTT PART PARTPART PARTPARRTRTPARPAIIART PART PTPAGaining Access and Securingthe Gateway67How to Build a Firewall . 3178SATAN and the Internet Inferno . 4299p1vPHCP/tr2IP Spoofing and Sniffing . 257K
National Institute of Technology, Calicut - CS - 101
Making a bootable Cracked Windows XP CDBy SilentIn Mirc efnet #WINXP &amp; #WINDOWSXP I was asked many times over how do you crackand make the cdrom autobooting with the crack inplace. Well this is a strait forwardthing to do when you know how. So my task
National Institute of Technology, Calicut - CS - 101
ProLib8 / Hacking Exposed: Network SecurityColor profile: Generic CMYK printer profileComposite Default screenSecrets and Solutions, Third Edition / McClure, Scambray &amp; Kurtz / 9381-6 / Chapter 1C HAPTER 1ingintrotpFo3P:\010Comp\Hacking\381-6\c
National Institute of Technology, Calicut - CS - 101
Hacking for Dummies(Access to other peoples systems made simple &amp; some extra database lore).IntroductionThe author is not responsible for any abuse of this information. It is intended for educational useonly. You may be quite shocked at how vulnerable
National Institute of Technology, Calicut - CS - 101
Download the coolest fonts for PC&amp; MAC at a -font [Click Here]Top 40 Wallpaper Websites on theWeb [Click Here]Latest Cell Phones reviewed plusvideo reviews [Click Here]Coolest Online Web Flash Games,Addictive &amp; Fun [Click Here]High resolution wall
National Institute of Technology, Calicut - CS - 101
Hacking GmailBen HammersleyHacking GmailHacking GmailBen HammersleyHacking GmailPublished byWiley Publishing, Inc.10475 Crosspoint BoulevardIndianapolis, IN 46256www.wiley.comCopyright 2006 by Wiley Publishing, Inc., Indianapolis, IndianaPubli
National Institute of Technology, Calicut - CS - 101
Download at WoWeBook.ComHacking: The Next GenerationDownload at WoWeBook.ComDownload at WoWeBook.ComHacking: The Next GenerationNitesh Dhanjani, Billy Rios, and Brett HardinBeijing Cambridge Farnham Kln Sebastopol Taipei TokyoDownload at WoWeBook.C
National Institute of Technology, Calicut - CS - 101
-Exploiting Cisco Systems(Even From Windows!;-) )Written by Cyvamp(with a few notes added by Raven)July 2000http:/blacksun.box.sk-Warning:DO NOT use this to damage cisco systems, or gain unauthorized access to systems.This tutorial is just someth
National Institute of Technology, Calicut - CS - 101
Hacking for Dummies(Access to other peoples systems made simple &amp; some extra database lore).IntroductionThe author is not responsible for any abuse of this information. It is intended for educational useonly. You may be quite shocked at how vulnerable
National Institute of Technology, Calicut - CS - 101
Full tutorial made by to Crack CD Protections: Full tutorial made for FOR #WAREZFRANCECREW, by FANATIKChapters:1). About, Programs needed etc.2). The easy protection.3). Finding the right file and the right error.4). Finding the right line number.5
National Institute of Technology, Calicut - CS - 101
How to hack Windows XP Admin Passwords the easy way by Estyle, Jaoibhand Azrael.-This hack will only work if the person that owns the machinehas no intelligence. This is how it works:When you or anyone installs Windows XP for the first time yourasked
National Institute of Technology, Calicut - CS - 101
Maximum Security: A Hacker's Guide toProtecting Your Internet Site andNetworkTable of Contents:IntroductionI Setting the StageChapter 1 - Why Did I Write This Book?Chapter 2 - How This Book Will Help YouChapter 3 - Hackers and CrackersChapter 4 -
National Institute of Technology, Calicut - CS - 101
SECURING IIS by BREAKING=by Mount Ararat Blossom9/15/2000mount_ararat_blossom@hotmail.com=01- AbstractI am not sure what you want to get out of this but basically this paperis intended on breaking merely IIS web servers especially versions 4.0 and
National Institute of Technology, Calicut - CS - 101
$%&amp;|#@*+++THE ULTIMATE BEGINNER'S GUIDE TO HACKING AND PHREAKING++++++BY+REVELATION++LOA-ASH++++++ Written: 08/4/96Volume: 1 ++*@#|
National Institute of Technology, Calicut - CS - 101
TMHACKERDICTIONARYBernadette Schell and Clemens MartinTMHACKERDICTIONARYBernadette Schell and Clemens MartinWebsters New World Hacker DictionaryPublished byWiley Publishing, Inc.10475 Crosspoint BoulevardIndianapolis, IN 46256www.wiley.comCo
National Institute of Technology, Calicut - CS - 101
/.oOTHE_\| /\ || |_| || - |''__\|\||_ / |/'presents||||__|\/||\_/||\_/|||''CreW Oo.DNS ID Hacking(and even more !)with colors &amp; in images ;)-[1]- DNS ID Hacking Presentationw00w00!Hi people you might be wondering
National Institute of Technology, Calicut - CS - 101
-EVERYTHING A HACKER NEEDS TO KNOW ABOUT GETTING BUSTED BY THE FEDS-Written By Agent Steal (From Federal Prison, 1997)Internet E-mail, agentsteal@usa.netContributions and editing by Minor Threat and Netta GilboaSpecial thanks to Evian S. SimThis arti
National Institute of Technology, Calicut - CS - 101
Thealt.2600/#Hack F.A.Q.Beta Revision .013A TNO Communications ProductionbyVoyagerwill@gnu.ai.mit.eduSysop ofHacker's Haven(303)343-4053Greets go out to:A-Flat, Al, Aleph1, Bluesman, Cavalier, Cruiser, Cybin, C-Curve,DeadKat, Disorder, Edison,
National Institute of Technology, Calicut - CS - 101
[-Stay anonymous on the web-].By MAx member of :MPD:(c) 1998 MAx [4d5044]Note.This tutorial will teach a average day user how to keep all hisEsentual info limited so attacks from Hackers cant be madeSHouth outs: Myth leader of MPD u rule dude,All mem
National Institute of Technology, Calicut - CS - 101
User's guide_Well, howdi folks. I guess you are all wondering who's this guy (me)that's trying to show you a bit of everything. ?Well, I ain't telling you anything of that.Copyright, and other stuff like this (below).Copyright and stuff._If you fe
National Institute of Technology, Calicut - CS - 101
Cable Modem IP Hijacking in Win95/98The purpose of this is to show you how bad cable modems security is and thateven with a win box you can take someone else's IP. You can hijack IP's usinga cable modem and it's very simple in any operating system. Jus
National Institute of Technology, Calicut - CS - 101
=CA-95:01CERT AdvisoryJanuary 23, 1995IP Spoofing Attacks and Hijacked Terminal Connections-The CERT Coordination Center has received reports of attacks in whichintruders create packets with spoofed source IP addresses. These attacksexploit applica
National Institute of Technology, Calicut - CS - 101
Author: van Hauser / THCI.INTRODUCTIONII.MENTALIII.BASICSIV.ADVANCEDV.UNDER SUSPECTVI.CAUGHTVII.PROGRAMSVIII.LAST WORDSI. INTRODUCTIONPlease excuse my poor english - I'm german so it's not my mother languageI'm writing in. Anyway if your englis
National Institute of Technology, Calicut - CS - 101
Cracking the Universal Product Codeby Count Nibble-Everyone encounters the UPC nowadays. You know, it's that set of black barsyou see on virtually every product whenever you go to the grocery store, tobuy a book or a magazine, or even to buy software
National Institute of Technology, Calicut - CS - 101
Newsgroups: comp.dcom.lans.ethernetFrom: barr@tramp.Colorado.EDU (BARR DOUG)Subject: Ethernet FAQOrganization: University of Colorado, BoulderDate: Tue, 5 Jan 1993 20:51:40 GMTThis has not been posted for a while, so I am taking the liberty ofpostin
National Institute of Technology, Calicut - CS - 101
From: ManifestationSubject: Security holes manifest themselves in (broadly) four ways.Date: 11.10.93( Please contribute by sending E-Mail to &lt;scott@santafe.edu&gt; . )[quoting from the comp.security.unix FAQ]Security holes manifest themselves in (broadl
National Institute of Technology, Calicut - CS - 101
Date:From:Subject:To:Wed, 12 Jul 1995 02:20:20 -0400*Hobbit* &lt;hobbit@avian.org&gt;The FTP Bounce AttackMultiple recipients of list BUGTRAQ &lt;BUGTRAQ@CRIMELAB.COM&gt;This discusses one of many possible uses of the &quot;FTP server bounce attack&quot;.The mechanism
National Institute of Technology, Calicut - CS - 101
020020The Phone Losers Of America PresentInformation Gathering On Anyone - RedBoxChiliPepper Written On March 20, 1993Last Revision on February 12, 1995 For Informational Cactuses Only. We're Not Responsible For Your Stupidity. 020020This file wil
National Institute of Technology, Calicut - CS - 101
+|The LOD/H Presents|++\A Novice's Guide to Hacking- 1989 edition/\=/\by/\The Mentor/\Legion of Doom/Legion of Hackers/\/\December, 1988/\Merry Christmas Everyone!/\+/*| The author hereby grants permission to reproduce, redi
National Institute of Technology, Calicut - CS - 101
Installing &amp; Hacking From Linux.All you people that thought you were good hackers, because you could fooldumb sysadmins, and do a bit of social engineering, or hack something byfollowing someones carefully prepared text file. Well you're about to getf
National Institute of Technology, Calicut - CS - 101
So you wanna be a HACKER huh? &lt;Bwahahaha!&gt; It's a state-of-MIND!.you can induce it - but only if you are willing to drive yourselfmad enough! Go read and practice until you have mastered at leastAssembly language and Intermediate Level Electronics! Wit
National Institute of Technology, Calicut - CS - 101
Hacking WebpagesThe Ultimate GuideBy Virtual Circuit and PsychoticWell Psychotic wrote one of the most helpful unix text files in cyberspace but with the maiGetting the Password File Through FTPOk well one of the easiest ways of getting superuser acc
National Institute of Technology, Calicut - CS - 101
INTERNET HOLES - ELIMINATING IP ADDRESS FORGERYCOPYRIGHT (C), 1996, MANAGEMENT ANALYTICS - ALL RIGHTS RESERVED_Series IntroductionThe Internet is now the world's most popular network and it is full ofpotential vulnerabilities. In this series of artic
National Institute of Technology, Calicut - CS - 101
Simple Active Attack Against TCPLaurent JoncherayMerit Network, Inc.4251 Plymouth Road, Suite CAnn Arbor, MI 48105, USAPhone: +1 (313) 936 2065Fax: +1 (313) 747 3185E-mail: lpj@merit.eduAbstractThis paper describes an active attack against the Tr
National Institute of Technology, Calicut - CS - 101
Understanding Microsoft Proxy Server 2.0By NeonSurgeRhino9 PublicationsPrefaceThis documented was not made for people who have been working with MicrosoftProxy Server since its beta (catapult) days. It is made for individuals whoare curious about the
National Institute of Technology, Calicut - CS - 101
-%-% % % % THE NEOPHYTE'S GUIDE TO HACKING % % = % % 1993 Edition % % Completed on 08/28/93 % % Modification 1.1 Done on 10/10/93 % % Modification 1.2 Done on 10/23/93 % % by % % &gt; Deicide &lt; % % % % &lt; &lt; &lt; &lt; &lt; &lt; The author of this file grants permission to
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Windows NT Deconstruction TaticsStep by Step NT Explotation Techniquesby vacuum of Rhino9 &amp; Technotronicvacuum@technotronic.comRevision 5 10/01/98Changes in Revision 5:Refined some NET.EXE examples.Included brief discussion of NetBus.Sambardisk /
National Institute of Technology, Calicut - CS - 101
Psychotic's Unix Bible Writen by Virtual Circuit**Psychotic's Unix Bible writen by Virtual Circuit.This document may not be changed in aA list of commands and a quick descriptionalias .awk .bdiff .bfs .cal .cat .cc .cd .chgrb .chmod .chown
National Institute of Technology, Calicut - CS - 101
* Data Kult *Lord LogicsShadow Walker-SMCRealm of Infinity(503)629-0814SMC Home* Kryptic Night *RaisingBounty HunterHellNacht Habicht with Unix -SMCKryptic NightThe Viking's Den(408)867-1224-SMCWestern Dist.Production # 3I- Introduction
National Institute of Technology, Calicut - CS - 101
$%&amp;|#@*+++THE ULTIMATE BEGINNER'S GUIDE TO HACKING AND PHREAKING++++++BY+REVELATION++LOA-ASH++++++ Written: 08/4/96Volume: 1 ++*@#|
National Institute of Technology, Calicut - CS - 101
Following is all the information that you need to understand the workings ofthe UNIX operating system (Berkley 4.2).Patched together by The WarOn the security side of UNIX:-On the Security of UNIX Dennis M. Ritchie Recently there has been much interes
National Institute of Technology, Calicut - CS - 101
_~____(_)(_)[xx]cDc communications, inc.[xx]\/presents.\/(` ')(` ')(U)(U)Gibe's UNIX COMMAND Bible~The latest file from the Cow's Information Series,Franken's UNIX Command Bible is suitable for the UNIXdilettante, as well as for th
National Institute of Technology, Calicut - CS - 101
Virus programming (basics) #1.-This section is dedicated to those who would like to write avirus, but don't have the knowledge to do so. First of all,writing a virus is no big deal. It is an easy project, but onewhich requires some basic programming s
National Institute of Technology, Calicut - CS - 101
Virus programming (not so basic) #2.-Infecting an .EXE is not much more difficult than infecting a.COM. To do so, you must learn about a structure known as the EXEheader. Once you've picked this up, it's not so difficult and itoffers many more options
National Institute of Technology, Calicut - CS - 101
Cracking the Windows 95 Screen Saver PasswordArticle Extracted from 2600 MagazineVolume 13 #4=Defeating the Windows 95 Screensaverby rdpzzaWhile many may consider this a trivial exercise, crackingthe password scheme for Win95 may be useful to some
National Institute of Technology, Calicut - CS - 101
An Introduction to3D Computer GraphicsExploring Photo-Realismwith MacRenderMan Malcolm A. KessonVersion 6.0 PDF 1995CONTENTS1 IntroductionInteractivity v scriptingIllusions and interfacesRenderManWhat is a script?Why use scripting?Whats the c
National Institute of Technology, Calicut - CS - 101
ContentsPREFACE1A Survey of ComputerGraphicsComputer-Aided DesignPresentation GraphicsComputer A rtEntertainmentEducation and TrainingVisualizationImage ProcessingGraphical User Interfaces2Overview of Graphicssystems2 -1VideoDisplayDevice
National Institute of Technology, Calicut - CS - 101
Trent Polack's OpenGL Game Programming TutorialsGame ProgrammingTutorial IndexThese tutorials will contain comprehensive coverage on Game Programming inOpenGL. These articles are going to assume some familiarty with OpenGL, andC/C+, but thats about i
National Institute of Technology, Calicut - CS - 101
The Artof Computer Game Designby Chris CrawfordPreface to the Electronic Version This text was originally composed by computer game designer Chris Crawford in 1982. When searching for literature on the nature of gaming and its relationship to narrative
National Institute of Technology, Calicut - CS - 101
The Ultimate Game Programming TutorialFIRST, IF YOU HAVE GOTTEN THIS FROM SOMEWHERE,IT REALLY DOESNT MATTER WHERE, VISIT THE BEST GAMEPROGRAMMING SITE:The Game Programming MegaSite: http:/gpmega.home.ml.orgIntroduction:This documents purpose is to t
National Institute of Technology, Calicut - CS - 101
Games+: Tile Based Games FAQPage 1 of 9GAMES+: GAMES &amp; GAME PROGRAMMINGClick Here to Return to Games+Tile Based Games FAQVersion 1.2by Greg TaylorIsometric GameProgramming withDirectX 7.0 w/CDTilefaq 1.2 Copyright 1995 Greg Taylor. All rights re
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Games+: Tile Graphics TechniquesPage 1 of 6GAMES+: GAMES &amp; GAME PROGRAMMINGClick Here to Return to Games+Tile Graphics Techniques 1.0by Jason McIntoshWhat's This Document (Not) About?Isometric GameProgramming withDirectX 7.0 w/CDI wrote a CRPG f
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0072313618 FM10/26/999:32 AMPage iTricks of theWindowsGame Programming Gurusfundamentals of 2D and 3D Game ProgrammingAndr Lamothe201 West 103rd Street, Indianapolis, Indiana 462900072313618 FM10/26/999:32 AMPage iiTricks of the Windows Game
National Institute of Technology, Calicut - CS - 101
Table of ContentsIntroductionDead or alive, youre coming with me.RobocopA long time ago, in a galaxy far, far, away, I wrote a book about game programming called Tricks ofthe Game Programming Gurus. For me, it was an opportunity to create something t