HW2Sol
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HW2Sol

Course Number: EE 3193, Spring 2011

College/University: NYU Poly

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EE3193/EL5473 Intro. to VLSI Homework Assignment 2 Solution 1. (Problem 2.1 in text) Consider an nMOS transistor in a 0.6 m process with W/L = 4/2 (i.e., 1.2/0.6 m). In this process, the gate oxide thickness is 100 and the mobility of electrons is 350 cm2/Vs. The threshold voltage is 0.7 V. Plot Ids for Vgs = 0, 1, 2, 3, 4, and 5 V. Cox 3.9 8.85 10 14 W (350) 100 10 8 L W W 120 A / V 2 L L...

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Intro. EE3193/EL5473 to VLSI Homework Assignment 2 Solution 1. (Problem 2.1 in text) Consider an nMOS transistor in a 0.6 m process with W/L = 4/2 (i.e., 1.2/0.6 m). In this process, the gate oxide thickness is 100 and the mobility of electrons is 350 cm2/Vs. The threshold voltage is 0.7 V. Plot Ids for Vgs = 0, 1, 2, 3, 4, and 5 V. Cox 3.9 8.85 10 14 W (350) 100 10 8 L W W 120 A / V 2 L L 2. (Problem 2.8 in text) Sometimes the substrate is connected to a voltage called the substrate bias to alter the threshold of the transistors. If the threshold of an nMOS transistor is to be raised, should a positive or negative substrate bias be used? The threshold is increased by applying a negative body voltage so Vbs > 0. 3. (Problem 2.14 in text) Peter Pitfall is offering to license to you his patented noninverting buffer circuit shown below. Graphically derive the transfer characteristics for this buffer. Assume n p = = and Vtn = |Vtp| = Vt. Why is it a bad circuit idea? Vin VDD VGSn Vin Vout Vt (essentially an nMOS pass transistor passing a 1) Vout VDD Vt Thus, there is a threshold drop on the output. If the output of this buffer dives another: Vin VDD Vt Vout VDD 2Vt From this, it can be seen that the VTC is linear with a threshold drop after each stage. This drop shows that the circuit is not a buffer at all as the output signal is always worse than the input. 4. Find the worst case Elmore parasitic delay for an n-input NAND gate. The output node has 3nC. Each internal node has nC. The resistance through each nMOS is R/n. Hence, the propagation delay is n 1 t pd R (3nC ) i 1 iR 1 (nC ) (n 2 5n) RC n 2 5. (a) Vout = 0V; (b) Vout = 1V; (c) Vout = 1.9V; (d) Vout = 1.9V For (a) and (b), Vin is the source and Vout is the drain For (c) and (d), Vin is the drain and Vout is the source Thus, NMOS pass transistors pass bad 1s

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