Digital Design with CPLD Applications & VHDL - Dueck
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Digital Design with CPLD Applications & VHDL - Dueck

Course Number: 1234 2134, Spring 2010

College/University: Whatcom Community College

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CHAPTER 1 Basic Principles of Digital Systems OUTLINE CHAPTER OBJECTIVES 1.1 Upon successful completion of this chapter, you will be able to: Describe some differences between analog and digital electronics. Understand the concept of HIGH and LOW logic levels. Explain the basic principles of a positional notation number system. Translate logic HIGHs and LOWs into binary numbers. Count in binary,...

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Principles CHAPTER 1 Basic of Digital Systems OUTLINE CHAPTER OBJECTIVES 1.1 Upon successful completion of this chapter, you will be able to: Describe some differences between analog and digital electronics. Understand the concept of HIGH and LOW logic levels. Explain the basic principles of a positional notation number system. Translate logic HIGHs and LOWs into binary numbers. Count in binary, decimal, or hexadecimal. Convert a number in binary, decimal, or hexadecimal to any of the other number bases. Calculate the fractional binary equivalent of any decimal number. Distinguish between the most signicant bit and least signicant bit of a binary number. Describe the difference between periodic, aperiodic, and pulse waveforms. Calculate the frequency, period, and duty cycle of a periodic digital waveform. Calculate the pulse width, rise time, and fall time of a digital pulse. 1.2 1.3 1.4 1.5 Digital Versus Analog Electronics Digital Logic Levels The Binary Number System Hexadecimal Numbers Digital Waveforms D igital electronics is the branch of electronics based on the combination and switching of voltages called logic levels. Any quantity in the outside world, such as temperature, pressure, or voltage, can be symbolized in a digital circuit by a group of logic voltages that, taken together, represent a binary number. I Each logic level corresponds to a digit in the binary (base 2) number system. The binary digits, or bits, 0 and 1, are sufcient to write any number, given enough places. The hexadecimal (base 16) number system is also important in digital systems. Since every combination of four binary digits can be uniquely represented as a hexadecimal digit, this system is often used as a compact way of writing binary information. Inputs and outputs in digital circuits are not always static. Often they vary with time. Time-varying digital waveforms can have three forms: 1. Periodic waveforms, which repeat a pattern of logic 1s and 0s 2. Aperiodic waveforms, which do not repeat 3. Pulse waveforms, which produce a momentary variation from a constant logic level 1 2 C H A P T E R 1 Basic Principles of Digital Systems 1.1 Digital Versus Analog Electronics KEY TERMS Continuous Smoothly connected. An unbroken series of consecutive values with no instantaneous changes. Discrete Separated into distinct segments or pieces. A series of discontinuous values. Analog A way of representing some physical quantity, such as temperature or velocity, by a proportional continuous voltage or current. An analog voltage or current can have any value within a dened range. Digital A way of representing a physical quantity by a series of binary numbers. A digital representation can have only specic discrete values. The study of electronics often is divided into two basic areas: analog and digital electronics. Analog electronics has a longer history and can be regarded as the classical branch of electronics. Digital electronics, although newer, has achieved greater prominence through the advent of the computer age. The modern revolution in microcomputer chips, as part of everything from personal computers to cars and coffee makers, is founded almost entirely on digital electronics. The main difference between analog and digital electronics can be stated simply. Analog voltages or currents are continuously variable between dened values, and digital voltages or currents can vary only by distinct, or discrete, steps. Some keywords highlight the differences between digital and analog electronics: Analog Continuously variable Amplication Voltages Digital Discrete steps Switching Numbers An example often used to illustrate the difference between analog and digital devices is the comparison between a light dimmer and a light switch. A light dimmer is an analog device, since it can make the light it controls vary in brightness anywhere within a dened range of values. The light can be fully on, fully off, or at some brightness level in between. A light switch is a digital device, since it can turn the light on or off, but there is no value in between those two states. The light switch/light dimmer analogy, although easy to understand, does not show any particular advantage to the digital device. If anything, it makes the digital device seem limited. One modern application in which a digital device is clearly superior to an analog one is digital audio reproduction. Compact disc players have achieved their high level of popularity because of the accurate and noise-free way in which they reproduce recorded music. This high quality of sound is possible because the music is stored, not as a magnetic copy of the sound vibrations, as in analog tapes, but as a series of numbers that represent amplitude steps in the sound waves. Figure 1.1 shows a sound waveform and its representation in both analog and digital forms. The analog voltage, shown in Figure 1.1b, is a copy of the original waveform and introduces distortion both in the storage and playback processes. (Think of how a photocopy deteriorates in quality if you make a copy of a copy, then a copy of the new copy, and so on. It doesnt take long before you cant read the ne print.) A digital audio system doesnt make a copy of the waveform, but rather stores a code (a series of amplitude numbers) that tells the compact disc player how to re-create the original sound every time a disc is played. During the recording process, the sound waveform 1.2 Digital Logic Levels 3 FIGURE 1.1 Digital and Analog Sound Reproduction is sampled at precise intervals. The recording transforms each sample into a digital number corresponding to the amplitude of the sound at that point. The samples (the voltages represented by the vertical bars) of the digitized audio waveform shown in Figure 1.1c are much more widely spaced than they would be in a real digital audio system. They are shown this way to give the general idea of a digitized waveform. In real digital audio systems, each amplitude value can be indicated by a number having as many as 16,000 to 65,000 possible values. Such a large number of possible values means the voltage difference between any two consecutive digital numbers is very small. The numbers can thus correspond extremely closely to the actual amplitude of the sound waveform. If the spacing between the samples is made small enough, the reproduced waveform is almost exactly the same as the original. SECTION 1.1 REVIEW PROBLEM 1.1 What is the basic difference between analog and digital audio reproduction? 1.2 Digital Logic Levels KEY TERMS Logic level A voltage level that represents a dened digital state in an electronic circuit. Logic HIGH (or logic 1) The higher of two voltages in a digital system with two logic levels. Logic LOW (or logic 0) The lower of two voltages in a digital system with two logic levels. Positive logic A system in which logic LOW represents binary digit 0 and logic HIGH represents binary digit 1. Negative logic A system in which logic LOW represents binary digit 1 and logic HIGH represents binary digit 0. Digitally represented quantities, such as the amplitude of an audio waveform, are usually represented by binary, or base 2, numbers. When we want to describe a digital quantity electronically, we need to have a system that uses voltages or currents to symbolize binary numbers. The binary number system has only two digits, 0 and 1. Each of these digits can be denoted by a different voltage called a logic level. For a system having two logic levels, the 4 C H A P T E R 1 Basic Principles of Digital Systems lower voltage (usually 0 volts) is called a logic LOW or logic 0 and represents the digit 0. The higher voltage (traditionally 5 V, but in some systems a specic value such as 1.8 V, 2.5 V or 3.3 V) is called a logic HIGH or logic 1, which symbolizes the digit 1. Except for some allowable tolerance, as shown in Figure 1.2, the range of voltages between HIGH and LOW logic levels is undened. FIGURE 1.2 Logic Levels Based on and 0 V 5V 5V Logic HIGH 2V Undefined 0.8 V Logic LOW 0V NOTE For the voltages in Figure 1.2: 5V 0V Logic HIGH Logic LOW 1 0 The system assigning the digit 1 to a logic HIGH and digit 0 to logic LOW is called positive logic. Throughout the remainder of this text, logic levels will be referred to as HIGH/LOW or 1/0 interchangeably. (A complementary system, called negative logic, also exists that makes the assignment the other way around.) 1.3 The Binary Number System KEY TERMS Binary number system A number system used extensively in digital systems, based on the number 2. It uses two digits, 0 and 1, to write any number. Positional notation A system of writing numbers where the value of a digit depends not only on the digit, but also on its placement within a number. Bit Binary digit. A 0 or a 1. Positional Notation The binary number system is based on the number 2. This means that we can write any number using only two binary digits (or bits), 0 and 1. Compare this to the decimal system, which is based on the number 10, where we can write any number with only ten decimal digits, 0 to 9. The binary and decimal systems are both positional notation systems; the value of a digit in either system depends on its placement within a number. In the decimal number 845, the digit 4 really means 40, whereas in the number 9426, the digit 4 really means 400 (845 800 40 5; 9426 9000 400 20 6). The value of the digit is determined by what the digit is as well as where it is. In the decimal system, a digit in the position immediately to the left of the decimal point is multiplied by 1 (100). A digit two positions to the left of the decimal point is mul- 1.3 The Binary Number System 5 tiplied by 10 (101). A digit in the next position left is multiplied by 100 (102). The positional multipliers, as you move left from the decimal point, are ascending powers of 10. The same idea applies in the binary system, except that the positional multipliers are powers of 2 (20 1, 21 2, 22 4, 23 8, 24 16, 25 32, . . .). For example, the binary number 101 has the decimal equivalent: 22) 4) (1 (1 4 5 EXAMPLE 1.1 21) 2) (0 (0 0 20) 1) (1 (1 1 Calculate the decimal equivalents of the binary numbers 1010, 111, and 10010. SOLUTIONS 1010 111 10010 (1 23) (1 8) 82 (1 22) (1 4) 42 (1 24) (1 16) 16 2 (0 22) (1 21) (0 20) (0 4) (1 2) (0 1) 10 (1 21) (1 20) (1 2) (1 1) 17 (0 23) (0 22) (1 21) (0 20) (0 8) (0 4) (1 2) (0 1) 18 Binary Inputs KEY TERMS Most signicant bit The leftmost bit in a binary number. This bit has the numbers largest positional multiplier. Least signicant bit The rightmost bit of a binary number. This bit has the numbers smallest positional multiplier. A major class of digital circuits, called combinational logic, operates by accepting logic levels at one or more input terminals and producing a logic level at an output. In the analysis and design of such circuits, it is frequently necessary to nd the output logic level of a circuit for all possible combinations of input logic levels. The digital circuit in the black box in Figure 1.3 has three inputs. Each input can have two possible states, LOW or HIGH, which can be represented by positive logic as 0 or 1. The number of possible input combinations is 23 8. (In general, a circuit with n binary inputs has 2n input combinations, ranging from 0 to 2n 1.) Table 1.1 shows a list of these combinations, both as logic levels and binary numbers, and their decimal equivalents. FIGURE 1.3 3-Input Digital Circuit 6 C H A P T E R 1 Basic Principles of Digital Systems TABLE 1.1 Possible Input Combinations for a 3-Input Digital Circuit Logic Level Binary Value Decimal Equivalent A B C A B C L L L L H H H H L L H H L L H H L H L H L H L H 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 A list of output logic levels corresponding to all possible input combinations, applied in ascending binary order, is called a truth table. This is a standard form for showing the function of a digital circuit. The input bits on each line of Table 1.1 can be read from left to right as a series of 3bit binary numbers. The numerical values of these eight input combinations range from 0 to 7 (2n possible input combinations, having decimal equivalents ranging from 0 to 2n 1) in decimal. Bit A is called the most signicant bit (MSB), and bit C is called the least signicant bit (LSB). As these terms imply, a change in bit A is more signicant, since it has the greatest effect on the number of which it is part. Table 1.2 shows the effect of changing each of these bits in a 3-bit binary number and compares the changed number to the original by showing the difference in magnitude. A change in the MSB of any 3-bit number results in a difference of 4. A change in the LSB of any binary number results in a difference of 1. (Try it with a few different numbers.) TABLE 1.2 Effect of Changing the LSB and MSB of a Binary Number A Original Change MSB Change LSB EXAMPLE 1.2 B C Decimal 0 1 0 1 1 1 1 1 0 3 7 2 Difference Difference 4 1 Figure 1.4 shows a 4-input digital circuit. List all the possible binary input combinations to this circuit and their decimal equivalents. What is the value of the MSB? Inputs Outputs Digital circuit A (MSB) B C D (LSB) FIGURE 1.4 Example 1.2: 4-Input Digital Circuit Y 1.3 The Binary Number System 7 SOLUTION Since there are four inputs, there will be 24 16 possible input combinations, ranging from 0000 to 1111 (0 to 15 in decimal). Table 1.3 shows the list of all possible input combinations. The MSB has a value of 8 (decimal). TABLE 1.3 Possible Input Combinations for a 4-Input Digital Circuit A B C D Decimal 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Knowing how to construct a binary sequence is a very important skill when working with digital logic systems. Two ways to do this are: 1. Learn to count in binary. You should know all the binary numbers from 0000 to 1111 and their decimal equivalents (0 to 15). Make this your rst goal in learning the basics of digital systems. Each binary number is a unique representation of its decimal equivalent. You can work out the decimal value of a binary number by adding the weighted values of all the bits. For instance, the binary equivalent of the decimal sequence 0, 1, 2, 3 can be written using two bits: the 1s bit and the 2s bit. The binary count sequence is: 00 ( 01 ( 10 ( 11 ( 0 0 2 2 0) 1) 0) 1) To count beyond this, you need another bit: the 4s bit. The decimal sequence 4, 5, 6, 7 has the binary equivalents: 100 ( 101 ( 110 ( 111 ( 4 4 4 4 0 0 2 2 0) 1) 0) 1) The two least signicant bits of this sequence are the same as the bits in the 0 to 3 sequence; a repeating pattern has been generated. 8 C H A P T E R 1 Basic Principles of Digital Systems The sequence from 8 to 15 requires yet another bit: the 8s bit. The three LSBs of this sequence repeat the 0 to 7 sequence. The binary equivalents of 8 to 15 are: 1000 ( 1001 ( 1010 ( 1011 ( 1100 ( 1101 ( 1110 ( 1111 ( 8 8 8 8 8 8 8 8 0 0 0 0 4 4 4 4 0 0 2 2 0 0 2 2 0) 1) 0) 1) 0) 1) 0) 1) Practice writing out the binary sequence until it becomes familiar. In the 0 to 15 sequence, it is standard practice to write each number as a 4-bit value, as in Example 1.2, so that all numbers have the same number of bits. Numbers up to 7 have leading zeros to pad them out to 4 bits. This convention has developed because each bit has a physical location in a digital circuit; we know a particular bit is logic 0 because we can measure 0 V at a particular point in a circuit. A bit with a value of 0 doesnt go away just because there is not a 1 at a more signicant location. While you are still learning to count in binary, you can use a second method. 2. Follow a simple repetitive pattern. Look at Tables 1.1 and 1.3 again. Notice that the least signicant bit follows a pattern. The bits alternate with every line, producing the pattern 0, 1, 0, 1, . . . . The 2s bit alternates every two lines: 0, 0, 1, 1, 0, 0, 1, 1, . . . . The 4s bit alternates every four lines: 0, 0, 0, 0, 1, 1, 1, 1, . . . . This pattern can be expanded to cover any number of bits, with the number of lines between alternations doubling with each bit to the left. Decimal-to-Binary Conversion There are two methods commonly used to convert decimal numbers to binary: sum of powers of 2 and repeated division by 2. Sum of Powers of 2 You can convert a decimal number to binary by adding up powers of 2 by inspection, adding bits as you need them to ll up the total value of the number. For example, convert 5710 to binary. 5710 6410 3210 We see that 32 ( 25) is the largest power of two that is smaller than 57. Set the 32s bit to 1 and subtract 32 from the original number, as shown below. 57 32 25 The largest power of two that is less than 25 is 16. Set the 16s bit to 1 and subtract 16 from the accumulated total. 25 16 9 8 is the largest power of two that is less than 9. Set the 8s bit to 1 and subtract 8 from the total. 9 8 1 4 is greater than the remaining total. Set the 4s bit to 0. 2 is greater than the remaining total. Set the 2s bit to 0. 1.3 The Binary Number System 9 1 is left over. Set the 1s bit to 1 and subtract 1. 1 1 0 Conversion is complete when there is nothing left to subtract. Any remaining bits should be set to 0. 32 16 8 4 2 1 57 32 = 25 1 32 16 8 4 2 1 1 1 57 (32 + 16) = 9 32 16 8 1 1 32 16 8 4 2 1 1 1 0 0 1 1 1 4 2 1 57 (32 + 16 + 8) = 1 57 (32 + 16 + 8 + 1) = 0 5710 = 1110012 EXAMPLE 1.3 Convert 9210 to binary using the sum-of-powers-of-2 method. SOLUTION 128 92 64 32 16 64 8 4 2 1 1 92 64 = 28 64 32 16 1 0 8 4 2 1 92 (64 + 16) = 12 1 64 32 16 8 4 2 1 1 1 64 32 16 8 4 2 1 1 1 0 0 1 1 0 0 1 92 (64 + 16 + 8) = 4 92 (64 + 16 + 8 + 4) = 0 9210 = 10111002 Repeated Division by 2 Any decimal number divided by 2 will leave a remainder of 0 or 1. Repeated division by 2 will leave a string of 0s and 1s that become the binary equivalent of the decimal number. Let us use this method to convert 4610 to binary. 1. Divide the decimal number by 2 and note the remainder. 46/2 23 remainder 0 (LSB) The remainder is the least signicant bit of the binary equivalent of 46. 2. Divide the quotient from the previous division and note the remainder. The remainder is the second LSB. 23/2 11 remainder 1 10 C H A P T E R 1 Basic Principles of Digital Systems 3. Continue this process until the quotient is 0. The last remainder is the most signicant bit of the binary number. 11/2 5/2 2/2 1/2 5 2 1 0 remainder 1 remainder 1 remainder 0 remainder 1 (MSB) To write the binary equivalent of the decimal number, read the remainders from the bottom up. 4610 EXAMPLE 1.4 1011102 Use repeated division by 2 to convert 11510 to a binary number. SOLUTION 115/2 57/2 28/2 14/2 7/2 3/2 1/2 57 28 14 7 3 1 0 remainder 1 (LSB) remainder 1 remainder 0 remainder 0 remainder 1 remainder 1 remainder 1 (MSB) Read the remainders from bottom to top: 1110011. 11510 11100112 In any decimal-to-binary conversion, the number of bits in the binary number is the exponent of the smallest power of 2 that is larger than the decimal number. For example, for the numbers 9210 and 4610, 27 26 128 64 92 46 7 bits: 1011100 6 bits: 101110 Fractional Binary Numbers KEY TERMS Radix point The generalized form of a decimal point. In any positional number system, the radix point marks the dividing line between positional multipliers that are positive and negative powers of the systems number base. Binary point A period (.) that marks the dividing line between positional multipliers that are positive and negative powers of 2 (e.g., rst multiplier right of binary point 2 1; rst multiplier left of binary point 20). In the decimal system, fractional numbers use the same digits as whole numbers, but the digits are written to the right of the decimal point. The multipliers for these digits are negative powers of 1010 1 (1/10), 10 2 (1/100), 10 3 (1/1000), and so on. So it is in the binary system. Digits 0 and 1 are used to write fractional binary numbers, but the digits are to the right of the binary pointthe binary equivalent of the decimal point. (The decimal point and binary point are special cases of the radix point, the general name for any such point in any number system.) 1.3 The Binary Number System 11 Each digit is multiplied by a positional factor that is a negative power of 2. The rst four multipliers on either side of the binary point are: binary point 23 22 8 EXAMPLE 1.5 21 4 20 2 2 1 1 2 1/2 2 2 1/4 3 1/8 2 4 1/16 Write the binary fraction 0.101101 as a decimal fraction. SOLUTION 1 0 1 1 0 1 1/2 1/2 1/4 1/8 1/16 1/32 1/64 1/8 1/2 0 1/8 1/16 0 1/64 1/16 1/64 32/64 8/64 45/64 0.70312510 4/64 1/64 Fractional-Decimal-to-Fractional-Binary Conversion Simple decimal fractions such as 0.5, 0.25, and 0.375 can be converted to binary fractions by a sum-of-powers method. The above decimal numbers can also be written 0.5 1/2, 0.25 1/4, and 0.375 3/8 1/4 1/8. These numbers can all be represented by negative powers of 2. Thus, in binary, 0.510 0.2510 0.37510 0.12 0.012 0.0112 The conversion process becomes more complicated if we try to convert decimal fractions that cannot be broken into powers of 2. For example, the number 1/5 0.210 cannot be exactly represented by a sum of negative powers of 2. (Try it.) For this type of number, we must use the method of repeated multiplication by 2. Method: 1. Multiply the decimal fraction by 2 and note the integer part. The integer part is either 0 or 1 for any number between 0 and 0.999. . . . The integer part of the product is the rst digit to the left of the binary point. 0.2 2 0.4 Integer part: 0 2. Discard the integer part of the previous product. Multiply the fractional part of the previous product by 2. Repeat step 1 until the fraction repeats or terminates. 0.4 0.8 0.6 0.2 2 2 2 2 0.8 1.6 1.2 0.4 Integer part: 0 Integer part: 1 Integer part: 1 Integer part: 0 (Fraction repeats; product is same as in step 1) 12 C H A P T E R 1 Basic Principles of Digital Systems Read the above integer parts from top to bottom to obtain the fractional binary number. Thus, 0.210 0.00110011 . . .2 0.00112. The bar shows the portion of the digits that repeats. EXAMPLE 1.6 Convert 0.9510 to its binary equivalent. SOLUTION 0.95 0.90 0.80 0.60 0.20 0.40 0.80 2 2 2 2 2 2 2 1.90 Integer part: 1 1.80 Integer part: 1 1.60 Integer part: 1 1.20 Integer part: 1 0.40 Integer part: 0 0.80 Integer part: 0 1.60 Fraction repeats last four digits 0.9510 0.1111002 SECTION 1.3 REVIEW PROBLEMS 1.2. 1.3. 1.4. 1.5. How many different binary numbers can be written with 6 bits? How many can be written with 7 bits? Write the sequence of 7-bit numbers from 1010000 to 1010111. Write the decimal equivalents of the numbers written for Problem 1.4. 1.4 Hexadecimal Numbers TABLE 1.4 Hex Digits and Their Binary and Decimal Equivalents Hex Decimal Binary 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 After binary numbers, hexadecimal (base 16) numbers are the most important numbers in digital applications. Hexadecimal, or hex, numbers are primarily used as a shorthand form of binary notation. Since 16 is a power of 2 (24 16), each hexadecimal digit can be converted directly to four binary digits. Hex numbers can pack more digital information into fewer digits. Hex numbers have become particularly popular with the advent of small computers, which use binary data having 8, 16, or 32 bits. Such data can be represented by 2, 4, or 8 hexadecimal digits, respectively. Counting in Hexadecimal The positional multipliers in the hex system are powers of sixteen: 160 1, 161 16, 2 3 16 256, 16 4096, and so on. We need 16 digits to write hex numbers; the decimal digits 0 through 9 are not sufcient. The usual convention is to use the capital letters A through F, each letter representing a number from 1010 through 1510. Table 1.4 shows how hexadecimal digits relate to their decimal and binary equivalents. NOTE Counting Rules for Hexadecimal Numbers: 1. Count in sequence from 0 to F in the least signicant digit. 2. Add 1 to the next digit to the left and start over. 3. Repeat in all other columns. For instance, the hex numbers between 19 and 22 are 19, 1A, 1B, 1C, 1D, 1E, 1F, 20, 21, 22. (The decimal equivalents of these numbers are 2510 through 3410.) 1.4 EXAMPLE 1.7 Hexadecimal Numbers 13 What is the next hexadecimal number after 999? After 99F? After 9FF? After FFF? SOLUTION The hexadecimal number after 999 is 99A. The number after 99F is 9A0. The number after 9FF is A00. The number after FFF is 1000. EXAMPLE 1.8 List the hexadecimal digits from 19016 to 20016, inclusive. SOLUTION The numbers follow the counting rules: Use all the digits in one position, add 1 to the digit one position left, and start over. For brevity, we will list only a few of the numbers in the sequence: 190, 191, 192, . . . , 199, 19A, 19B, 19C, 19D, 19E, 19F, 1A0, 1A1, 1A2, . . . , 1A9, 1AA, 1AB, 1AC, 1AD, 1AE, 1AF, 1B0, 1B1, 1B2, . . . , 1B9, 1BA, 1BB, 1BC, 1BD, 1BE, 1BF, 1C0, . . . , 1CF, 1D0, . . . , 1DF, 1E0, . . . , 1EF, 1F0, . . . , 1FF, 200 SECTION 1.4A REVIEW PROBLEMS 1.6. List the hexadecimal numbers from FA9 to FB0, inclusive. 1.7. List the hexadecimal numbers from 1F9 to 200, inclusive. Hexadecimal-to-Decimal Conversion To convert a number from hex to decimal, multiply each digit by its power-of-16 positional multiplier and add the products. In the following examples, hexadecimal numbers are indicated by a nal H (e.g., 1F7H), rather than a 16 subscript. EXAMPLE 1.9 Convert 7C6H to decimal. SOLUTION EXAMPLE 1.10 7 C 6 162 161 160 710 1210 610 25610 1610 110 163 162 161 160 110 1510 1310 510 409610 25610 1610 110 179210 19210 610 199010 Convert 1FD5H to decimal. SOLUTION 1 F D 5 409610 384010 20810 510 814910 SECTION 1.4B REVIEW PROBLEM 1.8 Convert the hexadecimal number A30F to its decimal equivalent. Decimal-to-Hexadecimal Conversion Decimal numbers can be converted to hex by the sum-of-weighted-hex-digits method or by repeated division by 16. The main difculty we encounter in either method is 14 C H A P T E R 1 Basic Principles of Digital Systems remembering to convert decimal numbers 10 through 15 into the equivalent hex digits, A through F. Sum of Weighted Hexadecimal Digits This method is useful for simple conversions (about three digits). For example, the decimal number 35 is easily converted to the hex value 23. 3510 EXAMPLE 1.11 3210 310 (2 16) (3 1) 23H Convert 17510 to hexadecimal. SOLUTION Since 256 25610 17510 1610 162, the hexadecimal number will have two digits. (11 16 A 16) 1 175 (10 16) 175 16 F 175 175 ((A (160 16) 175 160 15 1 A (A 16) 15) (F 0 1)) Repeated Division by 16 Repeated division by 16 is a systematic decimal-to-hexadecimal conversion method that is not limited by the size of the number to be converted. It is similar to the repeated-division-by-2 method used to convert decimal numbers to binary. Divide the decimal number by 16 and note the remainder, making sure to express it as a hex digit. Repeat the process until the quotient is zero. The last remainder is the most signicant digit of the hex number. EXAMPLE 1.12 Convert 3158110 to hexadecimal. SOLUTION 31581/16 1973/16 123/16 7/16 1973 remainder 13 (D) (LSD) 123 remainder 5 7 remainder 11 (B) 0 remainder 7 (MSD) 3158110 7B5DH SECTION 1.4C REVIEW PROBLEM 1.9 Convert the decimal number 8137 to its hexadecimal equivalent. Conversions Between Hexadecimal and Binary Table 1.4 shows all 16 hexadecimal digits and their decimal and binary equivalents. Note that for every possible 4-bit binary number, there is a hexadecimal equivalent. Binary-to-hex and hex-to-binary conversions simply consist of making a conversion between each hex digit and its binary equivalent. 1.5 EXAMPLE 1.13 Digital Waveforms 15 Convert 7EF8H to its binary equivalent. SOLUTION Convert each digit individually to its equivalent value: 7H EH FH 8H 01112 11102 11112 10002 The binary number is all the above binary numbers in sequence: 7EF8H 1111110111110002 The leading zero (the MSB of 0111) has been left out. SECTION 1.4D REVIEW PROBLEMS 1.10 Convert the hexadecimal number 934B to binary. 1.11 Convert the binary number 11001000001101001001 to hexadecimal. 1.5 Digital Waveforms KEY TERM Digital waveform A series of logic 1s and 0s plotted as a function of time. The inputs and outputs of digital circuits often are not xed logic levels but digital waveforms, where the input and output logic levels vary with time. There are three possible types of digital waveform. Periodic waveforms repeat the same pattern of logic levels over a specied period of time. Aperiodic waveforms do not repeat. Pulse waveforms follow a HIGH-LOW-HIGH or LOW-HIGH-LOW pattern and may be periodic or aperiodic. Periodic Waveforms KEY TERMS Periodic waveform A time-varying sequence of logic HIGHs and LOWs that repeats over a specied period of time. Period (T) Time required for a periodic waveform to repeat. Unit: seconds (s). Frequency ( f ) Number of times per second that a periodic waveform repeats. f 1/T Unit: Hertz (Hz). Time HIGH (th) Time during one period that a waveform is in the HIGH state. Unit: seconds (s). Time LOW (tl) Time during one period that a waveform is in the LOW state. Unit: seconds (s). Duty cycle (DC) Fraction of the total period that a digital waveform is in the HIGH state. DC th/T (often expressed as a percentage: %DC th/T 100%). Periodic waveforms repeat the same pattern of HIGHs and LOWs over a specied period of time. The waveform may or may not be symmetrical; that is, it may or may not be HIGH and LOW for equal amounts of time. 16 C H A P T E R 1 Basic Principles of Digital Systems EXAMPLE 1.14 Calculate the time LOW, time HIGH, period, frequency, and percent duty cycle for each of the periodic waveforms in Figure 1.5. FIGURE 1.5 Example 1.14: Periodic Digital Waveforms How are the waveforms similar? How do they differ? SOLUTION a. Time LOW: tl 3 ms Time HIGH: th 1 ms Period: T tl th 3 ms 1 ms 4 ms Frequency: f 1/T 1/(4 ms) 0.25 kHz 250 Hz Duty cycle: %DC (th/T ) 100% (1 ms/4 ms) 100% 25% (1 ms 1/1000 second; 1 kHz 1000 Hz.) b. Time LOW: tl 2 ms Time HIGH: th 2 ms Period: T tl th 2 ms 2 ms 4 ms Frequency: f 1/T 1/(4 ms) 0.25 kHz 250 Hz Duty cycle: %DC (th/T ) 100% (2 ms/ 4 ms) 100% 50% c. Time LOW: tl 1 ms Time HIGH: th 3 ms Period: T tl th 1 ms 3 ms 4 ms Frequency: f 1/T 1/(4 ms) 0.25 kHz and 250 Hz Duty cycle: %DC (th/T) 100% (3 ms/ 4 ms) 100% 75% The waveforms all have the same period but different duty cycles. A square waveform, shown in Figure 1.5b, has a duty cycle of 50%. Aperiodic Waveforms KEY TERM Aperiodic waveform A time-varying sequence of logic HIGHs and LOWs that does not repeat. An aperiodic waveform does not repeat a pattern of 0s and 1s. Thus, the parameters of time HIGH, time LOW, frequency, period, and duty cycle have no meaning for an aperiodic waveform. Most waveforms of this type are one-of-a-kind specimens. (It is also worth noting that most digital waveforms are aperiodic.) 1.5 Digital Waveforms 17 Figure 1.6 shows some examples of aperiodic waveforms. FIGURE 1.6 Aperiodic Digital Waveforms EXAMPLE 1.15 A digital circuit generates the following strings of 0s and 1s: a. b. c. d. 0011111101101011010000110000 0011001100110011001100110011 0000000011111111000000001111 1011101110111011101110111011 The time between two bits is always the same. Sketch the resulting digital waveform for each string of bits. Which waveforms are periodic and which are aperiodic? SOLUTION Figure 1.7 shows the waveforms corresponding to the strings of bits above. The waveforms are easier to draw if you break up the bit strings into smaller groups of, say, 4 bits each. For instance: a. 0011 1111 0110 1011 0100 0011 0000 All of the waveforms except Figure 1.7a are periodic. FIGURE 1.7 Example 1.15: Waveforms Pulse Waveforms KEY TERMS Pulse A momentary variation of voltage from one logic level to the opposite level and back again. Amplitude The instantaneous voltage of a waveform. Often used to mean maximum amplitude, or peak voltage, of a pulse. Edge The part of the pulse that represents the transition from one logic level to the other. Rising edge The part of a pulse where the logic level is in transition from a LOW to a HIGH. 18 C H A P T E R 1 Basic Principles of Digital Systems Falling edge The part of a pulse where the logic level is a transition from a HIGH to a LOW. Leading edge The edge of a pulse that occurs earliest in time. Trailing edge The edge of a pulse that occurs latest in time. Pulse width (tw) Elapsed time from the 50% point of the leading edge of a pulse to the 50% point of the trailing edge. Rise time (tr) Elapsed time from the 10% point to the 90% point of the rising edge of a pulse. Fall time (tf ) Elapsed time from the 90% point to the 10% point of the falling edge of a pulse. Figure 1.8 shows the forms of both an ideal and a nonideal pulse. The rising and falling edges of an ideal pulse are vertical. That is, the transitions between logic HIGH and LOW levels are instantaneous. There is no such thing as an ideal pulse in a real digital circuit. Circuit capacitance and other factors make the pulse more like the nonideal pulse in Figure 1.8b. Pulses can be either positive-going or negative-going, as shown in Figure 1.9. In a positive-going pulse, the measured logic level is normally LOW, goes HIGH for the duration 1 1 0.5 t 0 t1 t2 a. Ideal pulse (instantaneous transitions) FIGURE 1.8 Ideal and Nonideal Pulses FIGURE 1.9 Pulse Edges t 0 t1 t2 b. Nonideal pulse 1.5 Digital Waveforms 19 of the pulse, and returns to the LOW state. A negative-going pulse acts in the opposite direction. Nonideal pulses are measured in terms of several timing parameters. Figure 1.10 shows the 10%, 50%, and 90% points on the rising and falling edges of a nonideal pulse. (100% is the maximum amplitude of the pulse.) FIGURE 1.10 Pulse Width, Rise Time, Fall Time The 50% points are used to measure pulse width because the edges of the pulse are not vertical. Without an agreed reference point, the pulse width is indeterminate. The 10% and 90% points are used as references for the rise and fall times, since the edges of a nonideal pulse are nonlinear. Most of the nonlinearity is below the 10% or above the 90% point. EXAMPLE 1.16 Calculate the pulse width, rise time, and fall time of the pulse shown in Figure 1.11. FIGURE 1.11 Example 1.16: Pulse SOLUTION From the graph in Figure 1.11, read the times corresponding to the 10%, 50%, and 90% values of the pulse on both the leading and trailing edges. Leading edge: 10%: 50%: 90%: 2s 5s 8s Trailing edge: 90%: 50%: 10%: 20 s 25 s 30 s 20 C H A P T E R 1 Basic Principles of Digital Systems Pulse width: 50% of leading edge to 50% of trailing edge. tw 25 s 5s 20 s Rise time: 10% of rising edge to 90% of rising edge. tr 8s 2s 6s Fall time: 90% of falling edge to 10% of falling edge. tf 30 s 20 s 10 s SECTION 1.5 REVIEW PROBLEMS A digital circuit produces a waveform that can be described by the following periodic bit pattern: 0011001100110011. 1.12 What is the duty cycle of the waveform? 1.13 Write the bit pattern of a waveform with the same duty cycle and twice the frequency of the original. 1.14 Write the bit pattern of a waveform having the same frequency as the original and a duty cycle of 75%. SUMMARY 1. The two basic areas of electronics are analog and digital electronics. Analog electronics deals with continuously variable quantities; digital electronics represents the world in discrete steps. 2. Digital logic uses dened voltage levels, called logic levels, to represent binary numbers within an electronic system. 3. The higher voltage in a digital system represents the binary digit 1 and is called a logic HIGH or logic 1. The lower voltage in a system represents the binary digit 0 and is called a logic LOW or logic 0. 4. The logic levels of multiple locations in a digital circuit can be combined to represent a multibit binary number. 5. Binary is a positional number system (base 2) with two digits, 0 and 1, and positional multipliers that are powers of 2. 6. The bit with the largest positional weight in a binary number is called the most signicant bit (MSB); the bit with the smallest positional weight is called the least signicant bit (LSB). The MSB is also the leftmost bit in the number; the LSB is the rightmost bit. 7. A decimal number can be converted to binary by sum of powers of 2 (add place values to get a total) or repeated division by 2 (divide by 2 until quotient is 0; remainders are the binary value). 8. The hexadecimal number system is based on 16. It uses 16 digits, from 09 and AF, with power-of-16 multipliers. 9. Each hexadecimal digit uniquely corresponds to a 4-bit binary value. Hex digits can thus be used as shorthand for binary. 10. A digital waveform is a sequence of bits over time. A waveform can be periodic (repetitive), aperiodic (nonrepetitive), or pulsed (a single variation and return between logic levels.) 11. Periodic waveforms are measured by period (T: time for one cycle), time HIGH (th), time LOW (tl), frequency ( f: number of cycles per second), and duty cycle (DC or %DC: fraction of cycle in HIGH state). 12. Pulse waveforms are measured by pulse width (tw: time from 50% of leading edge of 50% of trailing edge), rise time (tr: time from 10% to 90% of rising edge) and fall time (tf: time from 90% to 10% of falling edge). GLOSSARY Amplitude The instantaneous voltage of a waveform. Often used to mean maximum amplitude, or peak voltage, of a pulse. Aperiodic waveform A time-varying sequence of logic HIGHs and LOWs that does not repeat. Analog A way of representing some physical quantity, such as temperature or velocity, by a proportional continuous voltage or current. An analog voltage or current can have any value within a dened range. Binary number system A number system used extensively in digital systems, based on the number 2. It uses two digits to write any number. Bit Binary digit. A 0 or a 1. Problems 21 Continuous Smoothly connected. An unbroken series of consecutive values with no instantaneous changes. Most signicant bit (MSB) The leftmost bit in a binary number. This bit has the numbers largest positional multiplier. Digital A way of representing a physical quantity by a series of binary numbers. A digital representation can have only specic discrete values. Negative logic A system in which logic LOW represents binary digit 1 and logic HIGH represents binary digit 0. Digital waveform A series of logic 1s and 0s plotted as a function of time. Discrete Separated into distinct segments or pieces. A series of discontinous values. Duty cycle (DC) Fraction of the total period that a digital waveform is in the HIGH state. DC th/T (often expressed as a percentage: %DC th/T 100%). Edge The part of the pulse that represents the transition from one logic level to the other. Fall time (tf) Elapsed time from the 90% point to the 10% point of the falling edge of a pulse. Falling edge The part of a pulse where the logic level is in transition from a HIGH to a LOW. Frequency ( f) Number of times per second that a periodic waveform repeats. f 1/T Unit: Hertz (Hz). Hexadecimal number system Base-16 number system. Hexadecimal numbers are written with sixteen digits, 09 and AF, with power-of-16 positional multipliers. Leading edge The edge of a pulse that occurs earliest in time. Least signicant bit (LSB) The rightmost bit of a binary number. This bit has the numbers smallest positional multiplier. Logic HIGH The higher of two voltages in a digital system with two logic levels. Logic level A voltage level that represents a dened digital state in an electronic circuit. Period (T) Time required for a period waveform to repeat. Unit: seconds (s). Periodic waveform A time-varying sequence of logic HIGHs and LOWs that repeats over a specied period of time. Positional notation A system of writing numbers in which the value of a digit depends not only on the digit, but also on its placement within a number. Positive logic A system in which logic LOW represents binary digit 0 and logic HIGH represents binary digit 1. Pulse A momentary variation of voltage from one logic level to the opposite level and back again. Pulse width (tw) Elapsed time from the 50% point of the leading edge of a pulse to the 50% point of the trailing edge. Radix point The generalized form of a decimal point. In any positional number system, the radix point marks the dividing line between positional multipliers that are positive and negative powers of the systems number base. Rise time (tr) Elapsed time from the 10% point to the 90% point of the rising edge of a pulse. Rising edge The part of a pulse where the logic level is in transition from a LOW to a HIGH. Time HIGH (th) Time during one period that a waveform is in the HIGH state. Unit: seconds (s). Time LOW (tl ) Time during one period that a waveform is in the LOW state. Unit: seconds (s). Trailing edge The edge of a pulse that occurs latest in time. Logic LOW The lower of two voltages in a digital system with two logic levels. PROBLEMS Problem numbers set in color indicate more difcult problems: those with underlines indicate most difcult problems. Section 1.3 The Binary Number System Section 1.1 Digital Versus Analog Electronics 1.3 Calculate the decimal values of each of the following binary numbers: 1.1 a. 100 f. 11101 Which of the following quantities is analog in nature and which digital? Explain your answers. b. 1000 g. 111011 a. Water temperature at the beach c. 11001 h. 1011101 b. Weight of a bucket of sand d. 110 i. 100001 c. Grains of sand in a bucket e. 10101 j. 10111001 d. Waves hitting the beach in one hour e. Height of a wave f. People in a square mile Section 1.2 Digital Logic Levels 1.2 A digital logic system is dened by the voltages 3.3 volts and 0 volts. For a positive logic system, state which voltage corresponds to a logic 0 and which to a logic 1. 1.4 Translate each of the following combinations of HIGH (H) and LOW (L) logic levels to binary numbers using positive logic: a. H H L H d. L L L H b. L H L H e. H L L L c. H L H L 22 C H A P T E R 1 Basic Principles of Digital Systems 1.5 List the sequence of binary numbers from 101 to 1000. mal equivalents. 1.6 List the sequence of binary numbers from 10000 to 11111. a. 70910 1.7 What is the decimal value of the most signicant bit for the numbers in Problem 1.6 1.8 Convert the following decimal numbers to binary. Use the sum-of-powers-of-2 method for parts a, c, e, and g. Use the repeated-division-by-2 method for parts b, d, f, and h. a. 7510 c. 23710 d. 409610 e. 1012810 f. 3200010 g. 3276810 g. 408710 d. 19810 1.9 f. 6410 c. 409510 e. 6310 b. 8310 b. 188910 h. 819310 1.18 Convert the following hexadecimal numbers to their binary equivalents. a. F3C8H b. D3B4H Convert the following fractional binary numbers to their decimal equivalents. c. 8037H a. 0.101 b. 0.011 e. 30ACH c. 0.1101 1.10 d. FABDH f. 3E7B6H Convert the following fractional binary numbers to their decimal equivalents. a. 0.01 1.11 c. 0.010101 b. 0.0101 g. 743DCFH 1.19 d. 0.01010101 a. 1011110100001102 b. 1011011010102 The numbers in Problem 1.10 are converging to a closer and closer binary approximation of a simple fraction that can be expressed by decimal integers a/b. What is the fraction? 1.12 Convert the following decimal numbers to their binary equivalents. If a number has an integer part larger than 0, calculate the integer and fractional parts separately. c. 1100010110112 d. 1101011110001002 e. 101010111100001012 What is the simple decimal fraction (a/b) represented by the repeating binary number 0.101010 . . . ? 1.13 Convert the following binary numbers to their hexadecimal equivalents. f. 110011000101101112 g. 1010000000000000002 Section 1.5 Digital Waveforms e. 1.7510 b. 0.62510 Calculate the time LOW, time HIGH, period, frequency, and percent duty cycle for the waveforms shown in Figure 1.12. How are the waveforms similar? How do they differ? Which of the waveforms in Figure 1.13 are periodic and which are aperiodic? Explain your answers. 1.22 f. 3.9510 c. 0.187510 1.20 1.21 a. 0.7510 g. 67.8410 d. 0.6510 Section 1.4 Hexadecimal Numbers 1.14 Write all the hexadecimal numbers in sequence from 308H to 321H inclusive. Sketch the pulse waveforms represented by the following strings of 0s and 1s. State which waveforms are periodic and which are aperiodic. 1.15 Write all the hexadecimal numbers in sequence from 9F7H to A03H inclusive. b. 111000111000111000111000111000111 Convert the following hexadecimal numbers to their decimal equivalents. d. 01100110011001100110011001100110 1.16 a. 1A0H c. FFFH g. C000H d. 1000H 1.17 f. D3B4H h. 30BAFH c. 11111111000000001111111111111111 e. F3C8H b. 10AH a. 11001111001110110000000110110101 Convert the following decimal numbers to their hexadeci- e. 011101101001101001011010011101110 1.23 Calculate the pulse width, rise time, and fall time of the pulse shown in Figure 1.14. 1.24 Repeat Problem 1.23 for the pulse shown in Figure 1.15. Answers To Section Review Problems FIGURE 1.12 Problem 1.20: Periodic Waveforms FIGURE 1.13 Problem 1.21: Aperiodic and Periodic Waveforms FIGURE 1.14 Problem 1.23: Pulse FIGURE 1.15 Problem 1.24: Pulse ANSWERS TO SECTION REVIEW PROBLEMS Section 1.1 Section 1.4b 1.1 An analog audio system makes a direct copy of the recorded sound waves. A digital system stores the sound as a series of binary numbers. 1.8 4174310. Section 1.3 1.2 64; 1.3. 128; 1.4. 1010000, 1010001, 1010010, 1010011, 1010100, 1010101, 1010110, 1010111; 1.5. 80, 81, 82, 83, 84, 85, 86, 87. Section 1.4a 1.6 FA9, FAA, FAB, FAC, FAD, FAE, FAF, FB0, 1FA, 1FB, 1FC, 1FD, 1FE, 1FF, 200. 1.7 1F9, Section 1.4c 1.9 1FC9. Section 1.4d 1.10 1001001101001011. 1.11 C8349. Section 1.5 1.12 50%; 1.13 0101010101010101; 1.14 0111011101110111. 23 CHAPTER 2 Logic Functions and Gates OUTLINE CHAPTER OBJECTIVES 2.1 Upon successful completion of this chapter, you will be able to: Describe the basic logic functions: AND, OR, and NOT Draw simple switch circuits to represent AND, OR and Exclusive OR functions. Draw simple logic switch circuits for single-pole single-throw (SPST) and normally open and normally closed pushbutton switches. Describe the use of light-emitting diodes (LEDs) as indicators of logic HIGH and LOW states. Describe those logic functions derived from the basic ones: NAND, NOR, Exclusive OR, and Exclusive NOR. Explain the concept of active levels and identify active LOW and HIGH terminals of logic gates. 2.2 2.3 2.4 2.5 2.6 Basic Logic Functions Logic Switches and LED Indicators Derived Logic Functions DeMorgans Theorems and Gate Equivalence Enable and Inhibit Properties of Logic Gates Integrated Circuit Logic Gates Choose appropriate logic functions to solve simple design problems. Draw the truth table of any logic gate. Draw any logic gate, given its truth table. Draw the DeMorgan equivalent form of any logic gate. Determine when a logic gate will pass a digital waveform and when it will block the signal. Describe several types of integrated circuit packaging for digital logic gates. A ll digital logic functions can be synthesized by various combinations of the three basic logic functions: AND, OR, and NOT. These so-called Boolean functions are the basis for all further study of combinational logic circuitry. (Combinational logic circuits are digital circuits whose outputs are functions of their inputs, regardless of the order the inputs are applied.) Standard circuits, called logic gates, have been developed for these and for more complex digital logic functions. Logic gates can be represented in various forms. A standard set of distinctive-shape symbols has evolved as a universally understandable means of representing the various functions in a circuit. A useful pair of mathematical theorems, called DeMorgans theorems, enables us to draw these gate symbols in different ways to represent different aspects of the same function. A newer way of representing standard logic gates is outlined in IEEE/ANSI Standard 91-1984, a standard copublished by the Institute of Electrical and 25 26 C H A P T E R 2 Logic Functions and Gates Electronic Engineers and the American National Standards Institute. It uses a set of symbols called rectangular-outline symbols. Logic gates can be used as electronic switches to block or allow passage of digital waveforms. Each logic gate has a different set of properties for enabling (passing) or inhibiting (blocking) digital waveforms. I 2.1 Basic Logic Functions KEY TERMS Boolean variable A variable having only two possible values, such as HIGH/LOW, 1/0, On/Off, or True/False. Boolean algebra A system of algebra that operates on Boolean variables. The binary (two-state) nature of Boolean algebra makes it useful for analysis, simplication, and design of combinational logic circuits. Boolean expression An algebraic expression made up of Boolean variables and operators, such as AND, OR, or NOT. Also referred to as a Boolean function or a logic function. Logic gate An electronic circuit that performs a Boolean algebraic function. At its simplest level, a digital circuit works by accepting logic 1s and 0s at one or more inputs and producing 1s or 0s at one or more outputs. A branch of mathematics known as Boolean algebra (named after 19th-century mathematician George Boole) describes the relation between inputs and outputs of a digital circuit. We call these input and output values Boolean variables and the functions Boolean expressions, logic functions, or Boolean functions. The distinguishing characteristic of these functions is that they are made up of variables and constants that can have only two possible values: 0 or 1. All possible operations in Boolean algebra can be created from three basic logic functions: AND, OR, and NOT.1 Electronic circuits that perform these logic functions are called logic gates. When we are analyzing or designing a digital circuit, we usually dont concern ourselves with the actual circuitry of the logic gates, but treat them as black boxes that perform specied logic functions. We can think of each variable in a logic function as a circuit input and the whole function as a circuit output. In addition to gates for the three basic functions, there are also gates for compound functions that are derived from the basic ones. NAND gates combine the NOT and AND functions in a single circuit. Similarly, NOR gates combine the NOT and OR functions. Gates for more complex functions, such as Exclusive OR and Exclusive NOR, also exist. We will examine all these devices later in the chapter. NOT, AND, and OR Functions KEY TERMS Truth table A list of all possible input values to a digital circuit, listed in ascending binary order, and the output response for each input combination. Inverter Also called a NOT gate or an inverting buffer. A logic gate that changes its input logic level to the opposite state. Bubble A small circle indicating logical inversion on a circuit symbol. 1 Words in uppercase letters represent either logic functions (AND, OR, NOT) or logic levels (HIGH, LOW). The same words in lowercase letters represent their conventional nontechnical meanings. 2.1 Basic Logic Functions 27 Distinctive-shape symbols Graphic symbols for logic circuits that show the function of each type of gate by a special shape. IEEE/ANSI Standard 91-1984 A standard format for drawing logic circuit symbols as rectangles with logic functions shown by a standard notation inside the rectangle for each device. Rectangular-outline symbols Rectangular logic gate symbols that conform to IEEE/ANSI Standard 91-1984. Qualifying symbol A symbol in IEEE/ANSI logic circuit notation, placed in the top center of a rectangular symbol, that shows the function of a logic gate. Some of the qualifying symbols include: 1 buffer; & AND; 1 OR Buffer An amplier that acts as a logic circuit. Its output can be inverting or noninverting. Table 2.1 NOT Function Truth Table A Y 0 1 1 0 NOT Function The NOT function, the simplest logic function, has one input and one output. The input can be either HIGH or LOW (1 or 0), and the output is always the opposite logic level. We can show these values in a truth table, a list of all possible input values and the output resulting from each one. Table 2.1 shows a truth table for a NOT function, where A is the input variable and Y is the output. The NOT function is represented algebraically by the Boolean expression: Y A This is pronounced Y equals NOT A or Y equals A bar. We can also say Y is the complement of A. The circuit that produces the NOT function is called the NOT gate or, more usually, the inverter. Several possible symbols for the inverter, all performing the same logic function, are shown in Figure 2.1. The symbols shown in Figure 2.1a are the standard distinctive-shape symbols for the inverter. The triangle represents an amplier circuit, and the bubble (the small circle on the input or output) represents inversion. There are two symbols because sometimes it is convenient to show the inversion at the input and sometimes it is convenient to show it at the output. Figure 2.1b shows the rectangular-outline inverter symbol specied by IEEE/ANSI Standard 91-1984. This standard is most useful for specifying the symbols for more complex digital devices. We will show the basic gates in both distinctive-shape and rectangular-outline symbols, although most examples will use the distinctive-shape symbols. The 1 in the top center of the IEEE symbol is a qualifying symbol, indicating the logic gate function. In this case, it shows that the circuit is a buffer, an amplifying circuit used as a digital logic element. The arrows at the input and output of the two IEEE symbols show inversion, like the bubbles in the distinctive-shape symbols. FIGURE 2.1 Inverter Symbols AND Function Table 2.2 2-input AND Function Truth Table A B Y 0 0 1 1 0 1 0 1 0 0 0 1 KEY TERMS AND gate A logic circuit whose output is HIGH when all inputs (e.g., A AND B AND C ) are HIGH. Logical product AND function. The AND function combines two or more input variables so that the output is HIGH only if all the inputs are HIGH. The truth table for a 2-input AND function is shown in Table 2.2. 28 C H A P T E R 2 Logic Functions and Gates Algebraically, this is written: Y FIGURE 2.2 2-Input AND Gate Symbols AB Pronounce this expression Y equals A AND B. The AND function is similar to multiplication in linear algebra and thus is sometimes called the logical product. The dot between variables may or may not be written, so it is equally correct to write Y AB. The logic circuit symbol for an AND gate is shown in Figure 2.2 in both distinctive-shape and IEEE/ANSI rectangular-outline form. The qualifying symbol in IEEE/ANSI notation is the ampersand (&). We can also represent the AND function as a set of switches in series, as shown in Figure 2.3. The circuit consists of a voltage source, a lamp, and two series switches. The lamp turns on when switches A AND B are both closed. For any other condition of the switches, the lamp is off. A Voltage source B Lamp AB FIGURE 2.3 AND Function Represented by Switches Table 2.3 3-input AND Function Truth Table A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 Table 2.3 shows the truth table for a 3-input AND function. Each of the three inputs can have two different values, which means the inputs can be combined in 23 8 different ways. In general, n binary (i.e., two-valued) variables can be combined in 2n ways. Figure 2.4 shows the logic symbols for the device. The output is HIGH only when all inputs are HIGH. FIGURE 2.4 3-Input AND Gate Symbols OR Function KEY TERMS Table 2.4 2-input OR Function Truth Table A B Y 0 0 1 1 0 1 0 1 0 1 1 1 OR gate A logic circuit whose output is HIGH when at least one input (e.g., A OR B OR C ) is HIGH. Logical sum OR function. The OR function combines two or more input variables in such a way as to make the output variable HIGH if at least one input is HIGH. Table 2.4 gives the truth table for the 2-input OR function. 2.1 Basic Logic Functions 29 The algebraic expression for the OR function is: Y FIGURE 2.5 2-Input OR Gate Symbols A B which is pronounced Y equals A OR B. This is similar to the arithmetic addition function, but it is not the same. The last line of the truth table tells us that 1 1 1 (pronounced 1 OR 1 equals 1), which is not what we would expect in standard arithmetic. The similarity to the addition function leads to the name logical sum. (This is different from the arithmetic sum, where, of course, 1 1 does not equal 1.) Figure 2.5 shows the logic circuit symbols for an OR gate. The qualifying symbol for the OR function in IEEE/ANSI notation is 1, which tells us that one or more inputs must be HIGH to make the output HIGH. The OR function can be represented by a set of switches connected in parallel, as in Figure 2.6. The lamp is on when either switch A OR switch B is closed. (Note that the lamp is also on if both A and B are closed. This property distinguishes the OR function from the Exclusive OR function, which we will study later in this chapter.) A B Voltage source Lamp A B FIGURE 2.6 OR Function Represented by Switches Table 2.5 3-input OR Function Truth Table A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 EXAMPLE 2.1 Application Like AND gates, OR gates can have several inputs, such as the 3-input OR gates shown in Figure 2.7. Table 2.5 shows the truth table for this gate. Again, three inputs can be combined in eight different ways. The output is HIGH when at least one input is HIGH. FIGURE 2.7 3-Input OR Gate Symbols State which logic function is most suitable for the following operations. Draw a set of switches to represent each function. 1. A manager and one other employee both need a key to open a safe. 2. A light comes on in a storeroom when either (or both) of two doors is open. (Assume the switch closes when the door opens.) 3. For safety, a punch press requires two-handed operation. SOLUTION 1. Both keys are required, so this is an AND function. Figure 2.8a shows a switch representation of the function. 30 C H A P T E R 2 Logic Functions and Gates 2. One or more switches closed will turn on the lamp. This OR function is shown in Figure 2.8b. 3. Two switches are required to activate a punch press, as shown in Figure 2.8c. This is an AND function. FIGURE 2.8 Example 2.1 Key switch (manager) Key switch (employee) DC voltage source Electronic lock a. Two keys to open a safe (AND) Door switch A AC voltage source Lamp Door switch B b. One or more switches turn on a lamp (OR) Hand switch A AC voltage source Hand switch B Solenoid (punch) c. Two switches are required to activate a punch press (AND) Active Levels KEY TERMS Active level A logic level dened as the ON state for a particular circuit input or output. The active level can be either HIGH or LOW. Active HIGH An active-HIGH terminal is considered ON when it is in the logic HIGH state. Indicated by the absence of a bubble at the terminal in distinctive-shape symbols. Active LOW An active-LOW terminal is considered ON when it is in the logic LOW state. Indicated by a bubble at the terminal in distinctive-shape symbols. An active level of a gate input or output is the logic level, either HIGH or LOW, of the terminal when it is performing its designated function. An active LOW is shown by a bubble or an arrow symbol on the affected terminal. If there is no bubble or arrow, we assume the terminal is active HIGH. 2.2 Logic Switches and LED Indicators 31 The AND function has active-HIGH inputs and an active-HIGH output. To make the output HIGH, inputs A AND B must both be HIGH. The gate performs its designated function only when all inputs are HIGH. The OR gate requires input A OR input B to be HIGH for its output to be HIGH. The HIGH active levels are shown by the absence of bubbles or arrows on the terminals. SECTION REVIEW PROBLEM FOR SECTION 2.1 A 4-input gate has input variables A, B, C, and D and output Y. Write a descriptive sentence for the active output state(s) if the gate is 2.1 AND; 2.2 OR. 2.2 Logic Switches and LED Indicators Before continuing on, we should examine a few simple circuits that can be used for input or output in a digital circuit. Single-pole single-throw (SPST) and pushbutton switches can be used, in combination with resistors, to generate logic voltages for circuit inputs. Light emitting diodes (LEDs) can be used to monitor outputs of circuits. Logic Switches KEY TERMS VCC The power supply voltage in a transistor-based electronic circuit. The term often refers to the power supply of digital circuits. Pull-up resistor A resistor connected from a point in an electronic circuit to the power supply of that circuit. Figure 2.9a shows a single-pole single-throw (SPST) switch connected as a logic switch. An important premise of this circuit is that the input of the digital circuit to which it is connected has a very high resistance to current. When the switch is open, the current owing through the pull-up resistor from VCC to the digital circuit is very small. Since the current is small, Ohms law states that very little voltage drops across the pull-up resistor; the voltage is about the same at one end as at the other. Therefore, an open switch generates a logic HIGH at point X. Vcc X High input resistance a. Circuit Digital circuit 1 Open Closed Open 0 b. Logic levels FIGURE 2.9 SPST Logic Switch When the switch is closed, the majority of current ows to ground, limited only by the value of the pull-up resistor. (Since a pull-up resistor is typically between 1 k and 10 k , the LOW-state current in the resistor is about 0.5 mA to 5 mA.) Point X is approximately at ground potential, or logic LOW. Thus the switch generates a HIGH when open and a LOW when closed. The pull-up resistor provides a connection to VCC in the HIGH state 32 C H A P T E R 2 Logic Functions and Gates and limits power supply current in the LOW state. Figure 2.9b shows the voltage levels when the switch is closed and when it is open. Figure 2.10 shows how pushbuttons can be used as logic inputs. Figure 2.10a shows a normally open pushbutton and a pull-up resistor. The pushbutton has a spring-loaded plunger that makes a connection between two internal contacts when pressed. When released, the spring returns the plunger to the normal (open) state. The logic voltage at X is normally HIGH, but LOW when the button is pressed. Vcc Press Release 1 X 0 a. Normally open pushbutton Press X Release 1 0 b. Normally closed pushbutton Vcc COM Press Release X N.C. N.O. X Vcc Y Y c. Two-pole pushbutton FIGURE 2.10 Pushbuttons as Logic Switches Figure 2.10b shows a normally closed pushbutton. The internal spring holds the plunger so that the connection is normally made between the two contacts. When the button is pressed, the connection is broken and the resistor pulls up the voltage at X to a logic HIGH. At rest, X is grounded and the voltage at X is LOW. It is sometimes desirable to have normally HIGH and normally LOW levels available from the same switch. The two-pole pushbutton in Figure 2.10c provides such a function. The switch has a normally open and a normally closed contact. One contact of each switch is connected to the other, in an internal COMMON connection, allowing the switch to have three terminals rather than four. The circuit has two pull-up resistors, one for X and one for Y. X is normally HIGH and goes LOW when the switch is pressed. Y is opposite. LED Indicators KEY TERMS LED Light-emitting diode. An electronic device that conducts current in one direction only and illuminates when it is conducting. 2.2 Logic Switches and LED Indicators 33 A device used to indicate the status of a digital output is the light-emitting diode or LED. This is sometimes pronounced as a word (led) and sometimes said as separate initials (ell ee dee). This device comes in a variety of shapes, sizes, and colors, some of which are shown in the photo of Figure 2.11. The circuit symbol, shown in Figure 2.12, has two terminals, called the anode (positive) and cathode (negative). The arrow coming from the symbol indicates emitted light. FIGURE 2.11 LEDs Anode Cathode FIGURE 2.12 Light-Emitting Diode (LED) 470 Vcc FIGURE 2.13 Condition for LED Illumination FIGURE 2.14 AND Gate Driving an LED The electrical requirements for the LED are simple: current ows through the LED if the anode is more positive than the cathode by more than a specied value (about 1.5 volts). If enough current ows, the LED illuminates. If more current ows, the illumination is brighter. (If too much ows, the LED burns out, so a series resistor is used to keep the current in the required range.) Figure 2.13 shows a circuit in which an LED illuminates when a switch is closed. Figure 2.14 shows an AND gate driving an LED. In Figure 2.14a, the LED is on when Y is HIGH (5 volts), since the anode of the LED is more positive than the cathode. A B Y 470 a. LED on when Y is HIGH Vcc 470 A B Y b. LED on when Y is LOW 34 C H A P T E R 2 Logic Functions and Gates Vcc Vcc 470 S1 1k FIGURE 2.15 LED Indicates Status of Switch In Figure 2.14b, the LED turns on when Y is LOW (0 volts), again since the anode is more positive than the cathode. Figure 2.15 shows a circuit in which an LED indicates the status of a logic switch. When the switch is open, the 1 k pull-up applies a HIGH to the inverter input. The inverter output is LOW, turning on the LED (anode is more positive than cathode). When the switch is closed, the inverter input is LOW. The inverter output is HIGH (same value as VCC), making anode and cathode voltages equal. No current ows through the LED, and it is therefore off. Thus, the LED is on for a HIGH state at the switch and off for a LOW. Note, however, that the LED is on when the inverter output is LOW. SECTION 2.2 REVIEW PROBLEM 2.3 A single-pole single-throw switch is connected such that one end is grounded and one end is connected to a 1 k pull-up resistor. The other end of the resistor connects to the circuit power supply, VCC. What logic level does the switch provide when it is open? When it is closed? 2.3 Derived Logic Functions KEY TERMS NAND gate A logic circuit whose output is LOW when all inputs are HIGH. NOR gate A logic circuit whose output is LOW when at least one input is HIGH. Exclusive OR gate A 2-input logic circuit whose output is HIGH when one input (but not both) is HIGH. Exclusive NOR gate A 2-input logic circuit whose output is the complement of an Exclusive OR gate. Coincidence gate An Exclusive NOR gate. The basic logic functions, AND, OR, and NOT, can be combined to make any other logic function. Special logic gates exist for several of the most common of these derived functions. In fact, for reasons we will discover later, two of these derived-function gates, NAND and NOR, are the most common of all gates, and each can be used to create any logic function. NAND and NOR Functions The names NAND and NOR are contractions of NOT AND and NOT OR, respectively. The NAND is generated by inverting the output of an AND function. The symbols for the NAND gate and its equivalent circuit are shown in Figure 2.16. The algebraic expression for the NAND function is: Y AB 2.3 Derived Logic Functions 35 FIGURE 2.16 NAND Gate Symbols Table 2.6 NAND Function Truth Table A B Y 0 0 1 1 0 1 0 1 1 1 1 0 The entire function is inverted because the bubble is on the NAND gate output. Table 2.6 shows the NAND gate truth table. The output is LOW when A AND B are HIGH. We can generate the NOR function by inverting the output of an OR gate. The NOR function truth table is shown in Table 2.7. The truth table tells us that the output is LOW when A OR B is HIGH. Figure 2.17 shows the logic symbols for the NOR gate. Table 2.7 NOR Function Truth Table A B Y 0 0 1 1 0 1 0 1 1 0 0 0 FIGURE 2.17 NOR Gate Symbols The algebraic expression for the NOR function is: Y A B The entire function is inverted because the bubble is on the gate output. We know that the outputs of both gates are active LOW because of the bubbles on the output terminals. The inputs are active HIGH because there are no bubbles on the input terminals. Multiple-Input NAND and NOR Gates Table 2.8 shows the truth tables of the 3-input NAND and NOR functions. The logic circuit symbols for these gates are shown in Figure 2.18. Table 2.8 3-input NAND and NOR Function Truth Tables A B C ABC 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 A B C 1 0 0 0 0 0 0 0 The truth tables of these gates can be generated by understanding the active levels of the gate inputs and outputs. The NAND output is LOW when A AND B AND C are HIGH. This is shown in the last line of the NAND truth table. The NOR output is LOW if one or more of A OR B OR C is HIGH. This describes all lines of the NOR truth table except the rst. 36 C H A P T E R 2 Logic Functions and Gates FIGURE 2.18 3-Input NAND and NOR Gates Exclusive OR and Exclusive NOR Functions The Exclusive OR function (abbreviated XOR) is a special case of the OR function. The output of a 2-input XOR gate is HIGH when one and only one of the inputs is HIGH. (Multiple-input XOR circuits do not expand as simply as other functions. As we will see in a later chapter, an XOR output is HIGH when an odd number of inputs is HIGH.) Unlike the OR gate, which is sometimes called an Inclusive OR, a HIGH at both inputs makes the output LOW. (We could say that the case in which both inputs are HIGH is excluded.) The gate symbol for the Exclusive OR gate is shown in Figure 2.19. FIGURE 2.19 Exclusive OR Gate Table 2.9 Exclusive OR Function Truth Table A B Y 0 0 1 1 0 1 0 1 0 1 1 0 Table 2.9 shows the truth table for the XOR function. Another way of looking at the Exclusive OR gate is that its output is HIGH when the inputs are different and LOW when they are the same. This is a useful property in some applications, such as error detection in digital communication systems. (Transmitted data can be compared with received data. If they are the same, no error has been detected.) The XOR function is expressed algebraically as: Y A B The Exclusive NOR function is the complement of the Exclusive OR function and shares some of the same properties. The symbol, shown in Figure 2.20, is an XOR gate FIGURE 2.20 Exclusive NOR Gate 2.4 Table 2.10 Exclusive NOR Function Truth Table A B Y 0 0 1 1 0 1 0 1 1 0 0 1 DeMorgans Theorems and Gate Equivalence 37 with a bubble on the output, implying that the entire function is inverted. Table 2.10 shows the Exclusive NOR truth table. The algebraic expression for the Exclusive NOR function is: Y A B The output of the Exclusive NOR gate is HIGH when the inputs are the same and LOW when they are different. For this reason, the XNOR gate is also called a coincidence gate. This same/different property is similar to that of the Exclusive OR gate, only opposite in sense. Many of the applications that make use of this property can use either the XOR or the XNOR gate. SECTION 2.3 REVIEW PROBLEMS The output of a logic gate turns on an LED when it is HIGH. The gate has two inputs, each of which is connected to a logic switch, as shown in Figure 2.21. Vcc A Vcc Logic gate Y B FIGURE 2.21 Section Review Problems: Logic Gate Properties 2.4 2.5 2.6 2.7 What type of gate will turn on the light when the switches are in opposite positions? Which gate will turn off the light only when both switches are HIGH? What type of gate turns on the light only when both switches are LOW? Which gate turns on the light when the switches are in the same position? 2.4 DeMorgans Theorems and Gate Equivalence KEY TERMS DeMorgans theorems Two theorems in Boolean algebra that allow us to transform any gate from an AND-shaped to an OR-shaped gate and vice versa. DeMorgan equivalent forms Two gate symbols, one AND-shaped and one ORshaped, that are equivalent according to DeMorgans theorems. Table 2.11 NAND Truth Table A B Y 0 0 1 1 0 1 0 1 1 1 1 0 Recall the truth table (repeated in Table 2.11) and description of a 2-input NAND gate. Output Y is LOW if inputs A AND B are HIGH. Or, Output Y is LOW if all inputs are HIGH. The condition of this sentence is satised in the last line of Table 2.11. We could also describe the gate function by saying, Output Y is HIGH if A OR B (OR both) are LOW, or, The output is HIGH if at least one input is LOW. These conditions are satised by the rst three lines of Table 2.11. The gates in Figure 2.22 represent positive- and negative-logic forms of a NAND gate. Figure 2.23 shows the logic equivalents of these gates. In the rst case, we combine the in- 38 C H A P T E R 2 Logic Functions and Gates FIGURE 2.22 NAND Gate and DeMorgan Equivalent A B AB AB A A A B B B a. AND then invert b. Invert then OR FIGURE 2.23 Logic Equivalents of Positive and Negative NAND Gates puts in an AND function, then invert the result. In the second case, we invert the variables, then combine the inverted inputs in an OR function. The Boolean function for the AND-shaped gate is given by: Y AB The Boolean expression for the OR-shaped gate is: Y A B The gates shown in Figure 2.22 are called DeMorgan equivalent forms. Both gates have the same truth table, but represent different aspects or ways of looking at the NAND function. We can extend this observation to state that any gate (except XOR and XNOR) has two equivalent forms, one AND, one OR. A gate can be categorized by examining three attributes: shape, input, and output. A question arises from each attribute: 1. What is its shape (AND/OR)? AND: all OR: at least one 2. What active level is at the gate inputs (HIGH/LOW)? 3. What active level is at the gate output (HIGH/LOW)? The answers to these questions characterize any gate and allow us to write a descriptive sentence and a truth table for that gate. The DeMorgan equivalent forms of the gate will yield opposite answers to each of the above questions. Thus the gates in Figure 2.22 have the following complementary attributes: Boolean Expression Shape Input Active Level Output Active Level EXAMPLE 2.2 FIGURE 2.24 Example 2.2 Logic Gates Basic Gate AB AND HIGH LOW DeMorgan Equivalent AB OR LOW HIGH Analyze the shape, input, and output of the gates shown in Figure 2.24 and write a Boolean expression, a descriptive sentence, and a truth table of each one. Write an asterisk beside the active output level on each truth table. Describe how these gates relate to each other. Y A B Y A B a. b. 2.4 DeMorgans Theorems and Gate Equivalence 39 SOLUTION a. Boolean expression: Y A B Shape: OR (at least one) Input: HIGH Output: LOW Descriptive sentence: Output Y is LOW if A OR B is HIGH. Table 2.12 Truth Table Truth table: of Gate in Figure 2.24a. A B Y 0 0 1 1 0 1 0 1 1 0* 0* 0* b. Boolean expression: Y A B Shape: AND (all) Input: LOW Output: HIGH Descriptive sentence: Output Y is HIGH if A AND B are LOW. Truth table: Table 2.13 Truth Table of Gate in Figure 2.124b. A B Y 0 0 1 1 0 1 0 1 1* 0 0 0 Both gates in this example yield the same truth table. Therefore they are DeMorgan equivalents of one another (positive- and negative-NOR gates). The gates in Figures 2.22 and 2.24 yield the following algebraic equivalencies: AB A B A B AB These equivalencies are known as DeMorgans theorems. (You can remember how to use DeMorgans theorems by a simple rhyme: Break the line and change the sign.) It is tempting to compare the rst gate in Figure 2.22 and the second in Figure 2.24 and declare them equivalent. Both gates are AND-shaped, both have inversions. However, the comparison is false. The gates have different truth tables, as we have found in Tables 2.11 and 2.13. Therefore they have different logic functions and are not equivalent. The same is true of the OR-shaped gates in Figures 2.22 and 2.24. The gates may look similar, but since they have different truth tables, they have different logic functions and are therefore not equivalent. The confusion arises when, after changing the logic input and output levels, you forget to change the shape of the gate. This is a common, but serious, error. These inequalities can be expressed as follows: AB AB AB AB 40 C H A P T E R 2 Logic Functions and Gates As previously stated, any AND- or OR-shaped gate can be represented in its DeMorgan equivalent form. All we need to do is analyze a gate for its shape, input, and output, then change everything. EXAMPLE 2.3 Analyze the gate in Figure 2.25 and write a Boolean expression, descriptive sentence, and truth table for the gate. Mark active output levels on the truth table with asterisks. Find the DeMorgan equivalent form of the gate and write its Boolean expression and description. FIGURE 2.25 Example 2.3: Logic Gates A B C Y SOLUTION Boolean expression: Y A Shape: OR (at least one) Input: LOW Output: LOW B C Descriptive sentence: Output Y is LOW if A OR B OR C is LOW. Truth table: Table 2.14 Truth Table of Gate in Figure 2.25 A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0* 0* 0* 0* 0* 0* 0* 1 Figure 2.26 shows the DeMorgan equivalent form of the gate in Figure 2.25. To create this symbol, we change the shape from OR to AND and invert the logic levels at both input and output. FIGURE 2.26 Example 2.3: DeMorgan Equivalent of Gate in Figure 2.25 A B C Y Boolean expression: Y ABC Descriptive sentence: Output Y is HIGH if A AND B AND C are HIGH. SECTION 2.4 REVIEW PROBLEM 2.8 The output of a gate is described by the following Boolean expression: Y A B C D Write the Boolean expression for the DeMorgan equivalent form of this gate. 2.5 Enable and Inhibit Properties of Logic Gates 41 2.5 Enable and Inhibit Properties of Logic Gates KEY TERMS Digital signal (or pulse waveform) A series of 0s and 1s plotted over time. True form Not inverted. Complement form Inverted. Enable A logic gate is enabled if it allows a digital signal to pass from an input to the output in either true or complement form. Inhibit (or disable) A logic gate is inhibited if it prevents a digital signal from passing from an input to the output. In phase Two digital waveforms are in phase if they are always at the same logic level at the same time. Out of phase Two digital waveforms are out of phase if they are always at opposite logic levels at any given time. In Chapter 1, we saw that a digital signal is just a string of bits (0s and 1s) generated over time. A major task of digital circuitry is the direction and control of such signals. Logic gates can be used to enable (pass) or inhibit (block) these signals. (The word gate gives a clue to this function; the gate can open to allow a signal through or close to block its passage.) AND and OR Gates The simplest case of the enable and inhibit properties is that of an AND gate used to pass or block a logic signal. Figure 2.27 shows the output of an AND gate under different conditions of input A when a digital signal (an alternating string of 0s and 1s) is applied to input B. FIGURE 2.27 Enable/Inhibit Properties of an AND Gate Recall the properties of an AND gate: both inputs must be HIGH to make the output HIGH. Thus, if input A is LOW, the output must always be LOW, regardless of the state of input B. The digital signal applied to B has no effect on the output, and we say that the gate is inhibited or disabled. This is shown in the rst half of the timing diagram in Figure 2.27. If A AND B are HIGH, the output is HIGH. When A is HIGH and B is LOW, the output is LOW. Thus, output Y is the same as input B if input A is HIGH; that is, Y and B are in phase with each other. The input waveform is passed to the output in true form, and we say the gate is enabled. The last half of the timing diagram in Figure 2.27 shows this waveform. It is convenient to dene terms for the A and B inputs. Since we apply a digital signal to B, we will call it the Signal input. Since input A controls whether or not the signal 42 C H A P T E R 2 Logic Functions and Gates passes to the output, we will call it the Control input. These denitions are illustrated in Figure 2.28. FIGURE 2.28 Control and Signal Inputs of an AND Gate Table 2.15 AND Truth Table Showing Enable/Inhibit Properties A B Y 0 0 0 1 0 0 (Y 0) Inhibit 1 1 0 1 0 1 (Y B) Enable EXAMPLE 2.4 Each type of logic gate has a particular set of enable/inhibit properties that can be predicted by examining the truth table of the gate. Let us examine the truth table of the AND gate to see how the method works. Divide the truth table in half, as shown in Table 2.15. Since we have designated A as the Control input, the top half of the truth table shows the inhibit function (A 0), and the bottom half shows the enable function (A 1). To determine the gate properties, we compare input B (the Signal input) to the output in each half of the table. Inhibit mode: If A 0 and B is pulsing (B is continuously going back and forth between the rst and second lines of the truth table), output Y is always 0. Since the Signal input has no effect on the output, we say that the gate is disabled or inhibited. Enable mode: If A 1 and B is pulsing (B is going continuously between the third and fourth lines of the truth table), the output is the same as the Signal input. Since the Signal input affects the output, we say that the gate is enabled. Use the method just described to draw the output waveform of an OR gate if the input waveforms of A and B are the same as in Figure 2.27. Indicate the enable and inhibit portions of the timing diagram. SOLUTION Divide the OR gate truth table in half. Designate input A the Control input and input B the Signal input. As shown in Table 2.16, when A 0 and B is pulsing, the output is the same as B and the gate is enabled. When A 1, the output is always HIGH. (At least one input HIGH makes the output HIGH.) Since B has no effect on the output, the gate is inhibited. This is shown in Figure 2.29 in graphical form. Table 2.16 OR Truth Table Showing Enable/Inhibit Properties A B Y 0 0 0 1 0 1 (Y B) Enable 1 1 0 1 1 1 (Y 1) Inhibit 2.5 Enable and Inhibit Properties of Logic Gates FIGURE 2.29 Example 2.4 OR Gate Enable/Inhibit Waveform 43 Example 2.4 shows that a gate can be in the inhibit state even if its output is HIGH. It is natural to think of the HIGH state as ON, but this is not always the case. Enable or inhibit states are determined by the effect the Signal input has on the gates output. If an input signal does not affect the gate output, the gate is inhibited. If the Signal input does affect the output, the gate is enabled. NAND and NOR Gates When inverting gates, such as NAND and NOR, are enabled, they will invert an input signal before passing it to the gate output. In other words, they transmit the signal in complement form. Figures 2.30 and 2.31 show the output waveforms of a NAND and a NOR gate when a square waveform is applied to input B and input A acts as a Control input. FIGURE 2.30 Enable/Inhibit Properties of a NAND Gate FIGURE 2.31 Enable/Inhibit Properties of a NOR Gate 44 C H A P T E R 2 Logic Functions and Gates Table 2.17 NAND Truth Table Showing Enable/Inhibit Properties A B Y 0 0 0 1 1 1 (Y 1) Inhibit 1 1 0 1 1 0 (Y B) Enable Table 2.18 NOR Truth Table Showing Enable/Inhibit Properties A B Y 0 0 0 1 1 0 0 1 0 0 Exclusive OR and Exclusive NOR Gates Neither the XOR nor the XNOR gate has an inhibit state. The Control input on both of these gates acts only to determine whether the output waveform will be in or out of phase with the input signal. Figure 2.32 shows the dynamic properties of an XOR gate. (Y B) Enable 1 1 The truth table for the NAND gate is shown in Table 2.17, divided in half to show the enable and inhibit properties of the gate. Table 2.18 shows the NOR gate truth table, divided in half to show its enable and inhibit properties. Figures 2.30 and 2.31 show that when the NAND and NOR gates are enabled, the Signal and output waveforms are opposite to one another; we say that they are out of phase. Compare the enable/inhibit waveforms of the AND, OR, NAND, and NOR gates. Gates of the same shape are enabled by the same Control level. AND and NAND gates are enabled by a HIGH on the Control input and inhibited by a LOW. OR and NOR are the opposite. A HIGH Control input inhibits the OR/NOR; a LOW Control input enables the gate. (Y 0) Inhibit FIGURE 2.32 Dynamic Properties of an Exclusive OR Gate Table 2.19 XOR Truth Table Showing Dynamic Properties A B Y 0 0 0 1 0 1 (Y B) Enable 1 1 0 1 1 0 (Y B) Enable The truth table for the XOR gate, showing the gates dynamic properties, is given in Table 2.19. Notice that when A 0, the output is in phase with B and when A 1, the output is out of phase with B. A useful application of this property is to use an XOR gate as a programmable inverter. When A 1, the gate is an inverter; when A 0, it is a noninverting buffer. The XNOR gate has properties similar to the XOR gate. That is, an XNOR has no inhibit state, and the Control input switches the output in and out of phase with the Signal waveform, although not the same way as an XOR gate does. You will derive these properties in one of the end-of-chapter problems. Table 2.20 summarizes the enable/inhibit properties of the six gates examined above. Table 2.20 Summary of Enable/Inhibit Properties Control AND OR A A Y Y Y Y 0 1 0 B NAND B 1 NOR XOR XNOR Y Y Y Y Y Y Y Y 1 B B 0 B B B B SECTION 2.5 REVIEW PROBLEM 2.9 Briey explain why an AND gate is inhibited by a LOW Control input and an OR gate is inhibited by a HIGH Control input. 2.5 Enable and Inhibit Properties of Logic Gates 45 Tristate Buffers KEY TERMS Tristate buffer A gate having three possible output states: logic HIGH, logic LOW, and high-impedance. High-impedance state The output state of a tristate buffer that is neither logic HIGH nor logic LOW, but is electrically equivalent to an open circuit. Bus A common wire or parallel group of wires connecting multiple circuits. IN OUT OE a. Noninverting IN OUT OE b. Inverting FIGURE 2.33 Tristate Buffers FIGURE 2.34 Electrical Equivalent of Tristate Operation In the previous section, logic gates were used to enable or inhibit signals in digital circuits. In the AND, NAND, NOR, and OR gates, however, the inhibit state was always logic HIGH or LOW. In some cases, it is desirable to have an output state that is neither HIGH nor LOW, but acts to electrically disconnect the gate output from the circuit. This third state is called the high-impedance state and is one of three available states in a class of devices known as tristate buffers. Figure 2.33 shows the logic symbols for two tristate buffers, one with a noninverting output and one with an inverting output. The third input, OE (Output enable), is an activeLOW signal that enables or disables the buffer output. When OE 0, as shown in Figure 2.34a, the noninverting buffer transfers the input value directly to the output as a logic HIGH or LOW. When OE 1, as in Figure 2.34b, the output is electrically disconnected from any circuit to which it is connected. (The open switch in Figure 2.34b does not literally exist. It is shown as a symbolic representation of the electrical disconnection of the output in the high-impedance state.) IN OUT OE IN OUT IN OE 0 a. Output enabled HI-Z 1 b. Output disabled This type of enable/disable function is particularly useful when digital data are transferred from more than one source to one or more destinations along a common wire (or bus), as shown in Figure 2.35. (This is the underlying principle in modern computer systems, where multiple components use the same bus to pass data back and forth.) The destination circuit in Figure 2.35 can receive data from source 1 or source 2. If the source circuits were directly connected to the bus, they could produce contradictory logic levels at the destination. To prevent this, only one source is enabled at a time, with control of this switching left to the two tristate buffers. FIGURE 2.35 Using Tristate Buffers to Switch Two Sources to a Single Destination Digital source 1 OE1 Digital source 2 OE2 Bus Destination 46 C H A P T E R 2 Logic Functions and Gates 2.6 Integrated Circuit Logic Gates KEY TERMS Integrated circuit (IC) An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package. Small scale integration (SSI) An integrated circuit having 12 or fewer gates in one package. Medium scale integration (MSI) An integrated circuit having the equivalent of 12 to 100 gates in one package. Large scale integration (LSI) An integrated circuit having from 100 to 10,000 equivalent gates. Very large scale integration (VLSI) An integrated circuit having more than 10,000 equivalent gates. Transistor-transistor logic (TTL) A family of digital logic devices whose basic element is the bipolar junction transistor. Complementary metal-oxide-semiconductor (CMOS) A family of digital logic devices whose basic element is the metal-oxide-semiconductor eld effect transistor (MOSFET). Chip An integrated circuit. Specically, a chip of silicon on which an integrated circuit is constructed. Dual in-line package (DIP) A type of IC with two parallel rows of pins for the various circuit inputs and outputs. Printed circuit board (PCB) A circuit board in which connections between components are made with lines of copper on the surfaces of the circuit board. Breadboard A circuit board for wiring temporary circuits, usually used for prototypes or laboratory work. Wire-wrap A circuit construction technique in which the connecting wires are wrapped around the posts of a special chip socket, usually used for prototyping or laboratory work. Through-hole A means of mounting DIP ICs on a circuit board by inserting the IC leads through holes in the board and soldering them in place. Surface-mount technology (SMT) A system of mounting and soldering integrated circuits on the surface of a circuit board, as opposed to inserting their leads through holes on the board. Small outline IC (SOIC) An IC package similar to a DIP, but smaller, which is designed for automatic placement and soldering on the surface of a circuit board. Also called gull-wing, for the shape of the package leads. Thin shrink small outline package (TSSOP) A thinner version of an SOIC package. Plastic leaded chip carrier (PLCC) A square IC package with leads on all four sides designed for surface mounting on a circuit board. Also called J-lead, for the prole shape of the package leads. Quad at pack (QFP) A square surface-mount IC package with gull-wing leads. Ball grid array (BGA) A square surface-mount IC package with rows and columns of spherical leads underneath the package. Data sheet A printed specication giving details of the pin conguration, electrical properties, and mechanical prole of an electronic device. Data book A bound collection of data sheets. A digital logic data book usually contains data sheets for a specic logic family or families. Portable document format (PDF) A format for storing published documents in compressed form. 2.6 Integrated Circuit Logic Gates 47 All the logic gates we have looked at so far are available in integrated circuit form. Most of these small scale integration (SSI) functions are available either in transistortransistor logic (TTL) or complementary metal-oxide-semiconductor (CMOS) technologies. TTL and CMOS devices differ not in their logic functions, but in their construction and electrical characteristics. TTL and CMOS chips are designated by an industry-standard numbering system. TTL devices and the more recent members of the CMOS family are numbered according to the general format 74XXNN, where XX is a family identier and NN identies the specic logic function. For example, the number 74ALS00 represents a quadruple 2-input NAND device (indicated by 00) in the advanced low power Schottky (ALS) family of TTL. (Earlier versions of CMOS had a different set of unrelated numbers of the form 4NNNB or 4NNNUB where NNN was the logic function designator. The sufxes B and UB stand for buffered and unbuffered, respectively.) Table 2.21 lists the quadruple 2-input NAND function as implemented in different logic families. These devices all have the same logic function, but different electrical characteristics. Table 2.21 Part Numbers for a Quad 2-input NAND Gate in Different Logic Families Part Number Logic Family 74LS00 74ALS00 74F00 74HC00 74HCT00 74LVX00 74ABT00 Low-power Schottky TTL Advanced low-power Schottky TTL FAST TTL High-speed CMOS High-speed CMOS (TTL-compatible inputs) Low-voltage CMOS Advanced BiCMOS (TTL/CMOS hybrid) Table 2.22 lists several logic functions available in the high-speed CMOS family. These devices all have the same electrical characteristics, but different logic functions. Table 2.22 Part Numbers for Different Functions within a Logic Family (High-Speed CMOS) Part Number Function 74HC00 74HC02 74HC04 74HC08 74HC32 74HC86 Quadruple 2-input NAND Quadruple 2-input NOR Hex inverter Quadruple 2-input AND Quadruple 2-input OR Quadruple 2-input XOR Until recently, the most common way to package logic gates has been in a plastic or ceramic dual in-line package, or DIP, which has two parallel rows of pins. The standard spacing between pins in one row is 0.1 (or 100 mil). For packages having fewer than 28 pins, the spacing between rows is 0.3 (or 300 mil). For larger packages, the rows are spaced by 0.6 (600 mil). This type of package is designed to be inserted in a printed circuit board in one of two says: (a) the pins are inserted through holes in the circuit board and soldered in place; or (b) a socket is soldered to the circuit board and the IC is placed in the socket. The latter method is more expensive, but makes chip replacement much easier. A socket can occasionally cause its own problems by making a poor connection to the pins of the IC. The DIP is also convenient for laboratory and prototype work, since it can also be inserted easily into a breadboard, a special type of temporary circuit board with internal connections between holes of a standard spacing. It is also convenient for wire-wrapping, a technique in which a special tool is used to wrap wires around posts on the underside of special sockets. 48 C H A P T E R 2 Logic Functions and Gates FIGURE 2.36 14-Pin DIP (Top View) The outline of a 14-pin DIP is shown in Figure 2.36. There is a notch on one end to show the orientation of the pins. When the IC is oriented as shown and viewed from above, pin 1 is at the top left corner and the pins number counterclockwise from that point. Besides DIP packages, there are numerous other types of packages for digital ICs, including, among others, small outline IC (SOIC), thin shrink small outline package (TSSOP), plastic leaded chip carrier (PLCC), quad at pack (QFP), and ball grid array (BGA) packages. They are used mostly in applications where circuit board space is at a premium and in manufacturing processes relying on surface-mount technology (SMT). In fact, these devices represent the majority of IC packages found in new designs. Some of these IC packaging options are shown in Figure 2.37. a. b. d. c. e. FIGURE 2.37 Some IC Packaging Options SMT is a sophisticated technology which relies on automatic placement of chips and soldering of pins onto the surface of a circuit board, not through holes in the circuit board. This technique allows a manufacturer to mount components on both sides of a circuit board. 2.6 Integrated Circuit Logic Gates 49 Primarily due to the great reduction in board space requirements, most new ICs are available only in the newer surface-mount packages and are not being offered at all in the DIP package. However, we will look at DIP offerings in logic gates because they are inexpensive and easy to use with laboratory breadboards and therefore useful as a learning tool. Logic gates come in packages containing several gates. Common groupings available in DIP packages are six 1-input gates, four 2-input gates, three 3-input gates, or two 4-input gates, although other arrangements are available. The usual way of stating the number of logic gates in a package is to use the numerical prexes hex (6), quad or quadruple (4), triple (3), or dual (2). Some common gate packages are listed in Table 2.23. Table 2.23 Some Common Logic Gate ICs Gate Family Function 74HC00A 74HC02 74ALS04 74LS11 74F20 74HC27 High-speed CMOS High-speed CMOS Advanced low-power Schottky TTL Low-power Schottky TTL FAST TTL High-speed CMOS Quad 2-input NAND Quad 2-input NOR Hex inverter Triple 3-input AND Dual 4-input NAND Triple 3-input NOR Information about pin congurations, electrical characteristics, and mechanical specications of a part is available in a data sheet provided by the chip manufacturer. A collection of data sheets for a particular logic family is often bound together in a data book. More recently, device manufacturers have been making data sheets available on their corporate World Wide Web sites in portable document format (PDF), readable by a special program such as Adobe Acrobat Reader. Links to some of these manufacturers can be found on the Online Companion Web site for this book. (http://www.electronictech.com) Figure 2.38 shows the internal diagrams of gates listed in Table 2.23. Notice that the gates can be oriented inside a chip in a number of ways. That is why it is important to conrm pin connections with a data sheet. In addition to the gate inputs and outputs there are two more connections to be made on every chip: the power (VCC) and ground connections. In TTL, connect VCC to 5 Volts and GND to ground. In CMOS, connect the VCC pin to the supply voltage ( 3 V to 6 V) and GND to ground. The gates wont work without these connections. Every chip requires power and ground. This might seem obvious, but its surprising how often it is forgotten, especially by students who are new to digital electronics. Probably this is because most digital circuit diagrams dont show the power connections, but assume that you know enough to make them. The only place a chip gets its required power is through the VCC pin. Even if the power supply is connected to a logic input as a logic HIGH, you still need to connect it to the power supply pin. Even more important is a good ground connection. A circuit with no power connection will not work at all. A circuit without a ground may appear to work, but it will often produce bizarre errors that are very difcult to detect and repair. In later chapters, we will work primarily with complex ICs in PLCC packages. The power and ground connections are so important to these chips that they will not be left to chance; they are provided on a specially designed circuit board. Only input and output pins are accessible for connection by the user. As digital designs become more complex, it is increasingly necessary to follow good practices in board layout and prototyping procedure to ensure even minimal functionality. 50 C H A P T E R 2 Logic Functions and Gates Vcc Vcc 14 13 12 11 10 9 1 2 3 4 5 8 67 Vcc 14 13 12 11 10 9 1 2 74HC00A 4 5 67 14 13 12 11 10 9 3 4 5 1 2 8 67 4 5 67 Vcc 14 13 12 11 10 9 1 3 8 74ALS04 Vcc 2 14 13 12 11 10 9 74HC02A Vcc 1 3 8 2 3 74LS11 4 5 8 67 14 13 12 11 10 9 1 74F20 2 3 4 5 8 67 74HC27 FIGURE 2.38 Pinouts of ICs Listed in Table 2.23 Thus, hardware platforms for prototype and laboratory work will need to be at least partially constructed by the board manufacturer in order to supply the requirements of a stable circuit conguration. SECTION REVIEW PROBLEM FOR SECTION 2.6 2.10. How are the pins numbered in a dual in-line package? SUMMARY 1. Digital systems can be analyzed and designed using Boolean algebra, a system of mathematics that operates on variables that have one of two possible values. 2. Any Boolean expression can be constructed from the three simplest logic functions: NOT, AND, and OR. 3. A NOT gate, or inverter, has an output state that is in the opposite logic state of the input. 4. The main 2-input logic functions are described as follows, for inputs A and B and output Y: AND: Y is HIGH if A AND B are HIGH. (Y A B) OR: Y is HIGH if A OR B is HIGH. (Y A B) NAND: Y is LOW if A AND B are HIGH. (Y A B) NOR: Y is LOW if A OR B is HIGH. (Y A B) XOR: Y is HIGH if A OR B is HIGH, but not if both are HIGH. (Y A B) XNOR: Y is LOW if A OR B is HIGH, but not if both are HIGH. (Y A B) 5. The function of a logic gate can be represented by a truth table, a list of all possible inputs in binary order and the output corresponding to each input state. 6. DeMorgans theorems (A B A B and A B A B) allow us to represent any gate in an AND form and an OR form. 7. To change a gate into its DeMorgan equivalent form, change its shape from AND to OR or vice versa and change the active levels of inputs and output. Glossary 8. A logic switch can be created from a single-pole singlethrow switch by grounding one end and tying the other end to VCC through a pull-up resistor. The logic level is available on the same side of the switch as the resistor. An open switch is HIGH and a closed switch is LOW. A similar circuit can be made with a pushbutton switch. 9. A light emitting diode (LED) can be used to indicate logic HIGH or LOW levels. To indicate a HIGH, ground the cathode through a series resistor (about 470 for a 5-volt power supply) and apply the logic level to the anode. To indicate a LOW, tie the anode to VCC through a series resistor and apply the logic level to the cathode. 10. Logic gates can be used to pass or block digital signals. For example, an AND gate will pass a digital signal applied to input B if the input A is HIGH (Y B). If input A is LOW, the signal is blocked and the gate output is always LOW (Y 0). Similar properties apply to other gates, as summarized in Table 2.20. 11. Tristate buffers have outputs that generate logic HIGH and LOW when enabled and a high-impedance state when disabled. The high-impedance state is electrically equivalent to an open circuit. 51 12. Logic gates are available as integrated circuits in a variety of packages. Packages that have fewer than 12 gates are called small scale integration (SSI) devices. 13. Many logic functions have an industry-standard part number of the form 74XXNN, where XX is an alphabetic family designator and NN is a numeric function designator (e.g. 74HC02 Quadruple 2-input NOR gate in the high-speed CMOS family). 14. Some common IC packages include dual in-line package (DIP), small outline IC (SOIC), thin shrink small outline package (TSSOP), plastic leaded chip carrier (PLCC), quad at pack (QFP), and ball grid array (BGA) packages. 15. Most new IC packages are for surface mounting on a printed circuit board. These have largely replaced DIPs in throughhole circuit boards, due to better use of board space. 16. IC pin connections and functional data can be determined from manufacturers data sheets, available in paper format or electronically via the Internet. 17. All ICs require power and ground, which must be applied to special power supply pins on the chip. GLOSSARY Active HIGH An active-HIGH terminal is considered ON when it is in the logic HIGH state. Indicated by the absence of a bubble at the terminal in distinctive-shape symbols. Active level A logic level dened as the ON state for a particular circuit input or output. The active level can be either HIGH or LOW. Active LOW An active-LOW terminal is considered ON when it is in the logic LOW state. Indicated by a bubble at the terminal in distinctive-shape symbols. AND gate A logic circuit whose output is HIGH when all inputs (e.g., A AND B AND C) are HIGH. Ball grid array (BGA) A square surface-mount IC package with rows and columns of spherical leads underneath the package. Boolean algebra A system of algebra that operates on Boolean variables. The binary (two-state) nature of Boolean algebra makes it useful for analysis, simplication, and design of combinational logic circuits. Boolean expression An algebraic expression made up of Boolean variables and operators, such as AND ( ), OR ( ), or NOT ( ). Also referred to as a Boolean function or a logic function. Chip An integrated circuit. Specically, a chip of silicon on which an integrated circuit is constructed. Clock generator A circuit that generates a periodic digital waveform. Coincidence gate An Exclusive NOR gate. Complement form Inverted. Complementary metal-oxide-semiconductor (CMOS) A family of digital logic devices whose basic element is the metaloxide-semiconductor eld effect transistor (MOSFET). Data book A bound collection of data sheets. A digital logic data book usually contains data sheets for a specic logic family or families. Data sheet A printed specication giving details of the pin conguration, electrical properties, and mechanical prole of an electronic device. DeMorgan equivalent forms Two gate symbols, one ANDshaped and one OR-shaped, that are equivalent according to DeMorgans theorems. DeMorgans theorems Two theorems in Boolean algebra that allow us to transform any gate from an AND-shaped to an ORshaped gate and vice versa. Boolean variable A variable having only two possible values, such as HIGH/LOW, 1/0, On/Off, or True/False. Digital signal (or pulse waveform) A series of 0s and 1s plotted over time. Breadboard A circuit board for wiring temporary circuits, usually used for prototypes or laboratory work. Distinctive-shape symbols Graphic symbols for logic circuits that show the function of each type of gate by a special shape. Bubble A small circle indicating logical inversion on a circuit symbol. Dual in-line package (DIP) A type of IC with two parallel rows of pins for the various circuit inputs and outputs. Buffer An amplier that acts as a logic circuit. Its output can be inverting or noninverting. Enable A logic gate is enabled if it allows a digital signal to pass from an input to the output in either true or complement form. Bus A common wire or parallel group of wires connecting multiple circuits. Exclusive NOR gate A two-input logic circuit whose output is the complement of an Exclusive OR gate. 52 C H A P T E R 2 Logic Functions and Gates Exclusive OR gate A two-input logic circuit whose output is HIGH when one input (but not both) is HIGH. Portable document format (PDF) A format for storing published documents in compressed form. Floating An undened logic state, neither HIGH nor LOW. Printed circuit board (PCB) A circuit board in which connections between components are made with lines of copper on the surfaces of the circuit board. High-impedance state The output state of a tristate buffer that is neither logic HIGH nor logic LOW, but is electrically equivalent to an open circuit. IEEE/ANSI Standard 91-1984 A standard format for drawing logic circuit symbols as rectangles with logic functions shown by a standard notation inside the rectangle for each device. In phase Two digital waveforms are in phase if they are always at the same logic level at the same time. Inhibit (or disable) A logic gate is inhibited if it prevents a digital signal from passing from an input to the output. Integrated circuit (IC) An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package. Inverter Also called a NOT gate or an inverting buffer. A logic gate that changes its input logic level to the opposite state. Large scale integration (LSI) An integrated circuit having from 100 to 10,000 equivalent gates. LED Light emitting diode. An electronic device that conducts current in one direction only and illuminates when it is conducting. Logic function See Boolean expression. Logic gate An electronic circuit that performs a Boolean algebraic function. Logical product AND function. Logical sum OR function. Pull-up resistor A resistor connected from a point in an electronic circuit to the power supply of that circuit. In a digital circuit it supplies the required logic level in a HIGH state and limits current from the power supply in the LOW state. Quad at pack (QFP) A square surface-mount IC package with gull-wing leads. Qualifying symbol A symbol in IEEE/ANSI logic circuit notation, placed in the top center of a rectangular symbol, that shows the function of a logic gate. Some qualifying symbols include: 1 buffer; & AND; 1 OR Rectangular-outline symbols Rectangular logic gate symbols that conform to IEEE/ANSI Standard 91-1984. Small outline IC (SOIC) An IC package similar to a DIP, but smaller, which is designed for automatic placement and soldering on the surface of a circuit board. Also called gull-wing, for the shape of the package leads. Small-scale integration (SSI) An integrated circuit having 12 or fewer gates in one package. Surface-mount technology (SMT) A system of mounting and soldering integrated circuits on the surface of a circuit board, as opposed to inserting their leads through holes on the board. Thin shrink small outline package (TSSOP) A thinner version of an SOIC package. Medium scale integration (MSI) An integrated circuit having the equivalent of 12 to 100 gates in one package. Through-hole A means of mounting DIP ICs on a circuit board by inserting the IC leads through holes in the board and soldering them in place. NAND gate A logic circuit whose output is LOW when all inputs are HIGH. Transistor-transistor logic (TTL) A family of digital logic devices whose basic element is the bipolar junction transistor. NOR gate A logic circuit whose output is LOW when at least one input is HIGH. Tristate buffer A gate having three possible output states: logic HIGH, logic LOW, and high-impedance. OR gate A logic circuit whose output is HIGH when at least one input (e.g., A OR B OR C) is HIGH. True form Not inverted. Out of phase Two digital waveforms are out of phase if they are always at opposite logic levels at any given time. Plastic leaded chip carrier (PLCC) A square IC package with leads on all four sides designed for surface mounting on a circuit board. Also called J-lead, for the prole shape of the package leads. Truth table A list of all possible input values to a digital circuit, listed in ascending binary order, and the output response for each input combination. VCC The power supply voltage in a transistor-based electronic circuit. The term often refers to the power supply of digital circuits. Very large scale integration (VLSI) An integrated circuit having more than 10,000 equivalent gates. PROBLEMS Problem numbers set in color indicate more difcult problems: those with underlines indicate most difcult problems. 2.2 Draw the distinctive-shape and rectangular-outline symbols for a 3-input AND gate. Section 2.1 Basic Logic Functions 2.3 Draw the distinctive-shape and rectangular-outline symbols for a 3-input OR gate. 2.4 Write a sentence that describes the operation of a 4-input AND gate that has inputs P, Q, R, and S and output T. Make the truth table of this gate and draw an asterisk be- 2.1 Draw the symbol for the NOT gate (inverter) in both rectangular-outline and distinctive-shape forms. Problems 53 side the line(s) of the truth table indicating when the gate output is in its active state. 2.5 Write a sentence that describes the operation of a 4-input OR gate with inputs J, K, L, and M and output N. Make the truth table of this gate and draw an asterisk beside the line(s) of the truth table indicating when the gate output is in its active state. 2.6 State how three switches must be connected to represent a 3-input AND function. Draw a circuit diagram showing how this function can control a lamp. 2.7 State how four switches must be connected to represent a 4-input OR function. Draw a circuit diagram showing how this function can control a lamp. FIGURE 2.39 Problem 2.19: Temperature and Pressure Sensors 2.21 Section 2.2 Logic Switches and LED Indicators 2.8 Sketch the circuit of a single-pole single-throw (SPST) switch used as a logic switch. Briey explain how it works. 2.9 Refer to Figure 2.10 (logic pushbuttons). Should the normally open pushbutton be considered an active HIGH or active LOW device? Briey explain your choice. 2.10 Should the normally closed pushbutton be considered an active HIGH or active LOW device? Why? 2.11 Briey state what is required for an LED to illuminate. 2.12 Briey state the relationship between the brightness of an LED and the current owing through it. Why is a series resistor required? Figure 2.40 shows a circuit for a two-way switch for a stairwell. This is a common circuit that allows you to turn 2.13 FIGURE 2.40 Problem 2.21: Circuit for Two-Way Switch on a light from either the top or the bottom of the stairwell and off at the other end. The circuit also allows anyone coming along after you to do the same thing, no matter which direction they are coming from. Draw a circuit showing how an OR-gate output will illuminate an LED when the gate output is LOW. Assume the required series resistor is 470 . The lamp is ON when the switches are in the same positions and OFF when they are in opposite positions. What logic function does this represent? Draw the truth table of the function and use it to explain your reasoning. Section 2.3 Derived Logic Functions 2.14 For a 4-input NAND gate with inputs A, B, C, and D and output Y: a. Write the truth table and a descriptive sentence. 2.22 Find the truth table for the logic circuit shown in Figure 2.41. b. Write the Boolean expression. c. Draw the logic circuit symbol in both distinctiveshape and rectangular-outline symbols. 2.15 Repeat Problem 2.14 for a 4-input NOR gate. 2.16 State the active levels of the inputs and outputs of a NAND gate and a NOR gate. FIGURE 2.41 Problem 2.22: Logic Circuit 2.17 Write a descriptive sentence of the operation of a 5-input NAND gate with inputs A, B, C, D, and E and output Y. How many lines would the truth table of this gate have? 2.23 2.18 Repeat Problem 2.17 for a 5-input NOR gate. 2.19 A pump motor in an industrial plant will start only if the temperature and pressure of liquid in a tank exceed a certain level. The temperature sensor and pressure sensor, shown in Figure 2.39 each produce a logic HIGH if the measured quantities exceed this value. The logic circuit interface produces a HIGH output to turn on the motor. Draw the symbol and truth table of the gate that corresponds to the action of the logic circuit. 2.20 Repeat Problem 2.19 for the case in which the motor is activated by a logic LOW. Recall the description of a 2-input Exclusive OR gate: Output is HIGH if one input is HIGH, but not both. This is not the best statement of the operation of a multiple-input XOR gate. Look at the truth table derived in Problem 2.22 and write a more accurate description of ninput XOR operation. Section 2.4 DeMorgans Theorems and Gate Equivalence 2.24 For each of the gates in Figure 2.42: a. Write the truth table. b. Indicate with an * which lines on the truth table show the gate output in its active state. 54 C H A P T E R 2 Logic Functions and Gates A B C Y A B How does this compare to the waveform that would appear at the output of an Exclusive OR gate under the same conditions? Y a. b. 2.27 A B C Y A: 0000 0000 0000 1111 1111 1111 1111 0000 B: 1010 0111 0010 1011 0101 0011 1001 1011 c. A B Sketch the input waveforms represented by the following 32-bit sequences (use 1/4-inch graph paper, 1 square per bit): Assume that these waveforms represent inputs to a logic gate. (Spaces are provided for readability only.) Sketch the waveform for gate output Y if the gate function is: Y d. FIGURE 2.42 Problem 2.24: Logic Gates a. AND b. OR c. NAND c. Convert the gate to its DeMorgan equivalent form. d. NOR d. Rewrite the truth table and indicate which lines on the truth table show output active states for the DeMorgan equivalent form of the gate. e. XOR f. XNOR 2.28 Repeat Problem 2.27 for the waveforms shown in Figure 2.44. 2.29 The A and B waveforms shown in Figure 2.45 are inputs to an OR gate. Complete the sketch by drawing the waveform for output Y. 2.30 Repeat Problem 2.29 for a NOR gate. 2.31 Figure 2.46 shows a circuit that will make a lamp ash at 3 Hz when the gasoline level in a cars gas tank drops below a certain point. A oat switch in the tank monitors the level of gasoline. What logic level must the oat switch produce to make the light ash when the tank is approaching empty? Why? Section 2.5 Enable and Inhibit Properties of Logic Gates 2.32 Repeat Problem 2.31 for the case where the AND gate is replaced by a NOR gate. 2.26 Draw the output waveform of the Exclusive NOR gate when a square waveform is applied to one input and 2.33 Will the circuit in Figure 2.46 work properly if theAND gate is replaced by an Exclusive OR gate? Why or why not? a. The other input is held LOW 2.34 Make a truth table for the tristate buffers shown in Figure 2.33. Indicate the high-impedence state by the notation 2.25 Refer to Figure 2.43. State which two gates of the three shown are DeMorgan equivalents of each other. Explain your choice. X Y X Y X Y a. b. c. FIGURE 2.43 Problem 2.25: Logic Gates b. The other input is held HIGH FIGURE 2.44 Problem 2.28: Input Waveforms A B Y FIGURE 2.45 Problem 2.29: Waveforms Answers to Section Review Problems 55 Section 2.6 Integrated Circuit Logic Gates 2.35 2.36 List the industry-standard numbers for a quadruple 2-input NAND gate in low power Schottky TTL, CMOS, and high-speed CMOS technologies. 2.37 Repeat Problem 2.36 for a quadruple 2-input NOR gate. How does each numbering system differentiate between the NAND and NOR functions? 2.38 FIGURE 2.46 Problem 2.31: Gasoline Level Circuit Name two logic families used to implement digital logic functions. How do they differ? List six types of packaging that a logic gate could come in. Hi-Z How do the enable properties of these gates differ from gates such as AND and NAND? ANSWERS TO SECTION REVIEW PROBLEMS Section 2.1 Section 2.5 2.1 AND: A AND B AND C AND D must be HIGH to make Y HIGH. 2.2. OR: A OR B OR C OR D must be HIGH to make Y HIGH. 2.9 An AND needs two HIGH inputs to make a HIGH output. If the Control input is LOW, the output can never be HIGH; the output remains LOW. An OR output is HIGH if one input is HIGH. If the Control input is HIGH, the output is always HIGH, regardless of the level at the Signal input. In both cases, the output is stuck at one level, signifying that the gate is inhibited. Section 2.2 2.3 When the switch is open, it provides a logic HIGH because of the pull-up resistor. A closed switch is LOW, due to the connection to ground. Section 2.3 2.4 XOR; 2.5 NAND; Section 2.4 2.8 Y ABCD 2.6 NOR; 2.7 XNOR. Section 2.6 2.10 Viewed from above, with the notch in the package away from you, pin 1 is on the left side at the far end. The pins are numbered counterclockwise from that point. CHAPTER 3 Boolean Algebra and Combinational Logic OUTLINE CHAPTER OBJECTIVES 3.1 Upon successful completion of this chapter you will be able to: Explain the relationship between the Boolean expression, logic diagram, and truth table of a logic gate network and be able to derive any one from either of the other two. Draw logic gate networks in such a way as to cancel out internal inversions automatically (bubble-to-bubble convention). Write the sum of products (SOP) or product of sums (POS) forms of a Boolean equation. Use rules of Boolean algebra to simplify the Boolean expressions derived from logic diagrams and truth tables. Apply the Karnaugh map method to reduce Boolean expressions and logic circuits to their simplest forms. 3.2 3.3 3.4 3.5 Boolean Expressions, Logic Diagrams, and Truth Tables Sum-of-Products (SOP) and Productof-Sums (POS) Forms Theorems of Boolean Algebra Simplifying SOP and POS Expressions Simplication by the Karnaugh Map Method I n Chapter 3, we will examine the rudiments of combinational logic. A combinational logic circuit is one in which two or more gates are connected together to combine several Boolean inputs. These circuits can be represented several ways, as a logic diagram, truth table, or Boolean expression. A Boolean expression for a network of logic gates is often not in its simplest form. In such a case, we may be using more components than would be required for the job, so it is of benet to us if we can simplify the Boolean expression. Several tools are available to us, such as Boolean algebra and a graphical technique known as Karnaugh mapping. We can also simplify the Boolean expression by taking care to draw the logic diagrams in such a way as to automatically eliminate inverting functions within the circuit. I 57 58 C H A P T E R 3 Boolean Algebra and Combinational Logic 3.1 Boolean Expressions, Logic Diagrams and Truth Tables KEY TERMS Logic gate network Two or more logic gates connected together. Logic diagram A diagram, similar to a schematic, showing the connection of logic gates. Combinational logic Digital circuitry in which an output is derived from the combination of inputs, independent of the order in which they are applied. Combinatorial logic Another name for combinational logic. In Chapter 2, we examined the functions of single logic gates. However, most digital circuits require multiple gates. When two or more gates are connected together, they form a logic gate network. These networks can be described by a truth table, a logic diagram (i.e., a circuit diagram), or a Boolean expression. Any one of these can be derived from any other. A digital circuit built from gates is called a combinational (or combinatorial) logic circuit. The output of a combinational circuit depends on the combination of inputs. The inputs can be applied in any sequence and still produce the same result. For example, an AND gate output will always be HIGH if all inputs are HIGH, regardless of the order in which they became HIGH. This is in contrast to sequential logic, in which sequence matters; a sequential logic output may have a different value with two identical sets of inputs if those inputs were applied in a different order. We will study sequential logic in a later chapter. Boolean Expressions from Logic Diagrams KEY TERMS Bubble-to-bubble convention The practice of drawing gates in a logic diagram so that inverting outputs connect to inverting inputs and noninverting outputs connect to noninverting inputs. Order of precedence The sequence in which Boolean functions are performed, unless otherwise specied by parentheses. Writing the Boolean expression of a logic gate network is similar to nding the expression for a single gate. The difference is that in a multiple gate network, the inputs will usually not consist of single variables, but compound expressions that represent outputs of previous gates. These compound expressions are combined according to the same rules as single variables. In an OR gate, with inputs x and y, the output will always be x y regardless of whether x and y are single variables (e.g., x A, y B, output A B) or compound expressions (e.g., x AB, y AC, output AB AC ). Figure 3.1 shows a simple logic gate network, consisting of a single AND and a single OR gate. The AND gate combines inputs A and B to give the output expression AB. The OR combines the AND function and input C to yield the compound expression AB C. A B C FIGURE 3.1 Boolean Expression from a Gate Network AB Y AB C 3.1 EXAMPLE 3.1 Boolean Expressions, Logic Diagrams and Truth Tables 59 Derive the Boolean expression of the logic gate network shown in Figure 3.2a. FIGURE 3.2 Example 3.1 A B Y C D a. Logic gate network Solution AB A B Y AB CD CD C D b. Boolean expression from logic gate network Figure 3.2b shows the gate network with the output terms indicated for each gate. The AND and NAND functions are combined in an OR function to yield the output expression: Y AB CD The Boolean expression in Example 3.1 includes a NAND function. It is possible to draw the NAND in its DeMorgan equivalent form. If we choose the gate symbols so that outputs with bubbles connect to inputs with bubbles, we will not have bars over groups of variables, except possibly one bar over the entire function. In a circuit with many inverting functions (NANDs and NORs), this results in a cleaner notation and often a clearer idea of the function of the circuit. We will follow this notation, which we will refer to as the bubbleto-bubble convention, as much as possible. EXAMPLE 3.2 Redraw the circuit in Figure 3.2 to conform to the bubble-to-bubble convention. Write the Boolean expression of the new logic diagram. Solution AB A B C D Y C AB C D D FIGURE 3.3 Example 3.2 Using DeMorgan Equivalents to Simplify a Circuit Figure 3.3 shows the new circuit. The NAND has been converted to its DeMorgan equivalent so that its active-HIGH output drives an active-HIGH input on the OR gate. The new Boolean expression is Y AB C D. Boolean functions are governed by an order of precedence. Unless otherwise specied, AND functions are performed rst, followed by ORs. This order results in a form similar to that of linear algebra, where multiplication is performed before addition, unless otherwise specied. 60 C H A P T E R 3 Boolean Algebra and Combinational Logic Figure 3.4 shows two logic diagrams, one whose Boolean expression requires parentheses and one that does not. AB A B AB AC AC C a. No parentheses required (AND, then OR) A A B B (A C A B B) (A B C) C b. Parentheses required (OR, then AND) FIGURE 3.4 Order of Precedence The AND functions in Figure 3.4a are evaluated rst, eliminating the need for parentheses in the output expression. The expression for Figure 3.4b requires parentheses since the ORs are evaluated rst. EXAMPLE 3.3 FIGURE 3.5 Example 3.5 Order of Precedence Write the Boolean expression for the logic diagrams in Figure 3.5. A 1 B 3 Y 2 C a. P 1 Q 3 S 2 R b. Solution Examine the output of each gate and combine the resultant terms as required. Figure 3.5a: Gate 1: A B Gate 2: B C Gate 3: Y Gate 1 Figure 3.5b: Gate 1: P Gate 2: Q Gate 3: S Gate2 QPQ R Gate1 Gate2 AB (P BC Q)(Q R) (P Q)(Q R) 3.1 Boolean Expressions, Logic Diagrams and Truth Tables 61 Note that when two bubbles touch, they cancel out, as in the doubly inverted P input or the connection between the outputs of gates 1 and 2 and the inputs of gate 3. In the resultant Boolean expression, bars of the same length cancel; bars of unequal length do not. SECTION 3.1A REVIEW PROBLEM 3.1 Write the Boolean expression for the logic diagrams in Figure 3.6, paying attention to the rules of order of precedence. A B Y C D a. W X OUT Y Z b. FIGURE 3.6 Section Review Problem 3.1 Logic Diagrams from Boolean Expressions KEY TERMS Levels of gating The number of gates through which a signal must pass from input to output of a logic gate network. Double-rail inputs Boolean input variables that are available to a circuit in both true and complement form. Synthesis The process of creating a logic circuit from a description such as a Boolean equation or truth table. We can derive a logic diagram from a Boolean expression by applying the order of precedence rules. We examine an expression to create the rst level of gating from the circuit inputs, then combine the output functions of the rst level in the second level gates, and so forth. Input inverters are often not counted as a gating level, as we usually assume that each variable is available in both true (noninverted) and complement (inverted) form. When input variables are available to a circuit in true and complement form, we refer to them as double-rail inputs. The rst level usually will be AND gates if no parentheses are present, OR gates if parentheses are used. (Not always, however; parentheses merely tell us which functions to synthesize rst.) Although we will try to eliminate bars over groups of variables by use of DeMorgans theorems and the bubble-to-bubble convention, we should recognize that a bar over a group of variables is the same as having those variables in parentheses. Let us examine the Boolean expression Y AC BD AD. Order of precedence tells us that we synthesize the AND functions rst. This yields three 2-input AND gates, with outputs AC, BD, and AD, as shown in Figure 3.7a. In the next step, we combine these AND functions in a 3-input OR gate, as shown in Figure 3.7b. 62 C H A P T E R 3 Boolean Algebra and Combinational Logic A AC B FIGURE 3.7 Logic Diagram for Y AC BD AD BD C AD D a. ANDs first A B Y AC BD AD C D b. Combine ANDs in an OR gate When the expression has OR functions in parentheses, we synthesize the ORs rst, as for the expression Y (A B)(A C D)(B C). Figure 3.8 shows this process. In the rst step, we synthesize three OR gates for the terms (A B), (A C D), and (B C). We then combine these terms in a 3-input AND gate. FIGURE 3.8 Logic Diagram for Y (A (A C D) (B C) (A B) (A C (B A B) C) B D) C D a. ORs first A B C D Y (A B)(A C D)(B C) b. Combine ORs in an AND gate EXAMPLE 3.4 Synthesize the logic diagrams for the following Boolean expressions: 1. P 2. X QRS ST (W Z Y )V (W V)Y Solution 1. Recall that a bar over two variables acts like parentheses. Thus the QRS term is synthesized from a NAND, then an AND, as shown in Figure 3.9a. Also shown is the second AND term, ST. 3.1 Boolean Expressions, Logic Diagrams and Truth Tables 63 Figure 3.9b shows the terms combined in an OR gate. FIGURE 3.9 Example 3.4 Logic Diagram of P QRS ST QRS Q RS R S S ST T a. Combine inputs (NAND, then AND) QRS Q RS R P QRS ST S S ST T b. First and second level gates combined in and OR 2. Figure 3.10 shows the synthesis of the second logic diagram in three stages. Figure 3.10a shows how the circuit inputs are rst combined in two OR gates. We do this rst because the ORs are in parentheses. In Figure 3.10b, each of these functions is combined in an AND gate, according to the normal order of precedence. The AND outputs are combined in a nal OR function, as shown in Figure 3.10c. FIGURE 3.10 Example 3.4 Logic Diagram for X (W Z Y)V (W W W V)Y Y Z W W Z Y V V a. ORs first (parentheses) W W Z Y Z Y (W Z Y)V (W V)Y V Y W W V V b. Combine with ANDs (order of precedence) W W Z Y Z Y (W Z Y)V V X Y W V W V (W V)Y c. Find output (OR) (W X Y)V (W V)Y 64 C H A P T E R 3 Boolean Algebra and Combinational Logic EXAMPLE 3.5 Use DeMorgans theorem to modify the Boolean equation in part 1 of Example 3.4 so that there is no bar over any group of variables. Redraw Figure 3.9b to reect the change. Solution P QRS ST Q(R S) ST Figure 3.11a shows the modied logic diagram. The levels of gating could be further reduced from three to two (not counting input inverters) by multiplying through the parentheses to yield the expression: P QR QS ST Figure 3.11b shows the logic diagram for this form. We will examine this simplication procedure more formally in a later section of this chapter. Q Q(R R (R S) S) S P S Q(R S) ST ST T a. Logic diagram of P Q(R S) ST QR Q R P QS QR QS ST S ST T b. Logic diagram of P QR QS ST FIGURE 3.11 Example 3.5: Reworking Figure 3.9b Truth Tables from Logic Diagrams or Boolean Expressions There are two basic ways to nd a truth table from a logic diagram. We can examine the output of each gate in the circuit and develop its truth table. We then use our knowledge of gate properties to combine these intermediate truth tables into the nal output truth table. Alternatively, we can develop a Boolean expression for the logic diagram and by examining the expression ll in the truth table in a single step. The former method is more thorough and probably easier to understand when you are learning the technique. The latter method is more efcient, but requires some practice and experience. We will look at both. Examine the logic diagram in Figure 3.12. Since there are three binary inputs, there will be eight ways those inputs can be combined. Thus, we start by making an 8-line truth table, as in Table 3.1. FIGURE 3.12 Logic Diagram for AB A C AB B AB C C 3.1 Boolean Expressions, Logic Diagrams and Truth Tables 65 The OR gate output will describe the function of the whole circuit. In order to assess the OR function, we must rst evaluate the AND output. We add a column to the truth table for the AND gate and look for the lines in the table where both A AND B equal logic 1 (in this case, the last two rows). For these lines, we write a 1 in the AB column. Next, we look at the values in column C and the AB column. If there is a 1 in either column, we write a 1 in the column for the nal output. Table 3.1 Truth Table for Figure 3.12 A C AB 0 0 0 0 1 1 1 1 EXAMPLE 3.6 B 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 AB 0 0 0 0 0 0 1 1 C 0 1 0 1 0 1 1 1 Derive the truth table for the logic diagram shown in Figure 3.13. A B C FIGURE 3.13 Example 3.6 Logic Diagram Solution The Boolean equation for Figure 3.13 is (A B)(A C). We will create a column for each input variable and for each term in parentheses, as well as a column for the nal output. Table 3.2 shows the result. For the lines where A OR B is 0, we write a 1 in the (A B) column. Where A OR C is 1, we write a 1 in the (A C) column. For the lines where there is a 1 in both the (A B) AND (A C) columns, we write a 1 in the nal output column. Table 3.2 Truth Table for Figure 3.13 A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 (A B) 1 1 1 1 1 1 0 0 (A C) 0 1 0 1 1 1 1 1 (A B)(A C) 0 1 0 1 1 1 0 0 66 C H A P T E R 3 Boolean Algebra and Combinational Logic Another approach to nding a truth table involves analysis of the Boolean expression of a logic diagram. The logic diagram in Figure 3.14 can be described by the Boolean expression Y ABC A C B D. FIGURE 3.14 Logic Diagram A B C Y D We can examine the Boolean expression to determine that the nal output of the circuit will be HIGH under one of the following conditions: 1. A 2. A 3. B 0 AND B 0 AND C 0 AND D 1 AND C 0; 0. 1; All we have to do is look for these conditions in the truth table and write a 1 in the output column whenever a condition is satised. Table 3.3 shows the result of this analysis with each line indicating which term, or terms, contribute to the HIGH output. Table 3.3 Truth Table for Figure 3.14 A B C D Y terms 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 1 1 1 1 0 1 0 0 0 0 0 A C, B D AC BD AC AC ABC ABC BD BD SECTION 3.16 REVIEW PROBLEM 3.2 Find the truth table for the logic diagram shown in Figure 3.15. A B C FIGURE 3.15 Section Review Problem 3.2 Y 3.2 67 Sum-of-Products and Product-of-Sums Forms 3.2 Sum-of-Products and Product-of-Sums Forms KEY TERMS Product term A term in a Boolean expression where one or more true or complement variables are ANDed (e.g., A C ). Minterm A product term in a Boolean expression where all possible variables appear once in true or complement form (e.g., A B C; A B C ). Sum term A term in a Boolean expression where one or more true or complement variables are ORed (e.g., A B D). Maxterm A sum term in a Boolean expression where all possible variables appear once, in true or complement form (e.g., (A B C ); (A B C )). Sum-of-products (SOP) A type of Boolean expression where several product terms are summed (ORed) together (e.g., A B C A B C A B C ). Product-of-sums (POS) A type of Boolean expression where several sum terms are multiplied (ANDed) together (e.g., (A B C )(A B C )(A B C )). Bus form A way of drawing a logic diagram so that each true and complement input variable is available along a continuous conductor called a bus. Suppose we have an unknown digital circuit, represented by the block in Figure 3.16. All we know is which terminals are inputs, which are outputs, and how to connect the power supply. Given only that information, we can nd the Boolean expression of the output. The rst thing to do is nd the truth table by applying all possible input combinations in binary order and reading the output for each one. Suppose the unknown circuit in Figure 3.16 yields the truth table shown in Table 3.4. The truth table output is HIGH for three conditions: 1. When A AND B AND C are all LOW, OR 2. When A is LOW AND B AND C are HIGH, OR 3. When A is HIGH AND B AND C are LOW. Table 3.4 Truth Table for Figure 3.19 FIGURE 3.16 Digital Circuit with Unknown Function A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 Each of those conditions represents a minterm in the output Boolean expression. (A minterm is a product term (AND term) that includes all variables (A, B, C ) in true or complement form.) The minterms are: 1. A B C 2. A B C 3. A B C 68 C H A P T E R 3 Boolean Algebra and Combinational Logic Since condition 1 OR condition 2 OR condition 3 produces a HIGH output from the circuit, the Boolean function Y consists of all three minterms summed (ORed) together, as follows: Y ABC ABC ABC This expression is in a standard form called sum-of-products (SOP) form. Figure 3.17 shows the equivalent logic circuit. FIGURE 3.17 Logic Circuit for Y ABC ABC ABC The inputs A, B, and C and their complements are shown in bus form. Each variable is available, in true or complement form, at any point along a conductor. This is a useful, uncluttered notation for circuits that require several of the input variables more than once. NOTE We can derive an SOP expression from a truth table as follows: 1. Every line on the truth table that has a HIGH output corresponds to a minterm in the truth tables Boolean expression. 2. Write all truth table variables for every minterm in true or complement form. If a variable is 0, write it in complement form (with a bar over it); if it is 1, write it in true form (no bar). 3. Combine all minterms in an OR function. EXAMPLE 3.7 Tables 3.5 and 3.6 show the truth tables for the Exclusive OR and the Exclusive NOR functions. Derive the sum-of-products expression for each of these functions and draw the logic diagram for each one. Table 3.5 XOR Truth Table A B 0 0 1 1 0 1 0 1 A B 0 1 1 0 Table 3.6 XNOR Truth Table A B 0 0 1 1 0 1 0 1 A B 1 0 0 1 3.2 Sum-of-Products and Product-of-Sums Forms 69 Solution XOR: The truth table yields two product terms: AB and AB. Thus, the SOP form of the XOR function is A B AB AB. Figure 3.18 shows the logic diagram for this equation. A B A B AB AB FIGURE 3.18 Example 3.7 SOP Form of XOR Function XNOR: The product terms for this function are: A B and AB. The SOP form of the XNOR function is A B A B AB. The logic diagram in Figure 3.19 represents the XNOR function. A B A B AB AB FIGURE 3.19 Example 3.7 SOP Form of XNOR Function We can also nd the Boolean function of a truth table in product-of-sums (POS) form. The product-of-sums form of a Boolean expression consists of a number of maxterms (i.e., sum terms (OR terms) containing all variables in true or complement form) that are ANDed together. To nd the POS form of Y, we will nd the SOP expression for Y and apply DeMorgans theorems. Recall DeMorgans theorems: x y z xyz xyz xy z When the theorems were introduced, they were presented as two-variable theorems, but in fact they are valid for any number of variables. 70 C H A P T E R 3 Boolean Algebra and Combinational Logic Lets reexamine Table 3.4. To nd the sum-of-products expression for Y, we wrote a minterm for each line where Y 1. To nd the SOP expression for Y, we must write a minterm for each line where Y 0. Variables A, B, and C must appear in each minterm, in true or complement form. A variable is in complement form (with a bar over the top) if its value is 0 in that minterm, and it is in true form (no bar) if its value is 1. We get the following minterms for Y: ABC ABC ABC ABC ABC Thus, the SOP form of Y is Y ABC ABC ABC ABC ABC To get Y in POS form, we must invert both sides of the above expression and apply DeMorgans theorems to the righthand side. Y Y ABC ABC ABC ABC ABC (A B C)(A B C)(A B C)(A B C)(A B C) (A B C)(A B C)(A B C)(A B C)(A B C) This Boolean expression can be implemented by the logic circuit in Figure 3.20. We dont have to go through the whole process outlined above every time we want to nd the POS form of a function. We can nd it directly from the truth table, following the FIGURE 3.20 Logic Circuit for Y (A B C) (A B C)(A B C) (A B C)(A B C) procedure summarized below. Use this procedure to nd the POS form of the expression given by Table 3.4. The terms in this expression are the same as those derived by DeMorgans theorem. 3.2 Sum-of-Products and Product-of-Sums Forms 71 NOTE Deriving a POS expression from a truth table: 1. Every line on the truth table that has a LOW output corresponds to a maxterm in the truth tables Boolean expression. 2. Write all truth table variables for every maxterm in true or complement form. If a variable is 1, write it in complement form (with a bar over it); if it is 0, write it in true form (no bar). 3. Combine all maxterms in an AND function. Note that these steps are all opposite to those used to nd the SOP form of the Boolean expression. EXAMPLE 3.8 Find the Boolean expression, in both SOP and POS forms, for the logic function represented by Table 3.7. Draw the logic circuit for each form. Table 3.7 Truth Table for Example 3.8 (with minterms and maxterms) A B C D Y Minterms 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 1 1 0 Maxterms ABCD ABCD A B C D A A A A B B B B C C C C D D D D A B C D A B C D A B C D ABCD ABCD ABCD ABCD ABCD ABCD Solution All minterms (for SOP form) and maxterms (for POS form) are shown in the last two columns of Table 3.5. Boolean Expressions: SOP form: Y ABCD ABCD ABCD ABCD ABCD ABCD ABCD POS form: Y (A B C D)(A B C D)(A B C D)(A (A B C D)(A B C D)(A B C D) (A B C D ) The logic circuits are shown in Figures 3.21 and 3.22. ABCD B C D) 72 C H A P T E R 3 Boolean Algebra and Combinational Logic FIGURE 3.21 Example 3.8 SOP Form FIGURE 3.22 Example 3.8 POS Form 3.3 Theorems of Boolean Algebra 73 SECTION 3.2 REVIEW PROBLEM 3.3 Find the SOP and POS forms of the Boolean functions represented by the following truth tables. a. A B C b. ABC Y Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 1 0 3.3 Theorems of Boolean Algebra The main reason to learn Boolean algebra is to learn how to minimize the number of logic gates in a network. Boolean expressions with many terms, such as those represented by the logic diagrams in Figures 3.21 and 3.22, are seldom in their simplest form. It is often possible to apply some techniques of Boolean algebra to derive a simpler form of expression that requires fewer gates to implement. For example, the logic circuit in Figure 3.21 requires eight 4-input AND gates and an 8-input OR gate. Using Boolean algebra, we can reduce its Boolean expression to Y AD A B C A B D A B C. This form can be implemented with 4 AND gates and a 4-input OR. You will use a simplication technique for this example in an end-ofchapter problem. In the meantime, let us examine some basic rules of Boolean algebra. Commutative, Associative, and Distributive Properties KEY TERMS Commutative property A mathematical operation is commutative if it can be applied to its operands in any order without affecting the result. For example, addition is commutative (a b b a), but subtraction is not (a b b a). Associative property A mathematical function is associative if its operands can be grouped in any order without affecting the result. For example, addition is associative ((a b) c a (b c)), but subtraction is not ((a b) c a (b c)). Distributive property Full name: distributive property of multiplication over addition. The property that allows us to distribute (multiply through) an AND across several OR functions. For example, a(b c) ab ac. AND and OR functions are both commutative and associative. The commutative property states that AND and OR operations are independent of input order. For inputs x and y, Theorem 1: xy and yx Theorem 2: x y y x The associative property allows us to perform several two-input AND or OR functions in any order. In other words, Theorem 3: (xy)z and Theorem 4: (x x(yz) y) z (xz)y x (y z) (x z) y 74 C H A P T E R 3 Boolean Algebra and Combinational Logic The distributive property allows us to multiply through an AND function across several OR functions. For example, Theorem 5: x(y z) xy xz and Theorem 6: (x y)(w z) xw xz yw yz Figure 3.23 shows the logic gate equivalents of these theorems. FIGURE 3.23 Distributive Properties EXAMPLE 3.9 FIGURE 3.24 Example 3.9 Distributive Property Find the Boolean expression of the POS circuit in Figure 3.24a. Apply the distributive property to transform the circuit to an SOP form. A B Y C D a. POS form A B C D AC BC AD BD b. SOP form Y 3.3 Theorems of Boolean Algebra 75 Solution The Boolean expression for Figure 3.24a is Y (A B)(C D). Using the distributive property, we get the expression Y A C BC AD BD. The logic diagram for this expression is shown in Figure 3.24b. In Example 3.9, we see that the distributive property can be used to convert a POS circuit to SOP or vice versa. In this case, the circuit was not simplied, just transformed. EXAMPLE 3.10 FIGURE 3.25 Example 3.10 Distributive Property Write the Boolean expression for the circuit in Figure 3.25a. Use the distributive property to convert this to an SOP circuit. A B C D Y E F a. POS form A B C D E F ABCE ABCF ABDE Y ABDF b. SOP form Solution The Boolean expression for Figure 3.25a is AB(C tive property can be applied in two stages: Y (ABC ABCE ABD)(E F) ABCF ABDE D)(E F). The distribu- ABDF The logic diagram for this equation is shown in Figure 3.25b. This results in a network that is wider (more gates on one level), but also atter (fewer levels). The advantage of the second circuit is that signals would pass through the network faster, since it has fewer levels of gating. Single-Variable Theorems There are thirteen theorems that can be used to manipulate a single variable in a Boolean expression. An easy way to remember these theorems is to divide them into three groups: 1. Six theorems: x AND/OR/XOR 0/1 2. Six theorems: x AND/OR/XOR x/ x 3. One theorem: Double Inversion 76 C H A P T E R 3 Boolean Algebra and Combinational Logic x AND/OR/XOR 0/1 The theorems in the rst group can be generated by asking what happens when x, a Boolean variable or expression, is at one input of an AND, an OR, or an XOR gate and a 0 or a 1 is at the other. Examine the truth table of the gate in question. Hold one input of the gate constant and nd the effect of the other on the output. This is the same procedure we used in Chapter 2 to examine the enable/inhibit properties of logic gates. Each of these six theorems can be represented by a logic gate, as shown in Figure 3.26. FIGURE 3.26 X AND/OR/XOR 0/1 x 0: A x Y 0 0 0 0 1 0 1 0 0 1 1 1 If x 0, Y 0 If x 1, Y 0 (Can never have both inputs HIGH, therefore output is always LOW.) Theorem 7: x 0 x 0 0: A x Y 0 0 0 0 1 1 1 0 1 1 1 1 If x 0, Y 0 If x 1, Y 1 (LOW input enables OR gate.) Theorem 8: x x 0: A x Y 0 0 0 0 1 1 1 0 1 1 1 0 0 x 3.3 Theorems of Boolean Algebra 77 If x 0, Y 0 If x 1, Y 1 (XOR acts as a noninverting buffer.) Theorem 9: x 0 x x 1: A x Y 0 0 0 0 1 0 1 0 0 1 1 1 If x 0, Y 0 If x 1, Y 1 (HIGH input enables AND gate.) Theorem 10: x 1 x x 1: A x Y 0 0 0 0 1 1 1 0 1 1 1 1 If x 0, Y 1 If x 1, Y 1 (One input always HIGH, therefore output is always HIGH.) Theorem 11: x x 1 1 1: A x Y 0 0 0 0 1 1 1 0 1 1 1 0 If x 0, Y 1 If x 1, Y 0 (XOR acts as an inverting buffer.) Theorem 12 x 1 x x AND/OR/XOR x/ x Six theorems are generated by combining a Boolean variable or expression, x, with itself or its complement in an AND, an OR, or an XOR function. Again, we can use the AND, OR, and XOR truth tables. For the rst three theorems, we look only at the lines where both inputs are the same. For the other three, we use the lines where the inputs are different. 78 C H A P T E R 3 Boolean Algebra and Combinational Logic Figure 3.27 shows the logic gates that represent these theorems. FIGURE 3.27 X AND/OR/XOR X/X x x: A x Y 0 0 0 0 1 0 1 0 0 1 1 1 If x If x 0, Y 1, Y 0 1 Theorem 13: x x x x: A x Y 0 0 0 0 1 1 1 0 1 1 1 1 If x If x 0, Y 1, Y Theorem 14: x x x 0 1 x x x: A x Y 0 0 0 0 1 1 1 0 1 1 1 0 If x 0, Y 0 If x 1, Y 0 (Output is LOW if neither input is HIGH or if both are.) Theorem 15: x x 0 3.3 Theorems of Boolean Algebra 79 x x: A x Y 0 0 0 0 1 0 1 0 0 1 1 1 If x 0, Y 0 If x 1, Y 0 (Since inputs are opposite, can never have both HIGH. Output always LOW.) Theorem 16: x x x 0 x: A x Y 0 0 0 0 1 1 1 0 1 1 1 1 If x 0, Y 1 If x 1, Y 1 (Since inputs are opposite, one input always HIGH. Therefore, output is always HIGH.) Theorem 17: x x x 1 x: A x Y 0 0 0 0 1 1 1 0 1 1 1 0 If x 0, Y 1 If x 1, Y 1 (One input HIGH, but not both.) Theorem 18: x x x FIGURE 3.28 Double Inversion x x x 1 Double Inversion The nal single-variable theorem is just common sense. It states that a variable or expression inverted twice is the same as the original variable or expression. It is given by: Theorem 19: x x This theorem is illustrated by the two inverters in Figure 3.28. Multivariable Theorems There are numerous multivariable theorems we could learn, but we will look only at ve of the most useful. 80 C H A P T E R 3 Boolean Algebra and Combinational Logic DeMorgans Theorems We have already seen DeMorgans theorems. We will list them again, but will not comment further on them at this time. Theorem 20: xy x Theorem 21: x y y xy Other Multivariable Theorems Theorem 22: x xy x Proof: x xy x (1 x1 x y) (Distributive property) (1 y 1; Theorem) Figure 3.29 illustrates the circuit in this theorem. Note that the equivalent is not a circuit at all, but a single, unmodied variable. Thus, the circuit shown need never be built. FIGURE 3.29 Theorem 22 x x y EXAMPLE 3.11 xy x xy Simplify the following Boolean expressions, using Theorem 22 and other rules of Boolean algebra. Draw the logic circuits of the unsimplied and simplied expressions. a. H b. Y c. W KL K (A B)CD (A (PQR P Q)(S B) T) (P Q)(S T) (S T) Solution Figure 3.30 shows the logic circuits for the unsimplied and simplied versions of the above expressions. a. Let x K, let y L: H x xy K Theorem 22 states x xy x. Therefore K b. Let x (A B), let y CD: Y KL KL K. x xy x A B c. Let x S T, let y (P Q): Since x xy x, (P Q)(S T) (S T) (S T). W Let x S T, let y (PQR (PQR P Q)(S T) (S S T) T P Q) W x xy x Alternate method: W (PQR P Q)(S T) (P Q)(S T) (S T) By the distributive property: W Let x S T, let y ((PQR ((PQR P Q) P Q) W x (P (P xy Q))(S T) Q)): x S T (S T) 3.3 Theorems of Boolean Algebra 81 FIGURE 3.30 Example 3.11 Logic Circuits for Unsimplied and Simplied Expressions 82 C H A P T E R 3 Boolean Algebra and Combinational Logic Theorem 23: (x Proof: (x y)(x y)(x z) x yz z) xx xz xy yz (Distributive property) (x xy) xz yz (xx x; Associative property) x xz yz (x xy x (Theorem 22)) (x xz) yz (Associative property) x yz (Theorem 22) Figure 3.31 shows the logic circuits for the left and right sides of the equation for Theorem 23. This theorem is a special case of one of the distributive properties, Theorem 6, where w x. FIGURE 3.31 Theorem 23 EXAMPLE 3.12 Simplify the following Boolean expressions, using Theorem 23 and other rules of Boolean algebra. Draw the logic circuits of the unsimplied and simplied expressions. a. L b. Y (M (A N )(M P) B AB)(A B C) Solution Figure 3.32 shows the logic circuits for the unsimplied and simplied versions of the above expressions. FIGURE 3.32 Example 3.12 Logic Circuits for Unsimplied and Simplied Expressions 3.3 Theorem 23: (x y)(x z) x a. Let x M, let y N, let z P: L b. Let x A B, let y Y (x Theorem 24: x Proof: Since (x (x y)(x z) z) x yz M NP yz A B ABC C: x xy x y y)(x z) x x 83 yz y)(x AB, let z Theorems of Boolean Algebra yz, then for y AB ABC x: xy (x x)(x y) 1 (x y) (x x 1) xy Figure 3.33 illustrates Theorem 24 with a logic circuit. FIGURE 3.33 Theorem 24 NOTE Here is another way to remember Theorem 24: If a variable (x) is ORed with a term consisting of a different variable (y) AND the rst variables complement (x), the complement disappears. x EXAMPLE 3.13 xy x y Simplify the following Boolean expressions, using Theorem 24 and other rules of Boolean algebra. Draw the logic circuits of the unsimplied and simplied forms of the expressions. a. W U UV b. P QRS (Q J KM (K L R S) T M) KM Solution Figure 3.34 shows the circuits for the unsimplied and simplied expressions. Theorem 24: x xy x y a. Let x U, let y V: W b. P Let x x xy x y U V QRS (Q R S) T QRS Q RS T (DeMorgans theorem) QRS, let y T: P x xy x y QRS T 84 C H A P T E R 3 Boolean Algebra and Combinational Logic FIGURE 3.34 Example 3.13 Logic Circuits for Unsimplied and Simplied Expressions c. Let x KM, let y J x xy (K x L y M): KM K L K L (M KLM M KM) (Associative property) (Theorem 22) The rules of Boolean algebra are summarized in Table 3.8. Dont try to memorize all these rules. The commutative, associative, and distributive properties are the same 3.3 Theorems of Boolean Algebra 85 as their counterparts in ordinary algebra. The single-variable theorems can be reasoned out by your knowledge of logic gate operation. That leaves only ve multivariable theorems. Table 3.8 Theorems of Boolean Algebra Commutative Properties 1. x y y x 2. x y y x Associative Properties 3. x ( y z) (x 4. x( yz) (xy)z y) z Distributive Properties 5. x( y z) xy xz 6. (x y)(w z) xw xz yw yz x AND/OR/XOR 0/1 7. 8. 9. 10. 11. 12. x0 0 x0x x0x x1 x x11 x1x 13. 14. 15. 16. 17. 18. xx x xxx xx0 xx 0 xx1 xx1 x AND/OR/XOR x/ x Double Inversion 19. x x DeMorgans Theorems 20. xy 21. x x y y xy Other Multivariable Theorems 22. x xy x 23. (x y)(x z) x 24. x xy x y yz SECTION 3.3 REVIEW PROBLEMS 3.4 Use theorems of Boolean algebra to simplify the following Boolean expressions. a. Y AC (A C)D b. Y A C ACD c. Y (AB BC)(AB C) 86 C H A P T E R 3 Boolean Algebra and Combinational Logic 3.4 Simplifying SOP and POS Expressions KEY TERMS Maximum SOP simplication The form of an SOP Boolean expression that cannot be further simplied by canceling variables in the product terms. It may be possible to get a POS form of the expression with fewer terms or variables. Maximum POS simplication The form of a POS Boolean expression that cannot be further simplied by canceling variables in the sum terms. It may be possible to get an SOP form of the expression with fewer terms or variables. Table 3.9 Truth Table for the SOP and POS Networks in Figure 3.35 A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Earlier in this chapter, we discovered that we can generate a Boolean equation from a truth table and express it in sum-of-products (SOP) or product-of-sums (POS) form. From this equation, we can develop a logic circuit diagram. The next step in the design or analysis of a circuit is to simplify its Boolean expression as much as possible, with the ultimate aim of producing a circuit that has fewer physical components than the unsimplied circuit. In Section 3.2, we found the SOP and POS forms of the Boolean expression represented by Table 3.9. These forms yield the logic diagrams shown in Figures 3.17 and 3.20. For convenience, the circuits are illustrated again in Figure 3.35. The corresponding algebraic expressions can be simplied by the rules of Boolean algebra to give us a simpler circuit in each case. 1 0 0 1 1 0 0 0 FIGURE 3.35 Unsimplied SOP and POS Networks The sum-of-products and product-of-sums expressions represented by Table 3.9 are: Y ABC ABC A B C (SOP) and Y (A B C)(A B C)(A B C)(A B C)(A B C) (POS) 3.4 Simplifying SOP and POS Expressions 87 The SOP form is fairly easy to simplify: Y ABC ABC ABC (A A) B C A B C (Distributive property) 1 BC ABC (x x 1) BC ABC (x 1 x) Since we cannot cancel any more SOP terms, we can call this nal form the maximum SOP simplication. The logic diagram for the simplied expression is shown in Figure 3.36. FIGURE 3.36 Simplied SOP Circuit NOTE Two terms in an SOP expression can be reduced to one if they are identical except for one variable that is in true form in one term and complement form in the other. Such a grouping of a variable and its complement always cancels. xyz xyz xy ( z z) xy There is a similar procedure for the POS form. Examine the following expression: Y (A Recall Theorem 23: (x y)(x z) Let x A B, let y C, let z Y (A (A (A B C)(A B C) x yz. C. B) B) B) CC (Theorem 23) 0 (xx 0) (x 0 x) NOTE A POS expression can be simplied by grouping two terms that are identical except for one variable that is in true form in one term and complement form in the other. (x y z )(x y z) (x y) zz x y Let us use this procedure to simplify the POS form of the previous Boolean expression, shown again below with the terms numbered for our reference. The numbered value of each term corresponds to the binary value of the line in the truth table from which it is derived. Y (A (1) B (2) C ) (A B (5) C ) (A B (6) C ) (A B (7) C ) (A B C) There can be more than one way to simplify an expression. The following grouping of the numbered POS terms is one possibility. 88 C H A P T E R 3 Boolean Algebra and Combinational Logic FIGURE 3.37 Simplied POS Circuit (1)(5): (A (2)(6): (A (6)(7): (A B B B C ) (A C ) (A C ) (A B B B C) C) C) B B A C C B Combining the above terms, we get the expression: Y (B C )(B C )(A B) Figure 3.37 shows the logic diagram for this expression. Compare this logic diagram and that of Figure 3.36 with the unsimplied circuits of Figure 3.35. Since there are no more cancellations of POS terms possible, we can call this the maximum POS simplication. We can, however, apply other rules of Boolean algebra and simplify further. Y (B C )(B C )(A B) (B AC )(B C ) BB BC ABC ACC BC ABC (Theorem 23) (Distributive property) (x x 0) This is the same result we got when we simplied the SOP form of the expression. To be sure you are getting the maximum SOP or POS simplication, you should be aware of the following guidelines: 1. Each term must be grouped with another, if possible. 2. When attempting to group all terms, it is permissible to group a term more than once, such as term (6) above. The theorems x x x (POS forms) and x x x (SOP forms) imply that using a term more than once does not change the Boolean expression. 3. Each pair of terms should have at least one term that appears only in that pair. Otherwise, you will have redundant terms that will need to be canceled later. For example, another possible group in the POS simplication above is terms (5) and (7). But since both these terms are in other groups, this pair is unnecessary and would yield a term you would have to cancel. EXAMPLE 3.14 Find the maximum SOP simplication for the Boolean function represented by Table 3.10. Draw the logic diagram for the simplied expression. Solution SOP form: (8) (9) Y A B CD A B CD (10) A BC D (11) A BC D (12) A B CD (14) ABCD 3.4 Simplifying SOP and POS Expressions 89 Table 3.10 Truth Table for Example 3.14 A B C D Y 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 0 Group the terms as follows: (8) (9): (10) (11): (12) (14): ABCD ABCD ABCD ABCD ABCD ABCD ABC ABC ABD Combine the simplied groups and apply techniques of Boolean algebra to simplify further: Y ABC A B(C AB A(B A(B AB ABC ABD C) A B D ABD B D) Distributive property D) Theorem 24: x xy x AD y Figure 3.38 Shows the logic diagram of the simplied expression. A Table 3.11 Truth Table for Section Review Problem A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 B Y AB AD D FIGURE 3.38 Example 3.14 Simplied SOP Circuit SECTION 3.4 REVIEW PROBLEM 3.5 Find the maximum SOP and POS simplications for the function represented by Table 3.11. 90 C H A P T E R 3 Boolean Algebra and Combinational Logic 3.5 Simplication by the Karnaugh Map Method KEY TERMS Karnaugh map A graphical tool for nding the maximum SOP or POS simplication of a Boolean expression. A Karnaugh map works by arranging the terms of an expression in such a way that variables can be canceled by grouping minterms or maxterms. Cell The smallest unit of a Karnaugh map, corresponding to one line of a truth table. The input variables are the cells coordinates, and the output variable is the cells contents. Adjacent cell Two cells are adjacent if there is only one variable that is different between the coordinates of the two cells. For example, the cells for minterms ABC and ABC are adjacent. Pair A group of two adjacent cells in a Karnaugh map. A pair cancels one variable in a K-map simplication. Quad A group of four adjacent cells in a Karnaugh map. A quad cancels two variables in a K-map simplication. Octet A group of eight adjacent cells in a Karnaugh map. An octet cancels three variables in a K-map simplication. In Example 3.14, we derived a sum-of-products Boolean expression from a truth table and simplied the expression by grouping minterms that differed by one variable. We made this task easier by breaking up the truth table into groups of four lines. (It is difcult for the eye to grasp an overall pattern in a group of 16 lines.) We chose groups of four because variables A and B are the same in any one group and variables C and D repeat the same binary sequence in each group. This allows us to see more easily when we have terms differing by only one variable. The Karnaugh map, or K-map, is a graphical tool for simplifying Boolean expressions that uses a similar idea. A K-map is a square or rectangle divided into smaller squares called cells, each of which represents a line in the truth table of the Boolean expression to be mapped. Thus, the number of cells in a K-map is always a power of 2, usually 4, 8, or 16. The coordinates of each cell are the input variables of the truth table. The cell content is the value of the output variable on that line of the truth table. Figure 3.39 shows the formats of Karnaugh maps for Boolean expressions having two, three, and four variables, respectively. There are two equivalent ways of labeling the cell coordinates: numerically or by true and complement variables. We will use the numerical labeling since it is always the same, regardless of the chosen variables. The cells in the Karnaugh maps are set up so that the coordinates of any two adjacent cells differ by only one variable. By grouping adjacent cells according to specied rules, we can simplify a Boolean expression by canceling variables in their true and complement forms, much as we did algebraically in the previous section. Two-Variable Map Table 3.12 shows the truth table of a two-variable Boolean expression. The Karnaugh map shown in Figure 3.40 is another way of showing the same information as the truth table. Every line in the truth table corresponds to a cell, or square, in the Karnaugh map. The coordinates of each cell correspond to a unique combination of input variables (A, B). The content of the cell is the output value for that input combination. If the truth table output is 1 for a particular line, the content of the corresponding cell is also 1. If the output is 0, the cell content is 0. 3.5 Simplication by the Karnaugh Map Method FIGURE 3.39 Karnaugh Map Formats Table 3.12 Truth Table for a TwoVariable Boolean Expression A B Y 0 0 1 1 0 1 0 1 FIGURE 3.40 Karnaugh Map for Table 3.12 1 1 0 0 The SOP expression of the truth table is Y AB AB Y A (B A B) which can be simplied as follows: 91 92 C H A P T E R 3 Boolean Algebra and Combinational Logic We can perform the same simplication by grouping the adjacent pair of 1s in the Karnaugh map, as shown in Figure 3.41. NOTE When we circle a pair of 1s in a K-map, we are grouping the common variable in two minterms, then factoring out and canceling the complements. FIGURE 3.41 Grouping a Pair of Adjacent Cells To nd the simplied form of the Boolean expression represented in the K-map, we examine the coordinates of all the cells in the circled group. We retain coordinate variables that are the same in all cells and eliminate coordinate variables that are different in different cells. In this case: A is a coordinate of both cells of the circled pair. (Keep A.) B is a coordinate of one cell of the circled pair, and B is a coordinate of the other. (Discard B/B.) Y A Three- and Four-Variable Maps Refer to the forms of three- and four-variable Karnaugh maps shown in Figure 3.39. Each cell is specified by a unique combination of binary variables. This implies that the three-variable map has 8 cells (since 23 8) and the four-variable map has 16 cells (since 2 4 16). The variables specifying the row (both maps) or the column (the four-variable map) do not progress in binary order; they advance such that there is only one change of variable per row or column. For example, the numbering of the rows is 00, 01, 11, 10, rather than the binary order 00, 01, 10, 11. If we were to use binary order, adjacent cells in rows 2 and 3 or 3 and 4 would differ by two variables, meaning we could not factor out and cancel a pair of complements by grouping these cells. For instance, we cannot cancel complementary variables from the pair A B C A B C, which differs by two variables. NOTE The number of cells in a group must be a power of 2, such as 1, 2, 4, 8, or 16. FIGURE 3.42 Quad A group of four adjacent cells is called a quad. Figure 3.42 shows a Karnaugh map for a Boolean function whose terms can be grouped in a quad. The Boolean expression displayed in the K-map is: Y ABC ABC ABC ABC A and B are both part of the quad coordinates in true and complement form. (Discard A and B.) C is a coordinate of each cell in the quad. (Keep C.) Y C Grouping cells in a quad is equivalent to factoring two complementary pairs of variables and canceling them. Y FIGURE 3.43 Octet (A A)(B B)C C You can verify that this is the same as the original expression by multiplying out the terms. An octet is a group of eight adjacent cells. Figure 3.43 shows the Karnaugh map for the following Boolean expression: 3.5 Y Simplication by the Karnaugh Map Method ABCD ABCD ABCD ABCD ABCD ABCD 93 ABCD ABCD Variables A, C, and D are all coordinates of the octet cells in true and complement form. (Discard A, C, and D.) B is a coordinate of each cell. (Keep B.) Y B The algebraic equivalent of this octet is an expression where three complementary variables are factored out and canceled. Y (A A)B(C C)(D D) B NOTE A Karnaugh map completely lled with 1s implies that all input conditions yield an output of 1. For a Boolean expression Y, Y 1. Grouping Cells Along Outside Edges The cells along an outside edge of a three- or four-variable map are adjacent to cells along the opposite edge (only one change of variable). Thus we can group cells around the outside of the map to cancel variables. In the case of the four-variable map, we can also group the four corner cells as a quad, since they are all adjacent to one another. EXAMPLE 3.15 Use Karnaugh maps to simplify the following Boolean expressions: a. Y b. Y ABC ABC ABC ABC ABCD ABCD ABCD ABCD Solutions Figure 3.44 shows the Karnaugh maps for the Boolean expressions labeled a and b. Cells in each map are grouped in a quad. FIGURE 3.44 Example 3.15 K-Maps a. A and C are both coordinates of two cells in true form and two cells in complement form. (Discard A and C.) B is a coordinate of each cell. (Keep B.) Y B b. A and C are both coordinates of two cells in true form and two cells in complement form. (Discard A and C.) B and D are coordinates of each cell. (Keep B and D.) Y BD 94 C H A P T E R 3 Boolean Algebra and Combinational Logic Loading a K-Map From a Truth Table NOTE We dont need a Boolean expression to ll a Karnaugh map if we have the functions truth table. Figures 3.45 and 3.46 show truth table and Karnaugh map forms for three- and four-variable Boolean expressions. The numbers in parentheses show the order of terms in binary sequence for both forms. The Karnaugh map is not laid out in the same order as the truth table. That is, it is not laid out in a binary sequence. This is due to the criterion for cell adjacency: no more than one variable change between rows or columns is permitted. FIGURE 3.45 Order of Terms (Three-Variable Function) FIGURE 3.46 Order of Terms (Four-Variable Function) Filling in a Karnaugh map from a truth table is easy when you understand a system for doing it quickly. For the three-variable map, ll row 1, then row 2, skip to row 4, then go back to row 3. By doing this, you trace through the cells in binary order. Use the mnemonic phrase 1, 2, skip, back to help you remember this. The system for the four-variable map is similar but must account for the columns as well. The rows get lled in the same order as the three-variable map, but within each row, ll column 1, then column 2, skip to column 4, then go back to column 3. Again, 1, 2, skip, back. 3.5 Simplication by the Karnaugh Map Method 95 The four-variable map is easier to ll from the truth table if we break up the truth table into groups of four lines, as we have done in Figure 3.46. Each group is one row in the Karnaugh map. Following this system will quickly ll the cells in binary order. Go back and follow the order of terms on the four-variable map in Figure 3.46, using this system. (Remember, for both rows and columns, 1, 2, skip, back.) Multiple Groups NOTE If there is more than one group of 1s in a K-map simplication, each group is a term in the maximum SOP simplication of the mapped Boolean expression. The resulting terms are ORed together. EXAMPLE 3.17 Use the Karnaugh map method to simplify the Boolean function represented by Table 3.13. Table 3.13 Truth Table for Example 4.3 A B C D Y 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 FIGURE 3.47 Example 3.17 K-Map Solution Figure 3.47 shows the Karnaugh map for the truth table in Table 3.14. There are two groups of 1sa pair and a quad. Pair: Variables A, B, and D are coordinates of both cells. (Keep A B D.) C is a coordinate of one cell and C is a coordinate of the other. (Discard C.) Term: A B D Quad: Both A and C are coordinates of two cells in true form and two cells in complement form. (Discard A and C.) B and D are coordinates of all four cells. (Keep B D.) Term: B D Combine the terms in an OR function: Y ABD BD 96 C H A P T E R 3 Boolean Algebra and Combinational Logic Overlapping Groups NOTE A cell may be grouped more than once. The only condition is that every group must have at least one cell that does not belong to any other group. Otherwise, redundant terms will result. EXAMPLE 3.18 Simplify the function represented by Table 3.14. Solution The Karnaugh map for the function in Table 3.14 is shown in Figure 3.48, with two different groupings of terms. FIGURE 3.48 Example 3.18 K-Maps Table 3.14 Truth Table for Example 3.18 A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 1 a. The simplied Boolean expression drawn from the rst map has three terms. Y AB AB BC b. The second map yields an expression with four terms. Y AB AB BC AC One of the last two terms is redundant, since neither of the pairs corresponding to these terms has a cell belonging only to that pair. We could retain either pair of cells and its corresponding term, but not both. We can show algebraically that the last term is redundant and thus make the expression the same as that in part a. Y AB AB AB BC AC A B B C A (B B) C AB AB BC ABC ABC A B (1 C ) A B B C (1 A) AB AB BC 3.5 Simplication by the Karnaugh Map Method 97 Conditions for Maximum Simplication NOTE The maximum simplication of a Boolean expression is achieved only if the circled groups of cells in its K-map are as large as possible and there are as few groups as possible. EXAMPLE 3.19 Find the maximum SOP simplication of the Boolean function represented by Table 3.15. Solution The values of Table 3.15 are loaded into the three K-maps shown in Figure 3.49. Three different ways of grouping adjacent cells are shown. One results in maximum simplication; the other two do not. FIGURE 3.49 Example 3.19 K-Maps Table 3.15 Truth Table for Example 3.19 A B C D Y 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 We get the maximum SOP simplication by grouping the two octets shown in Figure 3.49a. The resulting expression is a. Y B D Figures 3.49b and c show two simplications that are less than the maximum because the chosen cell groups are smaller than they could be. The resulting expressions are: b. Y c. Y AB AB B BD D Neither of these expressions is the simplest possible, since both can be reduced by Boolean algebra to the form in Figure 3.49a. 98 C H A P T E R 3 Boolean Algebra and Combinational Logic Using K-Maps for Partially Simplied Circuits Figure 3.50 shows a logic diagram that can be further simplied. If we want to use a Karnaugh map for this process, we must do one of two things: 1. Fill in the K-map from the existing product terms. Each product term that is not a minterm will represent more than one cell in the Karnaugh map. When the map is lled, regroup the cells for maximum simplication. 2. Expand the sum-of-products expression of the circuit to get a sum-of-minterms form. Each minterm represents one cell in the K-map. Group the cells for maximum simplification. FIGURE 3.50 Logic Diagram That Can Be Further Simplied FIGURE 3.51 Further Simplication of Logic Diagram (Figure 3.50) Figure 3.51 shows the K-map derived from the existing circuit and the regrouped cells that yield the maximum simplication. The algebraic method requires us to expand the existing Boolean expression to get a sum of minterms. The original expression is: Y ABCD ABD AC The theorem (x x) 1 implies that we can AND a variable with a term in true and complement form without changing the term. The expanded expression is: Y ABCD ABCD ABCD A B (C C) D A (B B) C (D ABCD ABCD ABCD ABCD ABCD D) The terms of this expression can be loaded into a K-map and simplied, as shown in Figure 3.51b. Figure 3.52 shows the logic diagram for the simplied expression. 3.5 Simplication by the Karnaugh Map Method 99 FIGURE 3.52 Simplied Circuit EXAMPLE 3.20 Use a Karnaugh map to nd the maximum SOP simplication of the circuit shown in Figure 3.53. FIGURE 3.53 Example 3.20 Circuit to Be Simplied Solution Figure 3.54a shows the Karnaugh map of Figure 3.53 with terms grouped as shown in the original circuit. Figure 3.54b shows the terms regrouped for the maximum simplication, which is given by: Y AD BD ABC Alternate method: The Boolean expression for the circuit in Figure 3.53 is: Y FIGURE 3.54 Example 3.20 Maximum Simplication of Figure 3.53 ABC ACD BCD ABCD 100 C H A P T E R 3 Boolean Algebra and Combinational Logic This expands to the following expression: Y A B C (D D) A (B B) C D (A A) B C D A B C D ABCD ABCD ABCD ABCD ABCD ABCD ABCD This expression can be loaded directly into the K-map and simplied, as shown in Figure 3.54b. The logic diagram for the simplied expression is shown in Figure 3.55. FIGURE 3.55 Example 3.20 Simplied Circuit Dont Care States KEY TERMS Dont care state An output state that can be regarded as either HIGH or LOW, as is most convenient. A dont care state is the output state of a circuit for a combination of inputs that will never occur. Sometimes a digital circuit will be intended to work only for certain combinations of inputs; any other input values will never be applied to the circuit. In such a case, it may be to our advantage to use so-called dont care states to simplify the circuit. A dont care state is shown in a K-map cell as an X and can be either a 0 or a 1, depending on which case will yield the maximum simplication. A common application of the dont care state is a digital circuit designed for binarycoded decimal (BCD) inputs. In BCD, a decimal digit (09) is encoded as a 4-bit binary number (00001001). This leaves six binary states that are never used (1010, 1011, 1100, 1101, 1110, 1111). In any circuit designed for BCD inputs, these states are dont care states. All cells containing 1s must be grouped if we are looking for a maximum SOP simplication. (If necessary, a group can contain one cell.) The dont care states can be used to maximize the size of these groups. We need not group all dont care states, only those that actually contribute to a maximum simplication. EXAMPLE 3.21 The circuit in Figure 3.56 is designed to accept binary-coded decimal inputs. The output is HIGH when the input is the BCD equivalent of 5, 7, or 9. If the BCD equivalent of the input is not 5, 7 or 9, the output is LOW. The output is not dened for input values greater than 9. Find the maximum SOP simplication of the circuit. 3.5 D1 LSB D2 D3 D4 Y MSB FIGURE 3.56 Example 3.21 Circuit to be Simplied Simplication by the Karnaugh Map Method 101 Solution The Karnaugh map for the circuit is shown in Figure 3.57a. We can designate three of the dont care cells as 1sthose corresponding to input states 1011, 1101, and 1111. This allows us to group the 1s into two overlapping quads, which yield the following simplication. Y D4 D1 D3 D1 The ungrouped dont care states are treated as 0s. The corresponding circuit is shown in Figure 3.57b. D2 D1 D4 D3 D3 D1 D4 D1 D4 D3 D1 FIGURE 3.57 Example 3.21 Karnaugh Map and Logic Diagram EXAMPLE 3.22 Applications One type of decimal code is called 2421 code, so called because of the positional weights of its bits. (For example, 1011 in 2421 code is equivalent to 2 2 1 5 in decimal. 1100 is equivalent to decimal 2 4 6.) Table 3.16 shows how this code compares to its equivalent decimal digits and to the BCD code used in Example 3.21. 2421 code is sometimes used because it is self-complementing, a property that BCD code does not have, but that is useful in digital decimal arithmetic circuits. The bits of the BCD code are designated D4 D3 D2 D1. The bits of the 2421 code are designated Y4 Y3 Y2 Y1. Use the Karnaugh map method to design a logic circuit that accepts any BCD input and generates an output in 2421 code, as specied by Table 3.16. Solution The required circuit is called a code converter. Each 4-bit BCD input corresponds to a 4-bit 2421 output. Thus, we must nd four Boolean expressions, one for each Table 3.16 BCD and 2421 Code Decimal Equivalent D4 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 BCD Code D3 D2 D1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Y4 0 0 0 0 0 1 1 1 1 1 2421 Code Y3 Y2 Y1 0 0 0 0 1 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 102 C H A P T E R 3 Boolean Algebra and Combinational Logic FIGURE 3.58 Example 3.22 K-Maps: BCD to 2421 FIGURE 3.59 Example 3.22 BCD-to-2421 Code Converter 3.5 Simplication by the Karnaugh Map Method 103 bit of the 2421 code. We can derive each Boolean expression from a truth table represented by the corresponding output column in Table 3.16. We can load the 2421 values into four different Karnaugh maps, as shown in Figure 3.58. The cells corresponding to the unused input BCD codes 1010, 1011, 1100, 1101, 1110, and 1111 are dont care states in each map. The K-maps yield the following simplications: Y4 D4 D3 D2 D3 D1 Y3 D4 D3 D2 D3 D1 Y2 D4 D3 D2 D3 D2 D1 Y1 D1 Figure 3.59 shows the logic diagram for these equations. POS Simplication Until now, we have looked only at obtaining the maximum SOP simplication from a Karnaugh map. It is also possible to nd the maximum POS simplication from the same map. Figure 3.60 shows a Karnaugh map with the cells grouped for an SOP simplication and a POS simplication. The SOP simplication is shown in Figure 3.60a and the POS simplication in Figure 3.60b. FIGURE 3.60 SOP and POS Forms on a K-Map When we derive the POS form of an expression from a truth table, we use the lines where the output is 0 and we use the complements of the input variables on these lines as the elements of the selected maxterms. The same principle applies here. The maxterms are: (A (A (A B B B C) C) C) Top left cell Bottom left cell Bottom right cell The variables are canceled in much the same way as in the SOP form. Remember, however, that the POS variables are the complements of the variables written beside the Karnaugh map. If there is more than one simplied term, the terms are ANDed together, as in a full POS form. Cancellations: Outside pair: A is present in both true and complement form in the pair. (Discard A.) B and C are present in both cells of the pair. (Keep B and C.) Term: B C 104 C H A P T E R 3 Boolean Algebra and Combinational Logic Bottom pair: A and B are present in both cells of the pair. (Keep A and B.) C is present in both true and complement form in the pair. (Discard C.) Term: A B Maximum POS simplication: Y (A B)(B C) Compare this with the maximum SOP simplication: Y y)(x By the Boolean theorem (x are equivalent. EXAMPLE 3.23 AC z) B x yz, we see that the SOP and POS forms Find the maximum POS simplication of the logic function represented by Table 3.17. Solution Figure 3.61 shows the Karnaugh map from the truth table in Table 3.17. The cells containing 0s are grouped in two quads and there is a single 0 cell left over. Table 3.17 Truth Table for Example 3.23 A B C D Y 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 (B (A (A D) B) BC 0 1 0 1 1 1 1 1 Simplication: Corner quad: Horizontal quad: Single cell: 1 0 1 1 Y (A B)(B D)(A B C D) D) FIGURE 3.61 Example 3.23 POS Simplication of Table 3.17 SUMMARY 1. Two or more gates connected together form a logic gate network or combinational logic circuit, which can be described by a truth table, a logic diagram, or a Boolean expression. 2. The output of a combinational logic circuit is always the same with the same combination of inputs, regardless of the order in which they are applied. 3. The order of precedence in a logic gate network is AND, then OR, unless otherwise indicated by parentheses. 4. DeMorgans theorems: x y x y x y xy 5. Inequalities: x y x y xyxy 6. A logic gate network can be drawn to simplify its Boolean expression by ensuring that bubbled (active-LOW) outputs drive bubbled inputs and outputs with no bubble (activeHIGH) drive inputs with no bubble. Some gates might need to be drawn in their DeMorgan equivalent form to achieve this. 7. In Boolean expressions, logic inversion bars of equal lengths Glossary 8. 9. 10. 11. 12. 13. 14. 15. 16. cancel; bars of unequal lengths do not. Bars of equal length represent bubble-to-bubble connections. A logic diagram can be derived from a Boolean expression by order of precedence rules: synthesize ANDs before ORs, unless parentheses indicate otherwise. Inversion bars act as parentheses for a group of variables. A truth table can be derived from a logic gate network either by nding truth tables for intermediate points in the network and combining them by the laws of Boolean algebra, or by simplifying the Boolean expression into a form that can be directly written into a truth table. A sum-of-products (SOP) network combines inputs in AND gates to yield a group of product terms that are combined in an OR gate (logical sum) output. A product-of-sums (POS) network combines inputs in OR gates to yield a group of sum terms that are combined in an AND gate (logical product) output. An SOP Boolean expression can be derived from the lines in a truth table where the output is at logic 1. Each product term contains all inputs in true or complement form, where inputs at logic 0 have a bar and inputs at logic 1 do not. A POS expression is derived from the lines where the output is at logic 0. Each sum term contains all inputs in true or complement form, where inputs at logic 1 have a bar and inputs at logic 0 do not. Theorems of Boolean algebra, summarized in Table 3.8, allow us to simplify logic gate networks. SOP networks can be simplied by grouping pairs of product terms and applying the Boolean identity xyz xyz xy. POS networks can be simplified by grouping pairs of sum terms and applying the Boolean identity (x y z) (x y z ) (x y). 105 17. To achieve maximum simplication of an SOP or POS network, each product or sum term should be grouped with another if possible. A product or sum term can be grouped more than once, as long as each group has a term that is only in that group. 18. A Karnaugh map can be used to graphically reduce a Boolean expression to its simplest form by grouping adjacent cells containing 1s. One cell is equivalent to one line of a truth table. A group of adjacent cells that contain 1s represents a simplied product term. 19. Adjacent cells in a K-map differ by only one variable. Cells around the outside of the map are considered adjacent. 20. A group in a K-map must be a power of two in size: 1, 2, 4, 8, or 16. A group of two is called a pair, a group of four is a quad, and a group of eight is an octet. 21. A pair cancels one variable. A quad cancels two variables. An octet cancels three variables. 22. A K-map can have multiple groups. Each group represents one simplified product term in a sum-of-products expression. 23. Groups in K-maps can overlap as long as each group has one or more cells that appear only in that group. 24. Groups in a K-map should be as large as possible for maximum SOP simplication. 25. Dont care states represent output states of input combinations that will never occur in a circuit. They are represented by Xs in a truth table or K-map and can be used as 0s or 1s, whichever is most advantageous for the simplication of the circuit. GLOSSARY Adjacent cell Two cells are adjacent if there is only one variable that is different between the coordinates of the two cells. Associative property A mathematical function is associative if its operands can be grouped in any order without affecting the result. For example, addition is associative ((a b) c c)), but subtraction is not ((a b) c a (b a (b c)). Bubble-to-bubble convention The practice of drawing gates in a logic diagram so that inverting outputs connect to inverting inputs and noninverting outputs connect to noninverting inputs. Bus form A way of drawing a logic diagram so that each true and complement input variable is available along a conductor called a bus. Cell The smallest unit of a Karnaugh map, corresponding to one line of a truth table. The input variables are the cells coordinates and the output variable is the cells contents. Combinational logic Digital circuitry in which an output is derived from the combination of inputs, independent of the order in which they are applied. Combinatorial logic Another name for combinational logic. Commutative property A mathematical operation is commutative if it can be applied to its operands in any order without affecting the result. For example, addition is commutative (a b b a), but subtraction is not (a b b a). Distributive property Full name: distributive property of multiplication over addition. The property that allows us to distrib- ute (multiply through) an AND across several OR functions. For example, a(b c) ac bc. Dont care state An output state that can be regarded either as HIGH or LOW, as is most convenient. A dont care state is the output state of a circuit for a combination of inputs that will never occur. Karnaugh map A graphical tool for nding the maximum SOP or POS simplication of a Boolean expression. A Karnaugh map works by arranging the terms of an expression in such a way that variables can be cancelled by grouping minterms or maxterms. Levels of gating The number of gates through which a signal must pass from input to output of a logic gate network. Logic diagram A diagram, similar to a schematic, showing the connection of logic gates. Logic gate network together. Two or more logic gates connected Maximum POS simplication The form of a POS Boolean expression which cannot be further simplied by cancelling variables in the sum terms. It may be possible to get an SOP form with fewer terms or variables. 106 C H A P T E R 3 Boolean Algebra and Combinational Logic Maximum SOP simplication The form of an SOP Boolean expression which cannot be further simplied by cancelling variables in the product terms. It may be possible to get a POS form with fewer terms or variables. Product-of-sums (POS) A type of Boolean expression where several sum terms are multiplied (ANDed) together. Maxterm A sum term in a Boolean expression where all possible variables appear once in true or complement form. Sum term A term in a Boolean expression where one or more true or complement variables are ORed. Minterm A product term in a Boolean expression where all possible variables appear once in true or complement form. Sum-of-products (SOP) A type of Boolean expression where several product terms are summed (ORed) together. Octet A group of eight cells in a Karnaugh map. An octet cancels three variables in a K-map simplication. Synthesis The process of creating a logic circuit from a description such as a Boolean equation or truth table. Order of precedence The sequence in which Boolean functions are performed, unless otherwise specied by parentheses. PROBLEMS Pair A group of two cells in a Karnaugh map. A pair cancels one variable in a K-map simplication. Product term A term in a Boolean expression where one or more true or complement variables are ANDed. Truth Tables 3.1 Write the unsimplied Boolean expression for each of the logic gate networks shown in Figure 3.62. 3.2 Write the unsimplied Boolean expression for each of the logic gate networks shown in Figure 3.63. 3.3 Redraw the logic diagrams of the gate networks shown in Figure 3.63 a, e, f, h, i, and j so that they conform to the FIGURE 3.62 Problem 3.1 Logic Circuits Quad A group of four cells in a Karnaugh map. A quad cancels two variables in a K-map simplication. Problem numbers set in color indicate more difcult problems: those with underlines indicate most difcult problems. Section 3.1 Boolean Expressions, Logic Diagrams, and 107 Problems bubble-to-bubble convention. Rewrite the Boolean expression of each of the redrawn circuits. 3.4 T The circuit in Figure 3.64 is called a majority vote circuit. It will turn on an active-HIGH indicator lamp only if a majority of inputs (two out of three) are HIGH. Write the Boolean expression for the circuit. H U V W X J K L M a. b. Q Q R R X X S T S T d. c. A A B B Y Y C C f. e. J A B Y M K L C g. h. A A B C D B Y Y C i. FIGURE 3.63 Problem 3.2 Logic Circuits j. 108 3.5 C H A P T E R 3 Boolean Algebra and Combinational Logic Suppose you wish to design a circuit that indicates when three out of four inputs are HIGH. The circuit has four inputs, D3, D2, D1, and D0 and an active-HIGH output, Y. Write the Boolean expression for the circuit and draw the function represented by the following truth table. Draw the logic diagram for each form. 3.12 Find the Boolean expression, in both sum-of-products (SOP) and product-of-sums (POS) forms, for the logic function represented by the following truth table. Draw the logic diagram for the SOP form only. A 3.13 C Y 0 0 0 0 1 1 1 1 FIGURE 3.64 Problem 3.4 Majority Vote Circuit B 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 Find the Boolean expression, in both sum-of-products (SOP) and product-of-sums (POS) forms, for the logic function represented by the following truth table. Draw the logic diagram for the POS form only. logic circuit. 3.6 Draw the logic circuit for each of the following Boolean expressions: A B C Y a. Y AB b. Y ACD 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 c. Y A BCD (A d. Y BC B)(C BC D) D e. Y AC B C f. Y AC B C g. Y ABD h. Y AB AC BC BC A i. Y AB AC C BC 3.7 Use DeMorgans theorems to modify the Boolean equations in Problem 3.6, parts e, f, g, h, and i so that there is no bar over any group of variables. Redraw the logic diagrams of the circuits to reect the changes. (The nal circuit versions should conform to the bubble-to-bubble convention.) 3.8 Write the truth tables for the logic diagrams in Figure 3.62, parts b, e, f, and g. 3.9 Write the truth tables for the logic diagrams in Figure 3.63, parts a, h, i, and j. 3.10 Write the truth tables for the Boolean expression in Problem 3.6, parts c, d, e, f, h, and i. Section 3.2 Sum-of-Products (SOP) and Product-ofSums (POS) Forms 3.11 Find the Boolean expression, in both sum-of-products (SOP) and product-of-sums (POS) forms, for the logic 3.14 Find the Boolean expression, in both sum-of-products (SOP) and product-of-sums (POS) forms, for the logic function represented by the following truth table. Draw the logic diagram for the SOP form only. A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1 109 Problems 3.15 Write the POS form of the 2-input XOR function. Draw the logic diagram of the POS form of the XOR function. b. Y AAB c. J K LL 3.16 Write the POS form of the 2-input XNOR function. Draw the logic diagram of the POS form of the XNOR func- d. S (T U) V V e. S T f. Y (A B A B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 3.20 C VV C)(B D Use the rules of Boolean algebra to simplify the following expressions as much as possible. a. M PQ PQR b. M PQ PQR c. S (T U) V d. Y (A B e. Y (A B f. P (Q R g. U 3.21 F) (X (T U) D) A C D) A C S T )(Q R Y ABD ABD Q) W Z)(W Y Y W Z) Use the rules of Boolean algebra to simplify the following expressions as much as possible. a. Y ABCD (A B) C D A B b. Y ABCD (A B) C D A B c. K (L M L M )(M N L M N) M(N L) tion. Section 3.3 Theorems of Boolean Algebra Section 3.4 Simplifying SOP and POS Expressions 3.17 Write the Boolean expression for the circuit shown in Figure 3.65 Use the distributive property to transform the circuit into a sum-of-products (SOP) circuit. 3.22 Use the rules of Boolean algebra to nd the maximum SOP and POS simplications of the function represented by the following truth table. 3.18 Write the Boolean expression for the circuit shown in Figure 3.66 Use the distributive property to transform the circuit into a sum-of-products (SOP) circuit. 3.23 Use the rules of Boolean algebra to nd the maximum SOP and POS simplications of the function represented by the following truth table. 3.19 Use the rules of Boolean algebra to simplify the follow- A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A B C Y D FIGURE 3.65 Problem 3.17 Logic Circuit ing expressions as much as possible. a. Y A B C D E F FIGURE 3.66 Problem 3.18 Logic Circuit AAB C 3.24 Use the rules of Boolean algebra to nd the maximum SOP and POS simplications of the function represented by the following truth table. A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 110 3.25 C H A P T E R 3 Boolean Algebra and Combinational Logic Use the rules of Boolean algebra to nd the maximum SOP simplication of the function represented by the following truth table. A C 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 A B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 0 1 Use the rules of Boolean algebra to nd the maximum SOP simplication of the function represented by the following truth table. A B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 3.29 B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Use the rules of Boolean algebra to nd the maximum SOP simplication of the function represented by the following truth table. A 3.27 Use the rules of Boolean algebra to nd the maximum SOP simplication of the function represented by the following truth table. Y 0 0 0 0 1 1 1 1 3.26 B 3.28 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 Use the rules of Boolean algebra to nd the maximum SOP simplication of the function represented by the following truth table. A B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 1 Problems 3.30 A A B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 3.35 B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Use the rules of Boolean algebra to nd the maximum SOP simplication of the function represented by the following truth table. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 111 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 1 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. Section 3.4 Simplication by the Karnaugh Map Method A B C D Y 3.31 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 0 1 Use the Karnaugh map method to nd the maximum SOP ABCD Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 3.36 simplication of the logic diagram in Figure 3.21. 3.32 Use the Karnaugh map method to reduce the following Boolean expressions to their maximum SOP simplications: a. Y ABC ABC ABC b. Y ABC ABC ABC ABC c. Y ABC ABC ABC ABC d. Y ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABC 3.33 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. 3.34 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. A B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 1 X X X X X X 112 3.37 C H A P T E R 3 Boolean Algebra and Combinational Logic A B C D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 0 B C D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. D Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 1 1 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. 3.41 B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C A Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. A 3.39 3.40 B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3.38 A Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 1 0 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. Problems A C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3.42 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 The circuit in Figure 3.67 represents the maximum SOP simplication of a Boolean function. Use a Karnaugh map to derive the circuit for the maximum POS A B C D Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. A B C D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 C D Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 simplication. FIGURE 3.67 Problem 3.44: Logic Circuit 3.45 Repeat Problem 3.44 for the circuit in Figure 3.68. 3.46 Refer to the BCD-to-2421 code converter developed in Example 3.22. Use a similar design procedure to develop Y 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Use the Karnaugh map method to reduce the Boolean expression represented by the following truth table to simplest SOP form. A 3.43 3.44 113 FIGURE 3.68 Problem 3.45: Logic Circuit the circuit of a 2421-to-BCD code converter. 3.47 Excess-3 code is a decimal code that is generated by adding 0011 ( 310) to a BCD code. Table 3.18 shows 114 C H A P T E R 3 Boolean Algebra and Combinational Logic ANSWERS TO SECTION REVIEW the relationship between a decimal digital code, natural BCD code, and Excess-3 code. Draw the circuit of a BCD-to-Excess-3 code converter, using the Karnaugh map method to simplify all Boolean expressions. 3.48 Repeat Problem 3.47 for an Excess-3-to-BCD code converter. Table 3.18 BCD and Excess-3 Code Decimal Equivalent D4 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 BCD Code D3 D2 D1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 E4 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 Excess-3 E3 E2 0 1 1 1 1 0 0 0 0 1 E1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 PROBLEMS Section 3.3 Section 3.1 3.1a Y ABC D b OUT (W X Y )Z 3.3a SOP: Y POS: Y Section 3.2 A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 b SOP: Y POS: Y ABC (A (A B B ABC ABC C )(A C )(A ABC (A (A B B C )(A C) 3.4a Y AC or Y A C 3.4c Y B B C )(A C )(A ABC B B B C) C) ABC C )(A B C) AB Section 3.4 3.4b Y Y AC D or ACD Section 3.5 3.5 SOP: Y AC BC POS: Y (A C )(B C) CHAPTER 4 Introduction to PLDs and MAX PLUS II OUTLINE CHAPTER OBJECTIVES 4.1 4.2 Upon successful completion of this chapter you will be able to: Describe some advantages of programmable logic over xed-function logic. Name some types of programmable logic devices (PLDs). Use Alteras MAX PLUS II PLD Design Software to enter simple combinational circuits using schematic capture. Use VHDL entity declarations, architecture bodies, and concurrent signal assignments to enter simple combinational circuits. Create circuit symbols from schematic or VHDL designs and use them in hierarchical designs for PLDs. Assign device and pin numbers to schematic or VHDL designs and compile them for programming Altera MAX7000S or FLEX10K20 devices. 4.3 4.4 4.5 4.6 4.7 What is a PLD? Programming PLDs using MAX PLUS II Graphic Design File Compiling MAX PLUS II Files Hierarchical Design Text Design File (VHDL) Creating a Physical Design Program Altera PLDs via a JTAG interface and a ByteBlaster Parallel Port Download Cable. I n the rst three chapters of this book, we examined logic gates and Boolean algebra. These basic foundations of combinational circuitry, as well as the sequential logic circuits we will study in a later chapter, form the fundamental building blocks of many digital integrated circuits (ICs). In the past, such digital ICs were xed in their logic functions; it was not possible to change designs without changing the chips in a circuit. Programmable logic offers the digital circuit designer the possibility of changing design function even after it has been built. A programmable logic device (PLD) can be programmed, erased, and reprogrammed many times, allowing easier prototyping and design modication. (The industry marketing buzz often refers to rapid prototyping and reduced time to market.) The number of IC packages required to implement a design with one or more PLDs is often reduced, compared to a design fabricated using standard xed-function ICs. PLDs can be programmed from a personal computer (PC) or workstation running special software. This software is often associated with a set of programs that allow us to design circuits for various PLDs. MAX PLUS II, owned by Altera Corporation, is such a software package. MAX PLUS II allows us to enter PLD designs, either as schematics or in several hardware description languages (specialized computer languages for modeling and synthesizing digital hardware). A design can contain components that are in themselves complete digital circuits. MAX PLUS II converts the design information 115 116 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II into a binary form that can be transferred into a PLD via a special interface connected to the parallel port of a PC. I 4.1 What Is a PLD? KEY TERMS Programmable logic device (PLD) A digital integrated circuit that can be programmed by the user to implement any digital logic function. Complex PLD (CPLD) A digital device consisting of several programmable sections with internal interconnections between the sections. MAX PLUS II CPLD design and programming software owned by Altera Corporation. Schematic capture A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD. Compile The process used by CPLD design software to interpret design information (such as a drawing or text le) and create required programming information for a CPLD. One of the most far-reaching developments in digital electronics has been the introduction of programmable logic devices (PLDs). Prior to the development of PLDs, digital circuits were constructed in various scales of integrated circuit logic, such as small scale integration (SSI) and medium scale integration (MSI) devices. These devices contained logic gates and other digital circuits. The functions were determined at the time of manufacture and could not be changed. This necessitated the manufacture of a large number of device types, requiring shelves full of data books just to describe them. Also, if a designer wanted a device with a particular function that was not in a manufacturers list of offerings, he or she was forced to make a circuit that used multiple devices, some of which might contain functions neither wanted nor needed, thus wasting circuit board space and design time. Programmable logic provides a solution to these problems. A PLD is supplied to the user with no logic function programmed in at all. It is up to the designer to make the PLD perform in whatever way a design requires; only those functions required by the design need be programmed. Since several functions can usually be combined in the design and programmed onto a single chip, the package count and required board space can be reduced as well. Also, if a design needs to be changed, a PLD can be reprogrammed with the new design information, often without removing it from the circuit. PLD is a generic term. There is a wide variety of PLD types, including PAL (programmable array logic), GAL (generic array logic), EPLD (erasable PLD), CPLD (complex PLD), FPGA (eld-programmable gate array), as well as several others. We will be focussing on CPLDs as a representative type of PLD. Although terminology varies somewhat throughout the industry, we will use the term CPLD to mean a device with several programmable sections that are connected internally. In effect, a CPLD is several interconnected PLDs on a single chip. This structure is not apparent to the user and doesnt really concern us at this time, except as background information. We will look at the structure of PALs, GALs, and CPLDs in Chapter 8. We will use the term PLD when we are referring to a generic device and CPLD as a more specic type of PLD. A complication in the use of programmable logic is that we must use specialized computer software to design and program our circuit. Initially, this might seem as though we are adding another level of work to the design, but when these computer techniques are mastered, it shortens the design process greatly and yields a level of exibility not otherwise available. 4.1 What Is a PLD? 117 Lets look at two examples, comparing the use of SSI logic versus programmable logic. EXAMPLE 4.1 Figure 4.1 shows a majority vote circuit, as described in Problem 3.4 of Chapter 3. This circuit will produce a HIGH output when two out of three inputs are HIGH. Write the Boolean equation for the circuit and state the minimum number and type of 74HC devices required to build the circuit. How many packages would be required to build two such circuits? A B Y C FIGURE 4.1 Majority Vote Circuit Solution Boolean equation: Y AB BC AC Figure 4.2 shows the 74HC devices required to build the majority vote circuit: one 74HC08A quad 2-input AND gate and one 74HC4075 triple 3-input OR gate. Figure 4.2 also shows connections between the devices. Note that unused gate inputs are grounded and unused outputs are left open. C Vcc Vcc A B 74HC08A Y 74HC4075 FIGURE 4.2 74HC Devices Required to Build a Majority Vote Circuit Two majority vote circuits would require 6 ANDs and two ORs. This requires one more 74HC08A package. EXAMPLE 4.2 Show how a CPLD can be programmed with a majority vote function, using a schematic capture tool. State how many CPLDs would be required to build two majority vote circuits. Solution A CPLD can be programmed by entering the schematic directly, using PLD programming software, such as Altera Corporations MAX PLUS II. Figure 4.3 shows the circuit as entered in a MAX PLUS II Graphic Design File. 118 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II INPUT AND2 INPUT AND2 A B OR3 OUTPUT Y AND2 INPUT C FIGURE 4.3 MAX PLUS II Graphic Design File of a Majority Vote Circuit The design can be compiled by MAX PLUS II to create the information required to program the CPLD with the majority vote circuit. If a second copy of the circuit is required, the rst circuit can easily be duplicated by a Copy and Paste procedure. The two circuits can than be compiled together and used to program a single CPLD. 4.2 Programming PLDs using MAX PLUS II KEY TERMS Design entry The process of using software tools to describe the design requirements of a PLD. Design entry can be done by entering a schematic or a text le that describes the required digital function. Fitting Assigning internal PLD circuitry, as well as input and output pins, for a PLD design. Simulation Verifying design function by specifying a set of inputs and observing the resultant outputs. Simulation is generally shown as a series of input and output waveforms. Programming Transferring design information from the computer running PLD design software to the actual PLD chip. Download Program a PLD from a computer running PLD design and programming software. Software tools Specialized computer programs used to perform specic functions such as design entry, compiling, tting, and so on. (Sometimes just called tools.) Suite (of software tools) A related collection of tools for performing specic tasks. MAX PLUS II is a suite of tools for designing and programming digital functions in a PLD. Target device The specic PLD for which a digital design is intended. Altera UP-1 board A circuit board, part ofAlteras University Program Design Laboratory Package, containing two CPLDs and a number of input and output devices. In order to take a digital design from the idea stage to the programmed silicon chip, we must go through a series of steps known as the PLD Design Cycle. These include design entry, simulation, compiling, tting, and programming. All steps require the use of PLD software, such as Alteras MAX PLUS II, a suite of software tools, to perform the various tasks of the design cycle. Some tasks, such as design entry, require a great deal of attention; others, such as tting a design to a specied CPLD, are done automatically during the compiling process. We will be using MAX PLUS II as a vehicle for learning the concepts that relate to PLD design and programming. The target devices for our designs will be two Altera CPLDs, both installed on a circuit board available from Altera called the University Pro- 4.2 Programming PLDs Using MAX+PLUS II 119 gram Design Laboratory Package. We will generally refer to this board, shown in Figure 4.4, as the Altera UP-1 board. FIGURE 4.4 Altera UP-1 Board Figure 4.5 shows photos of the two CPLDs used in the Altera UP-1 Board. Figure 4.5a shows the CPLD from the MAX7000S family, part number EPM7128SLC84-7. Figure 4.5b shows the CPLD from Alteras FLEX10K series, part number EPF10K20RC240-4. These part numbers are meaningful and will be discussed in detail in Chapter 8. FIGURE 4.5 Altera MAX7000S and FLEX10K CPLDs In the remaining part of this chapter, we will learn how to enter a design in MAX PLUS II in both graphical and text format, how to compile the design, and how to download it into either one of the CPLDs on the Altera UP-1 circuit board. Treat this design example as a tutorial in MAX PLUS II. Follow along with all the steps on your own computer to get the maximum benet from the chapter. If you do not have access to the Altera UP-1 board or an equivalent, you can still follow through most of the steps. 120 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II NOTE Although the examples in this book are created with the Altera UP-1 board in mind, they will easily adapt to other circuit boards carrying an Altera EPM7128S or other similar CPLD. One such board is available from Intectra Inc. For further information, contact Intectra at: Intectra, Inc 2629 Terminal Blvd Mountain View, CA 94043 U.S.A. Ph 650-967-8818 Fx 650-967-8836 intectra@best.com www.intectra.com (Web site in Spanish only) 4.3 Graphic Design File KEY TERMS Graphic Design File (gdf) A PLD design le in which the digital design is entered as a schematic. Project A set of MAX PLUS II les associated with a particular PLD design. One way of entering PLD designs is to create a Graphic Design File. This type of le contains a representation of a digital circuit, such as in Figure 4.3, showing components and their interconnections, as well as specifying the inputs and output names of the circuit. MAX PLUS II automatically generates a number of other les to keep track of the PLD programming information represented by the Graphic Design File. These les, taken together, represent a project in MAX PLUS II. All operations required to create a programming le for a CPLD are performed on a project, not a le. Thus, it is important during the design process to keep track of what the current project is. The MAX PLUS II toolbar, shown in Figure 4.6, makes this fairly easy. Hierarchy Display Create New File Open File Save File Timing Simulator Undo Last Action Project Save Programmer and Check Compiler Timing Analyzer Set Project to Current File Project Save and Simulate Search for Text Project Save and Compile Text Search and Replace FIGURE 4.6 MAX PLUS II Toolbar The toolbar has a number of buttons that pertain to the current project of a PLD design. The operations performed by these buttons can all be done through the regular menus of MAX PLUS II, but the toolbar offers a quick way to access many available functions. Not all buttons on the toolbar in Figure 4.6 are labeled, just the ones that you will nd particularly convenient at this time. You can nd out the function of any button by placing the cursor on the button and reading a description at the bottom of the window. 4.3 Graphic Design File 121 In particular, notice the buttons that create, open, and save les (standard Windows icons) and the button that sets the project to the current le. When creating a new le, make it standard practice to rst Save the le, then Set Project to Current File. If you do this as a habit, you (and MAX PLUS II) will always know what the current project is. If you dont, you will nd that you are saving or compiling some other project and wondering why your last set of changes didnt work. Another good practice is to create a new Windows folder for each new design that you enter. Since MAX PLUS II creates many les in the design process, the folders would become unmanageable if designs were not kept in separate folders. MAX PLUS II installs a folder for working with design les called max2work. The examples in this text will be created in a subfolder of max2work. If you are working in a situation where many people share a computer and you have access to a network drive of your own, you may wish to keep your working les in a max2work folder on the network drive. Avoid storing your working les on a local hard drive unless you are the only one with regular access to the computer. Examples in this book will not specify a drive letter, but will indicate drive:\max2work\folder. Most of these examples are also available on the accompanying CD in the folder called Student Files. A special icon, shown in the margin, will indicate the example lename. In the following sections, we will go through the process of creating a le in detail, using the majority vote circuit of Figure 4.3 as an example. The example assumes that MAX PLUS II is properly installed on your computer and running. For installation instructions, see the le SE_READ on the accompanying CD or the MAX PLUS II Installation section of MAX PLUS II Getting Started, available from Altera. Entering Components KEY TERMS Primitives Basic functional blocks, such as logic gates, used in PLD design les. Instance A single copy of a component in a PLD design le. To create a Graphic Design File, click the New File icon on the tool bar or choose New on the MAX PLUS II File menu. The dialog box, shown in Figure 4.7 appears. Select Graphic Editor le and choose OK. FIGURE 4.7 New Dialog Box Maximize the window and click the Save icon or choose Save As or Save from the File menu. In the dialog box shown in Figure 4.8, save the le in a new folder (e.g., drive:\max2work\maj_vote\maj_vote.gdf) and choose OK. (If you have not created the new folder, just type the complete path name in the File Name box. MAX PLUS II will 122 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II FIGURE 4.8 Save As Dialog Box create a new folder.) Click the icon to Set Project to Current File or choose this action from the File, Project menu. The rst design step is to lay out and align the required components. We require three 2-input AND gates, a 3-input OR gate, three input pins, and one output pin. These basic components are referred to as primitives. Let us start by entering three copies of the AND gate primitive, called and2. Click the left mouse button to place the cursor (a ashing square) somewhere in the middle of the active window. Right-click to get a pop-up menu, shown in Figure 4.9, and choose Enter Symbol. The dialog box in Figure 4.10 appears. Type and2 in the Symbol Name box and choose OK. A copy or instance of the and2 primitive appears in the active window. FIGURE 4.9 Enter Symbol Pop-up Menu You can repeat the above procedure to get two more instances of the and2 primitive, or you can use the Copy and Paste commands. These are the same icons and File commands as for other Windows programs. Highlight the and2 symbol by clicking it. Right-click the symbol to get the pop-up menu shown in Figure 4.11 and choose Copy. You can also click the Copy icon on the toolbar or use the Copy command in the File menu. 4.3 FIGURE 4.10 Enter Symbol Dialog Box FIGURE 4.11 Copying a Component Graphic Design File 123 124 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II Paste an instance of the primitive by clicking to place the cursor, then right-clicking to bring up the menu shown in Figure 4.12. Choose Paste. The component will appear at the cursor location, marked in Figure 4.12 by the square at the top left corner of the pop-up menu. Enter the remaining components by following the Enter Symbol procedure outlined above. The primitives are called or3, input, and output. When all components are entered we can align them, as in Figure 4.13 by highlighting, then dragging each one to a desired location. FIGURE 4.12 Pasting a Component FIGURE 4.13 Aligned Components Connecting Components To connect components, click over one end of one component and drag a line to one end of a second component. When you drag the line, a horizontal and a vertical broken line mark the cursor position, as shown in Figure 4.14. These lines help you align connections properly. 4.3 Graphic Design File 125 FIGURE 4.14 Dragging a Line to Connect Components FIGURE 4.15 Making a 90-degree Bend and a Connection A line will automatically make a connection to a perpendicular line, as shown in Figure 4.15. A line can have one 90-degree bend, as at the inputs of the AND gates. If a line requires two bends, such as shown at the AND outputs in Figure 4.16, you must draw two separate lines. Assigning Pin Names Before a design can be compiled, its inputs and outputs must be assigned names. We could also specify pin numbers, if we wished to make the design conform to a particular CPLD, but it is not necessary to do so at this stage. It may not even be desirable to assign pin numbers, since the design we enter can be used as a component or subdesign of a larger circuit. We may also wish MAX PLUS II to assign pins to make the best use of the CPLDs internal resources. At any rate, we will leave this step out for now. 126 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II FIGURE 4.16 Line with Two 90-degree Bends Figure 4.17 shows the naming procedure. Pins A and B have already been assigned names. Highlight a pin by clicking on it. Right-click the highlighted pin and choose Edit Pin Name from the pop-up menu. You could also double-click the pin name to highlight it. Type in the new name. If there are several pins that are spaced one above the other, you can highlight the top pin name, as described above, then highlight successive pin names by using the Enter key. FIGURE 4.17 Assigning Pin Names 4.4 Compiling MAX+PLUS II Files 127 4.4 Compiling MAX PLUS II Files KEY TERMS Programmer Object File (pof) Binary le used to program a PLD of the Altera MAX series. SRAM Object File (sof) Binary le used to congure a PLD of the Altera FLEX series. Volatile A device is volatile if it does not retain its stored information after the power to the device is removed. Nonvolatile Able to retain stored information after power is removed. The MAX PLUS II compiler converts design entry information into binary les that can be used to program a PLD. Before compiling, we should assign a target device to the design. From the Assign menu, shown in Figure 4.18, select Device. From the dialog box in Figure 4.19, select the target device. For the Altera UP-1 board, this would be either the EPM7128SLC84-7 (shown) or the FLEX10K20RC240-4. The device family for the EPM7128S device is MAX7000S. FIGURE 4.18 Assign Menu NOTE To see the EPM7128SLC84-7 device, the box that says Show Only Fastest Speed Grades must be unchecked. The compiler has a number of settings that can be chosen prior to the actual compile process. Figure 4.20 shows some of the settings that should be selected from the Processing menu of the Compiler window. You can open the Compiler window from the MAX PLUS II menu or by clicking the Compiler button on the toolbar at the top of the screen. 128 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II FIGURE 4.19 Device Dialog Box FIGURE 4.20 MAX PLUS II Compiler Settings Design Doctor is a utility that checks for adherence to good design practice and will warn you of any bad design choices. (Design Doctor will not stop the design from compiling, but will suggest potential problems that could result from a particular design.) The Timing SNF Extractor creates a Simulation Netlist File, which is required to perform a timing simulation of the design. We will perform this step in later MAX PLUS II designs. (If you are not able to select the Timing SNF Extractor, then uncheck the Functional SNF Extractor option.) Smart Recompile allows the compiler to use previously compiled portions of the design to which no changes have been made. This allows the compiler to avoid having to compile the entire design each time a change is made to one part of the design. To start the compile process, click Start in the Compiler window. While in progress, the window will look something like Figure 4.21. Message of three types may appear during the compile process. Info messages (green text) are for information only. Warning messages (blue text) tell you of potential, but nonfatal, problems with the design. Error messages (red text) inform you of design aws that render the design unusable. A PLD can still be programmed if the compiler generates info or warning messages, but not if it generates an error. Depending on the device chosen, the compiler generates either a Programmer Object File (pof) or SRAM Object File (sof). The pof is used to program a MAX-series PLD. The sof is used to congure a FLEX-series PLD. The difference is that the MAX de- 4.5 Hierarchial Design 129 FIGURE 4.21 MAX PLUS II Compiler Operation vice is nonvolatile, that is, it retains its programming information after the power has been removed. The FLEX-series device is volatile, meaning that its programming information must be loaded each time the device powers up. 4.5 Hierarchical Design KEY TERMS Hierarchical design A PLD design that is ordered in layers or levels. The highest level of design contains components that are themselves complete designs. These components may, in turn, have lower level designs embedded within them. A MAX PLUS II Graphical Design File can be used as part of a hierarchical design. That is, it can be represented as a component in a higher-level design. Figure 4.22 shows a gdf that is constructed as a hierarchical design. It contains two majority vote circuits whose maj_vote INPUT A1 B1 INPUT INPUT A Y B AND2 C C1 OUTPUT Y maj_vote INPUT A2 B2 INPUT INPUT C2 FIGURE 4.22 Two-level Majority Vote Circuit (2votes.gdf) A B C Y 130 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II outputs are combined in an AND gate. Thus, the output would be HIGH if two out of three inputs were HIGH on both blocks labeled maj_vote. These blocks are complete designs in their own right, and thus form a lower level of the design hierarchy. Default Symbols and User Libraries KEY TERMS Default symbol A graphical symbol that represents a PLD design as a block, showing only the designs inputs and outputs. The symbol can be used as a component in any Graphic Design File. User library A folder containing symbols that can be used in a gdf le. Top level (of a hierarchy) The le in a hierarchy that contains components specied in other design les and is not itself a component of a higher-level le. We can create a default symbol for the majority vote circuit of Figure 4.3 from the MAX PLUS II File menu, as shown in Figure 4.23. This action will create a symbol le with the same name as the Graphic Design File and the extension sym. Before creating the symbol, make sure that the gdf is saved and that the project is set to the current le. FIGURE 4.23 Creating a Default Symbol The symbol can be embedded into a gdf, as in Figure 4.22. Before we can use the new symbol, we must make sure that MAX PLUS II knows where to nd it. MAX PLUS II looks for a component rst in the present working directory, then in the user library folders in the order of priority listed in the User Libraries dialog box. To create a path to a user library, select User Libraries from the Options menu (Figure 4.24) in MAX PLUS II. In the resultant dialog box, shown in Figure 4.25, select the appropriate drive and directories by double-clicking on the name in the Directories box. When the desired directory appears in the Directory Name box, click 4.5 FIGURE 4.24 Options Menu FIGURE 4.25 User Libraries Dialog Box Add, then OK. Hierarchical Design 131 132 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II NOTE 2votes.gdf maj_vote.gdf 4votes.gdf If you are using MAX PLUS II on a shared computer (e.g., in a computer lab), you should be aware that a library path that points to another users directory can cause MAX PLUS II to look there before (or instead of) looking in your directory, resulting in the apparent inability of MAX PLUS II to nd your le. For example, suppose you have a le called g:\max2work\my_le.gdf, where g:\ is a network drive mapped exclusively to your user account. (i.e., everyone has a g:\ drive mapping, unique to their user account.) Further suppose that another user, against standard lab protocol, has created a le with the same name on the local hard drive: c:\max2work\my_le.gdf. (Dont think this doesnt happen. It does.) At compile time, MAX PLUS II will look for my_le.gdf rst in the directory where the active project resides, then in the folders specied in the user library paths. If the user library path c:\max2work\ has a higher priority than g:\max2work\, it will compile the version of myle.gdf found on the c: \drive. When you make changes to the copy on the g: \drive, they will not take effect because the le on g:\ is not being compiled. To remedy this, delete the user libraries that point to local drives, such as a:\ or c:\. If you have no assigned network drive on your system, delete all user libraries except for your own. Since a user library is just the name of a folder where MAX PLUS II should look for les, this wont do any great harm. Creating a Design Hierarchy The circuit in Figure 4.22 is saved as 2votes.gdf. If we double-click on either symbol la2votes INPUT A11 B11 C11 A21 B21 INPUT INPUT INPUT INPUT INPUT C21 A1 B1 C1 Y A2 B2 AND2 C2 OUTPUT Y 2votes INPUT A12 B12 C12 A22 B22 INPUT INPUT INPUT INPUT INPUT C22 A1 B1 C1 A2 Y B2 C2 FIGURE 4.26 Further Levels of Hierarchy (4votes.gdf) beled maj vote, the MAX PLUS II Graphic Editor will bring the le maj_vote.gdf to the foreground. Thus, we say that 2votes.gdf is at the top level of the current hierarchy. We can extend the hierarchy further by making a symbol for 2votes.gdf and embedding it in a higher-level le called 4votes.gdf, shown in Figure 4.26. This circuit generates a HIGH output if (two out of three of (A11, B11, C11) are HIGH AND two out of three of 4.6 Text Design File (VHDL) 133 FIGURE 4.27 Hierarchy Display for Project 4votes (A21, B21, C21) are HIGH) OR the same is true for (A12, B12, C12) AND (A22, B22, C22). If we double-click on either symbol for 2votes, the Graphic Editor will bring the le 2votes.gdf to the foreground. MAX PLUS II can display the hierarchy of a design. To see the hierarchy structure, click the Hierarchy icon on the MAX PLUS II toolbar (the yellow pyramid) or choose Hierarchy Display from the MAX PLUS II menu. Figure 4.27 shows the hierarchy for the project 4votes. Note that the highest level has two subdesigns, each of which breaks down further into two subdesigns. Thus, using hierarchical design and symbols for gdf or other design les allows us to create multiple instances of a basic design (maj_vote.gdf) and use it in many places. NOTE In order to correctly show the hierarchy display, the top-level le of the project (in this case 4votes.gdf) must be compiled rst. 4.6 Text Design File (VHDL) KEY TERMS Hardware description language A computer language used to design digital circuits by entering text-based descriptions of the circuits. AHDL (Altera Hardware Description Language) Alteras proprietary textentry design tool for PLDs. VHDL (VHSIC Hardware Description Language) An industry-standard computer language used to model digital circuits and produce programming data for PLDs. VHSIC Very high speed integrated circuit Syntax The grammar of a computer language. (i.e., the rules of construction of language statements) ASICs (application specic integrated circuits) Integrated circuits that are constructed for a specic design purpose. The term could refer to a PLD, although it usually means a custom-designed xed function device. An alternative to schematic entry, and ultimately a more powerful PLD design technique is the use of a text-based design tool, or hardware description language, such as Alteras AHDL (Altera Hardware Description Language) or the industry-standard VHDL (VHSIC Hardware Description Language). A designer creates a text le, framed within a certain set of rules known as the syntax of the language and uses a compiler to create pro- 134 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II gramming data much as he or she would with a Graphic Design File. Hardware description languages can be used to generate hardware for hierarchical designs, either as components in graphic or text les or as higher level design entities containing other designs. AHDL, while very easy to use, has a much narrower application than VHDL because it is one of many proprietary tools on the market aimed at the programming requirements of a particular manufacturers line of CPLDs. Since VHDL is an industry-standard language and the MAX PLUS II compiler supports both languages, we will concentrate on VHDL. VHDL was originally developed by defense contractors in the U.S. and is now the required standard for all ASICs (application specic integrated circuits) designed for the U.S. military. It has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) and has been enjoying increasing popularity in the electronics design community. The original VHDL standard was written in 1987 and updated in 1993 (IEEE Std. 1076-1993). This standard and other related ones continue to undergo revision. The current status of Std. 1076 can be determined from the IEEE Standards web site at http://www.standards.ieee.org. Entity and Architecture KEY TERMS Entity A VHDL structure that denes the inputs and outputs of a design. Architecture A VHDL structure than denes the relationship between input, output, and internal signals or variables in a design. Port A name assigned to an input or output of a VHDL design entity. Mode (of a port) The kind of port, such as input or output. Signal A name given to an internal connection in a VHDL architecture. Variable A block of working memory used for internal calculation or storage in a VHDL architecture. Type A set of characteristics associated with a VHDL port name, signal, or variable that determines the allowable values of the port, signal, or variable. Library A collection of VHDL design units that have been previously compiled. Package A group of VHDL design elements that can be used by more than one VHDL le. IEEE Standard 1164 The standard which denes a variety of VHDL types and operations, including the STD_LOGIC and STD_LOGIC_VECTOR types. Concurrent Simultaneous. Concurrent signal assignment A relationship between an input and output port or signal in which the output is changed as soon as there is a change in input. If the le has more than one concurrent signal assignment, they are all evaluated simultaneously. Selected signal assignment statement A concurrent signal assignment in VHDL in which a value is assigned to a signal, depending on the alternative values of another signal or variable. Comment Explanatory text in a VHDL (or other computer language) le that is ignored by the computer at compile time. Vector A group of digital signals or variables, usually related numerically, that can be treated as a single multibit variable. Bit string literal A group of bits assigned to the elements of a vector, enclosed in double quotes (e.g., 001011). 4.6 maj_vot2.vhd Text Design File (VHDL) 135 Every VHDL le requires at least two structures: an entity declaration and an architecture body. The entity declaration denes the external aspects of the VHDL function; that is, the input and output names and the name of the function. The architecture body denes the internal aspects; that is, how the inputs and outputs behave with respect to one another and with respect to other signals or functions that are internal only. Let us examine the structure of a VHDL design for the majority vote circuit dened in Figure 4.1. The complete VHDL le for the majority vote circuit is shown next. The double dashes before the rst two lines are to indicate that these lines are comments. There are also a few other comments to illustrate the use of VHDL. maj_vot2.vhd VHDL implementation of a majority vote circuit Library contains standard VHDL logic types LIBRARY ieee; USE ieee.std_logic_1164.ALL; Entity denes inputs and outputs ENTITY maj_vot2 IS PORT ( a, b, c : IN STD LOGIC; y : OUT STD LOGIC); END maj_vot2; Architecture describes input/output relationship ARCHITECTURE majority OF maj_vot2 IS BEGIN y <= (a and b) or (b and c) or (a and c); END majority; NOTE FIGURE 4.28 Graphical Representation of a VHDL Design Entity VHDL is not case-sensitive, so statements written in lowercase and uppercase are equivalent. For example, (Y A AND B;) is equivalent to (y a and b;). However, Alteras style guidelines for VHDL suggest that all keywords, devices, constants, and primitives be capitalized and everything else be written in lowercase letters. The VHDL style guideline can be referred to in the MAX PLUS II Help menu. The name of the entity, maj_vot2, is given in the rst and last lines of the entity declaration. The VHDL le that contains this entity must be named maj_vot2.vhd. Figure 4.28 shows how the design entity looks if it is converted to a symbol for use in a Graphic Design File. The Boolean equation for a 3-input majority vote circuit is Y AB BC AC. In the architecture body, we can write this operation as: y <= (a and b) or (b and c) or (a and c); The operator <= assigns the value of the right hand side of the equation to the left hand side. Whenever there is a change in a, b, or c, the statement is re-evaluated and the new value is assigned to y. Note that VHDL logical operators (such as and and or) have equal precedence, so we must make the order of precedence explicit with parentheses. The Boolean equation above is an example of a concurrent signal assignment statement. Concurrent means simultaneous. The implication is that any number of concurrent signal assignments can be listed in a VHDL architecture body and the order in which they are evaluated does not depend on the order in which they are written, since all statements are concurrent. In this way, a concurrent structure imitates combinational hardware, where 136 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II OUT IN INOUT BUFFER CPLD logic FIGURE 4.29 VHDL Port Modes a change in one input that is common to several circuits makes all circuits change at the same time. Enclosed in the entity declaration is a port denition. A port is a connection from the PLD to the outside world. Figure 4.29 shows the possible modes of a port. Mode IN refers BUFFER a x a and b; b OUT y x or c; c FIGURE 4.30 BUFFER and OUT Modes to a port that is only for input. Mode OUT is output only. Mode INOUT is a bidirectional port, in which data can ow in either direction, based on the status of a control input. Mode BUFFER is a special case of OUT that has a feedback connection back into the CPLD logic that can be used as part of another Boolean expression. Figure 4.30 shows the difference between BUFFER and OUT modes. Port x (dened by x <= a and b;) must be of mode BUFFER because it is fed back and used as part of the expression for port y (dened by y <= x or c;). Port y can be of mode OUT since it has no feedback, only an output. In addition to dening the port modes, the entity declaration also denes what type each port is. The type of a port, signal, or variable denes what values it is allowed to have. Three common types in VHDL are BIT, STD_LOGIC, and INTEGER. Multibit extensions of these types include BIT_VECTOR and STD_LOGIC_VECTOR. Ports, signals and variables of type BIT can have a value of 0 or 1. When using these values, they must be enclosed in single quotes. The STD_LOGIC (standard logic) type, also called IEEE Std.1164 Multi-Valued Logic, has been dened to give a broader range of output values than just 0 and 1. Any port, signal, or variable of type STD_LOGIC or STD_LOGIC_VECTOR can have any of the values listed below. U, X, 0, 1, Z, Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance 4.6 W, L, H, - Text Design File (VHDL) 137 Weak Unknown Weak 0 Weak 1 Dont care Forcing levels are deemed to be the equivalent of a gate output. Weak levels are specied by a pull-up or pull-down resistor. (Weak levels are usually used in circuit modeling, where it is important to distinguish between gate outputs and pull-up/down. These levels will not be of importance to us.) The Z state is used as the high-impedance state of a tristate buffer. The majority of applications can be handled by X, 0, 1, and Z values. To use STD_LOGIC in a VHDL le, you must include the following reference to the VHDL library called ieee and the std_logic_1164 package before the entity declaration: LIBRARY ieee; USE ieee.std_logic_1164.ALL; Table 4.1 Some Common VHDL Types Type Values How Written Examples BIT 0 or 1 Single quotes 0, 1 STD_LOGIC U, X, 0, 1, Z, W, L, H, - Single quotes X, 0, 1, Z INTEGER Whole numbers No quotes 4095, 7, -120, -1 BIT_VECTOR Multiple instances of 0 or 1 Double quotes 100110 STD_LOGIC_VECTOR Multiple instances of U, X, 0, 1, Z, W, L, H, - Double quotes 1001100, 00ZZ11, ZZZZZZZZ Why use STD_LOGIC rather than BIT, if we only use 0 and 1 values? The usual reason is for compatibility with existing VHDL components that might be used in our design entities. For example, the Altera Library of Parameterized Modules (LPM) contains FIGURE 4.31 2-line-to-4-line Decoder D0 D1 Y0 Y1 Y2 Y3 138 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II predesigned components that are written using STD_LOGIC types. To include these components in a VHDL design, the design must be written with STD_LOGIC types, as well. The INTEGER type can take on whole-number values. When used in a VHDL le, an integer is written without quotes. Table 4.1 summarizes the BIT, STD_LOGIC, and INTEGER types, as well as the BIT_VECTOR and STD_LOGIC_VECTOR types. EXAMPLE 4.3 decode1.vhd Figure 4.31 shows the logic diagram of a 2-line-to-4-line decoder. The circuit detects the presence of a particular binary code and makes one and only one output HIGH, depending on the value of the 2-bit number D1D0. Write a VHDL le that describes the decoder. Solution The circuit has two inputs and four outputs, which are numerically related. We could describe the two inputs as separate names, as we could the four outputs. Or, we could show the inputs and outputs as two groups of related ports, called vectors. The elements of the vector can be treated separately or as a group. Case 1: separate variables LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode1 IS PORT( d1, d0 y0, y1, y2, y3 END decode1; decode2.vhd : IN STD_LOGIC; : OUT STD_LOGIC); ARCHITECTURE decoder1 OF decode1 IS BEGIN y0 <= (not d1) and (not y1 <= (not d1) and ( y2 <= ( d1) and (not y3 <= ( d1) and ( END decoder1; d0); d0); d0); d0); Case 2: vectors (elements treated separately) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode2 IS PORT ( d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode2; decode2a.vhd ARCHITECTURE decoder2 OF decode2 BEGIN y(0) <= (not d(1)) and y(1) <= (not d(1)) and y(2) <= ( d(1)) and y(3) <= ( d(1)) and END decoder2; IS (not ( (not ( d(0)); d(0)); d(0)); d(0)); In Case 2, we specify the length of the vector by the construct (3 downto 0), indicating that Y3 is the leftmost bit in the vector. We could also use the constructs (0 to 3), (4 downto 1), or (1 to 4), depending on our requirements. Each individual element of the vector is specied by a number in parentheses. Case 3: vectors (elements treated as a group) decode2a.vhd 4-channel decoder 4.6 Text Design File (VHDL) 139 Makes one and only one output HIGH for each binary combination of (d1, d0). LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode2a IS PORT ( d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode2a; ARCHITECTURE decoder OF decode2a IS BEGIN Choose a signal assignment for y based on binary value of d Default case: all outputs deactivated WITH d SELECT y <= 0001 WHEN 00, 0010 WHEN 01, 0100 WHEN 10, 1000 WHEN 11, 0000 WHEN others; END decoder; In Case 3, we use a selected signal assignment statement to assign a value to all bits of vector y for each combined value of vector d. For example, when d(1) 0 and d(0) 0, the values assigned to y are: y(3) 1, y(2) 0, y(1) 0, y(0) 0. Similar assignments are made for other values of d. The result is a construct that acts much like a truth table of the decoder circuit. The others clause is necessary to dene a default case FIGURE 4.32 MAX PLUS II Template Menu FIGURE 4.33 VHDL Template Dialog Box 140 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II since the STD_LOGIC_VECTOR type contains values other than 0 and 1. The multibit values assigned to the vectors, called bit string literals, must be enclosed in double quotes. VHDL Templates in MAX PLUS II MAX PLUS II offers a shortcut to creating VHDL structure in a Template Menu. Figure 4.32 shows this menu, which is available in the MAX PLUS II Text Editor window. To choose a template, select the one desired from the VHDL Template dialog box, shown in Figure 4.33. Choosing the Entity Declaration template results in the following text: ENTITY __entity_name IS GENERIC (__parameter_name : string : __default_value; __parameter_name : integer: __default_value); PORT ( __input_name, __input_name : IN STD_LOGIC; __input_vector_name : IN STD_LOGIC_VECTOR (__high downto __low); __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, __output_name : OUT STD_LOGIC); END __entity_name; To convert this into a valid entity for our use, we delete the lines we do not need and substitute input and output names into the template. For our majority vote circuit, we had inputs called A, B, and C and an output called Y. Thus, we can modify the template to yield the entity declaration: ENTITY maj_vot2 IS PORT ( a, b, c maj_vote INPUT A1 B1 INPUT INPUT C1 : IN STD_LOGIC; A Y B AND2 C OUTPUT Y MAJ_VOT2 INPUT A2 B2 C2 INPUT INPUT a b y c FIGURE 4.34 GDF Containing Symbols from Other GDF and VHDL Files y END maj_vot2; : OUT STD_LOGIC); Integrating VHDL and Graphical Design Components We can create a default symbol for the VHDL majority vote function, much as we did for the same function in the Graphic Design File. In the Text Editor File menu, select Create 4.7 Creating a Physical Design 141 Default Symbol. We can integrate this new symbol into a two-level majority vote circuit, as shown in Figure 4.34. This circuit contains primitives (AND gate, input pins, and output pin), a gdf symbol (maj_vote), and a symbol created from a VHDL le (MAJ_VOT2). Double-clicking on either symbol will bring forward its original design le. 4.7 Creating a Physical Design KEY TERMS Assignment and Conguration File (acf) A MAX PLUS II le that contains information about the conguration options for a project, including assigned device and pin numbers. FIGURE 4.35 Pop-up Menu for Pin Assignments The previous sections have concentrated on the design aspects of a project. Of course, the ultimate goal of this procedure is to create a physical version of the design. Before we can program our majority vote circuit into hardware, we must assign the input and output pin numbers on the target CPLD. At that point we can recompile the design le and program the CPLD. Assigning Pin Numbers Before proceeding with this step, make sure that you have assigned a device part number to the design. Save the le and set the project to the current le. To assign a pin number, click on the pin to highlight it, then right-click to see the popup menu in Figure 4.35. Choose Assign, then Pin/Location/Chip. You could also do this from the Assign menu at the top of the screen. 142 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II FIGURE 4.36 Pin/Location/Chip Assignment Dialog Box Table 4.2 Pin Assignment for a Majority Vote Circuit Pin Name A1 B1 C1 A2 B2 C2 Y FIGURE 4.37 Pin Assignments in ACF (Before Copying) Pin Number 12 16 18 15 17 21 4 4.7 Creating a Physical Design 143 FIGURE 4.38 Pin Assignments in ACF (After Copying) FIGURE 4.39 Pin Assignments as Seen in gdf File We can assign pin numbers in the dialog box in Figure 4.36. Type A1 in the Node Name box, 12 in the Pin box and click Add. Type B1 in the Node Name box, assign this name to pin 16, and click Add. Repeat this procedure until all names are assigned, as in Table 4.2. When all assignments are complete, click OK. We can also assign pin numbers by editing the Assignment and Conguration File (acf), as shown in Figures 4.37 and 4.38. This technique works especially well if you need to assign pin numbers to a sequence of numerically related inputs and outputs. Figure 4.37 shows the acf with four pin assignments made. We can add the others easily by using a copy-and-paste procedure. Highlight the line you wish to copy and copy it to the Windows clipboard (use Copy in the File menu or the Copy icon on the toolbar or Ctrl-C). Paste three copies into the acf and modify them so that they represent the remaining required pin assignments, as shown in Figure 4.38. Figure 4.39 shows the input pin assignments as they appear in the gdf le. 144 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II Programming CPLDs on the Altera UP-1 Circuit Board KEY TERMS ByteBlaster An Altera ribbon cable and connector used to program or congure Altera CPLDs via the parallel port (LPT port) of an IBM PC or compatible. JTAG Joint Test Action Group. A standards body that developed the format (called IEEE Std. 1149.1) for testing and programming devices while they are installed in a system. ISP In-system programmability. The ability of a PLD (such as a MAX7000S) to be programmed without removing it from a circuit board. ICR In-circuit recongurability. The ability of a PLD (such as a FLEX10K) to be congured without removing it from a circuit board. FIGURE 4.40 ByteBlaster Parallel Port Download Cable (By Permission of Altera Corporation) TDI Test Data In. In a JTAG port, the serial input data to a device. TDO Test Data Out. The JTAG signal, the serial output data from a device. TMS Test Mode Select. The JTAG signal that controls the downloading of test or programming data. TCK Test Clock. The JTAG signal that drives the JTAG downloading process from one state to the next. JTAG Chain Multiple JTAG-compliant devices whose TDI and TDO ports form a continuous chain connection. Such a chain allows multi-device programming. The CPLDs on the Altera UP-1 circuit board are programmed via the programming software in MAX PLUS II and a ribbon cable called the ByteBlaster. The ByteBlaster, shown in Figure 4.40, connects to the parallel port of a PC running MAX PLUS II to a 10-pin male socket that complies with the JTAG standard. This standard species a fourwire interface, originally developed for testing chips without removing them from a circuit board, but can also be used to program or congure PLDs. 4.7 Creating a Physical Design 145 FIGURE 4.41 MAX9000, MAX7000S, and MAX7000A Programming with the ByteBlaster Cable (By Permission of Altera Corporation) FIGURE 4.42 JTAG Chain Device Programming and Conguration with the ByteBlaster Cable (By Permission of Altera Corporation) PLDs that can be programmed or congured while installed on a circuit board are called in-system programmable (ISP) or in-circuit recongurable (ICR). ISP is used to refer to nonvolatile devices, such as MAX7000S; ICR refers to volatile devices, such as FLEX10K. The JTAG interface has four wires, as well as power and ground connections, as shown in Figure 4.41. Data are sent to a device from a JTAG controller (i.e., the PC) via the TDI (Test Data In) line. Data return from the device via TDO (Test Data Out). The data transfer is controlled by TMS (Test Mode Select). The process is driven from one step to the next by TCK (Test Clock). Multiple devices can be programmed in a JTAG Chain, as shown in Figure 4.42. This connection allows both CPLDs on the Altera UP-1 Board to be programmed at the same time. The UP-1 board also has a female 10-pin socket labeled JTAG out, which allows two or more boards to be chained together. The choice of programming one or more CPLDs, or 146 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II the CPLDs on one or more UP-1 boards, is determined by the placement of four on-board jumpers. These jumper positions are explained in the Altera University Program Design Laboratory Package User Guide. A copy of the User Guide is included in Appendix A for reference and is available at Alteras Web site. The operation of the JTAG port is controlled automatically by MAX PLUS II, so further details are not necessary at this time. For further information on the JTAG interface, refer to Altera Application Note 39, JTAG Boundary-Scan Testing in Altera Devices, in- FIGURE 4.43 Hardware Setup Dialog Box cluded in the Altera Documentation folder on the accompanying CD. MAX PLUS II Programmer To program a device on the Altera UP-1 board, set the jumpers to program the EPM7128S or congure the EPF10K20, as shown in the Altera University Program Design Laboratory Package User Guide. Connect the ByteBlaster cable from the parallel port of the PC running MAX PLUS II to the 10-pin JTAG header. (You may have to run a 25-wire cable FIGURE 4.44 Programmer Dialog Box (MAX7000S Device) 4.7 Creating a Physical Design 147 (male-D-connector-to-female-D-connector) to make it reach.) Plug an AC adapter (9-volt dc output) into the power jack of the UP-1 board. Open the top-level le of the project you wish to download to the UP-1 board (e.g., maj_vote.gdf). Set the project to the current le. Invoke the MAX PLUS II Programmer from the MAX PLUS II menu or click the Programmer button (the icon showing the blue ribbon cable) on the MAX PLUS II toolbar. If you have never programmed a device with your copy of MAX PLUS II, you will need to set up the hardware conguration. Click Hardware Setup in the Options menu to FIGURE 4.45 JTAG Menu FIGURE 4.46 Multi-Device JTAG Chain Setup get the dialog box in Figure 4.43. Select ByteBlaster in the Hardware Type box. Ensure that Parallel Port is the same as the port the ByteBlaster is plugged into (usually LPT1:). Click OK. (If you have a choice, congure your parallel port as an Enhanced Communications Port (ECP) in your computers CMOS setup. For most users this step is not necessary, as the port is already congured this way.) 148 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II FIGURE 4.47 Select Programming File Dialog Box If the current project was compiled with the MAX7000S device selected, the pof le for the project will automatically be available. The Programmer dialog box will appear as in Figure 4.44. To download, click Program. If the project was compiled for the FLEX10K device and the device is to be congured via a ByteBlaster, it must be congured via the Multi-Device JTAG Chain available in the JTAG menu. Select the JTAG menu, shown in Figure 4.45, and choose Multi-Device JTAG Chain Setup. In the Multi-Device JTAG Chain Setup window, shown in Figure 4.46, select the pulldown menu for the device name. Select EPF10K20. Choose Delete All to clear the box of any previous programming le names. Choose the Select Programming File button. The Select Programming File dialog box will appear, as in Figure 4.47. Find and select the le drive:\max2work\maj_v Glossary ote\maj_vote.sof. Click OK. Choose the Add button in the JTAG setup box to add the SRAM Object File (sof) to the list. Choose the Detect JTAG Chain Info button to set up the hardware for programming. Choose OK. Click the Congure button in the Programmer dialog box to download the binary information to the FLEX10K CPLD on the UP-1 board. SUMMARY 1. A programmable logic device (PLD) is a digital device that is shipped blank and whose function is determined by the end user. 2. PLDs offer design exibility, reduce board space and package count, and can be used to develop digital designs more quickly than xed-function logic. 3. Some types of PLDs include PAL (programmable array logic), GAL (generic array logic), EPLD (erasable PLD), CPLD (complex PLD), FPGA (eld-programmable gate array). 4. Complex PLDs (CPLDs) are devices with several programmable sections that are interconnected inside the chip. 5. PLD design and programming requires special software, such as Alteras MAX PLUS II. 6. PLD designs can be entered by schematic capture (Graphic Design Files) or text-based languages, such as Altera Hardware Description Language (AHDL) and VHSIC Hardware Description Language (VHDL). 7. MAX PLUS II organizes PLD design les in a project. Since many operations in MAX PLUS II are performed on a project, you should set the project to the current le (File menu) whenever you change windows and make a modication to a design le. 8. Save your work every time you pause for thought. 9. A MAX PLUS II Graphic Design File (gdf) consists of graphical symbols of components that are interconnected by lines drawn between inputs and outputs of the components. 10. Circuit inputs and outputs in a gdf have special symbols. The input and output pins must be named, but need not be numbered in the rst stages of a design. 11. The MAX PLUS II compiler translates the design information from a gdf or text le into binary data that can be downloaded into a PLD. For a MAX7000S, the compiler generates a Programmer Object File (pof) to program the device. For a FLEX10K, an SRAM Object File (sof) is generated to congure the device. 12. MAX7000S devices are nonvolatile; they stay programmed when the power is removed from the chip. FLEX10K devices are volatile; they lose their programming data when power is removed. 13. If a CPLD part number is not specied, the MAX PLUS II compiler will automatically select one. It is good practice to assign the part number of the device before compiling, as this can affect the accuracy of certain parts of the design process, such as simulation. The CPLDs on the Altera UP-1 board are EPM7128SLC84-7 and EPF10K20RC240-4. 14. Some useful compiler options are: Design Doctor (checks for good design practice), Timing SNF Extractor (compiles data required for timing simulations), and Smart Recompile (allows part of the compile process to be skipped if only part of a design has changed). 15. Compiler messages can be in green text (Info), blue text (Warning; possible problems, but not fatal), or red text (Error; fatal, compiling stops). 16. MAX PLUS II les can be arranged in a design hierarchy. That is, a MAX PLUS II le can contain components that are complete MAX PLUS II designs in and of themselves. 17. A le that contains other designs, but is not part of a higherlevel design, is called the top level of a hierarchy. 18. If the top level of a hierarchy is a gdf, lower-level designs are embedded in the gdf as default symbols that are created from the original design les of the components. 19. MAX PLUS II looks for default symbols in the present working directory, then in the directories specied as user libraries. 20. VHDL (VHSIC Hardware Description Language) is a textbased programming language used to model and program digital circuits. 21. Every VHDL le requires an entity declaration, which describes the external aspects of the design (inputs and outputs), and an architecture body, which describes the relation- ship between the inputs and outputs. 22. The entity declaration denes ports (inputs and outputs) and the type of each port (the range of values each port can have). 23. Some common types are BIT (0 or 1), STD_LOGIC (ninevalued standard logic), and INTEGER (whole numbers). 24. The STD_LOGIC type can take on any of the following values: U, Uninitialized 149 X, 0, 1, Z, W, L, H, Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 150 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II - Dont care 25. STD_LOGIC is dened in a library called ieee. To use STD LOGIC, include the following two statements at the beginning of a le LIBRARY ieee; USE ieee.std_logic_1164.ALL; 26. A port in VHDL is an input or output. A signal is an internal connection, like a wire. A variable is a piece of working memory reserved by the VHDL le. 27. The simplest way to relate inputs and outputs in a VHDL design is with a concurrent signal assignment statement, which has the form: x <= (a and b) or c; The port or signal on the left side is assigned the value of the logic expression on the right side. (Variables are assigned with a different operator.) 28. A port, signal, or variable can have a multiple-bit construction of type BIT_VECTOR or STD_LOGIC_VECTOR. These structures are called vectors and can be referred to a separate elements (e.g., y(3) <= d(1) and d(0);) or as a group (e.g., y <= 1000). 29. A selected signal assignment statement can act as a truth table in VHDL. It assigns alternative values to one or more outputs, depending on the alternative values on one or more inputs. 30. VHDL constructs and statements can be selected in generic form from a template menu in MAX PLUS II. 31. VHDL designs can be embedded in a gdf as default symbols. 32. Pin numbers must be assigned to a design before it can be downloaded to a CPLD. Pins can be assigned in the Pin/ Location/Chip dialog box (accessed by highlighting a pin symbol and right-clicking) or by editing the projects Assignment and Conguration File (acf). 33. An Altera CPLD can be programmed directly from a PC parallel port via a ByteBlaster cable. 34. The ByteBlaster cable implements a programming interface specied by a standard (IEEE Std. 1149.1) of the Joint Test Action Group (JTAG). 35. A JTAG port is a 4-wire interface for loading test and programming information into one or more JTAG-compliant devices. It consists of an input (TDI), output (TDO), mode select (TMS), and clock (TCK). GLOSSARY AHDL (Altera Hardware Description Language) Alteras proprietary text-entry design tool for PLDs. Altera UP-1 Board A circuit board, part of Alteras University Program Design Laboratory Package, containing two CPLDs and a number of input and output devices. Architecture A VHDL structure than denes the relationship between input, output, and internal signals or variables in a design. ASICs (application specic integrated circuits) Integrated circuits that are constructed for a specic design purpose. The term could refer to a PLD, although it usually means a customdesigned xed function device. Assignment and Conguration File (acf) A MAX PLUS II le that contains information about the conguration options for a project, including assigned device and pin numbers. Bit string literal A group of bits assigned to the elements of a vector, enclosed in double quotes (e.g., 001011). ByteBlaster An Altera ribbon cable and connector used to program or congure Altera CPLDs via the parallel port (LPT port) of an IBM PC or compatible. Comment Explanatory text in a VHDL (or other computer language) le that is ignored by the computer at compile time. Compile The process used by CPLD design software to interpret design information (such as a drawing or text le) and create required programming information for a CPLD. Complex PLD (CPLD) A digital device consisting of several programmable sections with internal interconnections between the sections. Concurrent Simultaneous. Concurrent signal assignment A relationship between an input and output port or signal in which the output is changed as soon as there is a change in input. If the le has more than one concurrent signal assignment, they are all evaluated simultaneously. Default symbol A graphical symbol that represents a PLD design as a block, showing only the designs inputs and outputs. The symbol can be used as a component in any Graphic Design File. Design entry The process of using software tools to describe the design requirements of a PLD. Design entry can be done by entering a schematic or a text le that describes the required digital function. Download Program a PLD from a computer running PLD design and programming software. Entity A VHDL structure that denes the inputs and outputs of a design. Fitting Assigning internal PLD circuitry, as well as input and output pins, for a PLD design. Graphic Design File (gdf) A PLD design le in which the digital design is entered as a schematic. Hardware description language A computer language used to design digital circuits by entering text-based descriptions of the circuits. Hierarchical design A PLD design that is ordered in layers or levels. The highest level of design contains components that are themselves complete designs. These components may, in turn, have lower-level designs embedded within them. ICR In-circuit recongurability. The ability of a PLD (such as a FLEX10K) to be congured without removing it from a circuit board. IEEE Standard 1164 The standard which denes a variety of VHDL types and operations, including the STD_LOGIC and STD_LOGIC_VECTOR types. ISP In-system programmability. The ability of a PLD (such as a MAX7000S) to be programmed without removing it from a circuit board. JTAG Joint Test Action Group. A standards body that developed the format (called IEEE Std. 1149.1) for testing and programming devices while they are installed in a system. Problems JTAG Chain Multiple JTAG-compliant devices whose TDI and TDO ports form a continuous chain connection. Such a chain allows multi-device programming. Library A collection of VHDL design units that have been previously compiled. 151 Package A group of VHDL design elements that can be used by more than one VHDL le. Port A name assigned to an input or output of a VHDL design entity. Programmable logic device (PLD) A digital integrated circuit that can be programmed by the user to implement any digital logic function. MAX PLUS II CPLD design and programming software owned by Altera Corporation. Mode (of a port) The kind of port, such as input or output. Nonvolatile Able to retain stored information after power is removed. Programmer Object File (pof) Binary le used to program a PLD of the Altera MAX series. Programming Transferring design information from the computer running PLD design software to the actual PLD chip. Project A set of MAX PLUS II les associated with a particular PLD design. Schematic capture A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD. Selected signal assignment statement A concurrent signal assignment in VHDL in which a value is assigned to a signal, depending on the alternative values of another signal or variable. signing and programming digital functions in a PLD. Syntax The grammar of a computer language (i.e., the rules of construction of language statements). Target device The specic PLD for which a digital design is intended. TCK Test Clock. The JTAG signal that drives the JTAG downloading process from one state to the next. Table 4.3 Pin Assignments for Multiplexer Circuit Signal A name given to an internal connection in a VHDL architecture. Function S0 S1 Pin S1 S0 D0 D1 D2 D3 Y Simulation Verifying design function by specifying a set of inputs and observing the resultant outputs. Simulation is generally shown as a series of input and output waveforms. 12 16 15 17 21 25 4 TDI Test Data In. In a JTAG port, the serial input data to a device. TDO Test Data Out. The JTAG signal, the serial output data from a device. D0 D1 D2 Y S0 S1 D3 D FIGURE 4.48 Problem 4.4 4-to-1 Multiplexer Y1 Y2 Software tools Specialized computer programs used to perform specic functions such as design entry, compiling, tting, and so on. (Sometimes just called tools.) SRAM Object File (sof) Binary le used to congure a PLD of the Altera FLEX series. Suite (of software tools) A related collection of tools for performing specic tasks. MAX PLUS II is a suite of tools for de- Y0 Y3 FIGURE 4.49 Problem 4.9 4-channel Demultiplexer 152 C H A P T E R 4 Introduction to PLDs and MAX+PLUS II TMS Test Mode Select. The JTAG signal that controls the downloading of test or programming data. Table 4.5 Pin Assignments for Equality Comparator Top level (of a hierarchy) The le in a hierarchy that contains components specied in other design les and is not itself a component of a higher-level le. Function A1 A2 B1 B2 AEQB Table 4.4 Pin Assignments for Demultiplexer Circuit Function 12 16 15 4 6 8 10 12 16 15 17 4 Pin S1 S0 D Y0 Y1 Y2 Y3 Pin a gdf le. Variable A block of working memory used for internal calculation or storage in a VHDL architecture. Vector A group of digital signals or variables, usually related numerically, that can be treated as a single multi-bit variable. VHDL (VHSIC Hardware Description Language) An in- Type A set of characteristics associated with a VHDL port name, signal, or variable that determines the allowable values of the port, signal, or variable. A SUM B User library A folder containing symbols that can be used in CARRY FIGURE 4.51 Problem 4.11 Half Adder A1 B1 AEQB A2 B2 dustry-standard computer language used to model digital circuits and produce programming data for PLDs. FIGURE 4.50 Problem 4.10 2-bit Equality Comparator VHSIC Very high speed integrated circuit Volatile A device is volatile if it does not retain its stored in- A B CARRY IN FIGURE 4.52 Problem 4.12 Full Adder SUM CARRY OUT Problems formation after the power to the device is removed. a. primitives PROBLEMS 153 b. instance 4.8 Use MAX PLUS II to create a Graphic Design File for the multiplexer circuit shown in Figure 4.48. Save the le as drive:\max2work\chapt4\problems\4to1mux.gdf. Assign pins as in Table 4.3. Set the project to the current le and compile. 4.9 Figure 4.49 shows the circuit for a 4-channel demultiplexer, which switches a digital input to one of four outputs, depending in the states of two select inputs. Figure 4.49 Table 4.6 Pin Assignments for Full Adder Function Pin A B CARRY IN SUM CARRY OUT 12 15 33 6 4 Section 4.1 What Is a PLD? 4.1 List some types of PLDs other than CPLDs. 4.4 Figure 4.48 shows a 4-to-1 multiplexer circuit. (The circuit switches one of four digital inputs to a single output, depending on the states of two select inputs.) State the number of 74HC type devices required to make this circuit. You may use the following devices: 74HC04 hex inverter; 74HC11 triple 3-input AND gate; 74HC4002 dual 4-input NOR gate (there are no 4-input OR devices available in the 74HC family). State how many devices are required to make two multiplexers. Repeat Problem 4.9 for the 2-bit equality comparator in Figure 4.50. This circuit generates a HIGH output when the two 2-bit numbers A2A1 and B2B1 are equal. Save the le as drive:\max2work\chapt4\problems\eq_comp. gdf. Use the pin assignments in Table 4.5. 4.11 Use MAX PLUS II to create a Graphic Design File for the half-adder circuit shown in Figure 4.51. The halfadder adds 2 bits to generate a sum and a carry output. Save the le as drive:\max2work\chapt4\problems\ halfadd.gdf. Create a default symbol for the le and compile, after setting the project to the current le. Do not assign pin numbers at this time. 4.12 Use MAX PLUS II to create a Graphic Design File for the full adder circuit shown in Figure 4.52. The full adder combines two bits A and B, plus an input carry from a previous stage to generate a sum and a carry output. What does CPLD stand for? How is it different from the term PLD? 4.3 4.10 List some of the advantages of programmable logic over xed-function logic. 4.2 Use MAX PLUS II to create a Graphic Design File for the demultiplexer circuit. Save the le as drive:\max2work\chapt4\problems\4ch_dmux.gdf. Assign pins as in Table 4.4. Set the project to the current le and compile. Section 4.3 Graphic Design File Save the le as drive:\max2work\chapt4\problems\fulladd.gdf. Assign pin numbers as shown in Table 4.6. Set the project to the current le and compile. Section 4.4 Compiling MAX PLUS II Files 4.5 Briey describe the difference between a design le and a project in MAX PLUS II. 4.6 State two ways to set the MAX PLUS II project to the current le. 4.7 State the denitions of the following terms: 4.13 Examine the half adder circuit in Figure 4.51 and the full adder circuit in Figure 4.52. You should nd two half adders in the full adder circuit. Use the half adder symbol you created in Problem 4.11 to create a full adder as a hierarchical design, consisting of two half adders and other logic. Save the le as drive:\max2work\chapt4\ CHAPTER 5 Combinational Logic Functions OUTLINE CHAPTER OBJECTIVES 5.1 5.2 5.3 5.4 5.5 Upon successful completion of this chapter you will be able to: Design binary decoders using logic gates. Create decoder designs in MAX PLUS II, using Graphic Design Files or VHDL. Create MAX PLUS II simulation les to verify the operation of combinational circuits. Design BCD-to-seven-segment and hexadecimal-to-seven-segment decoders, including special features such as ripple blanking, using VHDL and Graphic Design Files in MAX PLUS II. Use MAX PLUS II Graphic Design Files and VHDL to generate the design for a 3-bit binary and a BCD priority encoder. Describe the circuit and operation of a simple multiplexer and program these functions in VHDL. Draw logic circuits for multiplexer applications, such as single-channel data selection, multibit data selection, waveform generation, and timedivision multiplexing (TDM). Describe demultiplexer circuits and program them using VHDL. Dene the operation of a CMOS analog switch and its use in multiplexers and demultiplexers. Dene the operation of a magnitude comparator and program its function in VHDL. Explain the use of parity as an error-checking system and draw simple parity-generation and checking circuits.. 5.6 Decoders Encoders Multiplexers Demultiplexers Magnitude Comparators Parity Generators and Checkers A number of standard combinational logic functions have been developed for digital circuits that represent many of the useful tasks that can be performed with digital circuits. Decoders detect the presence of particular binary states and can activate other circuits based on their input values or can convert an input code to a different output code. Encoders generate a binary or binary coded decimal (BCD) code corresponding to an active input. Multiplexers and demultiplexers are used for data routing. They select a transmission path for incoming or outgoing data, based on a selection made by a set of binary-related inputs. 155 156 C H A P T E R 5 Combinational Logic Functions Magnitude comparators determine whether one binary number is less than, greater than, or equal to another binary number. Parity generators and checkers are used to implement a system of checking for errors in groups of data. I 5.1 Decoders KEY TERMS Decoder A digital circuit designed to detect the presence of a particular digital state. The general function of a decoder is to activate one or more circuit outputs upon detection of a particular digital state. The simplest decoder is a single logic gate, such as a NAND or AND, whose output activates when all its inputs are HIGH. When combined with one or more inverters, a NAND or AND can detect any unique combination of binary input values. An extension of this type of decoder is a device containing several such gates, each of which responds to a different input state. Usually, for an n-bit input, there are 2n logic gates, each of which decodes a different combination of input variables. A variation is a BCD device with 4 input variables and 10 outputs, each of which activates for a different BCD input. Some types of decoders translate binary inputs to other forms, such as the decoders that drive seven-segment numerical displays, those familiar gure-8 arrangements of LED or LCD outputs (segments). The decoder has one output for every segment in the display. These segments illuminate in unique combinations for each input code. Single-Gate Decoders The simplest decoder is a single gate, sometimes in combination with one or more inverters, used to detect the presence of one particular binary value. Figure 5.1 shows two such decoders, both of which detect an input D3D2D1D0 1111. D3 D2 D1 D0 Y D3D2D1D0 D3 D2 D1 Y D3D2D1D0 D0 FIGURE 5.1 Single-Gate Decoders The decoder in Figure 5.1a generates a logic HIGH when its input is 1111. The decoder in Figure 5.1b responds to the same input, but makes the output LOW instead. In Figure 5.1, we designate D3 as the most signicant bit of the input and D0 the least signicant bit. We will continue this convention for multi-bit inputs. In Boolean expressions, we will indicate the active levels of inputs and outputs separately. For example, in Figure 5.1, the inputs to both gates are the same, so we write D3D2D1D0 for the inputs of both gates. The gates in Figures 5.1a and b have outputs with opposite active levels, so we write the output variables as complements (Y and Y ). EXAMPLE 5.1 Figure 5.2 shows three single-gate decoders. For each one, state the output active level and the input code that activates the decoder. Also write the Boolean expression of each output. 5.1 D3 Decoders 157 D3 D2 D2 D2 D1 D1 D1 D0 D0 D0 FIGURE 5.2 Example 5.1 Single-Gate Decoders Solution Each decoder is a NAND or AND gate. For each of these gates, the output is active when all inputs are HIGH. Because of the inverters, each circuit has a different code that fulls this requirement. Figure 5.2a: Output: Active LOW Input code: D3D2D1D0 Y 1001 D3D2D1D0 Figure 5.2b: Output: Active LOW Input code: D2D1D0 001 Y Figure 5.2c: Output: Active HIGH Input code: D3D2D1D0 Y D2D1D0 1010 D3D2D1D0 Single-gate decoders are often used to activate other digital circuits under various operating conditions, particularly if there is a choice of circuits to activate. For example, single-gate decoders are used to enable peripheral devices in a personal computer (PC). A combination of binary values, called the address, species a unique set of conditions to enable a particular peripheral device. EXAMPLE 5.2 Application A PC has two serial port cards called COM1 and COM2. Each card is activated when either one of two control inputs called IOR (Input/Output Read) and IOW (Input/Output Write) are active and a unique 10-bit address is present. IOR and IOW are active-LOW. The address is specied by bits A9 A8 A7 A6 A5 A4 A3 A2 A1 A0, which can be represented by three hexadecimal digits. The decoder outputs, COM1_Enable and COM2_Enable are both active-LOW. The card for COM1 activates when (IOR OR IOW is LOW) AND the address is between 3F8H and 3FFH. The card for COM2 activates when (IOR OR IOW is LOW) AND the address is between 2F8H and 2FFH. Create a Graphic Design File in MAX PLUS II that implements the specied decoder. Solution The lowest address that activates COM1 is A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 3F8H 11 1111 1000 3FFH 11 1111 1111 The highest COM1 address is A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 158 C H A P T E R 5 Combinational Logic Functions Since any address in this range is valid, we can represent the last three bits, A2 A1A0, as dont care states. Thus, for COM1, we should decode the address: A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11 1111 1XXX Similarly, for COM2: Low address: A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 High address: A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Decode: A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2F8H 10 1111 1000 2FFH 10 1111 1111 10 1111 1XXX Figure 5.3 shows the gdf representation of the decoder circuit, including inputs for the control signals IOR and IOW. NAND8 A9 A8 A7 A6 A5 A4 A3 IOW IOR INPUT INPUT INPUT OUTPUT INPUT COM1_Enable INPUT INPUT INPUT INPUT BOR2 INPUT NAND8 NOT OUTPUT COM2_enable FIGURE 5.3 Example 5.2 COM Port Decoders SECTION 5.1A REVIEW PROBLEM 5.1 Draw a single-gate decoder that detects the input state D3D2D1D0 1100 a. with active-HIGH indication b. with active-LOW indication Multiple-Output Decoders Decoder circuits often are constructed with multiple outputs. In effect, such a device is a collection of decoding gates controlled by the same inputs. A decoder circuit with n inputs can activate up to m 2n load circuits. Such a decoder is usually described an n-line-to-mline decoder. 5.1 Decoders 159 D0 D1 G Y0 Y1 Y2 Y3 FIGURE 5.4 2-line-to-4-line Decoder with Enable Figure 5.4 shows the logic circuit of a 2-line-to-4-line decoder. The circuit detects the presence of a particular state of the 2-bit input D1D0, as shown by the truth table in Table 5.1. One and only one output is HIGH for any input combination, provided the enable input G is LOW. The active input of each line is shown in boldface. The subscript of the active output is the same as the value of the 2-bit input. For example, if D1D0 10, output Y2 is active since 10 (binary) 2 (decimal). Table 5.1 Truth Table of a 2-to-4 Decoder with Enable G D1 D0 Y0 Y1 Y2 Y3 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 If we are using the decoder to activate one of four output loads, it is possible that there are situations where we want no output to be active. In such a case, we can deactivate all outputs (make them all LOW) by setting G HIGH. We can create the 2-line-to-4-line decoder of Figure 5.4 as a graphic or text le in MAX PLUS II and create a symbol for it that can be used in higher-level graphic les. Figure 5.5 shows the symbol for the decoder. FIGURE 5.5 MAX PLUS II Graphic Symbol for a 2-to-4 Decoder with Enable D1 Y0 D0 Y1 G Y2 Y3 1 160 C H A P T E R 5 Combinational Logic Functions FIGURE 5.6 3-line-to-8-line Decoder with Enable D2 D1 D0 G Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Figure 5.6 shows the circuit for a 3-line-to-8-line decoder, again with an active-LOW enable, G. In this case, the decoder outputs are active LOW. One and only one output is active for any given combination of D2D1D0. Table 5.2 shows the truth table for this decoder. Again if the enable line is HIGH, no output is active. Table 5.2 Truth Table of a 3-to-8 Decoder with Enable G D2 D1 D0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 X 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 EXAMPLE 5.3 Application Figure 5.7 shows a partial Graphic Design File, created in MAX PLUS II, that shows how a 3-line-to-8-line decoder, such as the one shown in Figure 5.6, can be used in a microcomputer memory system as an address decoder. Each block labeled 8k_sram is a memory chip capable of holding 8192 (8K) bytes of data. Since there are eight such devices, the 5.1 8k_sram ADDR[12..0] addr dq y0 g 8k_sram ADDR[12..0] addr dq y1 g ADDR[15..13] MEM_SELECT ADDR[12..0] INPUT d[2..0] INPUT g INPUT y[0..7] dq0 dq1 Decoders 8k_sram ADDR[12..0] addr dq y4 g 8k_sram ADDR[12..0] addr dq y5 g 161 dq4 dq5 y[0..7] 8k_sram ADDR[12..0] addr dq y2 g dq2 ADDR[12..0] y6 8k_sram addr dq dq6 g ADDR[12..0] 8k_sram ADDR[12..0] addr dq y3 g dq[0..7] dq3 ADDR[12..0] y7 OUTPUT 8k_sram addr dq dq7 g dq[0..7] FIGURE 5.7 Example 5.3 Address Decoder for a Memory System whole system can hold 8 8192 65,536 (64K) bytes. (Although this amount of memory may seem small by the standards of a desktop computer, it may be typical of a small stand-alone computer system (called an embedded system or a microcontroller) that is used in control applications.) Each 8K block is enabled by a LOW at its G input. Briey explain the function of the decoder in the system. Solution Since only one decoder output is LOW at any one time, the decoder allows only one memory block to be active at any one time. The active block is chosen by inputs ADDR15 ADDR14 ADDR13, which are connected to D2D1D0 on the decoder. The active memory block is the one connected to the y output whose subscript matches the binary value of these inputs. For example, when ADDR15 ADDR14 ADDR13 110, the block connected to y6 is active. If the decoder is the same as the one in Figure 5.6, no outputs will be active, and therefore no memory block will be enabled, when G 1. (Note that the MAX PLUS II Graphic Editor cannot represent an input or output with an inversion bar. Some conventions would represent an active-LOW terminal with an n prex, indicating NOT (e.g., nG). This is a matter of personal choice, but without such an indication it is not possible to tell the active level of an input or output from the MAX PLUS II Graphic Design File.) The decoders in Figure 5.6 and 5.7 have identical functions, but the symbol in Figure 5.7 shows the D inputs and Y outputs as multibit vectors or busses. Figure 5.7 also shows how the individual signals in a bus can be connected to separate parts of the circuit in a MAX PLUS II Graphic Design File. To make the connections, draw and label a line extending from each terminal. To label a line, highlight the line by clicking on it with the left mouse button, then right-click. Select Enter Node/Bus Name from the pop-up menu and enter the text. Lines that have the same names are automatically connected by their text references. If a line is a multiple line, 162 C H A P T E R 5 Combinational Logic Functions it must have signal designators in brackets (e.g., y[0..7]). Individual signals from a bus must be numbered in a way that corresponds to the multiple-bit line (e.g., y0, y1, y2, and so on). SECTION 5.1B REVIEW PROBLEM 5.2 How many inputs are required for a binary decoder with 16 outputs? How many inputs are required for a decoder with 32 outputs? Simulation of a 2-Line-to-4-Line Decoder KEY TERMS Timing diagram A diagram showing how two or more digital waveforms in a system relate to each other over time. Simulation The verication, using timing diagrams, of the logic of a digital design before programming it into a PLD. Stimulus waveforms A set of user-dened input waveforms in a simulator le designed to imitate input conditions of a digital circuit. Response waveforms A set of output waveforms generated by a simulator for a particular digital design in response to a set of stimulus waveforms. Propagation delay Time difference between a change on a digital circuit input and a change on an output in response to the input change. An important part of the CPLD design process is simulation of the design. A simulation tool allows us to see whether the output responses to a set of circuit inputs are what we expected in our initial design idea. The simulator works by creating a timing diagram. We specify a set of input (stimulus) waveforms. The simulator looks at the relationship between inputs and outputs, as dened by the design le, and generates a set of response outputs. Figure 5.8 shows a set of simulation waveforms created for the 2-line-to-4-line decoder in Figure 5.4. The inputs D1 and D0 are combined as a single 2-bit value, to which an increasing binary count is applied as a stimulus. The decoder output waveforms are observed individually to determine the decoders response. Once we have entered the design in the MAX PLUS II Graphic Editor and compiled it, we can create the waveforms as follows. FIGURE 5.8 Simulation Waveforms for a 2to-4 Decoder with Enable 2to4dcdr.gdf 2to4dcdr.scf From the File menu, select New. On the resultant dialog box, select Waveform Editor File, with a default le extension scf. From the File menu, choose Save As, then enter drive:\max2work\chapt05\decoders\2to4dcdr.scf. 5.1 Decoders 163 We specify the inputs and outputs we want to view by selecting Enter Nodes from SNF on the Node menu, shown in Figure 5.9. In the dialog box that pops up (Figure 5.10), there are two boxes labelled Available Nodes & Groups and Selected Nodes & Groups, with an arrow ( ) pointing from one to the other. Select the List button to show the available signals and click the arrow to transfer them all to the selected box. Click OK to close the box. FIGURE 5.9 Node Menu FIGURE 5.10 Selecting Nodes for Waveform Editor Figure 5.11 shows the simulation waveforms in their uninitialized (default) states. Inputs and outputs are shown by symbols in front of the signal names. Inputs are at logic 0 and outputs are indicated as X or unknown values. FIGURE 5.11 Default Values of Simulation Waveforms 164 C H A P T E R 5 Combinational Logic Functions We now set the timing length of the simulation. The default value is 1 s, written 1.0us. For this example, we will leave the end time at the default value. However, if we want to change it, we select End Time (File menu, Figure 5.12) and enter the new time for the end of simulation in the dialog box of Figure 5.13. Click OK. FIGURE 5.12 Setting the End Time of a Simulation (File Menu) FIGURE 5.13 End Time Dialog Box The End Time dialog sets the end of the simulation. We should also set the Grid Size, which determines the size of the smallest time division in the simulation. To do so, select Grid Size from the Options menu, shown in Figure 5.14. In the dialog box of Figure 5.15, enter the value 20ns and click OK. (We will use this value for many of our simulations FIGURE 5.14 Setting Simulation Grid Size (Options Menu) FIGURE 5.15 Grid Size Dialog Box 5.1 Decoders 165 because it corresponds to one half period of the oscillator on the Altera UP-1 board. In the simulator, one full period requires two grid spaces.) When we created the simulation le, the D inputs were entered as separate waveforms. We can join these waveforms to make a Group. Highlight both D1 and D0 by clicking on one name and dragging the mouse to the next name, as in Figure 5.16. From the Node menu or the pop-up menu in Figure 5.17, select Enter Group. The dialog box shown in Figure 5.18 appears, containing the most likely name derived from the highlighted group. Either type a new group name or accept the original name by clicking OK. FIGURE 5.16 Highlighting a Group FIGURE 5.17 Pop-up Menu (Enter Group) FIGURE 5.18 Enter Group Dialog Box 166 C H A P T E R 5 Combinational Logic Functions Overwrite Count Button As a decoder stimulus, we will dene an increasing binary count on the D inputs. Highlight the input group by clicking in the Value column. Use the Overwrite Count toolbar button to create an increasing binary count on the group, D[1..0]. Fill in the dialog box as shown in Figure 5.19 and click OK. The count is increased every 40 ns (2 20 ns), as shown in Figure 5.20. FIGURE 5.19 Overwrite Count Value Dialog Box FIGURE 5.20 Group Input with Binary Count Fit in Window Button FIGURE 5.21 Decoder Simulation with Enable Always Active Save the le. From the MAX PLUS II menu, bring the Simulator to the front and click Start. When the simulation is nished (almost immediately), click Open SCF and maximize the window. From the View menu, select Fit in Window or select the toolbar button for this function. The simulator output, shown in Figure 5.21, shows the result of a repeating binary count at the decoder input when the outputs are always enabled. The outputs activate in a repeating sequence, from Y0 to Y3. You will notice that the D inputs change exactly on the grid lines, but the Y outputs change slightly after. This is due to propagation delay, dened as the time between an 5.1 Overwrite with HIGH Button Decoders 167 input change and the time an output changes in response to that input. In the EPM7128SLC84-7 CPLD, for which this simulation is created, propagation delay is about 7 nanoseconds. (The MAX PLUS II simulator accounts for the propagation delay in different CPLDs.) Later simulations in this chapter will not necessarily show the delay, as the timing chosen may be very long compared to delay times. To see the result of the enable input, highlight the G waveform from approximately 500 ns to 1 s by dragging the mouse along this part of the waveform. Overwrite the highlighted part by clicking the Overwrite with HIGH button. When we run the simulation again, we get the waveforms shown in Figure 5.8. VHDL Binary Decoder KEY TERMS Selected signal assignment statement A concurrent signal assignment in VHDL in which a value is assigned to a signal, depending on the alternative values of another signal or variable. Conditional signal assignment statement A concurrent VHDL construct that assigns a value to a signal, depending on a sequence of conditions being true or false. In Chapter 4, we saw an example of how we can use VHDL to dene the function of a 2-line-to-4-line decoder. For reference the description is replicated below, with the difference that the input and output ports are dened as BIT rather than STD_LOGIC types. (This is sufcient for a combinational circuit like a decoder, as the only I/O (input/output) values required are 0 and 1. If we use BIT types, we do not require a reference to the IEEE library, as we do to dene STD_LOGIC types.) decode1.vhd ENTITY decode1 IS PORT( d1, d0 : IN BIT; y0, y1, y2, y3 : OUT BIT); END decode1; ARCHITECTURE decoder1 OF decode1 IS BEGIN y0 <= (not d1) and (not d0); y1 <= (not d1) and ( d0); y2 <= ( d1) and (not d0); y3 <= ( d1) and ( d0); END decoder1; The above formulation has no enable input. If we wish to include the enable function, we must modify the entity declaration to include that input and change the signal assignment statements, as well. The new VHDL code is as follows. ENTITY decode2 IS decode2.vhd PORT( d1, d0, g : IN BIT; y0, y1, y2, y3 : OUT BIT); END decode2; ARCHITECTURE decoder2 BEGIN y0 <= (not d1) and y1 <= (not d1) and y2 <= ( d1) and y3 <= ( d1) and END decoder2; OF decode2 IS (not ( (not ( d0) d0) d0) d0) and and and and (not (not (not (not g); g); g); g); 168 C H A P T E R 5 Combinational Logic Functions In addition to coding the Boolean expressions directly, we can use two types of concurrent signal assignments to create decoder circuits: the selected signal assignment statement and the conditional signal assignment statement. Both the Altera VHDL manual and the Help menu in MAX PLUS II have a section on Golden Rules for VHDL. The VHDL Golden Rules suggest that you should use a selected signal assignment rather than a conditional signal assignment, if possible. This is because, in certain cases, the selected signal assignment uses the internal circuitry of the CPLD more efciently. The selected signal assignment has the form: label: WITH __expression __signal <=__expression __expression __expression __expression SELECT WHEN __constant_value, WHEN __constant_value, WHEN __constant_value, WHEN __constant_value; The signal indicated in the second line of the statement template is assigned one of several expressions, depending on the constant value of the expression in the rst line. The label is optional. Examine the selected signal statement below: circuit: WITH mode SELECT y <= q WHEN 00 not q WHEN 01, p WHEN 11, 1 WHEN others; Signal y is assigned one of three values, p, q, or not q, depending on the status of a two-bit variable called mode. Note that the value of y for the case when mode 10 is not explicitly stated. This is covered by the last clause (WHEN others), which denes a default value for signal y of logic 1. The following VHDL code implements a 2-line-to-4-line decoder using a selected signal assignment statement. LIBRARY ieee; USE ieee.std_logic_1164.ALL; decode3.vhd ENTITY decode3 IS PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode3; ARCHITECTURE decoder OF BEGIN WITH d SELECT y <= 0001 WHEN 0010 WHEN 0100 WHEN 1000 WHEN 0000 WHEN END decoder; decode3 IS 00, 01, 10, 11, others; The selected signal assignment statement evaluates input d. For every possible combination of the 2-bit input vector, d, a particular value is assigned to the 4-bit vector, y. (For example, for the case d1d0 10 ( 210), the output y2 is HIGH: y3y2y1y0 0100.) The default case (WHEN others) is required because of the multivalued logic type STD_LOGIC_VECTOR. Since a STD_LOGIC_VECTOR can have values other than 0 and 1, the values listed for d dont cover all possible cases. The default output (which will never occur if we only use 0 and 1 inputs) is chosen such that no output is active in the 5.1 Decoders 169 default case. The default case would not be required if we chose to use BIT_VECTOR, rather than STD_LOGIC_VECTOR, since the listed combinations of d cover all possible combinations of a BIT_VECTOR. However, it is a good practice to include the default case, in order to account for all possible contingencies. In order to include an enable input (g) in a decoder, we can increase the input vector size to include the g input, as shown in the following code. decode3a.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode3a IS PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); g : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode3a; ARCHITECTURE decoder OF decode3a IS SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0); BEGIN inputs(2) <= g; inputs(1 downto 0) <= d; WITH inputs SELECT y <= 0001 WHEN 000, 0010 WHEN 001, 0100 WHEN 010, 1000 WHEN 011, 0000 WHEN others; END decoder; To include g and d in a single vector, we create a signal called inputs, a vector with three elements in the sequence g, d(1), d(0). When assigning the d to the last two elements of inputs, we must be explicit about which elements of inputs we want to use. Since d only contains two elements and we are assigning them to two elements of inputs, we dont need to list the elements of d explicitly. We can use a selected signal assignment statement to evaluate all inputs, including g , and assign outputs accordingly. When g 0, the decoder outputs are assigned the same as they were in the example without the enable input. The cases where g 1 are covered by the others clause. In this default case, all decoder outputs are LOW (inactive). Another way to include an enable input is to use a conditional signal assignment statement, which makes an assignment based on a Boolean expression. This template for the conditional signal assignment statement is: __signal <= __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE __expression; The rst Boolean expression in the statement is evaluated. If it is true, the corresponding expression is assigned to the signal. If false, the next Boolean expression is evaluated, and so on until a true Boolean expression is found. If none are true, the signal is assigned a default expression, listed last in the statement. The VHDL code below implements the decoder with an active-LOW enable. If g is LOW, one decoder output activates, depending on the value of d. Note that the d inputs are dened as type INTEGER, rather than BIT_VECTOR or STD_LOGIC_VECTOR. In this situation, we dont need to specify the number of inputs; the compiler automatically denes the required inputs d1 and d0 when tting the design to the selected CPLD. Also, since d is of type INTEGER, we write its value in the selected signal assignment statement directly, without quotes. 170 C H A P T E R 5 Combinational Logic Functions decode4g.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY decode4g IS PORT( d : IN INTEGER RANGE 0 to 3; g : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR (0 to 3)); END decode4g; ARCHITECTURE a OF decode4g IS BEGIN y <= 1000 WHEN (d=0 and g=0) 0100 WHEN (d=1 and g=0) 0010 WHEN (d=2 and g=0) 0001 WHEN (d=3 and g=0) 0000; END a; ELSE ELSE ELSE ELSE MAX PLUS II Report File In the Altera Golden Rules, we are told to choose a selected signal assignment over a conditional signal assignment because it uses the CPLD resources more efciently. How do we check this assertion? Is it always true? This information is stored in a MAX PLUS II report le (rpt), which is created at compile time. The compile process of MAX PLUS II goes on behind the scenes; until now we have not enquired about the result of this process. One of many functions of the compiler is to reduce the design information in a graphic or text le to a series of Boolean equations that can be programmed into a PLD. For example, the report le decode3a.rpt, for the le that uses the selected signal assignment, gives us the following information under the EQUATIONS heading. ** EQUATIONS ** decode3a.rpt d0 d1 g : INPUT; : INPUT; : INPUT; Node name is y0 Equation name is y0, location is LC117, type is output. y0 = LCELL( _EQ001 $ GND); _EQ001 = !d0 & !d1 & !g; Node name is y1 Equation name is y1, location is LC115, type is output. y1 = LCELL( _EQ002 $ GND); _EQ002 = d0 & !d1 & !g; Node name is y2 Equation name is y2, location is LC118, type is output. y2 = LCELL( _EQ003 $ GND); _EQ003 = !d0 & d1 & !g; Node name is y3 Equation name is y3, location is LC120, type is output. y3 = LCELL( _EQ004 $ GND); _EQ004 = d0 & d1 & !g; Each output is designated as a node. Let us examine the equation of one node in detail so that we will know how to interpret the others. 5.1 Decoders 171 The Boolean format in the report le uses different operators than VHDL. They are as follows: ! & # $ = = = = NOT AND OR XOR Thus, the equation given as _EQ001 = !d0 & !d1 & !g is equivalent to the Boolean expression _EQ001 d0 d1 g. In the expression (y0 = LCELL ( _EQ001 $ GND);), equation _EQ001 is XORed with GND (logic 0) and applied to an LCELL (logic cell) primitive to yield y0. The LCELL represents one output of the CPLD. The XOR function is a way to either invert or not invert a logic function by setting one XOR input to GND (noninverting) or VCC (inverting). Thus _EQ001 is applied to a CPLD output without inversion. A comment in the report le indicates that y0 is assigned to logic cell LC117 (out of 128), which corresponds to pin 75 (out of 84) on the CPLD. Other equations are assigned to other LCELLs with other Boolean functions, as appropriate. Every pin number on the CPLD package is permanently connected to a specic LCELL. The compiler chooses the LCELL/pin assignments automatically; if we desire specic pin number assignments, we must assign them explicitly before compiling. How does this compare with the report le for the design with the conditional signal assignment? If you examine decode4g.rpt, you will nd that the Boolean equations are exactly the same. Thus, we can conclude that for a simple function, such as a 2-line-to-4-line decoder with enable, the two statement forms are easy enough for the compiler to interpret both in the most efcient way. decode4g.rpt Seven-Segment Decoders KEY TERMS Seven-segment display An array of seven independently controlled light-emitting diode (LED) or liquid crystal display (LCD) elements, shaped like a gure-8, which can be used to display decimal digits and other characters by turning on the appropriate elements. Common anode display A seven-segment LED display where the anodes of all the LEDs are connected to the circuit supply voltage. Each segment is illuminated by a logic LOW at its cathode. Common cathode display A seven-segment display in which the cathodes of all LEDs are connected together and grounded. A logic HIGH illuminates a segment when applied to its anode. a b f g e c d FIGURE 5.22 Seven-segment Numerical Display Display The seven-segment display, shown in Figure 5.22, is a numerical display device used to show digital circuit outputs as decimal digits (and sometimes hexadecimal digits or other alphabetic characters). It is called a seven-segment display because it consists of seven luminous segments, usually LEDs or liquid crystals, arranged in a gure-8. We can display any decimal digit by turning on the appropriate elements, designated by lowercase letters, a through g. It is conventional to designate the top segment as a and progress clockwise around the display, ending with g as the center element. Figure 5.23 shows the usual convention for decimal digit display. Some variation from this convention is possible. For example, we could have drawn the digits 6 and 9 with tails (i.e., with segment a illuminated for 6 or segment d for 9). By convention, we 172 C H A P T E R 5 Combinational Logic Functions FIGURE 5.23 Convention for Displaying Decimal Digits display digit 1 by illuminating segments b and c, although segments e and f would also work. The electrical requirements for an LED circuit are simple. Since an LED is a diode, it conducts when its anode is positive with respect to its cathode, as shown in Figure 5.24a. A decoder/driver for an LED display will illuminate an element by completing this circuit, either by supplying VCC or ground. A series resistor limits the current to prevent the diode from burning out and to regulate its brightness. If the anode is 5 volts with respect to cathode, the resistor value should be in the range of 220 to 470 . Vcc a b c Vcc a a. Circuit requirements for an illuminated LED b. Common cathode b c b. Common anode FIGURE 5.24 Electrical Requirements for LED Displays Seven-segment displays are congured as common anode or common cathode, as shown in Figures 5.24b and c. In a common cathode display, the cathodes of all LEDs are connected together and brought out to one or more pin connections on the display package. The cathode pins are wired externally to the circuit ground. We illuminate the segments by applying logic HIGHs to individual anodes. Similarly, the common anode display has the anodes of the segments brought out to one or more common pins. These pins must be tied to the circuit power supply (VCC). The segments illuminate when a decoder/driver makes their individual cathodes LOW. Figure 5.25 shows how the diodes could be physically laid out in a common anode display. The two types of displays allow the use of either active HIGH or active LOW circuits to drive the LEDs, thus giving the designer some exibility. However, it should be noted that the majority of seven-segment decoders are for common-anode displays. 5.1 FIGURE 5.25 Physical Placement of LEDs in a Common Anode Display Decoders 173 a f b g e c d Vcc EXAMPLE 5.4 Sketch the segment patterns required to display all 16 hexadecimal digits on a sevensegment display. What changes from the patterns in Figure 5.23 need to be made? Solution The segment patterns are shown in Figure 5.26. FIGURE 5.26 Hexadecimal Digit Display Format Hex digits B and D must be displayed as lowercase letters, b and d, to avoid confusion between B and 8 and between D and 0. To make 6 distinct from b, 6 must be given a tail (segment a) and to make 6 and 9 symmetrical, 9 should also have a tail (segment d ). Decoder KEY TERMS BCD Binary coded decimal. A code in which each individual digit of a decimal number is represented by a 4-bit binary number (e.g., 905 (decimal) 1001 0000 0101 (BCD)). A BCD-to-seven-segment decoder is a circuit with a 4-bit input for a BCD digit and seven outputs for segment selection. To display a number, the decoder must translate the input bits to a combination of active outputs. For example, the input digit D3D2D1D0 0000 must illuminate segments a, b, c, d, e, and f to display the digit 0. We can make a truth 174 C H A P T E R 5 Combinational Logic Functions table for each of the outputs, showing which must be active for every digit we wish to display. The truth table for a common-anode decoder (active LOW outputs) is given in Table 5.3. Table 5.3 Truth Table for Common Anode BCD-to-Seven-Segment Decoder Digit D3 D2 D1 D0 a b c d e f g 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Invalid Range The illumination of each segment is determined by a Boolean function of the input variables, D3D2D1D0. From the truth table, the function for segment a is a D3D2D1D0 D3D2D1D0 D3D2D1D0 (Since the display is active-LOW, this means segment a is OFF for digits 1, 4, and 6.) If we assume that inputs 1010 to 1111 are never going to be used (dont care states, symbolized by X), we can make any of these states produce HIGH or LOW outputs, depending on which is most convenient for simplifying the segment functions. Figure 5.27a shows a Karnaugh map simplication for segment a. The resultant function is a D3D2D1D0 D2D0 The corresponding partial decoder is shown in Figure 5.27b. We could do a similar analysis for each of the other segments, but if we are programming the decoder function into a CPLD, it is just as simple to write the truth table directly into a selected signal assignment statement, as shown in the VHDL code that follows. bcd_7seg.vhd BCD-to-seven-segment decoder ENTITY bcd_7seg IS PORT( d3, d2, d1, d0 a, b, c, d, e, f, g END bcd_7seg; bcd_7seg.vhd : IN BIT; : OUT BIT); ARCHITECTURE seven_segment OF bcd_7seg IS SIGNAL input : BIT_VECTOR (3 downto 0); SIGNAL output: BIT_VECTOR (6 DOWNTO 0); BEGIN input <= d3 & d2 & d1 & d0; WITH input SELECT output <= 0000001 WHEN 0000, 1001111 WHEN 0001, 5.1 Decoders 175 0010010 WHEN 0010, 0000110 WHEN 0011, 1001100 0100100 1100000 0001111 WHEN WHEN WHEN WHEN 0100, 0101, 0110, 0111, 0000000 WHEN 1000, 0001100 WHEN 1001, 1111111 WHEN others; Separate the output vector to make individual pin outputs. a <= output(6); b <= output(5); c <= output(4); d <= output(3); e <= output(2); f <= output(1); g <= output(0); END seven_segment; FIGURE 5.27 Decoding Segment a D1D0 D3D2 00 01 11 10 00 0 1 0 0 01 1 0 0 1 11 X X X X 10 0 0 X X Segment a a. K map D3 D2 D1 a D0 b. Decoder for segment a (common anode) The inputs D3D2D1D0 are dened separately, then concatenated (linked in sequence) by the & operator to make a BIT_VECTOR called input. This is equivalent to the following four concurrent signal assignments: input input input input (3) (2) (1) (0) <= <= <= <= d3; d2; d1; d0; 176 C H A P T E R 5 Combinational Logic Functions Why not simply dene d as a vector? If we wish to create a graphic symbol for the seven-segment decoder, the above method creates a symbol shown with four separate inputs, rather than a single thick line for a 4-bit bus input. The design will work either way. For each value of input, a signal assignment denes the output vector, each bit of which represents the value of one segment. For example, the rst clause (0000001 WHEN 0000) sets all segments ON except segment g, thus displaying the digit 0. As a variation, we could dene a signal called d_inputs of type INTEGER with RANGE 0 to 9. The WHEN clauses would evaluate the integer values 0 to 9, as follows. WITH d_inputs SELECT output <= 0000001 1001111 0010010 0000110 WHEN WHEN WHEN WHEN 0, 1, 2, 3, 1001100 0100100 0100000 0001111 WHEN WHEN WHEN WHEN 4, 5, 6, 7, 0000000 WHEN 8, 0000100 WHEN 9, 1111111 WHEN others; blank Ripple Blanking KEY TERMS Ripple blanking A technique used in a multiple-digit numerical display that suppresses leading or trailing zeros in the display, but allows internal zeros to be displayed. RBI Ripple blanking input RBO Ripple blanking output PROCESS A VHDL construct that contains statements that are executed if there is a change in a signal in its sensitivity list. Sensitivity list A list of signals in a PROCESS statement that are monitored to determine whether the PROCESS should be executed. CASE statement A VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable. IF statement A VHDL construct within a process that executes a series of statements, if a Boolean test condition is true. A feature often included in seven-segment decoders is ripple blanking. The ripple blanking feature allows for suppression of leading or trailing zeros in a multiple digit display, while allowing zeros to be displayed in the middle of a number. Each display decoder has a ripple blanking input (RBI) and a ripple blanking output (RBO), which are connected in cascade, as shown in Figure 5.28. If the decoder input D3D2D1D0 is 0000, it displays digit 0 if RBI 1 and shows a blank if RBI 0. If RBI 1 OR D3D2D1D0 is (NOT 0000), then RBO 1. When we cascade two or more displays, these conditions suppress leading or trailing zeros (but not both) and still display internal zeros. To suppress leading zeros in a display, ground the RBI of the most signicant digit decoder and connect the RBO of each decoder to the RBI of the next least signicant digit. Any zeros preceding the rst nonzero digit (9 in this case) will be blanked, as RBI 0 AND D3D2D1D0 0000 for each of these decoders. The 0 inside the number 904 is displayed since its RBI 1. 5.1 Decoders D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 177 D3 D2 D1 D0 FIGURE 5.28 Zero Suppression in Seven-segment Displays Trailing zeros are suppressed by reversing the order of RBI and RBO from the above example. RBI is grounded for the least signicant digit and the RBO for each decoder cascades to the RBI of the next most signicant digit. We can implement the ripple blanking feature in a VHDL le by modifying the le for a standard BCD- or hexadecimal-to-seven-segment decoder to include a CASE statement within a PROCESS. A PROCESS is a construct containing statements that are executed if a signal in the sensitivity list of the PROCESS changes. The general form of a PROCESS is: PROCESS (sensitivity list) BEGIN statements; END PROCESS; A CASE statement can be one of the constructs used inside a process if we want to select among several alternatives. It takes the following form: 178 C H A P T E R 5 Combinational Logic Functions CASE statement within a PROCESS PROCESS (__signal_name, __signal_name, __signal_name) BEGIN CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE; END PROCESS; Whether the digit 0 is displayed or suppressed is conditional upon the value of RBI. This can be tested by an IF statement within the PROCESS. An IF statement executes one or more VHDL statements, depending on the state of a test condition. It has the following syntax. IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; __statement; END IF; The following VHDL code demonstrates the ripple blanking function. sevsegrb.vhd sevsegrb.vhd ENTITY sevsegrb IS PORT( nRBI, d3, d2, d1, d0 : IN BIT; a, b, c, d, e, f, g, nRBO : OUT BIT); END sevsegrb; ARCHITECTURE seven_segment OF sevsegrb IS SIGNAL input: BIT_VECTOR (3 DOWNTO 0); SIGNAL output: BIT_VECTOR (6 DOWNTO 0); BEGIN input <= d3 & d2 & d1 & d0; Process Statement PROCESS (input, nRBI) BEGIN IF (input = 0000 and nRBI =0) THEN 0 suppressed output <= 1111111; nRBO <= 0; ELSIF (input = 0000 and nRBI = 1) THEN 0 displayed output <= 0000001; nRBO <= 1; ELSE CASE input IS WHEN 0001 => output <= 1001111; 1 5.2 WHEN 0010 WHEN 0011 WHEN 0100 WHEN 0101 WHEN 0110 WHEN 0111 WHEN 1000 WHEN 1001 WHEN others END CASE; nRBO <= 1; END IF; Separate a <= b <= c <= d <= e <= f <= g <= Encoders 179 => output <= 0010010; 2 => output <= 0000110; 3 => => => => => => => output output output output output output output <= <= <= <= <= <= <= 1001100; 0100100; 0100000; 0001111; 0000000; 0000100; 1111111; 4 5 6 7 8 9 blank the output vector to make individual pin outputs. output(6); output(5); output(4); output(3); output(2); output(1); output(0); END PROCESS; END seven_segment; SECTION 5.1C REVIEW PROBLEM 5.3 When would it be logical to suppress trailing zeros in a multiple-digit display and when should trailing zeros be displayed? 5.2 Encoders KEY TERMS Encoder A circuit that generates a binary code at its outputs in response to one or more active input lines. Priority encoder An encoder that generates a binary or BCD output corresponding to the subscript of the active input having the highest priority. This is usually dened as the input with the largest subscript value. The function of a digital encoder is complementary to that of a digital decoder. A decoder activates a specied output for a unique digital input code. An encoder operates in the reverse direction, producing a particular digital code (e.g., a binary or BCD number) at its outputs when a specic input is activated. Figure 5.29 shows an 3-bit binary encoder. The circuit generates a unique 3-bit binary output for every active input provided only one input is active at a time. The encoder has only 8 permitted input states out of a possible 256. Table 5.4 shows the allowable input states, which yield the Boolean equations used to design the encoder. These Boolean equations are: Q2 Q1 Q0 D7 D7 D7 D6 D6 D5 D5 D3 D3 D4 D2 D1 The D0 input is not connected to any of the encoding gates, since all outputs are in their LOW (inactive) state when the 000 code is selected. 180 C H A P T E R 5 Combinational Logic Functions FIGURE 5.29 3-bit Encoder (No Input Priority) Table 5.4 Partial Truth Table for a 3-bit Encoder D7 D6 D5 D4 D3 D2 D1 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Priority Encoder The shortcoming of the encoder circuit shown in Figure 5.29 is that it can generate wrong codes if more than one input is active at the same time. For example, if we make D3 and D5 HIGH at the same time, the output is neither 011 or 101, but 111; the output code does not correspond to either active input. One solution to this problem is to assign a priority level to each input and, if two or more are active, make the output code correspond to the highest-priority input. This is called a priority encoder. Highest priority is assigned to the input whose subscript has the largest numerical value. EXAMPLE 5.5 Figures 5.30a through c show a priority encoder with three different combinations of inputs. Determine the resultant output code for each gure. Inputs and outputs are active HIGH. FIGURE 5.30 Example 5.5 Priority Encoder Inputs 5.2 Encoders 181 Solution Figure 5.30a: The highest-priority active input is D5. D4 and D1 are ignored. Q2Q1Q0 101. Figure 5.30b: The highest-priority active input is D4. D1 is ignored. Q2Q1Q0 100. Figure 5.30c: The highest-priority active input is D7. All other inputs are ignored. Q2Q1Q0 111. NOTE The encoding principle of a priority encoder is that a low-priority input must not change the code resulting from a higher-priority input. For example, if inputs D3 and D5 are both active, the correct output code is Q2Q1Q0 101. The code for D3 would be Q2Q1Q0 011. Thus, D3 must not make Q1 1. The Boolean expressions for Q2, Q1, and Q0 covering only these two codes are: Q2 Q1 Q0 D5 D3D5 D3 D5 (HIGH if D5 is active.) (HIGH if D3 is active AND D5 is NOT active.) (HIGH if D3 OR D5 is active.) The truth table of an 3-bit priority encoder is shown in Table 5.5. Table 5.5 Truth Table for an 3-bit Priority Encoder D7 D6 D5 D4 D3 D2 D1 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 X 0 0 0 0 0 1 X X 0 0 0 0 1 X X X 0 0 0 1 X X X X 0 0 1 X X X X X 0 1 X X X X X X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Restating the encoding principle, a bit goes HIGH if it is part of the code for an active input AND it is NOT kept LOW by an input with a higher priority. We can use this principle to develop a mechanical method for generating the Boolean equations of the outputs. 1. Write the codes in order from highest to lowest priority, as in Table 5.6. Table 5.6 Binary Outputs and Corresponding Decimal Values Q2 Q1 Q0 Code Value 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 7 6 5 4 3 2 1 0 182 C H A P T E R 5 Combinational Logic Functions 2. Examine each code. For a code with value n, add a Dn term to each Q equation where there is a 1. For example, for code 111, add the term D7 to the equations for Q2, Q1, and Q0. For code 110, add the term D6 to the equations for Q2 and Q1. (Steps 1 and 2 generate the nonpriority encoder equations listed earlier.) 3. Modify any Dn terms to ensure correct priority. Every time you write a Dn term, look at the previous lines in the table. For each previous code with a 0 in the same column as the 1 that generates Dn, use an AND function to combine Dn with a corresponding D. For example, code 101 generates a D5 term in the equations for Q2 and Q0. The term in the Q2 equation need not be modied because there are no previous codes with a 0 in the same column. The term in the Q0 equation must be modied since there is a 0 in the Q0 column for code 110. This generates the term D6D5. The equations from the 3-bit encoder of Figure 5.29 are modied by the priority encoding principle as follows: Q2 Q1 Q0 D7 D7 D7 D6 D5 D4 D6 D5D4D3 D5D4D2 D6D5 D6D4D3 D6D4D2D1 VHDL Priority Encoder The most obvious way to program a priority encoder in VHDL is to use the equations derived in the previous section in a set of concurrent signal assignment statements, as follows. hi_pri8a.vhd hi_pri8a.vhd ENTITY hi_pri8a IS PORT( d : IN q : OUT END hi_pri8a; BIT_VECTOR(7 downto 0); BIT_VECTOR (2 downto 0)); ARCHITECTURE a OF hi_pri8a IS BEGIN Concurrent Signal Assignments q(2) <= d(7) or d(6) or d(5) or d(4); q(1) <= d(7) or d(6) or ((not d(5)) and (not d(4)) and d(3)) or ((not d(5)) and (not d(4)) and d(2)); q(0) <= d(7) or ((not d(6)) and d(5)) or ((not d(6)) and (not d(4)) and d(3)) or ((not d(6)) and (not d(4)) and (not d(2)) and d(1)); END a; Although this code works, it is not terribly elegant, nor does it give any insight into the operation of the encoder circuit. Also, if we expand our encoder output by one or more bits, the equations become more cumbersome with each new bit and soon become impractically large and susceptible to typing errors. A VHDL conditional signal assignment statement is an ideal alternative for use in a priority encoder circuit. A section of VHDL code using this format is shown below. hi_pri8b.vhd hi_pri8b.scf hi_pri8b.vhd ENTITY hi_pri8b IS PORT( d : IN BIT_VECTOR (7 downto 0); q : OUT INTEGER RANGE 0 to 7); END hi_pri8b; 5.2 Encoders 183 ARCHITECTURE a OF hi_pri8b IS BEGIN Conditional Signal Assignment encoder: q <= 7 WHEN d(7)=1 ELSE 6 WHEN d(6)=1 ELSE 5 WHEN d(5)=1 ELSE 4 WHEN d(4)=1 ELSE 3 WHEN d(3)=1 ELSE 2 WHEN d(2)=1 ELSE 1 WHEN d(1)=1 ELSE 0; END a; Output q is dened as type INTEGER. Since it ranges from 0 to 7, the MAX PLUS II VHDL compiler will automatically assign three outputs: Q2, Q1, and Q0. The conditional signal assignment statement evaluates the rst WHEN clause to determine if its condition (d(7) 1) is true. If so, it assigns q the value of 7 (Q2Q1Q0 111). If the rst condition is false, the next WHEN clause is evaluated, assigning q the value 6 (Q2Q1Q0 110) if true, and so on until all WHEN clauses have been evaluated. If no clause is true, then the default value (0: Q2Q1Q0 000) is assigned to the output. In the conditional signal assignment, the highest-priority condition is examined rst. If it is true, the output is assigned according to that condition and no further conditions are evaluated. If the rst condition is false, the condition of next priority is evaluated, and so on until the end. Thus, a low-priority input cannot alter the code resulting from an input of higher priority, as required by the priority encoding principle. The effect is similar to that of an IF statement, where a sequence of conditions is evaluated, but only one output assignment is made. However, an IF statement must be used within a PROCESS statement, if we choose to use it. The IF statement for a priority encoder is as shown below. PROCESS (d) BEGIN IF (d(7) = 1) THEN q <= 7; ELSIF (d(6) = 1) THEN q <= 6; ELSIF (d(1) = 1 THEN q <= 1; ELSE q <= 0; END IF; END PROCESS; Figure 5.31 shows the simulation of an 3-bit priority encoder. The d inputs are shown separately, so that we can easily determine which inputs are active. The q outputs are grouped so as to show the encoded output value as a hexadecimal number. BCD Priority Encoder A BCD priority encoder, illustrated in Figure 5.32, accepts ten inputs and generates a BCD code (0000 to 1001), corresponding to the highest-priority active input. The truth table for this circuit is shown in Table 5.7, with a simulation of the circuit shown in Figure 5.33. 184 C H A P T E R 5 Combinational Logic Functions FIGURE 5.31 Simulation File for a 3-bit Priority Encoder Table 5.7 Truth Table of a BCD Priority Encoder HIPR/BCD D0 D1 D2 D3 D4 D5 D6 Q3 Q2 Q1 Q0 D7 D8 D9 D8 D7 D6 D5 D4 D3 D2 D1 Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 X 0 0 0 0 0 0 0 1 X X 0 0 0 0 0 0 1 X X X 0 0 0 0 0 1 X X X X 0 0 0 0 1 X X X X X 0 0 0 1 X X X X X X 0 0 1 X X X X X X X 0 1 X X X X X X X X 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 D9 FIGURE 5.32 BCD Priority Encoder FIGURE 5.33 Simulation File for a BCD Priority Encoder 5.3 CD: hi_pri10.scf Multiplexers 185 Derivation of the BCD priority encoder equations and development of a VHDL description of the circuit are left as exercises in the end-of-chapter problems. SECTION 5.2 REVIEW PROBLEM 5.4 State the main limitation of the 3-bit binary encoder shown in Figure 5.29. How can the encoder be modied to overcome this limitation? 5.3 Multiplexers KEY TERMS Multiplexer A circuit that directs one of several digital signals to a single output, depending on the states of several select inputs. Data inputs The multiplexer inputs that feed a digital signal to the output when selected. Select inputs The multiplexer inputs that select a digital input channel. Double-subscript notation A naming convention where two or more numerically related groups of signals are named using two subscript numerals. Generally, the rst digit refers to a group of signals and the second to an element of a group. (e.g., X03 represents element 3 of group 0 for a set of signal groups, X.) A multiplexer (abbreviated MUX) is a device for switching one of several digital signals to an output, under the control of another set of binary inputs. The inputs to be switched are called the data inputs; those that determine which signal is directed to the output are called the select inputs. D0 D1 INPUT INPUT INPUT NOT S1 INPUT NOT S0 AND3 AND3 OR4 OUTPUT D2 D3 INPUT INPUT Y AND3 AND3 FIGURE 5.34 4-to-1 Multiplexer Figure 5.34 shows the logic circuit for a 4-to-1 multiplexer, with data inputs labelled D0 to D3 and the select inputs labelled S0 and S1. By examining the circuit, we can see that the 4-to-1 MUX is described by the following Boolean equation: Y D0S1S0 D1S1S0 D2S1S0 D3S1S0 186 C H A P T E R 5 Combinational Logic Functions Table 5.8 4-to-1 MUX Truth Table S1 S0 Y 0 0 1 1 0 1 0 1 D0 D1 D2 D3 For any given combination of S1S0, only one of the above four product terms will be enabled. For example, when S1S0 10, the equation evaluates to: Y (D0 0) (D1 0) (D2 1) (D3 0) D2 The MUX equation can be described by a truth table as in Table 5.8. The subscript of the selected data input is the decimal equivalent of the binary combination S1S0. Figure 5.35 shows two symbols used for a 4-to-1 multiplexer. The rst symbol shows the data and select inputs as individual lines. The second symbol shows the data inputs as a single 4-bit bus line and the select inputs as a 2-bit bus. D0 4 D1 D2 Y D Y D3 2 S1S0 a. 4-to-1 MUX symbol showing individual lines S b. 4-to-1 MUX symbol showing bus lines FIGURE 5.35 Multiplexer Symbols In general, a multiplexer with n select inputs will have m 2n data inputs. Thus, other common multiplexer sizes are 8-to-1 (for 3 select inputs) and 16-to-1 (for 4 select inputs). Data inputs can also be multiple-bit busses, as in Figure 5.36. The slash through a thick data line and the number 4 above the line indicate that it represents four related data signals. In this device, the select inputs switch groups of data inputs, as shown in the truth table in Table 5.9. Table 5.9 Truth Table for a 4-to-1 4-bit Bus MUX 4 D0 4 4 D1 D2 4 D3 S1 S0 Y3 Y2 Y1 Y0 0 0 1 1 Y 4 0 1 0 1 D03D02D01D00 D13D12D11D10 D23D22D21D20 D33D32D31D30 S1S0 FIGURE 5.36 4-to-1 4-bit Bus Multiplexer The naming convention shown in Table 5.9, known as double-subscript notation, is used frequently for identifying variables that are bundled in numerically related groups, the elements of which are themselves numbered. The rst subscript identies the group that a variable belongs to; the second subscript indicates which element of the group a variable represents. Multiplexing of Time-Varying Signals We can observe the function of a multiplexer by using time-varying waveforms, such as a series of digital pulses. If we apply a different digital signal to each data input, and step the 5.3 Multiplexers 187 select inputs through an increasing binary sequence, we can see the different input waveforms appear at the output in a predictable sequence, as shown by the simulation waveforms in Figure 5.37. The frequencies shown in the simulation were chosen to make as great a contrast as possible between adjacent inputs so that the different selected inputs could easily be seen. FIGURE 5.37 Simulation Waveforms for a 4-to-1 MUX In Figure 5.37, we initially see the D0 waveform appearing at the Y output when S1S0 00, followed in sequence by the D1, D2, and D3 waveforms when S1S0 01, 10, and 11, respectively. (The S1S0 input combination is shown as a single hexadecimal value between 0 and 3, labelled S[1..0].) This simulation can be created in the MAX PLUS II simulator by dening a base clock pulse length (e.g., 40 ns) and assigning that to one of the inputs (D1 in this case). Other input waveforms are set to periods of 2, 4, and 8 times the base waveform period (for D3, D2, and D0, respectively). The select input count waveforms are set to allow three cycles of the longest waveform (D0) to appear at Y when selected. VHDL Implementation of Multiplexers A multiplexer can be represented in MAX PLUS II as a Graphic Design File, similar to the diagram of Figure 5.34, or in a hardware description language such as VHDL. Several different VHDL constructs can be used to dene a multiplexer. We can use a concurrent signal assignment statement, a selected signal assignment statement, or a CASE statement within a PROCESS. We will briey look at each form for a 4-to-1 multiplexer. Later, you will be required to extend these constructs to larger multiplexer circuits. Concurrent Signal Assignment Recall that the concurrent signal assignment statement takes the form: __signal <= __expression; We can use this to encode the Boolean expression that describes a 4-to-1 MUX. The VHDL le that incorporates this statement is as follows. mux4.vhd mux4.scf mux4.vhd 4-to-1 multiplexer Directs one of four input signals (d0 to d3) to output, depending on status of select bits (s1, s0). 188 C H A P T E R 5 Combinational Logic Functions ENTITY mux4 IS PORT( d0, d1, d2, d3 : IN s : IN y : OUT END mux4; BIT; BIT_VECTOR (1 downto 0); BIT); ARCHITECTURE mux4to1 OF mux4 IS BEGIN Concurrent Signal Assignment y <= ((not s(1)) and (not s(0)) and or ((not s(1)) and ( s(0)) and or (( s(1)) and (not s(0)) and or (( s(1)) and ( s(0)) and END mux4to1; d0) d1) d2) d3); While the concurrent signal assignment is fairly easy to use, it becomes cumbersome for larger multiplexers, such as 8-to-1 or greater. The entity declaration will be identical for the other VHDL examples. The only change we will make will be to replace the concurrent signal assignment in the architecture body with some other VHDL construct. Selected Signal Assignment Statement This construct has the following form (the label is optional): __label: WITH __expression SELECT __signal <= __expression __expression __expression __expression WHEN WHEN WHEN WHEN __constant_value, __constant_value, __constant_value, __constant_value; The 4-to-1 MUX can be described in VHDL as follows, using a selected signal assignment: mux4sel.vhd ENTITY mux4sel IS PORT( d0, d1, d2, d3 : IN s : IN y : OUT END mux4sel; BIT; BIT_VECTOR (1 downto 0); BIT); ARCHITECTURE mux4to1 OF mux4sel IS BEGIN M: WITH s SELECT y <= d0 WHEN 00, d1 WHEN 01, d2 WHEN 10, d3 WHEN 11; END mux4to1; The selected signal assignment evaluates the expression in the WITH clause (in this case, the 2-bit vector, s) and, depending on its value, selects an expression to assign to y. Thus, if s1s0 00, y d0. If s1s0 01, then y d1, and so on for the remaining values of s1s0. 5.3 Multiplexers 189 CASE Statement within a PROCESS In our MUX example, we could use a CASE statement as follows: mux4case.vhd ENTITY mux4case IS PORT( d0, d1, d2, d3 : IN s : IN y : OUT END mux4case; BIT; BIT_VECTOR (1 downto 0); BIT); ARCHITECTURE mux4to1 OF mux4case IS BEGIN CASE statement within a PROCESS Monitor select inputs and execute PROCESS (s) BEGIN CASE s IS WHEN 00 => y <= WHEN 01 => y <= WHEN 10 => y <= WHEN 11 => y <= WHEN others => y <= END CASE; END PROCESS; END mux4to1; if they change d0; d1; d2; d3; 0; If the select inputs change, the PROCESS statements are executed. The CASE statement evaluates the select input vector, s, and chooses a signal assignment based on its value. It is good design practice to include a default case (the others clause) even when there are no obvious other cases. A default case is essential when using STD_LOGIC types rather than BIT types, as 0 and 1 values do not cover all possible cases for STD LOGIC signals. (Recall from Chapter 4 that STD_LOGIC is a nine-valued logic type, incorporating such things as Dont Care (-), Unknown (X), and High Impedance (Z), as well as 0 and 1.) Multiplexer Applications Multiplexers are used for a variety of applications, including selection of one data stream out of several choices, switching multiple-bit data from several channels to one multiplebit output, sharing data on one output over time, and generating bit patterns or waveforms. Single-Channel Data Selection The simplest way to use a multiplexer is to switch the select inputs manually in order to direct one data source to the MUX output. Example 5.6 shows a pair of single-pole singlethrow (SPST) switches supplying the select input logic for this type of application. EXAMPLE 5.6 Figure 5.38 shows a digital audio switching system. The system shown can select a signal from one of four sources (compact disc (CD) players, labelled CD0 to CD3) and direct it to a digital signal processor (DSP) at its output. We assume we have direct access to the audio signals in digital form. Make a table listing which digital audio source in Figure 5.38 is routed to the DSP for each combination of the multiplexer select inputs, S1 and S0. 190 C H A P T E R 5 Combinational Logic Functions FIGURE 5.38 Example 5.6 Single-Channel Data Selection CD0 CD1 CD2 MUX D0 CD3 D1 DSP Y D2 D3 Vcc S1 S0 Channel-select switches Solution Table 5.10 Sources Selected by a 4-to-1 MUX in Figure 5.38 S1 S0 Selected Input Selected Source 0 0 1 1 0 1 0 1 D0 D1 D2 D3 CD0 CD1 CD2 CD3 Multi-Channel Data Selection Example 5.6 assumes that the output of a multiplexer is a single bit or stream of bits. Some applications require several bits to be selected in parallel, such as when data would be represented on a numerical display. Figure 5.39 shows a circuit, based on a quadruple (4-channel) 2-to-1 multiplexer, that will direct one of two BCD digits to a seven-segment display. The bits D03D02D01D00 act as a 4-bit group input, since the rst digit of all four subscripts is 0. When the MUX select input (S) is 0, these inputs are all connected to the outputs Y3Y2Y1Y0. Similarly, when the select input is 1, inputs D13D12D11D10 are connected to the Y outputs. The seven-segment display in Figure 5.39 will display 4 if S 0 (D0 inputs selected) and 9 if S 1 (D1 inputs selected). 5.3 FIGURE 5.39 Quadruple 2-to-1 MUX as a Digital Output Selector BCD/7SEG 0 Multiplexers 191 7-Segment Display D03 1 BCD0 D02 0 a D01 0 b 1 D13 0 BCD1 D12 0 Y3 D3 Y2 D00 D2 d Y1 D1 e Y0 D0 c f g D11 1 D10 S EXAMPLE 5.7 Draw the symbol for a multiplexer that will select one of four 4-bit channels and direct it to a 4-bit output. Create a VHDL le that implements this function and a simulation showing the operation of the device. 4 D0 4 D1 4 4 D2 4 D3 S1 S0 FIGURE 5.40 Example 5.7 4-channel 4-bit MUX quad4to1.vhd quad4to1.scf Y Solution Figure 5.40 shows the symbol for the 4-channel, 4-bit multiplexer. This symbol is shown with the data inputs and outputs in bus form. The data inputs are labelled in groups D0 to D3, which contain the individual inputs [D03..D00] to [D33..D30]. A VHDL le describing this function is listed below. quad4to1.vhd ENTITY quad4to1 PORT( s : IN d0 : IN d1 : IN d2 : IN d3 : IN y : OUT END quad4to1; IS INTEGER RANGE BIT_VECTOR (3 BIT_VECTOR (3 BIT_VECTOR (3 BIT_VECTOR (3 BIT_VECTOR (3 0 to 3; downto 0); downto 0); downto 0); downto 0); downto 0)); ARCHITECTURE mux4 OF quad4to1 IS BEGIN Selected Signal Assignment MUX4: WITH s SELECT y <= d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3; END mux4; Figure 5.41 shows a set of simulation waveforms for the multiplexer. The D inputs are shown in groups of four, the value of each shown as a steady hexadecimal value. The select inputs are grouped, showing an increasing 2-bit binary count as a hexadecimal value (0 to 3, then repeating). As the S inputs select each group of D inputs, their combined value is directed to the Y output group. 192 C H A P T E R 5 Combinational Logic Functions FIGURE 5.41 Example 5.7 Simulation for a 4-channel 4-bit MUX Time-Dependent Multiplexer Applications KEY TERMS Counter A digital circuit whose output produces a xed sequence of binary states when an input called the clock receives a series of pulses. The output advances by one for each clock pulse (e.g., the output state of a 4-bit binary counter progresses in order from 0000 to 1111, then repeats). Clock A signal that controls the operation of a sequential digital circuit, such as a counter, by advancing its outputs to the next state when it receives a pulse. Positive edge The point on a digital waveform where the logic level of the waveform makes a LOW-to-HIGH transition. A time-dependent multiplexer application is one that uses the MUX input channels one after the other in a repeating time sequence. We can create such an application by applying a set of changing binary signals to the MUX select inputs. For this function, we can use a 3bit binary counter to generate a binary sequence that goes from 000 to 111 (8 states) and repeats indenitely, the outputs advancing by one with every pulse applied to the clock input of the counter. CLOCK Q0 Q1 Q2 FIGURE 5.42 Timing Diagram of a 3-bit Counter Figure 5.42 shows the timing diagram of a 3-bit counter. The outputs Q2Q1Q0 change every time the clock signal makes a transition from LOW to HIGH. If you read the Q 5.3 Multiplexers 193 waveforms from bottom to top, you will see that they generate a repeating binary sequence (000, 001, 010, 011, 100, 101, 110, 111, 000 . . .). MUX D0 D1 D2 D3 Y D4 D5 D6 D7 CTR DIV 8 S2 Q2 CLOCK S1 Q1 S0 Q0 FIGURE 5.43 Time-Dependent Selection of Eight Multiplexer Channels If we connect the counter outputs Q2Q1Q0 to the select inputs of an 8-to-1 MUX, as in Figure 5.43, we will select the channels in sequence, one after the other. The counter is labelled CTR DIV 8 because its most signicant bit output has a frequency equal to the clock frequency divided by eight. The triangle on the clock input indicates that it is active when the clock waveform makes a transition from one logic level to another. Since there is no inverting bubble on the clock input, we know that the active clock transition is from LOW to HIGH (i.e., a positive edge). Waveform Generation. A multiplexer and counter can be used as a programmable waveform generator. The output waveform can be programmed to any pattern by switching the logic levels on the data inputs. This is an easy way to generate an asymmetrical waveform, a task which is more complicated using other digital circuits. The circuit can also generate symmetrical waveforms by alternating the logic levels of consecutive groups of inputs. EXAMPLE 5.8 Draw a circuit that uses an 8-to-1 multiplexer to generate a programmable 8-bit repeating pattern. Draw the timing diagram of the select inputs and the output waveform for the following pattern of data inputs. D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 1 0 1 Solution Figure 5.44a shows the waveform generator circuit. The output waveform with respect to the counter inputs is shown in Figure 5.44b. This pattern is relatively difcult to generate by other means since it has several unequal HIGH and LOW sequences in one period. 194 C H A P T E R 5 Combinational Logic Functions FIGURE 5.44 Example 5.8 Programmable Waveform Generator MUX D0 D1 D2 D3 D4 Y D5 D6 D7 CTR DIV 8 Q2 CLOCK Q1 Q0 S2 S1 S0 Q0 Q1 Q2 Y EXAMPLE 5.9 The programmable waveform generator in Figure 5.44 generates a symmetrical pulse waveform having a frequency of 1 kHz when the data inputs are set as follows. D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 1 How should the switches be set to generate a symmetrical 2 kHz waveform? A symmetrical 4 kHz waveform? Solution Pattern for 2 kHz: D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 1 5.3 Multiplexers 195 Pattern for 4 kHz: D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 Time Division Multiplexing KEY TERMS Time division multiplexing (TDM) A technique of using one transmission line to send many signals simultaneously by making them share the line for equal fractions of time. Time slot A period of time during which a transmitted data element has sole access to a transmission path. Bit multiplexing A TDM technique in which one bit is sent from each channel during the channels assigned time slot. Byte (or word) multiplexing A TDM technique in which a byte (or word) is sent from each channel during its assigned time slot. (A byte is eight bits; a word is a group of bits whose size varies with the particular system.) Time division multiplexing is a method of improving the efciency of a transmission system by sharing one transmission path among many signals. For example, if we wish to send four 4-bit numbers over a single transmission line, we can transmit the bits one after the other, as shown in Figure 5.45. p00 p10 p20 p30 p01 p11 p21 p23 p33 p00 FIGURE 5.45 4 4 Data Stream (Bit Multiplexing) In Figure 5.45, we see the least signicant bit of the 4-bit word p0 transmitted, followed by the LSB of p1, p2, then p3. After that, the second bit of each word is transmitted in sequence, then all the third bits, and nally, all MSBs in sequence. Each bit is assigned a time slot in the sequence. During that time, the bit has sole access to the transmission line. When its time elapses, the next bit is sent and so on in sequence, until the channel assignment returns to the original location. This technique, known as bit multiplexing, can be implemented by a circuit similar to the waveform generator shown in Figure 5.44. Rather than xed switch inputs, the data inputs would be some data source, such as a digitized audio signal. We can also arrange our circuit so that one byte (8 bits) or one word (a group of bits) is sent through a selected channel. In this case, we must keep the channel selected for enough clock pulses to transmit the byte or word, then move to the next one. This technique is called byte (or word) multiplexing. Figure 5.46 shows a data stream of four 4-bit words that are word-multiplexed down a data transmission path. p00 p01 p02 p03 FIGURE 5.46 4 4 Data Stream (Word Multiplexing) p10 p11 p12 p32 p33 p00 196 C H A P T E R 5 Combinational Logic Functions Telephone companies use TDM to maximize the use of their phone lines. Speech or data is digitally encoded for transmission. Each speech or data channel becomes a multiplexer data input which shares time with all other channels on a single phone line. A counter on the MUX selects the speech channels one after the other in a continuous sequence. The counter must switch the channels fast enough so that there is no apparent interruption of the transmitted conversation or data stream. EXAMPLE 5.10 Draw a diagram of a circuit that uses an 8-to-1 multiplexer to share one telephone line among eight digitized speech channels. Write a VHDL le for the multiplexer and create a simulation to show its operation. Solution Figure 5.47 shows the required multiplexer circuit. Each channel is connected to a data input and a 3-bit binary counter is connected to the select inputs. Digitized speech channels MUX CH0 D0 CH1 D1 D2 D3 CH2 D4 CH3 CH4 D7 Y D5 D6 S2 S1 CH5 S0 CH6 CH7 CTR DIV 8 Q2 CLOCK Q1 Q0 FIGURE 5.47 Example 5.10 Time-Division Multiplexing of Telephone Channels The VHDL code for the multiplexer is: mux_8ch.vhd mux_8ch.scf ENTITY mux_8ch PORT( sel : IN d : IN y : OUT END mux_8ch; IS BIT_VECTOR (2 downto 0); BIT_VECTOR (7 downto 0); BIT); ARCHITECTURE a OF mux_8ch IS BEGIN Selected Signal Assignment MUX8: WITH sel SELECT y <= d(0) WHEN 000, Telephone line 5.4 d(1) d(2) d(3) d(4) d(5) d(6) d(7) WHEN WHEN WHEN WHEN WHEN WHEN WHEN Demultiplexers 197 001, 010, 011, 100, 101, 110, 111; END a; The simulation is shown in Figure 5.48. For clarity, digital data are present on the MUX inputs just before and after they are switched to the Y output. The output shows the channel data in sequence, starting with channel 0. FIGURE 5.48 Simulation for an 8-bit Time-Division Multiplexer SECTION 5.3 REVIEW PROBLEM 5.5 What denes whether a multiplexer application is time-dependent or not? What additional component can be added to make a MUX application time-dependent? 5.4 Demultiplexers KEY TERMS Demultiplexer A circuit that uses a binary decoder to direct a digital signal from a single source to one of several destinations. A demultiplexer performs the reverse function of a multiplexer. A multiplexer (MUX) directs one of several input signals to a single output; a demultiplexer (DMUX) directs a single input signal to one of several outputs. In both cases, the selected input or output is chosen by the state of an internal decoder. Figure 5.49 shows the logic circuit for a 1-to-4 demultiplexer. Compare this to Figure 5.4, a 4-output decoder. This circuits are the same except that the active-LOW enable input has been changed to an active-HIGH data input. The circuit in Figure 5.49 could still be used as a decoder, except that its enable input would be active-HIGH. 198 C H A P T E R 5 Combinational Logic Functions S0 S1 D Y0 Y1 Y2 Y3 FIGURE 5.49 4-bit Decoder/Demultiplexer Each AND gate in the demultiplexer enables or inhibits the signal output according to the state of the select inputs, thus directing the data to one of the output lines. For instance, S1S0 10 directs incoming digital data to output Y2. S1 Binary input S0 Y0 S1 Channel select S0 Y1 Y2 Vcc D Y3 a. Decoder Y0 Y1 Y2 Signal D Y3 b. Demultiplexer FIGURE 5.50 Same Device Used as a Decoder or Demultiplexer Figure 5.50 illustrates the use of a single device as either a decoder or a demultiplexer. In Figure 5.50a, input D is tied HIGH. When an output is selected by S1 and S0, it goes HIGH, acting as a decoder with active-HIGH outputs. In Figure 5.50b, D acts as a demultiplexer data input. The data are directed to the output selected by S1 and S0. NOTE Since a single device can be used either way, this implies that any of the VHDL binary decoder designs used in this chapter can also be used as demultiplexers. A decoder/demultiplexer can have active-LOW outputs, but only if the D input is also active-LOW. This is important because the demultiplexer data must be inverted twice to retain its original logic values. Demultiplexing a TDM Signal In Example 5.10, we saw how a multiplexer could be used to send 8 digital channels across a single line, multiplexed over time. Obviously, such a system is not of much value if the signals cannot be sorted out at the receiving end. The received digital data must be demultiplexed and sent to their appropriate destinations. 5.4 Demultiplexers 199 The process is the reverse of multiplexing; data are sent to an output selected by a counter at the DMUX select inputs. (We assume that the counters at the MUX and DMUX select inputs are somehow synchronized or possibly, if located close together, are the same counter.) EXAMPLE 5.11 Draw a demultiplexing circuit that will take the multiplexed output of the circuit in Figure 5.47 and distribute it to 8 different local telephone circuits. Write a VHDL le for the demultiplexer and create a simulation le that shows its operation. Use active-LOW outputs for the demultiplexer. How does this affect the outputs when they are not transmitting data? Solution Figure 5.51 shows the original multiplexing circuit connecting to the new demultiplexing circuit. The diagram indicates that the two sides of the circuit are separated by some distance. The clock is shared between both sides of the circuit, but is generated on the MUX side. Both sides share a common ground. Each side of the circuit has its own 3-bit counter. FIGURE 5.51 Example 5.11 Time-Division Multiplexing and Demultiplexing MUX DMUX CH0 D0 Y0 CH0 CH1 D1 D2 Y1 CH1 D3 CH2 D4 CH3 D7 S2 S1 CH5 S2 S1 S0 S0 CH2 Y3 CH3 Y4 D5 D6 CH4 Y2 D Y CH4 Y5 CH5 Y6 CH6 Y7 CH7 CTR DIV 8 CH6 CH7 Q2 Q2 Q1 Q0 Q1 Q0 CTR DIV 8 CLOCK The VHDL code for the demultiplexer is as follows. (This is the same implementation as a 3-line-to-8-line decoder with an enable input.) dmux8.vhd dmux8.scf dmux8.vhd 1-to-8 demultiplexer/decoder Decoder: set d to 0; outputs are activated by binary combination of s. Demultiplexer: apply data stream to d; data directed to y output with subscript same as value of s. Outputs and d are active-LOW. DMUX data are inverted twice to keep them true. 200 C H A P T E R 5 Combinational Logic Functions ENTITY dmux8 IS PORT( s : IN INTEGER Range 0 to 7; d : IN BIT; y : OUT BIT_VECTOR (0 to 7)); END dmux8; ARCHITECTURE a OF dmux8 IS SIGNAL output : BIT_VECTOR (0 to BEGIN PROCESS (d, s) BEGIN IF (d 1) THEN output <= 11111111; ELSE CASE s IS WHEN 0 => output WHEN 1 => output WHEN 2 => output WHEN 3 => output WHEN 4 => output WHEN 5 => output WHEN 6 => output WHEN 7 => output WHEN OTHERS => output END CASE; END IF; y <= output; END PROCESS; END a; www.electronictech.com 7); <= <= <= <= <= <= <= <= <= 01111111; 10111111; 11011111; 11101111; 11110111; 11111011; 11111101; 11111110; 11111111; The simulation, shown in Figure 5.52, has as its input data the output of the original MUX simulation in Figure 5.48. Data are distributed to the outputs in sequence. Compare the DMUX output data to the MUX input data in Figure 5.48. FIGURE 5.52 Example 5.11 Demultiplexer Simulation Note that idle channels sit HIGH. This is opposite from the status of the idle MUX lines and may affect circuit operation. If so, a DMUX with active-HIGH outputs and active-HIGH enable should be used. 5.4 Demultiplexers 201 CMOS Analog Multiplexer/Demultiplexer KEY TERMS CMOS analog switch A CMOS device that will pass an analog or digital signal in either direction, when enabled. Also called a transmission gate. There is no TTL equivalent. An interesting device used in some CMOS medium-scale integration multiplexers and demultiplexers, as well as other applications, is the CMOS analog switch, or transmission gate. This device has the property of allowing signals to pass in two directions, instead of only one, thus allowing both positive and negative voltages and currents to pass. It also has no requirement that the voltages be of a specic value such as 5 volts. These properties make the device suitable for passing analog signals. FIGURE 5.53 Line Drivers Figure 5.53 shows several symbols, indicating the development of the transmission gate concept. Figures 5.53a and b show ampliers whose output and input are clearly dened by the direction of the triangular amplier symbol. A signal has one possible direction of ow. Figure 5.53b includes an active-LOW gating input, which can turn the signal on and off. Figure 5.53c shows two opposite-direction overlapping amplier symbols, with a gating input to enable or inhibit the bidirectional signal ow. The signal through the transmission gate may be either analog or digital. Analog switches are available in packages of four switches with part numbers such as 4066B (standard CMOS) or 74HC4066 (high-speed CMOS). Several available CMOS MUX/DMUX chips use analog switches to send signals in either direction. Figure 5.54 illustrates the design principle as applied to a 4-channel MUX/DMUX. FIGURE 5.54 4-Channel CMOS MUX/DMUX S0 S1 If four signals are to be multiplexed, they are connected to inputs D0 to D3. The decoder, activated by S1 and S0, selects which one of the four switches is enabled. Figure 5.54 shows Channel 2 active (S1S0 10). 202 C H A P T E R 5 Combinational Logic Functions Since all analog switch outputs are connected together, any selected channel connects to Y, resulting in a multiplexed output. To use the circuit in Figure 5.54 as a demultiplexer, the inputs and outputs are merely reversed. EXAMPLE 5.12 A CMOS 4097B dual 8-channel MUX/DMUX can be used simultaneously as a multiplexer on one half of the device and as a demultiplexer on the other side. FIGURE 5.55 Example 5.12 4097B MUX/DMUX as a Time Division MUX/DMUX S0 Q0 S1 Q1 S2 Q2 5.5 Magnitude Comparators 203 A circuit in a recording studio uses one side of a 4097B MUX/DMUX to multiplex 8 digital audio channels into a digital signal processor (DSP), using time division multiplexing. The other half of the 4097B takes the processed signals from a DSP output and distributes them to 8 channels on a digital audio tape (DAT) unit. Draw the circuit. Solution Figure 5.55 shows a possible circuit. The counter can be part of the DSP. An audio source channel is selected by the counter inputs, data are sent to the DSP, where they are processed and sent to the same channel of the DAT. The counter advances by one, selecting a new channel and repeating the process. Some analog MUX/DMUX devices in high-speed CMOS include: 74HC4051 8-channel MUX/DMUX, 74HC4052 dual 4-channel MUX/DMUX, and 74HC4053 triple 2-channel MUX/DMUX. 5.5 Magnitude Comparators KEY TERMS Magnitude comparator A circuit that compares two n-bit binary numbers, indicates whether or not the numbers are equal, and, if not, which one is larger. FIGURE 5.56 Exclusive NOR Gate Table 5.11 XNOR Truth Table A B Y 0 0 1 1 0 1 0 1 1 0 0 1 If we are interested in nding out whether or not two binary numbers are the same, we can use a magnitude comparator. The simplest comparison circuit is the Exclusive NOR gate, whose circuit symbol is shown in Figure 5.56 and whose truth table is given in Table 5.11. The output of the XNOR gate is 1 if its inputs are the same (A B, symbolized AEQB) and 0 if they are different. For this reason, the XNOR gate is sometimes called a coincidence gate. We can use several XNORs to compare each bit of two multi-bit binary numbers. Figure 5.57 shows a 2-bit comparator with one output that goes HIGH if all bits of A and B are identical. FIGURE 5.57 2-bit Magnitude Comparator AEQB If the most signicant bit (MSB) of A equals the MSB of B, the output of the upper XNOR is HIGH. If the least signicant bits (LSBs) are the same, the output of the lower XNOR is HIGH. If both these conditions are satised, then A B, which is indicated by a HIGH at the AND output. This general principle applies to any number of bits: AEQB (An 1 Bn 1) (An 2 Bn 2) ... (A1 B1) (A0 B0) for two n-bit numbers, A and B. Some magnitude comparators also include an output that activates if A is greater than B (symbolized A B or AGTB) and another that is active when A is less than B (symbolized A B or ALTB). Figure 5.58 shows the comparator of Figure 5.57 expanded to include the greater than and less than functions. Let us analyze the AGTB circuit. The AGTB function has two AND-shaped gates that compare A and B bit-by-bit to see which is larger. 204 C H A P T E R 5 Combinational Logic Functions FIGURE 5.58 2-bit Comparator With AEQB, AGTB, and ALTB Outputs AEQB AGTB ALTB 1. The 2-input gate examines the MSBs of A and B. If A1 1 AND B1 0, then we know that A B. (This implies one of the following inequalities: 10 00; 10 01; 11 00; or 11 01.) 2. If A1 B1, then we dont know whether or not A B until we compare the next most signicant bits, A0 and B0. The 3-input gate makes this comparison. Since this gate is enabled by the XNOR, which compares the two MSBs, it is only active when A1 B1. This yields the term (A1 B1)A0B0 in the Boolean expression for the AGTB function. 3. If A1 B1 AND A0 1 AND B0 0, then the 3-input gate has a HIGH output, telling us, via the OR gate, that A B. (The only possibilities are (01 00) and (11 10).) Similar logic works in the ALTB circuit, except that inversion is on the A, rather than the B bits. Alternatively, we can simplify either the AGTB or the ALTB function by using a NOR function. For instance, if we have developed a circuit to indicate AEQB and ALTB, we can make the AGTB function from the other two, as follows: AGTB AEQB ALTB This Boolean expression implies that if A is not equal to or less than B, then it must be greater than B. Figure 5.59 shows a 4-bit comparator with AEQB, ALTB, and AGTB outputs. The Boolean expressions for the outputs are: AEQB ALTB AGTB (A3 B3)(A2 B2)(A1 A3B3 (A3 B3)A2 B2 (A2 B2)(A1 B1)A0B0 AEQB ALTB B1)(A0 B0) (A3 B3)(A2 B2)A1B1 (A3 B3) This comparison technique can be expanded to as many bits as necessary. A 4-bit comparator requires four AND-shaped gates for its ALTB function. We can interpret the Boolean expression for this function as follows. A 1. 2. 3. 4. B if: The MSB of A is less than the MSB of B, OR The MSBs are equal, but the second bit of A is less than the second bit of B, OR The rst two bits are equal, but the third bit of A is less than the third bit of B, OR The rst three bits are equal, but the LSB of A is less than the LSB of B Expansion to more bits would use the same principle of comparing bits one at a time, beginning with the MSBs. 5.5 Magnitude Comparators 205 ALTB AEQB AGTB FIGURE 5.59 4-bit Magnitude Comparator EXAMPLE 5.13 Application A digital thermometer has two input probes. A circuit in the thermometer converts the measured temperature at each probe to an 8-bit number, as shown by the block in Figure Probe input A A7 A6 A5 A4 A3 A2 A1 A0 Probe input Converter B B7 B6 B5 B4 B3 B2 B1 B0 FIGURE 5.60 Example 5.13 Two-channel Digital Thermometer 5.60. In addition to measuring the temperature at each input, the thermometer has a comparison function that indicates whether the temperature at one input is greater than, equal to, or less than the temperature at the other input. Draw a logic diagram showing how a magnitude comparator could be connected to light a green LED for AGTB, an amber LED for AEQB, and a red LED for ALTB. Solution Figure 5.61 shows the logic diagram of the magnitude comparator connected 206 C H A P T E R 5 Combinational Logic Functions Probe input Probe input A Vcc B Converter A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Vcc B7 B6 B5 B4 B3 B2 B1 B0 A7 A6 A5 A4 A3 A2 A1 A0 Vcc ALTB Comparator AEQB G A R AGTB FIGURE 5.61 Example 5.13 Temperature Comparator Block Diagram to the thermometers digital output. When one of the comparator outputs goes HIGH, it sets the output of the corresponding inverter LOW. This provides a current path to ground for the indicator LED for that output, causing it to illuminate. VHDL Magnitude Comparators The most obvious way to create a VHDL representation of a magnitude comparator is to use a concurrent signal assignment statement for each comparing function. For example, the following VHDL code can represent the 2-bit magnitude comparator of Figure 5.57: compare2.vhd ENTITY compare2 IS PORT( a, b agtb, aeqb, altb END compare2; compare2.vhd compare2.scf ARCHITECTURE a BEGIN altb <= or aeqb <= agtb <= or END a; : IN : OUT BIT_VECTOR (1 downto 0); BIT); OF compare2 IS (not (a(1)) and b(1)) ((not (a(1) xor b(1))) and (not (a(0)) and b(0))); (not (a(1) xor b(1))) and (not (a(0) xor b(0))); (a(1) and not (b(1))) ((not (a(1) xor b(1))) and (a(0) and not (b(0)))); A simulation for this le is shown in Figure 5.62. The comparison outputs go HIGH to indicate A B, A B, or A B. Although this approach works, it is not a very good one. Due to the complexity of the Boolean equations for ALTB and AGTB, it is difcult to type them without making errors. (Try it!) The difculty increases greatly with the number of required inputs. 5.5 Magnitude Comparators 207 FIGURE 5.62 Simulation for a 2-bit Magnitude Comparator The following code for a 4-bit comparator illustrates a much more efcient method. Since VHDL allows inputs to be represented as integers, we can dene the required size of inputs A and B and compare them using IF statements. For every comparison, we assign an output vector consisting of bits for ALTB, AEQB, and AGTB one of the values 110, 101, or 011, for active-LOW outputs. For example, if A 12 and B 9, then the output vector would be 011 (i.e., A B). An active-LOW output will illuminate a LOW-sense LED, such as those on the Altera UP-1 board. compare4.vhd compare4.scf compare4.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY compare4 IS PORT( a, b : IN agtb, aeqb, altb : OUT END compare4; INTEGER RANGE 0 TO 15; STD_LOGIC); ARCHITECTURE a OF compare4 IS SIGNAL compare : STD_LOGIC_VECTOR (2 downto 0); BEGIN PROCESS (a,b) BEGIN IF a <b THEN compare <= 110; ELSIF a=b THEN compare <= 101; ELSIF a>b THEN compare <= 011; ELSE compare <= 111; END IF; agtb <= compare(2); aeqb <= compare(1); altb <= compare(0); END PROCESS; END a; The beauty of this method is that the number of input bits can be changed by modifying one number: the range of the INTEGER-type input. For example, a 12-bit comparator is identical to the 4-bit comparator in the previous VHDL code, except that the inputs have a range of 0 to 4095 ( 212 1). Using this method, we can program an EPM7128S CPLD 208 C H A P T E R 5 Combinational Logic Functions with a comparator up to 28 bits wide (range of 0 to 268,435,455). If we do, however, there is no room for anything else. EXAMPLE 5.14 Write a VHDL le that uses IF statements to compare two 8-bit numbers A and B. The design should have outputs for AEQB, ALTB, and AGTB. Solution compare8.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; compare8.vhd ENTITY compare8 IS PORT( a, b agtb, aeqb, altb END compare8; : IN : OUT INTEGER RANGE 0 TO 255; STD_LOGIC); ARCHITECTURE a OF compare8 IS SIGNAL compare : STD_LOGIC_VECTOR (2 downto 0); BEGIN PROCESS (a,b) BEGIN IF a<b THEN compare <= 110; ELSIF a=b THEN compare <= 101; ELSIF a>b THEN compare <= 011; ELSE compare <= 111; END IF; agtb <= compare(2); aeqb <= compare(1); altb <= compare(0); END PROCESS; END a; 5.6 Parity Generators and Checkers KEY TERMS Parity A system that checks for errors in a multi-bit binary number by counting the number of 1s. Even parity An error-checking system that requires a binary number to have an even number of 1s. Odd parity An error-checking system that requires a binary number to have an odd number of 1s. Parity bit A bit appended to a binary number to make the number of 1s even or odd, depending on the type of parity. When data are transmitted from one device to another, it is necessary to have a system of checking for errors in transmission. These errors, which appear as incorrect bits, occur as a result of electrical limitations such as line capacitance or induced noise. 5.6 Parity Generators and Checkers 209 FIGURE 5.63 Parity Error Checking Parity error checking is a way of encoding information about the correctness of data before they are transmitted. The data can then be veried at the systems receiving end. Figure 5.63 shows a block diagram of a parity error-checking system. The parity generator in Figure 5.63 examines the outgoing data and adds a bit called the parity bit that makes the number of 1s in the transmitted data odd or even, depending on the type of parity. Data with EVEN parity have an even number of 1s, including the parity bit, and data with ODD parity have an odd number of 1s. The data receiver knows whether to expect EVEN or ODD parity. If the incoming number of 1s matches the expected parity, the parity checker responds by indicating that correct data have been received. Otherwise, the parity checker indicates an error. EXAMPLE 5.16 Data are transmitted from a PC serial port to a modem in groups of 7 data bits plus a parity bit. What should the parity bit, P, be for each of the following data if the parity is EVEN? If the parity is ODD? a. 0110110 b. 1000000 c. 0010101 Solution a. 0110110 b. 1000000 c. 0010101 FIGURE 5.64 Exclusive OR Gate Four 1s in data. (4 is an even number.) EVEN parity: P 0 ODD parity: P 1 One 1 in data. (1 is an odd number.) EVEN parity: P 1 ODD parity: P 0 Three 1s in data. (3 is an odd number.) EVEN parity: P 1 ODD parity: P 0 An Exclusive OR gate can be used as a parity generator or a parity checker. Figure 5.64 shows the gate, and Table 5.12 is the XOR truth table. Notice that each line of the XOR truth table has an even number of 1s if we include the output column. Figure 5.65 shows the block diagram of a circuit that will generate an EVEN parity bit from 2 data bits, A and B, and transmit the three bits one after the other, that is, serially, to a data receiver. 210 C H A P T E R 5 Combinational Logic Functions Table 5.12 Exclusive OR Truth Table A B 0 0 1 1 0 1 0 1 A B 0 1 1 0 FIGURE 5.65 Even Parity Generation FIGURE 5.66 Even Parity Checking Figure 5.66 shows a parity checker for the parity generator in Figure 5.65. Data are received serially, but read in parallel. The parity bit is re-created from the received values of A and B, and then compared to the received value of P to give an error indication, P . If P and A B are the same, then P 0 and the transmission is correct. If P and A B are different, then P 1 and there has been an error in transmission. EXAMPLE 5.17 The following data and parity bits are transmitted four times: ABP 101. 1. State the type of parity used. 2. The transmission line over which the data are transmitted is particularly noisy and the data arrive differently each time as follows: a. ABP 101 b. ABP 100 c. ABP 111 d. ABP 110 Indicate the output P of the parity checker in Figure 5.66 for each case and state what the output means. Solution 1. The system is using EVEN parity. 2. The parity checker produces the following responses: a. ABP 101 A B 10 1 P (A B ) P 1 1 0 Data received correctly. b. ABP 100 AB101 P (A B) P 1 0 1 Transmission error. (Parity bit incorrect.) c. ABP 111 5.6 A B P d. ABP AB P 1 (A 110 1 (A Parity Generators and Checkers 211 10 B) P 0 1 1 Transmission error. (Data bit B incorrect.) 10 B) P 0 0 0 Transmission error undetected. (B and P incorrectly received.) The second and third cases in Example 5.17 show that parity error-detection cannot tell which bit is incorrect. The fourth case points out the major aw of parity error detection: An even number of errors cannot be detected. This is true whether the parity is EVEN or ODD. If a group of bits has an even number of 1s, a single error will change that to an odd number of 1s, but a double error will change it back to even. (Try a few examples to convince yourself this is true.) An ODD parity generator and checker can be made using an Exclusive NOR, rather than an Exclusive OR, gate. If a set of transmitted data bits require a 1 for EVEN parity, it follows that they require a 0 for ODD parity. This implies that EVEN and ODD parity generators must have opposite-sense outputs. EXAMPLE 5.18 Modify the circuits in Figures 5.65 and 5.66 to operate with ODD parity. Verify their operation with the data bits AB 11 transmitted twice and received once as AB 11 and once as AB 01. Solution Figure 5.67a shows an ODD parity generator and Figure 5.67b shows an ODD parity checker. The checker circuit still has an Exclusive OR output since it presents the same error codes as an EVEN parity checker. The parity bit is re-created at the receive end FIGURE 5.67 Example 5.18 ODD Parity Generator and Checker of the transmission path and compared with the received parity bit. If they are the same, P 0 (correct transmission). If they are different, P 1 (transmission error). Verication: Generator: Data: AB 11 Parity: P A B 1 1 1 1 1 0 1 Checker: Received data: AB P (A B) P 11 (1 1) (Correct transmission) 212 C H A P T E R 5 Combinational Logic Functions Generator: Data: AB 11 Parity: P A B 1 1 1 0 1 1 1 Checker: Received data: AB P (A B) P 01 (0 1) (Incorrect transmission) Parity generators and checkers can be expanded to any number of bits by using an XOR gate for each pair of bits and combining the gate outputs in further stages of 2-input XOR gates. The true form of the generated parity bit is PE, the EVEN parity bit. The complement form of the bit is PO, the ODD parity bit. Table 5.13 shows the XOR truth table for 4 data bits and the ODD and EVEN parity bits. The EVEN parity bit PE is given by (A B) (C D). The ODD parity bit Table 5.13 Even and Odd Parity Bits for 4-bit Data A B C D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A B 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C D 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 PE PO 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 PO is given by PE (A B) (C D). For every line in Table 5.13, the bit combination ABCDPE has an even number of 1s and the group ABCDPO has an odd number of 1s. EXAMPLE 5.19 FIGURE 5.68 Example 5.19 4-bit Parity Generator Use Table 5.13 to draw a 4-bit parity generator and a 4-bit parity checker that can generate and check either EVEN or ODD parity, depending on the state of one select input. 5.6 Parity Generators and Checkers 213 Solution Figure 5.68 shows the circuit for a 4-bit parity generator. The XOR gate at the output is congured as a programmable inverter to give PE or PO. When EVEN/ODD 0, the parity output is not inverted and the circuit generates PE. When EVEN/ODD 1, the FIGURE 5.69 Example 5.19 4-bit Parity Checker EXAMPLE 5.20 Draw the circuit for an 8-bit EVEN/ODD parity generator. Solution An 8-bit parity generator is an expanded version of the 4-bit generator in the previous example. The circuit is shown in Figure 5.70. FIGURE 5.70 Example 5.20 8-bit Parity Generator SECTION 5.6 REVIEW PROBLEM 5.6 Data (including a parity bit) are detected at a receiver congured for checking ODD parity. Which of the following data do we know are incorrect? Could there be errors in the remaining data? Explain. a. 010010 b. 011010 c. 1110111 d. 1010111 e. 1000101 214 C H A P T E R 5 Combinational Logic Functions SUMMARY 1. A decoder detects the presence of a particular binary code. The simplest decoder is an AND or NAND gate, which can detect a binary code when combined with the right combination of input inverters. 2. Multiple-output decoders are implemented by a series of single-gate decoders, each of which responds to a different input code. 3. For an n-input decoder, there can be as many as 2n unique outputs. 4. MAX PLUS II can simulate the function of a digital circuit by generating a set of output waveforms in response to a dened set of input waveforms. 5. VHDL constructs such as selected signal assignment statements and conditional signal assignments can describe decoders. Both statement types assign alternative values to a VHDL port or signal, based on the state of another port or signal. 6. A selected signal assignment statement has the form: label: WITH __expression SELECT __signal __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value; 7. A conditional signal assignment statement has the form: __signal __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE __expression; 8. SIGNALs act as internal connections in a VHDL design entity. They can be single lines or vectors and are declared before the BEGIN clause of an ARCHITECTURE body. 9. The report le of a MAX PLUS II project contains design and conguration information, including the Boolean equations that the compiler derives from the design entry le(s) of the project. 10. A seven-segment display is an array of seven luminous segments (usually LED or LCD), arranged in a gure-8 pattern, used to display numerical digits. 11. The segments in a seven-segment display are designated by lowercase letters a through g. The sequence of labels goes clockwise, starting with segment a at the top and ending with g in the center. 12. Seven-segment displays are congured as common anode (active-LOW inputs) or common cathode (active-HIGH segments). 13. A seven-segment decoder can be described with a truth table or Boolean equation for each segment function. Since the segment functions do not simplify very much, it is often easier to program a CPLD with a VHDL truth table, in the form of a selected signal assignment statement, rather than with the Boolean equations of the decoder. 14. A multiplexer (MUX) is a circuit that directs a signal or group of signals (called the data inputs) to an output, based on the status of a set of select inputs. 15. Generally, for n select inputs in a multiplexer, there are m 2n data inputs. Such a multiplexer is referred to as an m-to-1 multiplexer. 16. The selected data input in a MUX is usually denoted by a subscript that is the decimal equivalent of the combined binary value of the select inputs. For example, if the select inputs in an 8-to-1 MUX are set to S2S1S0 100, data input D4 is selected since 100 (binary) 4 (decimal). 17. A MUX can be designed to switch groups of signals to a multi-bit output. The inputs can be denoted by double subscript notation, where the rst subscript indicates the number of the signal group and the second subscript the element in the group. For example, a MUX can have a 4-bit set of inputs called D03D02D01D00 and another 4-bit input group called D13D12D11D10, each of which can be switched to a 4-bit output called Y3Y2Y1Y0 by the state of one select input. 18. A multiplexer can be used in time-dependent applications if a binary counter is applied to its select inputs. 19. Some examples of time-dependent MUX applications are waveform or bit pattern generation and time-division multiplexing (TDM). 20. In time division multiplexing, several digital signals share a single transmission path by allotting a time slot for every signal, during which that signal has sole access to the transmission path. 21. TDM can be congured for bit multiplexing, in which a channel transmits one bit each time it is selected, or byte (or word) multiplexing, in which a channel transmits and entire byte or word each time it is selected. 22. A demultiplexer (DMUX) receives data from a single source and directs the data to one of several outputs, which is selected by the status of a set of select inputs. 23. A decoder with an enable input can also act as a demultiplexer if the enable input of the decoder is used as a data input for a demultiplexer. 24. A TDM signal can be demultiplexed by applying a binary count to the DMUXs select inputs at the same rate as the count is applied to the select input of the multiplexer that originally sent the data. 25. A CMOS analog multiplexer or demultiplexer works by using a decoder to enable a set of analog data transmission switches. It can be used in either direction. 26. A magnitude comparator determines whether two binary numbers are equal and, if not, which one is greater. 27. The simplest equality comparator is an XNOR gate, whose output is HIGH if both inputs are the same. 28. A pair of multiple-bit numbers can be compared by a set of XNOR gates whose outputs are ANDed. The circuit compares the two numbers bit-by-bit. 29. Given two numbers A and B, the Boolean function AnBn, if true, indicates that the nth bit of A is less than the nth bit of B. 30. Given two numbers A and B, the Boolean function AnBn, if true, indicates that the nth bit of A is greater than the nth bit of B. Glossary 31. The less-than and greater-than functions can be combined with an equality comparator to determine, bit-by-bit, how two numbers compare in magnitude to one another. 32. A magnitude comparator can be best implemented in VHDL by using INTEGER types for the inputs and using IF statements to compare their respective magnitudes. 33. Parity checking is a system of error detection that works by counting the number of 1s in a group of bits. 34. Even parity requires a group of bits to have an even number of 1s. Odd parity requires a group of bits to have an odd number of 1s. This is achieved by appending a parity bit to the data whose value depends on the number of 1s in the data bits. 215 35. An XOR gate is the simplest even parity generator. Each line in its truth table has an even number of 1s, if the output column is included. 36. An XNOR gate can be used to generate an odd parity bit from two data bits. 37. A parity checker consists of a parity generator on the receive end of a transmission system and a comparator to determine if the locally generated parity bit is the same as the transmitted parity bit. 38. Parity generators and checkers can be expanded to any number of bits by using an XOR gate for each pair of bits and combining the gate outputs in further stages of 2-input XOR gates. GLOSSARY BCD Binary coded decimal. A code in which each individual digit of a decimal number is represented by a 4-bit binary number. (e.g., 905 (decimal) 1001 0000 0101 (BCD)). subscript numerals. Generally, the rst digit refers to a group of signals and the second to an element of a group. (e.g., X03 represents element 3 of group 0 for a set of signal groups, X.) Bit multiplexing A TDM technique in which one bit is sent from each channel during its assigned time slot. Encoder A circuit that generates a digital code at its outputs in response to one or more active input lines. Byte (or word) multiplexing A TDM technique in which a byte (or word) is sent from each channel during its assigned time slot. (A byte is eight bits; a word is a group of bits whose size varies with the particular system.) Even parity An error-checking system that requires a binary number to have an even number of 1s. CASE statement A VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable. Magnitude comparator A circuit that compares two n-bit binary numbers, indicates whether or not the numbers are equal, and, if not, which one is larger. Clock A signal that controls the operation of a sequential digital circuit, such as a counter, by advancing its outputs to the next state when it receives a pulse. Multiplexer A circuit that directs one of several digital signals to a single output, depending on the states of several select inputs. CMOS analog switch A CMOS device that will pass an analog or digital signal in either direction, when enabled. Also called a transmission gate. There is no TTL equivalent. Odd parity An error-checking system that requires a binary number to have an odd number of 1s. Common anode display A seven-segment LED display where the anodes of all the LEDs are connected to the circuit supply voltage. Each segment is illuminated by a logic LOW at its cathode. Common cathode display A seven-segment display in which the cathodes of all LEDs are connected together and grounded. A logic HIGH illuminates a segment when applied to its anode. Conditional signal assignment statement A concurrent VHDL construct that assigns a value to a signal, depending on a sequence of conditions being true or false. Counter A digital circuit whose output produces a xed sequence of binary states when an input called the clock receives a series of pulses. The output advances by one for each clock pulse (e.g., the output state of a 4-bit binary counter progresses in order from 0000 to 1111, then repeats). Data inputs The multiplexer inputs that feed a digital signal to the output when selected. Decoder A digital circuit designed to detect the presence of a particular digital state. Demultiplexer A circuit that uses a binary decoder to direct a digital signal from a single source to one of several destinations. Double-subscript notation A naming convention where two or more numerically related groups of signals are named using two IF statement A VHDL construct within a process that executes a series of statements, if a Boolean test condition is true. Parity A system that checks for errors in a multi-bit binary number by counting the number of 1s. Parity bit A bit appended to a binary number to make the number of 1s even or odd, depending on the type of parity. Positive edge The point on a digital waveform where the logic level of the waveform makes a LOW-to-HIGH transition. Priority encoder An encoder that generates a binary or BCD output corresponding to the subscript of the active input having the highest priority. This is usually dened as the input with the largest subscript value. PROCESS A VHDL construct that contains statements that are executed if there is a change in a signal in its sensitivity list. Propagation delay Time difference between a change on a digital circuit input and a change on an output in response to the input change. RBI Ripple blanking input. RBO Ripple blanking output. Response waveforms A set of output waveforms generated by a simulator tool for a particular digital design in response to a set of stimulus waveforms. Ripple blanking A technique used in a multiple-digit numerical display that suppresses leading or trailing zeros in the display, but allows internal zeros to be displayed. 216 C H A P T E R 5 Combinational Logic Functions Select inputs The multiplexer inputs which select a digital input channel. Simulation The verication of the logic of a digital design before programming it into a PLD. Selected signal assignment statement A concurrent signal assignment in VHDL in which a value is assigned to a signal, depending on the alternative values of another signal or variable. Stimulus waveforms A set of user-dened input waveforms on a simulator le designed to imitate input conditions of a digital circuit. Sensitivity list A list of signals in a PROCESS statement that are monitored to determine whether the PROCESS should be executed. Time division multiplexing (TDM) A technique of using one transmission line to send many signals simultaneously by making them share the line for equal fractions of time. Seven-segment display An array of seven independently controlled light-emitting diode (LED) or liquid crystal display (LCD) elements, shaped like a gure-8, which can be used to display decimal digits and other characters by turning on the appropriate elements. Time slot A period of time during which a transmitted data element has sole access to a transmission path. Timing diagram A diagram showing how two or more digital waveforms in a system relate to each other over time. PROBLEMS Section 5.1 Decoders 5.1 When a HIGH is on the outputs of each of the decoding circuits shown in Figure 5.71, what is the binary code appearing at the inputs? Write the Boolean expression for each decoder output. D0 D0 D0 D1 D2 D1 D2 D1 D2 D3 D3 D3 FIGURE 5.71 Problem 5.1 Decoding Circuits 5.2 Draw the decoding circuit for each of the following Boolean expressions: a. Y D3 D2 D1 D0 b. Y D3 D2 D1 D0 c. Y 5.4 5.5 D3 D2 D1 D0 A microcomputer system has a RAM capacity of 128 megabytes (MB), split into 16 MB portions. Each RAM device is enabled by a low at a G input. Draw a logic diagram showing how a binary decoder can select one particular RAM device. 5.7 Briey describe the difference between a selected signal assignment statement and a conditional signal assignment statement in VHDL. State which one is the preferred statement in VHDL les and why. D3 D2 D1 D0 e. Y 5.6 D3 D2 D1 D0 d. Y 5.3 Write the equation giving the general relation between n and m. Use a Graphic Design File in MAX PLUS II to draw the logic diagram of a 2-line-to-4-line decoder with activeHIGH outputs and an active-LOW enable input. Create a simulation le to show the operation of the circuit. Use a Graphic Design File in MAX PLUS II to draw the logic diagram of a 3-line-to-8-line decoder with activeHIGH outputs and an active-LOW enable input. Create a simulation le to show the operation of the circuit. For a generalized n-line-to-m-line decoder, state the value of m if n is: a. 5 b. 6 c. 8 5.8a. Write a VHDL le for a 3-line-to-8-line decoder with active-LOW outputs and no enable. Use a selected signal assignment statement. Assign the device as an EPM 7128SLC84. b. Write the Boolean equations for the decoder in part a, as reported in the decoders MAX PLUS II report le. (Use the form (x y z x y z) rather than (!x & !y & !z #x & y & z).) c. Change the decoder in part a so that its outputs are active-HIGH. Compile the design and examine the resulting report le to nd the Boolean equations of the modied design. Write the equations and state Problems 217 how the compiler deals the change in output active level. 5.14 Write a VHDL le for the hexadecimal-to-seven-segment decoder described in Problem 5.12. 5.9 Create a MAX PLUS II simulation le for the decoder in Problem 5.8. 5.15 5.10 Write a VHDL le for a 3-line-to-8-line decoder with active-LOW outputs and an active-LOW enable input. Modify the VHDL le for the hexadecimal-to-sevensegment decoder from Problem 5.14 to add a rippleblanking feature. 5.16 5.11 Create a MAX PLUS II simulation le for the decoder in Problem 5.10. 5.12 Write a truth table for a hexadecimal-to-seven-segment decoder for a common anode display. Use the digit patterns of Figure 5.26 as a model. Draw a diagram consisting of four seven-segment displays, each driven by a BCD-to-seven-segment decoder with ripple blanking. The circuit should be congured to suppress all leading zeros. Show the displayed digits and RBO/RBI logic levels for each of the following displayed values: 100, 217, 1024. 5.13 Use the truth table derived in Problem 5.12 to derive the Boolean equations for each segment driver. Simplify the equations as much as possible, using any convenient method. Section 5.2 Encoders 5.17 Figure 5.72 shows a BCD priority encoder with three different sets of inputs. Determine the resulting output code for each input combination. Inputs and outputs are active HIGH. FIGURE 5.72 Problem 5.17 BCD Priority Encoder 5.18 Derive the Boolean equations for the outputs of a BCD priority encoder, based on the encoding principle stated in Section 5.2. Show all work. 5.19 Create a Graphic Design File in MAX PLUS II for a BCD priority encoder, based on the equations in Problem 5.18. Also generate a simulation for this function. 5.20 Write a VHDL le that implements the function of a BCD priority encoder. Create a simulation le for this function. Write the Boolean equations of the encoder, as shown in the encoders report le. State how the equations from the report le compare to the equations you derived in Problem 5.18. 5.21 Write a VHDL le that implements the function of a 4-bit binary priority encoder. Create a simulation le for this function. Section 5.3 Multiplexers 5.22 Make a table listing which digital audio source in Figure 5.73 is routed to output Y for each combination of the multiplexer select inputs. (CD DAT digital audio tape.) compact disc; 5.23 Draw symbols for an 8-to-1 and a 16-to-1 multiplexer. Write the truth table for each multiplexer, showing which data input is selected for every binary combination of the select inputs. 5.24 Make a Graphic Design File in MAX PLUS II for an 8to-1 multiplexer circuit. Also create a simulation that shows the operation of the device. 5.25 Write the Boolean expression describing an 8-to-1 multiplexer. Evaluate the equation for the case where input D5 is selected. 5.26 Draw the symbol for a quadruple 8-to-1 multiplexer (i.e., a MUX with eight switched groups of 4 bits each). Write the truth table for this device, showing which data inputs are selected for every binary combination of the select inputs. Use double-subscript notation. 218 C H A P T E R 5 Combinational Logic Functions FIGURE 5.73 Problem 5.22 Digital Audio Multiplexer 5.27 Write a VHDL le for the quadruple 8-to-1 multiplexer in Problem 5.26. Create a MAX PLUS II simulation for the design to verify its operation. 5.28 Draw the symbol for an octal 4-to-1 multiplexer (i.e., a MUX with four switched groups of 8 bits each). Write the truth table for this device, showing which data inputs are selected for every binary combination of the select inputs. Use double-subscript notation. 5.34 The data pattern in Problem 5.34b generates a symmetrical 12 kHz waveform. Write the data patterns required to produce a 6 kHz waveform and a 3 kHz waveform at the output of a MUX-based programmable waveform generator. Section 5.4 Demultiplexers 5.35 Make a Graphic Design File in MAX PLUS II for a 1-to-4 demultiplexer circuit with active-LOW outputs and an active-LOW enable input. Create a simulation that shows how this device can be used as a demultiplexer or decoder. 5.29 Write a VHDL le for the octal 4-to-1 multiplexer in the Problem 5.28. Create a MAX PLUS II simulation for the design to verify its operation. Write its Boolean equations from the project report le. 5.36 5.30 Write a VHDL le for an 8-to-1 multiplexer using a concurrent signal assignment statement to encode the multiplexers Boolean equation directly. Would this be a good method for encoding a larger device, such as a 16-to-1 multiplexer? Explain your answer. Make a Graphic Design File in MAX PLUS II for a 1-to-8 demultiplexer circuit with active-HIGH outputs. Create a simulation that shows the operation of the device. 5.37 Write a VHDL le that implements the function of a 1-to16 demultiplexer. Write a VHDL le for an 8-to-1 multiplexer using a selected signal assignment statement. Would this be a good method for encoding a larger device, such as a 16-to-1 multiplexer? Explain your answer. 5.38 Briey state what characteristics of an analog switch make it suitable for transmitting analog signals. 5.39 Draw a diagram showing how eight analog switches can be connected to a decoder to form an 8-channel MUX/DMUX circuit. Briey explain why the same circuit can be used as a multiplexer or as a demultiplexer. 5.40 Draw a circuit showing how a 74HC4052 dual 4-channel analog MUX/DMUX can be used to multiplex four transmitted digital audio channels onto a phone line and demultiplex four received audio channels from another phone line. 5.31 5.32 Write a VHDL le for a 16-to-1 multiplexer using the method you believe to be most efcient. 5.33 Draw the circuit of a programmable waveform generator based on an 8-to-1 multiplexer. Draw a timing diagram of this circuit for the following input data: a. D7 D6 D5 D4 D3 D2 D1 D0 01100101 b. D7 D6 D5 D4 D3 D2 D1 D0 01010101 Answers to Section Review Problems Section 5.5 Magnitude Comparators 5.49 5.41 Briey explain the operation of the ALTB portion of the 2-bit magnitude comparator shown in Figure 5.58. 5.42 Draw the ALTB portion of a 4-bit magnitude comparator as a Graphic Design File in MAX PLUS II. Create a simulation for the circuit and briey explain its operation. 5.43 Use MAX PLUS II to create a 3-bit magnitude comparator that has outputs for AEQB, AGTB, and ALTB functions. Create a simulation that shows the operation of this circuit. 5.44 Write a VHDL le that implements the functions A A B and A B for two 16-bit numbers. a. ABCDEFGHP 5.46 c. ABCDP 5.47 5.48 What parity bit, P, should be added to the following data if the parity is EVEN? If the parity is ODD? a. 1111100 101011 111011 The data ABCDEFGHP 110001100 are transmitted in a serial communication system. Give the output P of a receiver parity checker for the following received data. State the meaning of the output P for each case. a. ABCDEFGHP 110101100 b. ABCDEFGHP 110001101 c. ABCDEFGHP 110001100 d. ABCDEFGHP 110010100 5.51 Use MAX PLUS II to create a Graphic Design File for a 5-bit parity generator with a switchable EVEN/ODD output. Create a simulation le to show the operation of the device. 5.52 Use MAX PLUS II to create a Graphic Design File for a 5-bit parity checker corresponding to the parity generator in Problem 5.51. Create a simulation le to show the operation of the device. Create a simulation that veries the operation of the sixfunction comparator in Problem 5.46. Section 5.6 Parity Generators and Checkers 01101 e. ABCDEP B, Write a VHDL le that implements the following six comparison functions in a single device for two 4-bit inputs A and B: A B, A B, A B, A B, A B, and A B. Make the outputs indicate active-LOW. 010000101 011000101 d. ABCDEP Write the Boolean expressions for the AEQB, ALTB, and AGTB outputs of a 6-bit magnitude comparator. 5.45 The following data are transmitted in a serial communication system (P is the parity bit). What parity is being used in each case? b. ABCDEFGHP 5.50 219 b. 1010110 c. 0001101 ANSWERS TO SECTION REVIEW PROBLEMS Section 5.1a Section 5.2 5.1 The decoders are shown in Figure 5.74. 5.4 The encoder in Figure 5.29 can have only one input active at any time. If more than one input is active, it may generate incorrect output codes. The circuit can be modied according to the priority encoding principle, as expressed by the Boolean equations for the 3-bit priority encoder, to ensure that a lowpriority input is not able to modify the code generated by a higher-priority input. D3 D2 Y D1 D0 Section 5.3 D1 5.5 A multiplexer application is time-dependent if its channels are selected in a repeating sequence. This can be accomplished by connecting a binary counter to the select inputs of the multiplexer. D0 Section 5.6 D3 D2 Y FIGURE 5.74 Decoders Section 5.1b 5.2 A decoder with 16 outputs requires 4 inputs. A decoder with 32 outputs requires 5 inputs. Section 5.1c 5.3 Trailing zeros could logically be suppressed after a decimal point or if there are digits displaying a power-of-ten exponent (e.g., 455. or 4.55 02), that is, if the zeros are nonsignicant. The zeros should be displayed if they set the location of the decimal point (e.g., 450). 5.6 Parts a and c are certainly incorrect because each has an even number of 1s. Items b, d, and e could have an even number of errors, which is undetectable by parity checking. CHAPTER 6 Digital Arithmetic and Arithmetic Circuits OUTLINE CHAPTER OBJECTIVES 6.1 6.2 Upon successful completion of this chapter, you will be able to: Add or subtract two unsigned binary numbers. Write a signed binary number in true-magnitude, 1s complement, or 2s complement form. Add or subtract two signed binary numbers. Explain the concept of overow. Calculate the maximum sum or difference of two signed binary numbers that will not result in an overow. Add or subtract two hexadecimal numbers. Write decimal numbers in BCD codes, such as 8421 (Natural BCD) and Excess-3 code. Construct a Gray code sequence. Use the ASCII table to convert alphanumeric characters to hexadecimal or binary numbers and vice versa. Derive the logic gate circuits for full and half adders, given their truth tables. Demonstrate the use of full and half adder circuits in arithmetic and other applications. Add and subtract n-bit binary numbers, using parallel binary adders and logic gates. Explain the difference between ripple carry and parallel carry. Design a circuit to detect sign-bit overow in a parallel adder. Draw circuits to perform BCD arithmetic and explain their operation. Use VHDL to program CPLD devices to perform various arithmetic functions, such as parallel adders, overow detectors, and 1s complementers. 6.3 6.4 6.5 6.6 6.7 6.8 Digital Arithmetic Representing Signed Binary Numbers Signed Binary Arithmetic Hexadecimal Arithmetic Numeric and Alphanumeric Codes Binary Adders and Subtractors BCD Adders Carry Generation in MAX PLUS II T here are two ways of performing binary arithmetic: with unsigned binary numbers or with signed binary numbers. Signed binary numbers incorporate a bit dening the sign of a number; unsigned binary numbers do not. Several ways of writing signed binary numbers are true-magnitude form, which maintains the magnitude of the number in binary value, and 1s complement and 2s complement forms, which modify the magnitude but are more suited to digital circuitry. 221 222 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits Hexadecimal arithmetic is used for calculations that would be awkward in binary due to the large number of bits involved. Important applications of hexadecimal arithmetic are found in microcomputer systems. In addition to positional number systems, binary numbers can be used in a variety of nonpositional number codes, which can represent numbers, letters, and computer control codes. Binary coded decimal (BCD) codes represent decimal digits as individually encoded groups of bits. Gray code is a binary code used in special applications. American Standard Code for Information Interchange (ASCII) represents alphanumeric and control code characters in a 7- or 8-bit format. There are a number of different digital circuits for performing digital arithmetic, most of which are based on the parallel binary adder, which in turn is based on the full adder and half adder circuits. The half adder adds two bits and produces a sum and a carry. The full adder also allows for an input carry from a previous adder stage. Parallel adders have many full adders in cascade, with carry bits connected between the stages. Specialized adder circuits are used for adding and subtracting binary numbers, generating logic functions, and adding numbers in binary-coded decimal (BCD) form. I 6.1 Digital Arithmetic KEY TERMS Signed binary number A binary number of xed length whose sign is represented by one bit, usually the most signicant bit, and whose magnitude is represented by the remaining bits. Unsigned binary number A binary number whose sign is not specied by a sign bit. A positive sign is assumed unless explicitly stated otherwise. Digital arithmetic usually means binary arithmetic, or perhaps BCD arithmetic. Binary arithmetic can be performed using signed binary numbers, in which the MSB of each number indicates a positive or negative sign, or unsigned binary numbers, in which the sign is presumed to be positive. The usual arithmetic operations of addition and subtraction can be performed using signed or unsigned binary numbers. Signed binary arithmetic is often used in digital circuits for two reasons: 1. Calculations involving real-world quantities require us to use both positive and negative numbers. 2. It is easier to build circuits to perform some arithmetic operations, such as subtraction, with certain types of signed numbers than with unsigned numbers. Unsigned Binary Arithmetic KEY TERMS Operand A number upon which an arithmetic function operates (e.g., in the expression x y z, x and y are the operands). Augend The number in an addition operation to which another number is added. Addend The number in an addition operation that is added to another. Sum The result of an addition operation. Carry A digit that is carried over to the next most signicant position when the sum of two single digits is too large to be expressed as a single digit. 6.1 Digital Arithmetic 223 Sum bit (single-bit addition) The least signicant bit of the sum of two 1-bit binary numbers. Carry bit A bit that holds the value of a carry (0 or 1) resulting from the sum of two binary numbers. Addition When we add two numbers, they combine to yield a result called the sum. If the sum is larger than can be contained in one digit, the operation generates a second digit, called the carry. The two numbers being added are called the augend and the addend, or more generally, the operands. For example, in the decimal addition 9 6 15, 9 is the augend, 6 is the addend, and 15 is the sum. Since the sum cannot t into a single digit, a carry is generated into a second digit place. Four binary sums give us all of the possibilities for adding two n-bit binary numbers: 0 1 1 1 0 0 1 00 01 10 1 1 11 (110 (110 110 110 110 210) 310) Each of these results consists of a sum bit and a carry bit. For the rst two results above, the carry bit is 0. The nal sum in the table is the result of adding a carry bit from a sum in a less signicant position. When we add two 1-bit binary numbers in a logic circuit, the result always consists of a sum bit and a carry bit, even when the carry is 0, since each bit corresponds to a measurable voltage at a specic circuit location. Just because the value of the carry is 0 does not mean it has ceased to exist. EXAMPLE 6.1 Calculate the sum 10010 1010. SOLUTION (Carry from sum of 2nd LSBs) 1 10010 1010 11100 EXAMPLE 6.2 Calculate the sum 10111 10010. SOLUTION (Carry bits) 1 11 10111 10010 101001 SECTION 6.1A REVIEW PROBLEMS 6.1 Add 11111 6.2 Add 10011 1001. 1101. 224 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits Subtraction KEY TERMS Difference The result of a subtraction operation. Minuend The number in a subtraction operation from which another number is subtracted. Subtrahend The number in a subtraction operation that is subtracted from another number. Borrow A digit brought back from a more signicant position when the subtrahend digit is larger than the minuend digit. In unsigned binary subtraction, two operands, called the subtrahend and the minuend, are subtracted to yield a result called the difference. In the operation x a b, x is the difference, a is the minuend, and b is the subtrahend. To remember which comes rst, think of the minuend as the number that is diminished (i.e., something is taken away from it). Unsigned binary subtraction is based on the following four operations: 0 1 1 10 0 0 1 1 0 1 0 1 (210 110 110) The last operation shows how to obtain a positive result when subtracting a 1 from a 0: borrow 1 from the next most signicant bit. Borrowing Rules: 1. If you are borrowing from a position that contains a 1, leave behind a 0 in the borrowedfrom position. 2. If you are borrowing from a position that already contains a 0, you must borrow from a more signicant digit that contains a 1. All 0s up to that point become 1s, and the last borrowed-from digit becomes a 0. EXAMPLE 6.3 Subtract 1110 1001. SOLUTION (New 2nd LSB) (Bit borrowed from 2nd LSB) 01 1110 1001 0101 EXAMPLE 6.4 Subtract 10000 101. SOLUTION 10000 (original 101 problem) 1111 10000 (After borrowing 101 from higher-order bits) 1011 6.2 Representing Signed Binary Numbers 225 SECTION 6.1B REVIEW PROBLEMS 6.3 Subtract 10101 6.4 Subtract 10000 10010. 1111. 6.2 Representing Signed Binary Numbers KEY TERMS Sign bit A bit, usually the MSB, that indicates whether a signed binary number is positive or negative. Magnitude bits The bits of a signed binary number that tell us how large the number is (i.e., its magnitude). True-magnitude form A form of signed binary number whose magnitude is represented in true binary. 1s complement A form of signed binary notation in which negative numbers are created by complementing all bits of a number, including the sign bit. 2s complement A form of signed binary notation in which negative numbers are created by adding 1 to the 1s complement form of the number. NOTE Positive numbers are the same in all three notations. Binary arithmetic operations are performed by digital circuits that are designed for a xed number of bits, since each bit has a physical location within a circuit. It is useful to have a way of representing binary numbers within this framework that accounts not only for the magnitude of the number, but for the sign as well. This can be accomplished by designating one bit of a binary number, usually the most signicant bit, as the sign bit and the rest as magnitude bits. When the number is negative, the sign bit is 1, and when the number is positive, the sign bit is 0. There are several ways of writing the magnitude bits, each having its particular advantages. True-magnitude form represents the magnitude in straight binary form, which is relatively easy for a human operator to read. Complement forms, such as 1s complement and 2s complement, modify the magnitude so that it is more suited to digital circuitry. True-Magnitude Form In true-magnitude form, the magnitude of a number is translated into its true binary value. The sign is represented by the MSB, 0 for positive and 1 for negative. EXAMPLE 6.5 Write the following numbers in 6-bit true-magnitude form: a. 2510 b. 2510 c. 1210 d. 1210 SOLUTION Translate the magnitudes of each number into 5-bit binary, padding with leading zeros as required, and set the sign bit to 0 for a positive number and 1 for a negative number. a. 011001 b. 111001 c. 001100 d. 101100 226 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits 1s Complement Form True-magnitude and 1s complement forms of binary numbers are the same for positive numbersthe magnitude is represented by the true binary value and the sign bit is 0. We can generate a negative number in one of two ways: 1. Write the positive number of the same magnitude as the desired negative number. Complement each bit, including the sign bit; or 2. Subtract the n-bit positive number from a binary number consisting of n 1s. EXAMPLE 6.6 Convert the following numbers to 8-bit 1s complement form: a. 5710 b. 5710 c. 7210 d. 7210 SOLUTION Positive numbers are the same as numbers in true-magnitude form. Negative numbers are the bitwise complements of the corresponding positive number. a. b. c. d. 5710 5710 7210 7210 00111001 11000110 01001000 10110111 We can also generate an 8-bit 1s complement negative number by subtracting its positive magnitude from 11111111 (eight 1s). For example, for part b: 11111111 00111001 ( 5710) 11000110 ( 5710) 2s Complement Form Positive numbers in 2s complement form are the same as in true-magnitude and 1s complement forms. We create a negative number by adding 1 to the 1s complement form of the number. EXAMPLE 6.7 Convert the following numbers to 8-bit 2s complement form: a. 5710 b. 5710 c. 7210 d. 7210 SOLUTION a. b. c. d. 57 57 72 72 00111001 11000110 1 11000111 01001000 10110111 1 10111000 (1s complement) (2s complement) (1s complement) (2s complement) A negative number in 2s complement form can be made positive by 2s complementing it again. Try it with the negative numbers in Example 6.7. 6.3 Signed Binary Arithmetic 227 6.3 Signed Binary Arithmetic KEY TERM Signed binary arithmetic Arithmetic operations performed using signed binary numbers. Signed Addition Signed addition is done in the same way as unsigned addition. The only difference is that both operands must have the same number of magnitude bits, and each has a sign bit. EXAMPLE 6.8 Add 3010 and 7510. Write the operands and the sum as 8-bit signed binary numbers. SOLUTION 30 75 105 00011110 01001011 01101001 (Magnitude bits) (Sign bit) Subtraction The real advantage of complement notation becomes evident when we subtract signed binary numbers. In complement notation, we add a negative number instead of subtracting a positive number. We thus have only one kind of operationadditionand can use the same circuitry for both addition and subtraction. This idea does not work for true-magnitude numbers. In the complement forms, the magnitude bits change depending on the sign of the number. In true-magnitude form, the magnitude bits are the same regardless of the sign of the number. Let us subtract 8010 6510 1510 using 1s complement and 2s complement addition. We will also show that the method of adding a negative number to perform subtraction is not valid for true-magnitude signed numbers. 1s Complement Method KEY TERM End-around carry An operation in 1s complement subtraction where the carry bit resulting from a sum of two 1s complement numbers is added to that sum. Add the 1s complement values of 80 and 65. If the sum results in a carry beyond the sign bit, perform an end-around carry. That is, add the carry to the sum. 8010 6510 6510 01010000 01000001 10111110 (1s complement) 80 01010000 65 10111110 1 00001110 1 15 00001111 (End-around carry) 228 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits 2s Complement Method Add the 2s complement values of 80 and bit, discard it. 8010 01010000 6510 6510 01000001 10111110 1 10111111 65. If the sum results in a carry beyond the sign (1s complement) (2s complement) 80 01010000 65 10111111 15 1 00001111 (Discard carry) True-Magnitude Method 8010 01010000 6510 6510 01000001 11000001 80 65 ? 01010000 11000001 1 00010001 If we perform an end-around carry, the result is 00010010 1810. If we discard the carry, the result is 00010001 1710. Neither answer is correct. Thus, adding a negative true-magnitude number is not equivalent to subtraction. Negative Sum or Difference All examples to this point have given positive-valued results. When a 2s complement addition or subtraction yields a negative sum or difference, we cant just read the magnitude from the result, since a 2s complement operation modies the bits of a negative number. We must calculate the 2s complement of the sum or difference, which will give us the positive number that has the same magnitude. That is, ( x) x. EXAMPLE 6.9 Subtract 6510 8010 in 2s complement form. SOLUTION 6510 01000001 8010 8010 01010000 10101111 1 10110000 65 80 (1s complement) (2s complement) 01000001 10110000 11110001 Take the 2s complement of the difference to nd the positive number with the same magnitude. 11110001 00001110 1 00001111 ( 15) (1s complement) (2s complement) ( 15) 6.3 Signed Binary Arithmetic 229 00001111 1510. We generated this number by complementing 11110001. Thus, 11110001 1510. Range of Signed Numbers Table 6.1 4-bit 2s Complement Numbers Decimal 2s Complement 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 EXAMPLE 6.10 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 The largest positive number in 2s complement notation is a 0 followed by n 1s for a number with n magnitude bits. For instance, the largest positive 4-bit number is 0111 710. The negative number with the largest magnitude is not the 2s complement of the largest positive number. We can nd the largest negative number by extension of a sequence of 2s complement numbers. The 2s complement form of 710 is 1000 1 1001. The positive and negative numbers with the next largest magnitudes are 0110 ( 610) and 1010 ( 610). If we continue this process, we will get the list of numbers in Table 6.1. We have generated the 4-bit negative numbers from 110 (1111) through 710 (1001) by writing the 2s complement forms of the positive numbers 1 through 7. Notice that these numbers count down in binary sequence. The next 4-bit number in the sequence (which is the only binary number we have left) is 1000. By extension, 1000 810. This number is its own 2s complement. (Try it.) It exemplies a general rule for the n-bit negative number with the largest magnitude. NOTE A 2s complement number consisting of a 1 followed by n 0s is equal to 2n. Therefore, the range of a signed number, x, is 2n x 2n 1 for a number with n magnitude bits. Write the largest positive and negative numbers for an 8-bit signed number in decimal and 2s complement notation. SOLUTION 01111111 10000000 EXAMPLE 6.11 Write 127 128 (7 magnitude bits: 27 1 127) (1 followed by seven 0s: 27 128) 1610 a. As an 8-bit 2s complement number b. As a 5-bit 2s complement number (8-bit numbers are more common than 5-bit numbers in digital systems, but it is useful to see how we must write the same number differently with different numbers of bits.) SOLUTION a. An 8-bit number has 7 magnitude bits and 1 sign bit. 16 00010000 16 11101111 1 11110000 (1s complement) (2s complement) b. A 5-bit number has 4 magnitude bits and 1 sign bit. Four magnitude bits are not enough to represent 16. However, a 1 followed by n 0s is equal to 2n. For a 1 and four 0s, 2n 24 16. Thus, 10000 1610. 230 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits The last ve bits of the binary equivalent of numbers. 16 are the same in both the 5-bit and 8-bit NOTE The 8-bit number is padded with leading 1s. This same general pattern applies for any negative number with a power-of-2 magnitude. ( 2n n 0s preceded by all 1s within the dened number size.) SECTION 6.3 REVIEW PROBLEM 6.5 Write 6.6 Write 32 as an 8-bit 2s complement number. 32 as a 6-bit 2s complement number. Sign Bit Overow KEY TERM Overow An erroneous carry into the sign bit of a signed binary number that results from a sum or difference larger than can be represented by the number of magnitude bits. Signed addition of positive numbers is performed in the same way as unsigned addition. The only problem occurs when the number of bits in the sum of two numbers exceeds the number of magnitude bits and overows into the sign bit. This causes the number to appear to be negative when it is not. For example, the sum 75 96 171 causes an overow in 8-bit signed addition. In unsigned addition the binary equivalent is: 1001011 1100000 10101011 In signed addition, the sum is the same, but has a different meaning. 0 1001011 0 1100000 1 0101011 (Sign bit) (Magnitude bits) The sign bit is 1, indicating a negative number, which cannot be true, since the sum of two positive numbers is always positive. NOTE A sum of positive signed binary numbers must not exceed 2n 1 for numbers having n magnitude bits. Otherwise, there will be an overow into the sign bit. Overow in Negative Sums Overow can also occur with large negative numbers. For example, the addition of and 6510 should produce the result: 8010 ( 6510) 14510 8010 6.3 Signed Binary Arithmetic 231 In 2s complement notation, we get: 8010 8010 6510 6510 80 ( 65)8 ? 01010000 10101111 1 10110000 01000001 10111110 1 10111111 (1s complement) (2s complement) (1s complement) (2s complement) 10110000 10111111 1 01101111 (Incorrect magnitude 11110) (Erroneous sign bit 0) (Discard carry) This result shows a positive sum of two negative numbersclearly incorrect. We can extend the statement we made earlier about permissible magnitudes of sums to include negative as well as positive numbers. NOTE A sum of signed binary numbers must be within the range of 2n sum 2n 1 for numbers having n magnitude bits. Otherwise, there will be an overow into the sign bit. For an 8-bit signed number in 2s complement form, the permissible range of sums is 10000000 sum 01111111. In decimal, this range is 128 sum 127. NOTE A sum of two positive numbers is always positive. A sum of two negative numbers is always negative. Any 2s complement addition or subtraction operation that appears to contradict these rules has produced an overow into the sign bit. EXAMPLE 6.12 Which of the following sums will produce a sign bit overow in 8-bit 2s complement notation? How can you tell? a. 6710 3310 b. 6710 6310 c. 9610 2210 d. 9610 4210 SOLUTION A sign bit overow is generated if the sum of two positive numbers appears to produce a negative result or the sum of two negative numbers appears to produce a positive result. In other words, overow occurs if the operand sign bits are both 1 and the sum sign bit is 0 or vice versa. We know this will happen if an 8-bit sum is outside the range ( 128 sum 127). a. 6710 3310 10010 01000011 00100001 01100100 (no overow; sum of positive numbers is positive.) 232 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits b. 6710 6310 13010 01000011 00111111 10000010 c. 96 96 01100000 10011111 1 10100000 22 22 96 22 118 00010110 11101001 1 11101010 (Overow; sum of positive numbers is negative. Sum 127; out of range.) (1s complement) (2s complement) (1s complement) (2s complement) 10100000 11101010 1 10001010 (Magnitude bits) (Sign bit) (Discard carry) (No overow; sum of two negative numbers is negative.) d. 96 96 42 42 96 42 138 01100000 10011111 1 10100000 00101010 11010101 1 11010110 (1s complement) (2s complement) (1s complement) (2s complement) 10100000 11010110 1 01110110 (Magnitude bits) (Sign bit) (Discard carry) (Overow; sum of two negative numbers is positive. Sum 128; out of range.) NOTE The carry bit generated in 1s and 2s complement operations is not the same as an overow bit. (See Example 6.12, parts c and d.) An overow is a change in the sign bit, which leads us to believe that the number is opposite in sign from its true value. A carry is the result of an operation carrying beyond the physical limits of an n-bit number. It is similar to the idea of an odometer rolling over from 999999.9 to 1 000000.0. There are not enough places to hold the new number, so it goes back to the beginning and starts over. 6.4 Hexadecimal Arithmetic (This section may be omitted without loss of continuity.) The main reason to be familiar with addition and subtraction in the hexadecimal system is that it is useful for calculations related to microcomputer and memory systems. 6.4 Hexadecimal Arithmetic 233 Microcomputer systems often use binary numbers of 8, 16, 20, or 32 bits. Rather than write out all these bits, we use hex numbers as shorthand. Binary numbers having 8, 16, 20, or 32 bits can be represented by 2, 4, 5, or 8 hex digits, respectively. Hex Addition Hex addition is very much like decimal addition, except that we must remember how to deal with the hex digits A to F. A few sums are helpful: F F F F 1 F 1 10 1E 1F The positional multipliers for the hexadecimal system are powers of 16. Thus, the most signicant bit of the rst sum is the 16s column. The equivalent sum in decimal is: 1510 110 1610 10H The second sum is the largest possible sum of two hex digits; the carry to the next position is 1. This shows that the sum of two hex digits will never produce a carry larger than 1. The second sum can be calculated as follows: FH FH 1510 1510 3010 1610 10H 1EH 1410 EH The third sum shows that if there is a carry from a previous sum, the carry to the next bit will still be 1. NOTE It is useful to think of any digits larger than 9 as their decimal equivalents. For any digit greater than 1510 (FH), subtract 1610, convert the difference to its hex equivalent, and carry 1 to the next digit position. EXAMPLE 6.13 Add 6B3H A9CH. SOLUTION Hex 6B3 A9C Decimal Equivalents ( 6) (11) ( 3) (10) ( 9) (12) (16) (20) (15) For sums greater than 15, subtract 16 and carry 1 to the next position: (Carry) Sum: 6B3H A9CH Hex 11 6B3 A9C 114F 114FH. Decimal Equivalents ( 1) ( 1) ( 6) (11) ( 3) (10) ( 9) (12) ( 1) ( 1) ( 4) (15) 234 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits Hex Subtraction There are two ways to subtract hex numbers. The rst reverses the addition process in the previous section. The second is a complement form of subtraction. EXAMPLE 6.14 Subtract 6B3H 49CH. SOLUTION Hex 6B3 49C Decimal Equivalent (6) (11) ( 3) (4) ( 9) (12) To subtract the least signicant digits, we must borrow 10H (1610) from the previous position. This leaves the subtraction looking like this: Hex (Borrow) Decimal Equivalent 1 6A3 49C 217 (6) (10) (16 3) (4) ( 9) (12) (2) ( 1) ( 7) The second subtraction method is a complement method, where, as in 2s complement subtractions, we add a negative number to subtract a positive number. Calculate the 15s complement of a hex number by subtracting it from a number having the same number of digits, all Fs. Calculate the 16s complement by adding 1 to this number. This is the negated value of the number. EXAMPLE 6.15 Negate the hex number 15AC by calculating its 16s complement. SOLUTION FFFF 15AC EA53 1 EA54 (15s complement) (16s complement) The original value, 15AC, can be restored by calculating the 16s complement of EA54. Try it. EXAMPLE 6.16 Subtract 8B63 55D7 using the complement method. SOLUTION Find the 16s complement of 55D7. FFFF 55D7 AA28 1 AA29 (15s complement) (16s complement) 6.5 Therefore, 55D7 Numeric and Alphanumeric Codes 235 AA29. 1 8B63 AA29 1 358C (Discard carry) Difference: 8B63 55D7 358C. SECTION 6.4 REVIEW PROBLEM 6.7 Perform the following hexadecimal calculations: a. A25F 74A2 b. 7380 5FFF 6.5 Numeric and Alphanumeric Codes BCD Codes KEY TERM Binary-coded decimal (BCD). A code that represents each digit of a decimal number by a binary value. BCD stands for binary-coded decimal. As the name implies, BCD is a system of writing decimal numbers with binary digits. There is more than one way to do this, as BCD is a code, not a positional number system. That is, the various positions of the bits do not necessarily represent increasing powers of a specied number base. Two commonly used BCD codes are 8421 code, where the bits for each decimal digit are weighted, and Excess-3 code, where each decimal digit is represented by a binary number that is 3 larger than the true binary value of the digit. Table 6.2 Decimal Digits and Their 8421 BCD Equivalents Decimal Digit BCD (8421) 0 1 2 3 4 5 6 7 8 9 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 EXAMPLE 6.17 8421 Code KEY TERM 8421 code A BCD code that represents each digit of a decimal number by its 4bittrue binary value. The most straightforward BCD code is the 8421 code, also called Natural BCD. Each decimal digit is represented by its 4-bit true binary value. When we talk about BCD code, this is usually what we mean. This code is called 8421 because these are the positional weights of each digit. Table 6.2 shows the decimal digits and their BCD equivalents. 8421 BCD is not a positional number system, because each decimal digit is encoded separately as a 4-bit number. Write 498710 in both binary and 8421 BCD. SOLUTION The binary value of 498710 can be calculated by repeated division by 2: 498710 1 0011 0111 10112 236 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits The BCD digits are the binary values of each decimal digit, encoded separately. We can break bits into groups of 4 for easier reading. Note that the rst and last BCD digits each have a leading zero to make them 4 bits long. 498710 0100 1001 1000 0111BCD Excess-3 Code KEY TERMS Table 6.3 Decimal Digits and Their 8421 and Excess-3 Equivalents Decimal Digit 8421 Excess-3 0 1 2 3 4 5 6 7 8 9 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Excess-3 Code A BCD code that represents each digit of a decimal number by a binary number derived by adding 3 to its 4-bit true binary value. 9s complement A way of writing decimal numbers where a number is made negative by subtracting each of its digits from 9 (e.g., 726 999 726 273 in 9s complement). Self-complementing A code that automatically generates a negative equivalent (e.g., 9s complement for a decimal code) when all its bits are inverted. Excess-3 code is a type of BCD code that is generated by adding 112 (310) to the 8421 BCD codes. Table 6.3 shows the Excess-3 codes and their 8421 and decimal equivalents. The advantage of this code is that it is self-complementing. If the bits of the Excess-3 digit are inverted, they yield the 9s complement of the decimal equivalent. We can generate the 9s complement of an n-digit number by subtracting it from a number made up of n 9s. Thus, the 9s complement of 632 is 999 632 367. The Excess-3 equivalent of 632 is 1001 0110 0101. If we invert all the bits, we get 0110 1001 1010. The decimal equivalent of this Excess-3 number is 367, the 9s complement of 632. This property is useful for performing decimal arithmetic digitally. Gray Code KEY TERM Table 6.4 4-Bit Gray Code Decimal True Binary Gray Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 Gray code A binary code that progresses such that only one bit changes between two successive codes. Table 6.4 shows a 4-bit Gray code compared to decimal and binary values. Any two adjacent Gray codes differ by exactly one bit. Gray code can be extended indenitely if you understand the relationship between the binary and Gray digits. Let us name the binary digits b3b2b1b0, with b3 as the most signicant bit, and the Gray code digits g3g2g1g0 for a 4-bit code. For a 4-bit code: g3 g2 g1 g0 b3 b3 b2 b1 b2 b1 b0 For an n-bit code, the MSBs are the same in Gray and binary (gn bn). The other Gray digits are generated by the Exclusive OR function of the binary digits in the same position and the next most signicant position. 6.5 Numeric and Alphanumeric Codes 237 Another way to generate a Gray code sequence is to recognize the inherent symmetry in the code. For example, a 2-bit Gray code sequence is given by: 00 01 11 10 To generate a 3-bit Gray code, write the 2-bit sequence, then write it again in reverse order. 00 01 11 10 10 11 01 00 Add an MSB of 0 to the rst four codes and an MSB of 1 to the last four codes. The sequence followed by the last two bits of all codes is symmetrical about the center of the sequence. 000 001 011 010 110 111 101 100 We can apply a similar process to generate a 4-bit Gray code. Write the 3-bit sequence, then again in reverse order. Add an MSB of 0 to the rst half of the table and an MSB of 1 to the second half. This procedure yields the code in Table 6.4. ASCII Code KEY TERMS Alphanumeric code A code used to represent letters of the alphabet and numerical characters. ASCII American Standard Code for Information Interchange. A 7-bit code for representing alphanumeric and control characters. Case shift Changing letters from capitals (uppercase) to small letters (lowercase) or vice versa. Digital systems and computers could operate perfectly well using only binary numbers. However, if there is any need for a human operator to understand the input and output data of a digital system, it is necessary to have a system of communication that is understandable to both a human operator and the digital circuit. A code that represents letters (alphabetic characters) and numbers (numeric characters) as binary numbers is called an alphanumeric code. The most commonly used alphanumeric code is ASCII (askey), which stands for American Standard Code for Information Interchange. ASCII code represents letters, numbers, and other typewriter characters in 7 bits. In addition, ASCII has a repertoire of control characters, codes that 238 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits are used to send control instructions to and from devices such as video display terminals, printers, and modems. Table 6.5 shows the ASCII code in both binary and hexadecimal forms. The code for any character consists of the bits in the column heading, then those in the row heading. For example, the ASCII code for A is 10000012 or 41H. The code for a is 11000012 or 61H. The codes for capital (uppercase) and lower case letters differ only by the second most signicant bit, for all letters. Thus, we can make an alphabetic case shift, like using the Shift key on a typewriter or computer keyboard, by switching just one bit. Numeric characters are listed in column 3, with the least signicant digit of the ASCII code being the same as the represented number value. For example, the numeric character 0 is equivalent to 30H in ASCII. The character 9 is represented as 39H. The codes in columns 0 and 1 are control characters. They cannot be displayed on any kind of output device, such as a printer or video monitor, although they may be used to control the device. For instance, if the codes 0AH (Line Feed) and ODH (Carriage Return) Table 6.5 ASCII Code MSBs 000 (0) 001 (1) 010 (2) 011 (3) 100 (4) 101 (5) 110 (6) 111 (7) NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US SP ! # $ % & ( ) * 0 1 2 3 4 5 6 7 8 9 : ; @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ a b c d e f g h i j k l m n o p q r s t u v w x y z { | } LSBs 0000 (0) 0001 (1) 0010 (2) 0011 (3) 0100 (4) 0101 (5) 0110 (6) 0111 (7) 1000 (8) 1001 (9) 1010 (A) 1011 (B) 1100 (C) 1101 (D) 1110 (E) 1111 (F) Control Characters: NULNUll SOHStart of Header STXStart Text ETXEnd Text EOTEnd of Transmission ENQEnquiry ACKAcknowledge BELBell BSBackspace HTHorizontal Tabulation LFLine Feed VTVertical Tabulation FFForm Feed CRCarriage Return SOShift Out SIShift In SPSpace , . / = ? DEL DLEData Link Escape DC1Device Control 1 DC2Device Control 2 DC3Device Control 3 DC4Device Control 4 NAKNo Acknowledgment SYNSynchronous Idle ETBEnd of Transmission Block CANCancel EMEnd of Medium SUBSubstitute ESCEscape FSForm Separator GSGroup Separator RSRecord Separator USUnit Separator DELDelete 6.6 Binary Adders and Subtractors 239 are sent to a printer, the paper will advance by one line and the print head will return to the beginning of the line. The displayable characters begin at 20H (space) and continue to 7EH (tilde). Spaces are considered ASCII characters. EXAMPLE 6.17 Encode the following string of characters into ASCII (hexadecimal form). Do not include quotation marks. Total system cost: $4,000,000. @ 10% SOLUTION Each character, including spaces, is represented by two hex digits as follows: 54 T 24 $ 6F o 34 4 74 t 2C , 61 a 30 0 6C 1 30 0 20 SP 30 0 73 s 2C , 79 y 30 0 73 s 30 0 74 t 30 0 65 e 2E . 6D m 20 SP 20 SP 40 @ 63 c 20 SP 6F o 31 1 73 s 30 0 74 3A 20 t: SP 25 % SECTION 6.5 REVIEW PROBLEM 6.8 Decode the following sequence of hexadecimal ASCII codes. 54 72 75 65 20 6F 72 20 46 61 6C 73 65 2F 34 20 3C 20 31 2F 32 3A 20 31 6.6 Binary Adders and Subtractors Half and Full Adders KEY TERMS Half adder A circuit that will add two bits and produce a sum bit and a carry bit. Full adder A circuit that will add a carry bit from another full or half adder and two operand bits to produce a sum bit and a carry bit. There are only three possible sums of two 1-bit binary numbers: 0 0 1 FIGURE 6.1 Half Adder Table 6.6 Half Adder Truth Table A B COUT 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 00 01 10 We can build a simple combinational logic circuit to produce the above sums. Let us designate the bits on the left side of the above equalities as inputs to the circuit and the bits on the right side as outputs. Let us call the LSB of the output the sum bit, symbolized by , and the MSB of the output the carry bit, designated COUT. Figure 6.1 shows the logic symbol of the circuit, which is called a half adder. Its truth table is given in Table 6.6. Since addition is subject to the commutative property, (A B B A), the second and third lines of the truth table are the same. The Boolean functions of the two outputs, derived from the truth table, are: NOTE COUT AB AB AB A B 240 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits The corresponding logic circuit is shown in Figure 6.2. The half adder circuit cannot account for an input carry, that is, a carry from a lowerorder 1-bit addition. A full adder, shown in Figure 6.3, can add two 1-bit numbers and accept a carry bit from a previous adder stage. Operation of the full adder is based on the following sums: 0 0 0 1 FIGURE 6.2 Half Adder Circuit 0 0 1 1 0 1 1 1 00 01 10 11 Designating the left side of the above equalities as circuit inputs A, B, and CIN and the right side as outputs COUT and , we can make the truth table in Table 6.7. (The second and third of the above sums each account for three lines in the full adder truth table.) The unsimplied Boolean expressions for the outputs are: FIGURE 6.3 Full Adder COUT A B CIN A B CIN Table 6.7 Full Adder Truth Table A B CIN 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 A B CIN A B CIN A B CIN A B CIN A B CIN There are a couple of ways to simplify these expressions. COUT 0 0 0 0 1 1 1 1 A B CIN 0 1 1 0 1 0 0 1 Karnaugh Map Method Since we have expressions for and COUT in sum-of-products form, let us try to use the Karnaugh maps in Figure 6.4 to simplify them. The expression for doesnt reduce at all. The simplied expression for COUT is: COUT AB A CIN B CIN FIGURE 6.4 K-Maps for a Full Adder The corresponding logic circuits for much of a simplication. and COUT, shown in Figure 6.5, dont give us Boolean Algebra Method The simplest circuit for COUT and involves the Exclusive OR function, which we cannot derive from K-map groupings. This can be shown by Boolean algebra, as follows: COUT A B CIN A B CIN A B CIN A B CIN (A B A B)CIN A B (CIN CIN) (A B) CIN A B 6.6 Binary Adders and Subtractors 241 FIGURE 6.5 Full Adder from K-Map Simplication (A B AB) CIN (A B A B) CIN (A B) CIN (A B) CIN Let x x CIN x CIN x CIN (A B) CIN A B The simplied expressions are as follows: NOTE COUT (A (A B) CIN A B B) CIN Figure 6.6 shows the logic circuit derived from these equations. If you refer back to the half adder circuit in Figure 6.2, you will see that the full adder can be constructed from two half adders and an OR gate, as shown in Figure 6.7. FIGURE 6.6 Full Adder from Logic Gates 242 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits Half Adder Half Adder FIGURE 6.7 Full Adder From Two Half Adders EXAMPLE 6.18 Evaluate the Boolean expression for and COUT of the full adder in Figure 6.8 for the following input values. What is the binary value of the outputs in each case? a. A b. A 0, CIN 0, CIN c. A d. A FIGURE 6.8 Example 6.18 Full Adder 0, B 1, B 1, B 1, B 0, CIN 1, CIN 1 0 1 0 SOLUTION The output of a full adder for any set of inputs is simply given by COUT A B CIN. For each of the stated sets of inputs: a. b. c. d. COUT COUT COUT COUT A A A A B B B B CIN CIN CIN CIN 0 1 1 1 0 0 0 1 1 0 1 0 01 01 10 10 We can verify each of these sums algebraically by plugging the specied inputs into the full adder Boolean equations: COUT a. COUT (0 0 b. COUT (1 1 c. COUT (1 1 (0 0) 1 01 0 000 0) 1 11 (1 0) 0 10 0 000 0) 0 01 (1 0) 1 11 0 101 (A (A B) CIN A B B) CIN 00 (Binary equivalent: COUT 01) 10 (Binary equivalent: COUT 10 0) 1 1 0 (Binary equivalent: COUT 10) 01) 6.6 d. COUT (1 1) 0 00 1 011 (1 0 Binary Adders and Subtractors 243 11 1) 0 00 (Binary equivalent: COUT 10) In each case, the binary equivalent is the same as the number of HIGH inputs, regardless of which inputs they are. EXAMPLE 6.19 Combine a half adder and a full adder to make a circuit that will add two 2-bit numbers. Check that the circuit will work by adding the following numbers and writing the binary equivalents of the inputs and outputs: a. A2 A1 b. A2 A1 01, B2 B1 11, B2 B1 01 10 SOLUTION The 2-bit adder is shown in Figure 6.9. The half adder combines A1 and B1; A2, B2, and C1 are added in the full adder. The carry output, C1, of the half adder is connected to the carry input of the full adder. (A half adder can be used only in the LSB of a multiple-bit addition.) FIGURE 6.9 Example 6.19 2-Bit Adder Sums: a. 01 A1 01 010 1, B1 1 C1 1, 1 0 A2 0, B2 0, C1 1 C2 0, 2 1 (Binary equivalent: A2 A1 B2 B1 C2 2 b. 11 A1 10 101 1, B1 0 C1 0, 1 1 010) 1 A2 1, B2 1, C1 0 C2 1, 2 0 (Binary equivalent: A2 A1 B2 B1 C2 2 1 101) 244 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits Parallel Binary Adder/Subtractor KEY TERMS www.electronictech.com Parallel binary adder A circuit, consisting of n full adders, that will add two n-bit binary numbers. The output consists of n sum bits and a carry bit. Ripple carry A method of passing carry bits from one stage of a parallel adder to the next by connecting COUT of one full adder to CIN of the following stage. Cascade To connect an output of one device to an input of another, often for the purpose of expanding the number of bits available for a particular function. As Example 6.19 implies, a binary adder can be expanded to any number of bits by using a full adder for each bit addition and connecting their carry inputs and outputs in cascade. Figure 6.10 shows four full adders connected as a 4-bit parallel binary adder. FIGURE 6.10 4-Bit Parallel Binary Adder The rst stage (LSB) can be either a full adder with its carry input forced to logic 0 or a half adder, since there is no previous stage to provide a carry. The addition is done one bit at a time, with the carry from each adder propagating to the next stage. EXAMPLE 6.20 Verify the summing operation of the circuit in Figure 6.10 by calculating the output for the following sets of inputs: a. A4 A3 A2 A1 b. A4 A3 A2 A1 0101, B4 B3 B2 B1 1111, B4 B3 B2 B1 SOLUTION At each stage, A B a. 0101 (510 A1 A2 A3 A4 1, 0, 0, 0, 1001 0001 1001 1110 910 1410) 1, B1 1, C0 0, B2 0, C1 1, B3 0, C2 0, B4 1, C3 (Binary equivalent: C4 0; C1 1; C2 0; C3 0; C4 4 3 2 CIN 1 2 3 4 1 COUT . 0 1 1 1 01110) 6.6 b. 1111 0001 (1510 110 A1 1, B1 A2 1, B2 A3 1, B3 A4 1, B4 10000 1610) 1, C0 0; C1 0, C1 1; C2 0, C2 1; C3 0, C3 1; C4 (Binary equivalent: C4 4 1, 1, 1, 1, 3 2 Binary Adders and Subtractors 245 0 0 0 0 1 2 3 4 10000) 1 The internal carries in the parallel binary adder in Figure 6.10 are achieved by a system called ripple carry. The carry output of one full adder cascades directly to the carry input of the next. Every time a carry bit changes, it ripples through some or all of the following stages. A sum is not complete until the carry from another stage has arrived. The equivalent circuit of a 4-bit ripple carry is shown in Figure 6.11. A2B2 A1 B1 A1B1 A2 A3 A4 A3B3 B3 B4 A4B4 C4 B2 C3 C2 C0 C1 FIGURE 6.11 4-bit Ripple Carry Chain A potential problem with this design is that the adder circuitry does not switch instantaneously. A carry propagating through a ripple adder adds delays to the summation time and, more importantly, can introduce unwanted intermediate states. Examine the sum (1111 0001 10000). For a parallel adder having a ripple carry, the output goes through the following series of changes as the carry bit propagates through the circuit: C4 4 3 2 1 01111 01110 01100 01000 10000 If the output of the full adder is being used to drive another circuit, these unwanted intermediate states may cause erroneous operation of the load circuit. Fast Carry KEY TERM Fast carry (or look-ahead carry) A gate network that generates a carry bit directly from all incoming operand bits, independent of the operation of each full adder stage. An alternative carry circuit is called fast carry or look-ahead carry. The idea behind fast carry is that the circuit will examine all the A and B bits simultaneously and produce an output carry that uses fewer levels of gating than a ripple carry circuit. Also, since there is 246 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits OR2 c1 OUTPUT c1 c2 OUTPUT c2 c3 OUTPUT c3 AND2 a1 b1 INPUT AND2 OR3 INPUT AND2 OR2 a2 b2 INPUT INPUT AND3 AND2 OR4 OR2 AND2 a3 b3 INPUT AND2 AND3 INPUT OR2 AND4 a4 b4 c0 INPUT AND2 INPUT OR2 INPUT OR6 AND2 c4 OUTPUT c4 AND3 AND4 GND AND6 VCC FIGURE 6.12 4-bit Fast Carry Circuit a carry bit gate network for each internal stage, the propagation delay is the same for each full adder, regardless of the input operands. The algebraic relation between operand bits and fast carry output is presented below, without proof. It can be developed from the fast carry circuit of Figure 6.12 by tracing the logic of the gates in the circuit. C4 A4 B4 A3 B3 (A4 B4) A2 B2 (A4 B4)(A3 A1 B1 (A4 B4)(A3 B3)(A2 B2) C0 (A4 B4)(A3 B3)(A2 B2)(A1 B1) B3) 6.6 Binary Adders and Subtractors 247 We can make some intuitive sense of the above expression by examining it a term at a time. The rst term says if the MSBs of both operands are 1, there will be a carry (e.g., 1000 1000 10000; carry generated). The second term says if both second bits are 1 AND at least one MSB is 1, there will be a carry (e.g., 0100 1100 10000, or 1100 1100 11000; carry generated in either case). This pattern can be followed logically through all the terms. The internal carry bits are generated by similar circuits that drive the carry input of each full adder stage in the parallel adder. In general, we can generate each internal carry by expanding the following expression: Cn AnBn Cn 1 (An Bn) The algebraic expressions for the remaining carry bits are: C1 C2 C3 A1B1 C0 (A1 B1) A2B2 A1 B1 (A2 B2) C0 (A2 B2)(A1 B1) A3B3 A2 B2 (A3 B3) A1 B1 (A3 B3)(A2 B2) C0 (A3 B3)(A2 B2)(A1 B1) SECTION 6.6A REVIEW PROBLEM 6.9 Refer to the logic diagrams for the ripple carry and fast carry circuits (Figures 6.11 and 6.12). How many gates must a carry bit propagate through in each device if the effect of the carry input ripples through to the 4 bit? (See Figure 6.32 on page 273 and Figure 6.33 on page 273.) Using VHDL Components to Implement a Parallel Adder KEY TERMS Hierarchy A group of design entities associated in a series of levels or layers in which complete designs form portions of another, more general design entity. The more general design is considered to be the higher level of the hierarchy. Component A complete VHDL design entity that can be used as a part of a higher-level le in a hierarchical design. Port An input or output of a VHDL design entity or component. Component declaration statement A statement that denes the input and output port names of a component used in a VHDL design entity. Instantiate To use an instance of a component. Component instantiation statement A statement that maps port names of a VHDL component to the port names, internal signals, or variables of a higher-level VHDL design entity. VHDL designs can be created using a hierarchy of design entities. Certain functions, such as full adders, decoders, and so on, can be created once and used in many designs or multiple times in a single design. We can create a parallel adder in VHDL by using multiple instances of a full adder component in the top-level le of a VHDL design hierarchy. Figure 6.13 shows a graphical illustration of this concept. Each full adder shown is an instance of a component written in VHDL, as shown in the following. Full_add.vhd full_add.vhd Full adder: adds two bits, a and b, plus input carry to yield sum bit and output carry. 248 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits ENTITY full_add IS PORT ( a, b, c_in : IN c_out, sum : OUT END full_add; BIT; BIT); ARCHITECTURE adder OF full_add IS BEGIN c_out ((a xor b) and c_in) or (a and b) ; sum (a xor b) xor c_in; END adder; FIGURE 6.13 4-bit Parallel Adder with Ripple Carry FULL_ADD a1 b1 c0 INPUT INPUT INPUT a2 b2 INPUT INPUT a b c_in a3 b3 INPUT INPUT a b c_in a b c_in c_out sum OUTPUT OUTPUT c1 sum1 OUTPUT OUTPUT c2 sum2 OUTPUT OUTPUT c3 sum3 OUTPUT OUTPUT c4 sum4 FULL_ADD c_out sum FULL_ADD c_out sum FULL_ADD a4 b4 INPUT INPUT a b c_in c_out sum We can create the same design as in Figure 6.13 using VHDL only. To make this hierarchical design we require: 1. A separate component le for a full adder (full_add.vhd), saved in a folder where the compiler can nd it (i.e., on a library path) 2. A component declaration statement in the top-level le of the design hierarchy 3. A component instantiation statement for each instance of the full adder component The general form of a design entity using components is: ENTITY entity_name IS PORT ( input and output denitions); END entity_name; ARCHITECTURE arch_name OF entity_name IS component declaration(s); signal declaration(s); 6.6 Binary Adders and Subtractors 249 BEGIN Component instantiation(s); Other statements; END arch_name; The VHDL le for a 4-bit parallel adder using full adder components is shown next. add4par.vhd add4par.vhd 4-bit parallel adder, using 4 instances of the component full_add ENTITY add4par IS PORT( c0 : IN a, b : IN c4 : OUT sum : OUT END add4par; BIT; BIT_VECTOR (4 downto 1); BIT; BIT_VECTOR (4 downto 1)); ARCHITECTURE adder OF add4par IS Component declaration COMPONENT full_add PORT ( a, b, c_in : IN BIT; c_out, sum : OUT BIT); END COMPONENT; Dene a signal for internal carry bits SIGNAL c : BIT_VECTOR (3 downto 1); BEGIN Four Component Instantiation Statements adder1: full_add PORT MAP ( a a(1), b b(1), c_in c0, c_out c(1), sum sum (1)); adder2: full_add PORT MAP ( a a(2), b b(2), c_in c(1), c_out c(2), sum sum (2)); adder3: full_add PORT MAP ( a a(3), b b(3), c_in c(2), c_out c(3), sum sum (3)); adder4: full_add PORT MAP ( a a(4), b b(4), c_in c(3), c_out c4, sum sum (4)); END adder; 250 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits The component declaration statement denes the ports of the component with the same names as in the full_add.vhd. Note that the form of the component declaration statement is almost the same as that of the components entity declaration. In effect, we are redening the component entity in the top-level le of the design hierarchy. The component instantiation statement is of the following form: __instance_name: __component_name GENERIC MAP (__parameter_name __parameter_value , __parameter_name __parameter_value) PORT MAP (__component_port __connect_port, __component_port __connect_port); In the generic map, a generalized parameter name can be mapped to a specic value when the component is instantiated. For example, a parameter name can be given a value that species the number of component output bits. We will not use this feature in our present examples. In the port map, component ports are the names of the ports used in the component le and connect ports are the names of the ports, variables, or signals used in the higher-level design entity. For example, the component ports of the full adder component are a, b, c in, c_out, and sum. The connect ports for the instance adder1 are a(1), b(1), c0, c(1), and sum(1). The ripple carry from adder1 to adder2 is achieved by mapping the port c_in of adder2 to c(1), which is also mapped to the port c_out of adder1. We can write the component instantiation statements more efciently if we decide to use all ports of the component in the order they are dened. In this case, we can simply list the connect ports in the port map in the correct order, as follows: adder1: adder2: adder3: adder4: full_add full_add full_add full_add PORT PORT PORT PORT MAP MAP MAP MAP (a(1),b(1),c0, c(1),sum(1)); (a(2),b(2),c(1),c(2),sum(2)); (a(3),b(3),c(2),c(3),sum(3)); (a(4),b(4),c(3),c4, sum(4)); If we only wish to use some of the component ports or use them in a different order than the order in which theywere originally dened, we must use the previous form of port map (i.e., a a(1), etc.). GENERATE Statements KEY TERM GENERATE statement A VHDL construct that is used to create repetitive portions of hardware. The four component instantiation statements shown previously can be written in a more general form: adder(i): full_add PORT MAP (a(i), b(i), c(i-1), c(i), sum(i)); A statement that can be written in this indexed form can be implemented using a GENERATE statement, which has the form: label: FOR index IN range GENERATE statements; END GENERATE; The VHDL code that follows shows how to use the statement to create a 4-bit adder. add4gen.vhd add4gen.vhd 4-bit parallel adder, using a generate statement and components 6.6 ENTITY add4gen IS PORT ( c0 : IN a, b : IN c4 : OUT sum : OUT END add4gen; Binary Adders and Subtractors 251 BIT; BIT_VECTOR (4 downto 1); BIT; BIT_VECTOR (4 downto 1)); ARCHITECTURE adder OF add4gen IS Component declaration COMPONENT full_add PORT ( a, b, c_in : IN BIT; c_out, sum : OUT BIT); END COMPONENT; Dene a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto 0); BEGIN c(0) c0; adders: FOR i IN 1 to 4 GENERATE adder: full_add PORT MAP (a(i),b(i),c(i-1),c(i),sum(i)); END GENERATE; c4 c(4); END adder; The GENERATE statement will create hardware that corresponds to the range of the index variable, i. In this case i goes from 1 to 4, so the statement instantiates four instances of the full adder. Since we have an input carry, an output carry and three internal carries, we must use a 5-bit signal (BIT_VECTOR (4 downto 0)) if we are to include all carry bits in indexed form. The input carry, c0, dened in the entity declaration, is assigned to the vector element c(0). Similarly, the output, c4, is assigned the value of the element c(4). It is easy to expand the adder width by changing the range of the FOR GENERATE statement. For example, to make an 8-bit adder, we change the vectors to have a width of eight bits. The required VHDL code, shown next, requires the same number of lines of code as the 4-bit adder. add8gen.vhd add8gen.vhd 8-bit parallel adder, using a generate statement and components ENTITY add8gen IS PORT ( C0 : IN BIT; a, b : IN BIT_VECTOR (8 downto 1); c8 : OUT BIT; sum : OUT BIT_VECTOR (8 downto 1)); END add8gen; ARCHITECTURE adder OF add8gen IS Component declaration COMPONENT full_add PORT ( a, b, c_in : IN BIT; c_out, sum : OUT BIT); 252 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits END COMPONENT; Dene a signal for internal carry bits SIGNAL c : BIT_VECTOR (8 downto 0); BEGIN c(0) c0; adders: FOR i IN 1 to 8 GENERATE adder: full_add PORT MAP (a(i), b(i), c(i-1), c(i), sum(i)); END GENERATE; c8 c(8); END adder; 2s Complement Subtractor Recall the technique for subtracting binary numbers in 2s complement notation. For example, to nd the difference 0101 0011 by 2s complement subtraction: 1. Find the 2s complement of 0011: 0011 1100 1 1101 (1s complement) (2s complement) 2. Add the 2s complement of the subtrahend to the minuend: 0101 1101 1 0010 ( 5) ( 3) ( 2) (Discard carry) We can easily build a circuit to perform 2s complement subtraction, using a parallel binary adder and an inverter for each bit of one of the operands. The circuit shown in Figure 6.14 performs the operation (A B). FIGURE 6.14 2s Complement Subtractor The four inverters generate the 1s complement of B. The parallel adder generates the 2s complement by adding the carry bit (held at logic 1) to the 1s complement at the B inputs. Algebraically, this is expressed as: A B A ( B) where B is the 1s complement of B, and (B A B 1 1) is the 2s complement of B. 6.6 EXAMPLE 6.21 Binary Adders and Subtractors 253 Verify the operation of the 2s complement subtractor in Figure 6.14 by subtracting: a. 1001 b. 0100 0011 (unsigned) 0111 (signed) SOLUTION Let B be the 1s complement of B. a. Inverter inputs (B): Inverter outputs (B): Sum (A B 1): 0011 1100 1001 1100 1 1 0110 (Discard carry) b. Inverter inputs (B): ( 9) ( 3) ( 6) 0111 Inverter outputs (B): 1000 Sum (A 0100 1000 1 1101 0010 1 0011 B 1): Negative result: 1s complement of 1101: 2s complement of 1101: ( 4) ( 7) ( 3) ( 3) Parallel Binary Adder/Subtractor Figure 6.15 shows a parallel binary adder congured as a programmable adder/subtractor. The Exclusive OR gates work as programmable inverters to pass B to the parallel adder in either true or complement form, as shown in Figure 6.16. FIGURE 6.15 2s Complement Adder/Subtractor 254 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits FIGURE 6.16 XOR as a Programmable Inverter The ADD/SUB input is tied to the XOR inverter/buffers and to the carry input of the parallel adder. When ADD/SUB 1, B is complemented and the 1 from the carry input is added to the complement sum. The effect is to subtract (A B). When ADD/SUB 0, the B inputs are presented to the adder in true form and the carry input is 0. This produces an output equivalent to (A B). This circuit can add or subtract 4-bit signed or unsigned binary numbers. EXAMPLE 6.22 Write a VHDL le to implement the 4-bit adder/subtractor shown in Figure 6.15. Also create a simulation le to test a representative selection of addition and subtraction operations. SOLUTION The VHDL le is as follows: addsub4g.vhd addsub4g.vhd ENTITY addsub4g PORT ( sub : a, b : c4 : sum : END addsub4g; IS IN IN OUT OUT BIT; BIT_VECTOR (4 downto 1); BIT; BIT_VECTOR (4 downto 1)); ARCHITECTURE adder OF addsub4g IS Component declaration COMPONENT full_add PORT ( a, b, c_in : IN BIT; c_out, sum : OUT BIT); END COMPONENT; Dene a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto 0); SIGNAL b_comp : BIT_VECTOR (4 downto 1); BEGIN add/subtract select to carry input (sub 1 for subtract) c(0) sub; adders: FOR i IN 1 to 4 GENERATE invert b for subtract (b(i) xor 1), do not invert for add (b(i) xor 0) b_comp(i) b(i) xor sub; adder: full_add PORT MAP (a(i), b_comp(i), c(i-1), c(i), sum(i)); END GENERATE; c4 c(4); END adder; 6.6 255 Binary Adders and Subtractors The VHDL code for the adder/subtractor is the same as that for the 4-bit adder created using a GENERATE statement, except that there is an input to select the add or subtract function. This input (sub) is tied to c(0) and to a set of XOR functions that invert b for subtraction. Input b is transferred through the XOR functions without inversion for the add function. FIGURE 6.17 Example 6.21 Simulation of a 4-bit Adder/Subtractor addSub4g.scf Figure 6.17 shows the simulation for the adder/subtractor. Table 6.8 shows the operations included in the simulation in both hexadecimal and binary form. Note that the sums are interpreted as unsigned operations and the differences are interpreted as signed operations. Any sum or difference can be interpreted either way, but this will sometimes result in a sign bit overow. (e.g., the sums 8 8 10 and F 1 10 both indicate an overow if they are interpreted as signed additions.) Table 6.8 Add/Subtract Results Hexadecimal Sum/Difference 7 8 A F F 0 0 0 0 EXAMPLE 6.23 Binary Equivalent 0111 1000 1010 1111 1111 0000 0000 0000 0000 1 8 1 0 1 1 8 A F 8 10 B F 10 F 8 6 1 0001 1000 0001 0000 0001 0001 1000 1010 1111 0 1000 (Unsigned) 1 0000 (Unsigned) 0 1011 (Unsigned) 0 1111 (Unsigned) 1 0000 (Unsigned) 1111 (Signed: 1) 1000 (Signed: 8) 0110 (Signed: 0 ( 6) 0001 (Signed: 0 ( 1) 6) 1) Note that the simulation in Figure 6.17 shows some intermediate states on the sum waveform in between steady state values. Examine the transition from the sum F 0 F to the sum F 1 10 by using the Zoom In function in the Simulator window. Briey explain how the intermediate states arise in this transition. SOLUTION Figures 6.18 and 6.19 show the transition from F 0 F to F 1 10. The transition on the sum waveform is from F to E to 0 or in binary from 1111 to 1110 to FIGURE 6.18 Example 6.22 Interval from F to E 256 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits FIGURE 6.19 Example 6.22 Interval from F to 0 0000. This transition is the result of a change from 0 to 1 on the b1 input of the adder/ subtractor. Figure 6.18 shows the interval from F to E (the time difference between the vertical line marking 36 ns and the arrow cursor, shown in the box labeled Interval) as 7.4 ns. This is the delay from b1 to sum1. Figure 6.19 shows the interval from F to 0 on the sum waveform, given as 12.6 ns. This interval represents the time required for sum2, sum3, and sum4 to change after a change on b1. Overow Detection We will examine two methods for detecting overow in a binary adder/subtractor: one that requires access to the sign bits of the operands and result and another that requires access to the internal carry bits of the circuit. Recall from Example 6.12 the condition for detecting a sign bit overow in a sum of two binary numbers. NOTE If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overow has occurred. This implies that overow is not possible if the sign bits of the operands are different from each other. This is true because the sum of two opposite-sign numbers will always be smaller in magnitude than the larger of the two operands. Here are two examples: Table 6.9 Overow Detector Truth Table SA SB S V 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1. ( 15) 2. ( 13) ( 7) ( 9) ( 8); ( 4); 8 has a smaller magnitude than 4 has a smaller magnitude than 15. 13. No carry into the sign bit will be generated in either case. An 8-bit parallel binary adder will add two signed binary numbers as follows: SA A7 A6 A5 A4 A3 A2 A1 SB B7 B6 B5 B4 B3 B2 B1 S 7654321 (SA (SB (S Sign bit of A) Sign bit of B) Sign bit of sum) From our condition for overow detection, we can make a truth table for an overow variable, V, in terms of SA, SB, and S . Let us specify that V 1 when there is an overow condition. This condition occurs when (SA SB) S . Table 6.9 shows the truth table for the overow detector function. 6.6 Binary Adders and Subtractors 257 The SOP Boolean expression for the overow detector is: V SA SB S SA SB S Figure 6.20 shows a logic circuit that will detect a sign bit overow in a parallel binary adder. The inputs SA, SB, and S are the MSBs of the adder A and B inputs and outputs, respectively. FIGURE 6.20 Overow Detector EXAMPLE 6.24 Combine two instances of the 4-bit counter shown in Figure 6.15 and other logic to make an 8-bit adder/subtractor that includes a circuit to detect sign bit overow. SOLUTION Figure 6.21 represents the 8-bit adder/subtractor with an overow detector of the type shown in Figure 6.20. FIGURE 6.21 Example 6.24 8-Bit Adder With Overow Detector 258 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits A second method of overow detection generates an overow indication by examining the carry bits into and out of the MSB of a 2s complement adder/subtractor. Consider the following 8-bit 2s complement sums. We will use our previous knowledge of overow to see whether overow occurs and then compare the carry bits into and out of the MSB. a. b. c. d. 80H 7FH 7FH 7FH a. 80H 80H 01H 80H C0H 10000000 Carry into MSB 0 Carry out of MSB 1 b. 7FH 01111111 01H 00000001 Carry into MSB 1 Carry out of MSB 0 c. 7FH 01111111 80H 10000000 Carry into MSB 0 Carry out of MSB 0 d. 7FH 01111111 C0H 11000000 10000000 10000000 1 00000000 (Sign bit overow; V 1) 01111111 00000001 0 10000000 (Sign bit overow; V 1) 01111111 10000000 0 11111111 (No sign bit overow; V 0) 01111111 1 1000000 1 00111111 (No sign bit overow; V 0) Carry into MSB 1 Carry out of MSB 1 The above examples suggest that a 2s complement sum has overowed if there is a carry into or out of the MSB, but not both. For an 8-bit adder/subtractor, we can write the Boolean equation for this condition as V C8 C7. More generally, for an n-bit adder/subtractor, V Cn Cn 1. Figure 6.22 shows a circuit that can implement the overow detection from the carry into and out of the MSB of an 8-bit adder. 8 A8 7 B7 B8 C8 A7 C7 C7 C6 V FIGURE 6.22 6.7 BCD Adders 259 SECTION 6.6B REVIEW PROBLEM 6.10 What is the permissible range of values of a sum or difference, x, in a 12-bit parallel binary adder if it is written as: a. A signed binary number? b. An unsigned binary number? 6.7 BCD Adders (This section may be omitted without loss of continuity.) KEY TERM BCD adder A parallel adder whose output is in groups of 4 bits, each group representing a BCD digit. It is sometimes convenient to have the output of an adder circuit available as a BCD number, particularly if the result is to be displayed numerically. The problem is that most parallel adders have binary outputs, and 6 of the 16 possible 4-bit binary sums1010 to 1111are not within the range of the BCD code. BCD numbers range from 0000 to 1001, or 0 to 9 in decimal. The unsigned binary sum of any two BCD numbers plus an input carry can range from 00000 ( 0000 0000 0) to 10011 ( 1001 1001 1 1910). For any sum up to 1001, the BCD and binary values are the same. Any sum greater than 1001 must be modied, since it requires a second BCD digit. For example, the binary value of 1910 is 100112. The BCD value of 1910 is 0001 1001BCD. (The most signicant digit of a sum of two BCD digits and a carry will never be larger than 1, since the largest such sum is 1910.) Table 6.10 shows the complete list of possible binary sums of two BCD digits (A and B) and a carry (C ), their decimal equivalents, and their corrected BCD values. The MSD of the BCD sum is shown only as a carry bit, with leading zeros suppressed. Table 6.10 Binary Sums of Two BCD Digits and a Carry Bit BinarySum (A B C) Decimal 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Corrected BCD (Carry BCD) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 260 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits FIGURE 6.23 BCD Adder (112 Digit Output) 4-bit Adder Figure 6.23 shows how we can add two BCD digits and get a corrected output. The BCD adder circuit consists of a standard 4-bit parallel adder to get the binary sum and a code converter to translate it into BCD. The Binary-to-BCD code converter operates on the binary inputs as follows: 1. A carry output is generated if the binary sum is in the range 01010 sum 10011 (BCD equivalent: 1 0000 sum 1 1001). 2. If the binary sum is less than 01001, the output is the same as the input. 3. If the sum is in the range 01010 sum 10011, the four LSBs of the input must be corrected to a BCD value. This can be done by adding 0110 to the four LSBs of the input and discarding any resulting carry. We add 01102 (610) because we must account for six unused codes. Lets look at how each of these requirements can be implemented by a digital circuit. Carry Output The carry output will be automatically 0 for any uncorrected sum from 00000 to 01001 and automatically 1 for any sum from 10000 to 10011. Thus, if the binary adders carry output, which we will call C4 , is 1, the BCD adders carry output, C4, will also be 1. Any sum falling between these ranges, that is, between 01010 and 01111, must have its MSB modied. This modifying condition is a function, designated C4 , of the binary adders sum outputs when its carry output is 0. This function can be simplied by a Karnaugh map, as shown in Figure 6.24, resulting in the following Boolean expression. C4 4 3 4 2 The BCD carry output C4 is given by: C4 C4 C4 C4 4 3 The BCD carry circuit is shown in Figure 6.25. 4 2 6.7 BCD Adders 261 C4 4 3 C4 2 FIGURE 6.24 Carry as a Function of Sum Bits When C4 0 FIGURE 6.25 BCD Carry Circuit Sum Correction The four LSBs of the binary adder output need to be corrected if the sum is 01010 or greater and need not be corrected if the binary sum is 01001 or less. This condition is indicated by the BCD carry. Let us designate the binary sum outputs as 4 3 2 1 and the BCD sum outputs as 4 3 2 1. If C4 If C4 0, 1, 4 3 2 1 4 3 2 4 3 2 1 4 3 2 0000; 0110. 1 1 Figure 6.26 shows a BCD adder, complete with a binary adder, BCD carry, and sum correction. A second parallel adder is used for sum correction. The B inputs are the uncorrected binary sum inputs. The A inputs are either 0000 or 0110, depending on the value of the BCD carry. A4 A3 A2 A1 B4 B3 B2 B1 A4 A3 A2 A1 B4 B3 B2 B1 C4 C0 4-bit Adder 4 A4 Code converter C4 FIGURE 6.26 BCD Adder A3 A2 C4 A1 3 2 1 B4 B3 B2 B1 C0 4-bit Adder 4 3 2 1 4 3 2 1 C0 262 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits EXAMPLE 6.25 Write a VHDL le for a BCD adder, using two parallel adder components, such as in the logic diagram in Figure 6.26. SOLUTION bcd_add.vhd bcd_add.vhd BCD adder, using 2 instances of the component add4par ENTITY bcd_add IS PORT ( c0 : IN a, b : IN c4 : OUT sum : OUT END bcd_add; BIT; BIT_VECTOR (4 downto 1); BIT; BIT_VECTOR (4 downto 1)); ARCHITECTURE adder OF bcd add IS Component declaration COMPONENT add4par PORT ( c0 : IN BIT; a, b : IN BIT_VECTOR (4 downto 1); c4 : OUT BIT; sum : OUT BIT_VECTOR (4 downto 1)); END COMPONENT; SIGNAL c4_bin : BIT; SIGNAL sum_bin : BIT_VECTOR (4 downto 1); SIGNAL a_bcd : BIT_VECTOR (4 downto 1); SIGNAL b_bcd : BIT_VECTOR (4 downto 1); SIGNAL c0_bcd: BIT; BEGIN Instantiate 4-bit adder (binary sum) add_bin: add4par PORT MAP ( c0 c0, a a, b b, c4 c4_bin, sum sum_bin); Instantiate 4-bit adder (binary-BCD converter) converter: add4par PORT MAP ( c0 c0_bcd, a a_bcd, b b_bcd, sum sum); Connect components c0_bcd 0; b_bcd sum_bin; a_bcd(4) 0; a_bcd(3) c4 bin or (sum_bin(4) and sum_bin(3)) or (sum_bin(4) and sum_bin(2)); a_bcd(2) c4 bin or (sum_bin(4) and sum_bin(3)) or (sum_bin(4) and sum_bin(2)); a_bcd(1) 0; c4 c4_bin or (sum_bin(4) and sum_bin(3)) or (sum_bin(4) and sum_bin(2)); END adder; 6.8 Carry Generation in MAX PLUS II 263 Multiple-Digit BCD Adders Several BCD adders can be cascaded to add multidigit BCD numbers. Figure 6.27 shows a 4 1 -digit BCD adder. The carry output of the most signicant digit is considered to be a 2 half-digit since it can only be 0 or 1. The output range of the 4 1 -digit BCD adder is 00000 2 to 19999. FIGURE 6.27 41 2-Digit BCD Adder BCD adders are cascaded by connecting the code converter carry output of one stage to the binary adder carry input of the next most signicant stage. Each BCD output digit represents a decade, designated as the units, tens, hundreds, thousands, and ten thousands digits. SECTION 6.7 REVIEW PROBLEM 6.11 What is the maximum BCD sum of two 3-digit numbers with no carry input? How many digits are required to display this result on a numerical output? 6.8 Carry Generation in MAX PLUS II KEY TERMS Speed grade A specication that indicates the internal delay time that can be expected of a CPLD. Expander buffer A MAX PLUS II primitive that supplies an inverted product term for general use within a CPLD. The VHDL adder circuits implemented in Section 6.6 were all dened using a ripple carry format. Is it necessary to design a fast carry circuit when compiling one of these adder designs in MAX PLUS II? Probably not. Recall that the design strategy behind the fast carry circuit was to atten the gate network, that is, to replace a long network (many gates for the carry bit to pass through) with a wide one (fewer levels of gating). Also recall that any combinational logic function can be implemented as a sum-of-products (SOP) network, which inherently is a very at network form. 264 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits The internal circuit of a MAX7000S CPLD is a programmable SOP network. In order to program such a device, the MAX PLUS II compiler must analyze the design entity, break it into product terms and reassemble it as an SOP network. (This is an oversimplication. Sometimes SOP outputs are fed back into the circuit to be reused by other parts of the circuit, thus lengthening the logic path.) MAX PLUS II allows us to choose a style of logic synthesis that balances circuit speed and chip area occupied by the programmed circuit. The styles can be user-dened or we can use one of three predened synthesis styles called Normal, Fast, and WYSIWYG (What You See Is What You Get). Each one of these styles is optimized for speed, area, or a compromise. The Normal and Fast styles disassemble the design entity and reassemble it after optimizing the logic according to the style rules. The WYSIWYG style allows us (rather than the compiler) to largely dene the logic synthesis without altering our design format by very much. To choose a synthesis style, select Global Project Logic Synthesis, from the MAX PLUS II Assign menu, as shown in Figure 6.28. A drop-down menu in the resulting dialog box, shown in Figure 6.29, allows us to select one of the three Altera-dened synthesis styles. FIGURE 6.28 Assigning a Synthesis Style (Assign Menu) FIGURE 6.29 Assigning a Synthesis Style NOTE To use the WYSIWYG style, you must also check the box that says Multi-Level Synthesis for MAX 5000/7000 Devices. We can calculate the circuit delays for an adder by running the compiled design through the MAX PLUS II Timing Analyzer. Figure 6.30 shows an example of such an analysis for the parallel adder add4par.vhd with a Normal synthesis style and an EPM7128SLC84-7 as the selected device. 6.8 Carry Generation in MAX PLUS II 265 FIGURE 6.30 Delay matrix for a 4-bit adder (Normal Synthesis) The values in the Destination columns are the delays from logic level changes on the inputs specied by the Source rows. For example, a change on input a1 reaches the output sum1 in 7.5 ns and sum4 in 12.5 ns. Most of the entries in the c4 column have two values (7.5 ns and 11.5 ns), indicating that the delay to output carry is the same from all input bits (i.e., a fast carry). The actual delay to c4 will depend on the logic level change that takes place on the source line and thus which logic path is taken. The delay time of 7.5 ns is about the lowest value possible in the EPM7128SLC84-7 device. (The 7 tells us that the chip has a speed grade of minus 7, meaning an internal delay of about 7 ns.) Figure 6.31 shows the timing analysis of the same adder with a WYSIWYG synthesis style. (The synthesis style is the only design change.) In this analysis, the delay from an input bit to c4 varies from 7.5 ns (from a4 or b4) to as much as 16.5 ns (for a1, b1, a2, or b2). Since the lower-order bits result in a longer delay to the carry bit, we can infer that the compiler has not synthesized a fast carry circuit. FIGURE 6.31 Delay matrix for a 4-bit adder (WYSIWYG Synthesis) 266 C H A P T E R 6 Digital Arithmetic and Arithmetic Circuits We can examine the actual equations from the MAX PLUS II report le to conrm our assessment. The synthesized equations for c4 are given below. WYSIWYG Synthesis: Node name is c4 |full_add:adder4| :12 Equation name is c4, type is output c4 LCELL( _EQ001 $ GND); _EQ001 a3 & b3 & b4 # b4 & _LC113 & _LC114 # a3 & a4 & b3 # a4 & _LC113 & _LC114 # a4 & b4; Node name is |full_add:adder2|:12 Equation name is _LC113, type is buried _LC113 LCELL( _EQ008 $ GND); _EQ008 a2 & b2 # a2 & c0 & _X007 # b2 & c0 & _X007 # a1 & b1 & _X002; _X007 EXP (!a1 & !b1); _X002 EXP (!a2 & !b2); Node name is |full_add:adder3|:9 Equation name is _LC114, type is buried _LC114 LCELL( b3 $ a3); Normal synthesis: Node name is c4 Equation name is c4, location is LC123, type is output. c4 LCELL ( EQ001 $ VCC); _EQ001 !a1 & _X001 & _X002 & _X003 & _X004 # !b1 & !c0 & _X001 & _X003 & _X004 # !a2 & !b2 & _X003 & _X004 # !a3 & !b3 & _X004 # !a4 & !b4; _X001 EXP ( a2 & b2); _X002 EXP ( b1 & c0); _X003 EXP ( a3 & b3); _X004 EXP ( a4 & b4); The function EXP(signal) is for a MAX PLUS II primitive called an expander buffer, which represents a shared logic expander in the CPLD. There will be more detail about this type of buffer in Chapter 8, but for now, just be aware that this type of buffer supplies inverted product terms for general use within the CPLD. The Normal synthesis mode generates a sum-of-products equation that uses a number of expanders, but only one logic cell (i.e., one SOP output), indicated as LC123. The WYSIWYG synthesis uses an unnumbered output logic cell, which in turn uses two other logic cell outputs (LC113 and LC114) as inputs. Thus, in the Normal synthesis mode, the input signals propagate through one logic cell, and in the WYSIWYG mode, the input signals go through two layers of logic cells, increasing the path length, and thus the delay. What can we conclude? If MAX PLUS II is allowed to synthesize a design for a full adder in the dened Normal style, it will optimize the design equations to produce as at a network as possible. Thus we do not need to explicitly design an adder circuit to have a fast carry function. Summary 267 SUMMARY 1. Addition combines an addend (x) and an augend (y) to get a sum (z x y). 2. Binary addition is based on four sums: 0 1 1 1 1 10 1 1 14. 0 0 1 0 11 3. A sum of two bits generates a sum bit and a carry bit. (For the rst two sums above, the carry bit is 0; the last two sums have a carry of 1. The last sum includes a carry from a lowerorder bit.) 4. Subtraction combines a minuend (x) and a subtrahend (y) to get a difference (z x y). 5. Binary subtraction is based on the following four differences: 0 0 0 1 0 1 1 1 0 10 1 15. 16. 1 6. If the subtrahend bit is larger than the minuend bit, as in the fourth difference above, a 1 must be borrowed from the next higher-order bit. 7. Binary addition or subtraction can be unsigned, where the magnitudes of the operands and result are presumed to be positive, or signed, where the operands and result can be positive or negative. The sign is indicated by a sign bit. 8. The sign bit (usually MSB) of a binary number indicates that the number is positive if it is 0 and negative if it is 1. 9. Signed binary numbers can be written in true-magnitude, 1s complement, or 2s complement form. True magnitude has the same binary value for positive and negative numbers, with only the sign bit changed. A 1s complement negative number is generated by inverting all bits of the positive number of the same magnitude. A 2s complement negative number is generated by adding 1 to the equivalent 1s complement number. Positive numbers are the same in all three forms. 10. 1s complement or 2s complement binary numbers are used in signed addition or subtraction. Subtraction is performed by adding a negative number in complement form to another number in complement form (i.e., x y x ( y)). This technique does not work for true-magnitude form. 11. A negative sum or difference in 2s complement subtraction must be converted to a positive form to read its magnitude (i.e., ( x) x). 12. A signed binary number, x, with n bits has a valid range of 2n x ( 2n 1). 13. A negative number with a power-of-2 magnitude (i.e., 2n) is written in 2s complement form as n 0s preceded by all 1s to ll the dened size of the number (e.g., in 8bit 2s complement form, 128 10000000 (1 followed 17. 18. 19. 20. 21. by seven 0s; 128 27); in 8-bit 2s complement form, 8 11111000 (all 1s, followed by three 0s; 8 23). If a sum or difference falls outside the permissible range of magnitudes for a 2s complement number, it generates an overow into the sign bit of the number. The result is that the sum of two positive numbers appears to be negative (e.g., 01111111 00000010 10000001; 127 2 129) or the sum of two negative numbers appears to be positive (e.g., 11111111 10000000 01111111, where the carry beyond the 8th place is discarded: 1 ( 128) 129). When adding two hexadecimal digits, any digit sum greater than 15 (F) can be converted to a hexadecimal value by subtracting 16 and carrying a 1 to the next digit position. Hexadecimal numbers can be subtracted conventionally or by a complement method. To get the 16s complement of a number, obtain the 15s complement by subtracting the number from all Fs and adding 1 to the result. Binary numbers can be used in nonpositional codes to represent numbers or alphanumeric characters. Binary coded decimal (BCD) codes represent decimal numbers as a series of 4-bit groups of numbers. Natural BCD or 8421 code does this as a positionally weighted code for each digit (e.g., 158 0001 0101 1000 (NBCD)). Other codes, such as Excess-3, are not positionally weighted. Gray code is a binary code that has a difference of one bit between adjacent codes. It can be generated by a set of XOR functions or by recognizing the symmetry inherent in the code. In any Gray code sequence, the MSB is 0 for the rst half of the sequence and 1 for the second half. The remaining bits are symmetrical about the halfway point of the sequence. ASCII code represents alphanumeric characters and computer control codes as a 7-bit group of binary numbers. Alpha characters are listed in uppercase in columns 4 and 5 of the ASCII table. Lowercase alpha characters are in columns 6 and 7. Numeric characters are in column 3. A half adder combines two bits to generate a sum and a carry. It can be represented by the following truth table: A B COUT 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 22. From the half adder truth table, we can derive two equations: COUT AB AB 23. A full adder can accept an input carry from a lower-order adder and combine the input carry with two operands to generate 268 C H A P T E R 6 Digital Arithmetic and Arithemtic Circuits a sum and output carry. Its operation can be summarized in the following truth table: A B CIN COUT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 adder1: full_add PORT MAP (a(1), b(1), c0, c(1), sum(1)); 33. If only a portion of the component ports are to be used or they are not used in the same sequence as they are declared, the port map must be more explicit. For example: 24. The following Boolean equations for a full adder can be derived from the truth table and Boolean algebra: COUT 31. The port map of a component maps the port names dened in a component to the port, signal, or variable names dened in the design entity that uses the component. 32. If all ports of a component are to be used in the same order as in the component denition in the original component design entity, the port map can simply contain the user names in the same order. For example: (A B) CIN (A B) AB CIN 25. Two half adders can be combined to make a full adder. Operands A and B go to the rst half adder. The sum output of the rst half adder and the carry input go to the inputs of the second half adder. The carry outputs of both half adders are combined in an OR gate. 26. Multiple full adders can be cascaded to make a parallel binary adder. Operands A1 and B1 are applied to the rst full adder. Carry bit C0 is grounded. A2 and B2 go to the second adder stage, and so on. The carry output of one stage is cascaded to the carry input of the following stage. This connection is called ripple carry. 27. Ripple carry has the disadvantage of increasing the time required to generate an output result as more stages are added. Fast carry, or look-ahead carry, examines all adder inputs simultaneously and generates each internal and output carry with a separate circuit. This makes the carry circuit wider, but atter, thus reducing the delay time of the circuit. 28. A parallel adder can be implemented in VHDL by creating a design entity for a full adder, then using multiple instances of the full adder as components in the parallel adder. 29. To use a component in a VHDL design hierarchy, we require a design entity that denes the component, a component declaration in the design entity that uses the component, and a component instantiation statement for every instance of the component in the higher-level design entity. 30. The general form of a design entity using components is: ENTITY entity_name IS PORT ( input and output denitions); END entity_name; ARCHITECTURE arch_name OF entity_name IS component declaration (s); signal declaration(s); BEGIN Component instantiation(s); Other statements; END arch_name; adder1: full_add PORT MAP ( b a c_in sum c_out b(1), a(1), c0, sum(1)), c(1); 34. A GENERATE statement can be used to instantiate multiple instances of a component. The GENERATE statement has the form: label: FOR index IN range GENERATE statements; END GENERATE; 35. MAX PLUS II will synthesize an adder to minimize carry delays without much intervention. 36. A parallel binary adder can be made into a 2s complement subtractor by inverting one set of inputs and tying the input carry to a logic HIGH. 37. A parallel binary adder can be made into a 2s complement adder/subtractor by using a set of XOR gates as programmable inverters and connecting the XOR control line to the carry input of the adder. 38. One method of detecting a sign bit overow in a 2s complement adder/subtractor is to compare the sign bits of the operands to the sign bit of the result. If the sign bits of the operands are the same as each other, but different from the sign bit of the result, there has been an overow. The Boolean equation for this detector is given by V S SA SB S SA SB. 39. Another method of overow detection compares the carry out of the MSB of the adder/subtractor to the carry into the MSB. An overow occurs if there is a carry out of or into the MSB, but not both. The Boolean equation for this detector is given by V Cn Cn 1, for an n-bit adder/subtractor. 40. A BCD adder adds two binary coded decimal (BCD) digits and generates a BCD digit and a carry bit. 41. Since BCD is a 4-bit code, BCD addition can be done with a 4-bit binary adder and a code converter. The code converter can be synthesized from another 4-bit binary adder and a circuit to generate a carry. Glossary 269 GLOSSARY 1s complement A form of signed binary notation in which negative numbers are created by complementing all bits of a number, including the sign bit. 10s complement A way of writing decimal numbers where a negative number is generated by adding 1 to its 9s complement. 2s complement A form of signed binary notation in which negative numbers are created by adding 1 to the 1s complement form of the number. 8421 Code (or NBCD; natural binary coded decimal) A BCD code that represents each digit of a decimal number by its 4-bit true binary value. 9s complement A way of writing decimal numbers where a number is made negative by subtracting each of its digits from 9 (e.g., 726 999 726 273 in 9s complement). Excess-3 code A BCD code that represents each digit of a decimal number by a binary number derived by adding 3 to its 4-bit true binary value. Excess-3 code has the advantage of being self-complementing. Expander buffer A MAX PLUS II primitive that supplies an inverted product term for general use within a CPLD. Fast carry (or look-ahead carry) A gate network which generates a carry bit directly from all incoming operand bits, independent of the operation of each full adder stage. Full adder A circuit that will add a carry bit from another full or half adder and two operand bits to produce a sum bit and a carry bit. GENERATE statement A VHDL construct that is used to create repetitive portions of hardware. Addend The number in an addition operation that is added to another. Gray code A binary code which progresses such that only one bit changes between two successive codes. Alphanumeric code A code used to represent letters of the alphabet and numerical characters. Half adder A circuit that will add two bits and produce a sum bit and a carry bit. ASCII American Standard Code for Information Interchange. A 7-bit code for representing alphanumeric and control characters. Hierarchy A group of design entities associated in a series of levels or layers in which complete designs form portions of another, more general design entity. The more general design is considered to be the higher level of the hierarchy. Augend The number in an addition operation to which another number is added. Instantiate To use an instance of a component. BCD Binary coded decimal. A code that represents each digit of a decimal number by a 4-bit binary value. Magnitude bits The part of a signed binary number that tell us how large the number is (i.e., its magnitude). BCD adder A parallel adder whose output is in groups of 4 bits, each group representing a BCD digit. Minuend The number in a subtraction operation from which another number is subtracted. Borrow A digit brought back from a more signicant position when the subtrahend digit is larger than the minuend digit. Operand A number upon which an arithmetic function operates (e.g., in the expression x y z, x and y are the operands). Carry A digit which is carried over to the next most signicant position when the sum of two single digits is too large to be expressed as a single digit. Overow An erroneous carry into the sign bit of a signed binary number which results from a sum larger than can be represented by the number of magnitude bits. Carry bit A bit that holds the value of a carry (0 or 1) resulting from the sum of two binary numbers. Parallel binary adder A circuit, consisting of n full adders, which will add two n-bit binary numbers. The output consists of n sum bits and a carry bit. Cascade To connect an output of one device to a input of another, often for the purpose of expanding the number of bits available for a particular function. Case shift Changing letters from capitals (UPPERCASE) to small letters (lowercase) or vice versa. Component A complete VHDL design entity that can be used as a part of a higher-level le in a hierarchical design. Component declaration statement A statement that denes the input and output port names of a component used in a VHDL design entity. Component instantiation statement A statement that maps port names of a VHDL component to the port names, internal signals, or variables of a higher-level VHDL design entity. Difference The result of a subtraction operation. End-around carry An operation in 1s complement subtraction where the carry bit resulting from a sum of two 1s complement numbers is added to that sum. Port An input or output of a VHDL design entity or component. Ripple carry A method of passing carry bits from one stage of a parallel adder to the next by connecting COUT of one full adder to CIN of the following stage. Self-complementing A code that automatically generates a negative-equivalent (e.g., 9s complement for a decimal code) when all its bits are inverted. Sign bit A bit, usually the MSB, that indicates whether a signed binary number is positive or negative. Signed binary arithmetic Arithmetic operations performed using signed binary numbers. Signed binary number A binary number of xed length whose sign is represented by one bit, usually the most signicant bit, and whose magnitude is represented by the remaining bits. 270 C H A P T E R 6 Digital Arithmetic and Arithemtic Circuits Speed grade A specication that indicates the internal delay time that can be expected of a CPLD. True-magnitude form A form of signed binary number whose magnitude is represented in true binary. Subtrahend The number in a subtraction operation that is subtracted from another number. Unsigned binary arithmetic Arithmetic operations performed using unsigned binary numbers. Sum The result of an addition operation. Unsigned binary number A binary number whose sign is not indicated by a sign bit. A positive sign is assumed unless explicitly stated otherwise. Sum bit (single-bit addition) The least signicant bit of the sum of two 1-bit binary numbers. PROBLEMS Section 6.1 Digital Arithmetic c. 95 63 6.1 Add the following unsigned binary numbers. d. 63 95 a. 10101 1010 e. b. 10101 1011 f. 120 c. 1111 1111 d. 11100 1110 e. 11001 6.2 g. 73 10011 f. 111011 a. 1100 50 73 120 6.5 What are the largest positive and negative numbers, expressed in 2s complement notation, that can be represented by an 8-bit signed binary number? 6.6 Perform the following signed binary operations, using 2s complement notation where required. State whether or not sign bit overow occurs. Give the signed decimal equivalent values of the sums in which overow does not occur. 101001 Subtract the following unsigned binary numbers. 23 100 b. 10001 1001 c. 10101 1100 d. 10110 1010 a. 01101 00110 e. 10110 1001 b. 01101 10110 f. 10001 1111 g. 100010 h. 1100011 6.7 Write the following decimal numbers in 8-bit true-magnitude, 1s complement, and 2s complement forms. a. 110 b. 67 c. 93 109 c. 65 1 36 36 72 110 29 e. 117 127 Perform the following arithmetic operations in the truemagnitude (addition only), 1s complement, and 2s complement systems. Use 8-bit numbers consisting of a sign bit and 7 magnitude bits. (The numbers shown are in the decimal system.) Convert the results back to decimal to prove the correctness of each operation. Also demonstrate that the idea of adding a negative number to perform subtraction is not valid for the true-magnitude form. 6.8 11 f. 117 Section 6.3 Signed Binary Arithmetic 6.4 Without doing any binary complement arithmetic, indicate which of the following operations will result in 2s complement overow. (Assume 8-bit representation consisting of a sign bit and 7 magnitude bits.) Explain the reasons for each choice. d. g. 127 h. 00010 b. 109 e. 0 f. 00010 a. 54 d. 01001 e. 11110 100111 Section 6.2 Representing Signed Binary Numbers 6.3 c. 01110 d. 11110 10111 11 Explain how you can know, by examining sign or magnitude bits of the numbers involved, when overow has occurred in 2s complement addition or subtraction. Section 6.4 Hexadecimal Arithmetic 6.9 Add the following hexadecimal numbers. a. 27H 16H b. 87H 99H c. A55H C5H a. 37 25 d. C7FH 380H b. 85 40 e. 1FFFH A80H Problems 6.10 Subtract the following hexadecimal numbers. a. A4 A3 A2 A1 0100, B4 B3 B2 B1 1001 a. F86H 614H b. A4 A3 A2 A1 1010, B4 B3 B2 B1 0110 b. E72H 229H c. A4 A3 A2 A1 0101, B4 B3 B2 B1 1101 d. A4 A3 A2 A1 1111, B4 B3 B2 B1 0111 c. 37FFH 137FH d. 5764H ACBH e. 7D30H 5D33H 6.21 Briey describe the differences in the underlying design strategies of the ripple carry adder and the fast carry adder (i.e., what makes the fast carry faster than the ripple carry?). What is the main limitation for the fast carry circuit? 6.22 Write the general form of the fast carry equation. Use it to generate Boolean expression for C1, C2, and C3 for a fast carry adder. 6.23 f. 5D33H The following equation describes the carry output function for a parallel binary adder: 7D30H g. 813AH A318H Section 6.5 Numeric and Alphanumeric Codes 6.11 271 Convert the following decimal numbers to true binary, 8421 BCD code, and Excess-3 code. a. 70910 b. 188910 COUT c. 239510 A4 B4 A3 B3 (A4 A2 B2 (A4 B4)(A3 e. 397210 A1 B1 (A4 B4)(A3 f. 773010 CIN (A4 B4)(A3 (A1 B1) d. 125910 B4) B3) B3)(A2 B3)(A2 B2) B2) 6.12 Make a table showing the equivalent Gray codes corresponding to the range from 010 to 3110. 6.13 Write your name in ASCII code. 6.14 Encode the following text into ASCII code: 10% off purchases over $50. (Monday only) 6.24 Write a VHDL le for an 8-bit parallel adder, using eight instances of a full adder component. 6.15 Decode the following string of ASCII code. 6.25 Create a simulation for the 8-bit adder of Problem 6.24, showing a representative sample of sums. How many different sums would be required to show all possible combinations of inputs? 6.26 Write a VHDL le that creates a 12-bit adder using a GENERATE statement. 6.27 Create a simulation le for the 12-bit adder of Problem 6.26 showing only one transition, as follows. Set input a to 000 from 0 to 500 ns, then 001 from 500 ns to 1 s. Set input b to FFF from 0 to 1 s. From the simulation, determine the internal delays from a1 to each of the sum bits. Conrm your observations with the delay matrix from a timing analysis. 6.28 Use MAX PLUS II to create a Graphic Design File for a 2s complement subtractor based on a 4-bit parallel binary adder. Explain how the circuit generates the 2s complement of B for the subtraction A B. 6.29 Use MAX PLUS II to create a Graphic Design File for a 2s complement adder/subtractor based on a 4-bit parallel binary adder. Explain how the circuit is programmed to add or subtract and how it produces the 2s complement of B for the subtraction A B. 6.30 Use MAX PLUS II to draw a circuit that will detect an overow condition in a 4-bit 2s complement adder/ subtractor. The detector output should go HIGH upon overow detection. Draw the circuit truth table, explain what all input and output variables are, and show any Boolean equations you need to complete the circuit design. 6.31 Modify the 4-bit adder/subtractor drawn in Figure 6.15 to include an overow detection circuit. Briey explain how to interpret the third term of this equation. 57 41 52 4E 49 4E 47 21 20 54 68 69 73 20 63 6F 6D 6D 61 6E 64 20 65 72 61 73 65 73 20 36 34 30 4D 20 6F 66 20 6D 65 6D 6F 72 79 2E Section 6.6 Binary Adders and Subtractors 6.16 Write the truth table for a half adder, and from the table derive the Boolean expressions for both Co (carry output) and (sum output) in terms of inputs A and B. Draw the half adder circuit. 6.17 Write the truth table for a full adder, and from the table derive the simplest possible Boolean expressions for COUT and in terms of A, B, and CIN. 6.18 From the equations in Problems 6.16 and 6.17, draw a circuit showing a full adder constructed from two half adders. 6.19 Evaluate the Boolean expression for and COUT of the full adder in Figure 6.7 for the following input values. What is the binary value of the outputs in each case? a. A 0, B 0, CIN 0 b. A 0, B 1, CIN 0 c. A 6.20 0, B 1, CIN 1 d. A 1, B 1, CIN 1 Verify the summing operation of the circuit in Figure 6.10, as follows. Determine the output of each full adder based on the inputs shown below. Calculate each sum manually and compare it to the 5-bit output (C4 4 3 2 1) of the parallel adder circuit. 272 6.32 C H A P T E R 6 Digital Arithmetic and Arithemtic Circuits Create a simulation for the 4-bit adder/subtractor with overow detection (Problem 6.31), using the following representative hexadecimal input values: F 1 10 (carry, but no overow); 7 1 8 (overow, but no carry); 8 8 10 (carry and overow); 0 1 F (result 1). 6.33 Modify the VHDL le for the 4-bit parallel binary adder/subtractor (addsub4g.vhd) to include an overow detection circuit. Use two different methods. 6.34 What is the permissible range of values that a sum or difference, x, can have in a 16-bit parallel binary adder if it is written as: a. A signed binary number b. An unsigned binary number 6.37 Based on the answers to Problems 6.35 and 6.36, formulate a general rule to calculate the maximum BCD sum of two n-digit BCD numbers plus a carry bit. 6.38 Derive the Boolean expression for a BCD carry output as a function of the sum of two BCD digits. 6.39 Draw the circuit for a binary-to-BCD code converter. 6.40 Write a VHDL le to implement a binary-to-BCD code converter for a BCD adder. Use a selected signal assignment or CASE statement. 6.41 Write a VHDL le that uses the binary-to-BCD code converter of Problem 6.40 and a 4-bit parallel binary adder as components in a BCD adder. 6.42 Write a VHDL le that uses a code converter and parallel adder as components in a design that will add two 2-digit BCD numbers and produce a 212 digit result. 6.43 Draw the block diagram of a circuit that will add two 3-digit BCD numbers and display the result as a series of decimal digits. How many digits will the output display? Section 6.7 BCD Adders 6.35 What is the maximum BCD sum of two 3-digit BCD numbers plus an input carry? How many digits are needed to display the result? 6.36 What is the maximum BCD sum of two 4-digit BCD numbers plus an input carry? How many digits are needed to display the result? ANSWERS TO SECTION REVIEW PROBLEMS Section 6.1a 6.1 101000; Section 6.6a 6.2 100000. Section 6.1b 6.3 11; Fast carry: 3 gates 6.4 1 Ripple carry: 8 gates Section 6.3 6.5 11100000; Section 6.6b 6.6 100000. Section 6.4 6.7a 11701H 6.9 Figures 6.32 and 6.33 show the propagation paths for the carry bits. 6.7b 1281H Section 6.5 6.8 True or False: 1/4 6.10a Signed: 2048 x 2047 (11 magnitude bits, 1 sign bit) 6.10b Unsigned: 0 x 4095 (12 magnitude bits, no sign bit: positive implied) Section 6.7 1/2 6.11 Maximum BCD sum 1001 1001 1001 1001 1001 1001 1 1001 1001 1000BCD 199810. This sum requires a 3 1 -digit numerical display. 2 Answers to Section Review Problems 273 OR2 c1 OUTPUT c1 c2 OUTPUT c2 c3 OUTPUT c3 AND2 AND2 INPUT a1 OR3 INPUT b1 AND2 OR2 AND3 AND2 INPUT a2 INPUT b2 OR4 OR2 AND2 AND2 INPUT a3 AND3 INPUT b3 OR2 AND4 AND2 INPUT a4 INPUT b4 OR2 INPUT c0 OR6 AND2 c4 OUTPUT c4 AND3 AND4 GND AND6 VCC FIGURE 6.32 Fast Carry from A4/B4 to C4. A2B2 A1 B1 A1B1 C0 FIGURE 6.33 Ripple Carry from C0 to C4 A2 B2 A3 B3 A3B3 A4 B4 A4B4 C4 CHAPTER 7 Introduction to Sequential Logic OUTLINE CHAPTER OBJECTIVES 7.1 7.2 7.3 7.4 Upon successful completion of this chapter, you will be able to: Explain the difference between combinational and sequential circuits. Dene the set and reset functions of an SR latch. Draw circuits, function tables, and timing diagrams of NAND and NOR latches. Explain the effect of each possible input combination to a NAND and a NOR latch, including set, reset, and no change functions, as well as the ambiguous or forbidden input condition. Design circuit applications that employ NAND and NOR latches. Describe the use of the ENABLE input of a gated SR or D latch as an enable/inhibit function and as a synchronizing function. Outline the problems involved with using a level-sensitive ENABLE input on a gated SR or D latch. Explain the concept of edge-triggering and why it is an improvement over level-sensitive enabling. Draw circuits, function tables, and timing diagrams of edge-triggered D, JK, and T ip-ops. Describe the toggle function of a JK ip-op and a T ip-op. Describe the operation of the asynchronous preset and clear functions of D, JK, and T ip-ops and be able to draw timing diagrams showing their functions. Use MAX PLUS II to create simple circuits and simulations with D latches and D, JK, and T ip-ops. Create simple ip-op designs using VHDL. 7.5 7.6 7.7 Latches NAND/NOR Latches Gated Latches Edge-Triggered D Flip-Flops Edge-Triggered JK Flip-Flops Edge-Triggered T Flip-Flops Timing Parameters T he digital circuits studied to this point have all been combinational circuits, that is, circuits whose outputs are functions only of their present inputs. A particular set of input states will always produce the same output state in a combinational circuit. 275 276 C H A P T E R 7 Introduction to Sequential Logic This chapter will introduce a new category of digital circuitry: the sequential circuit. The output of a sequential circuit is a function both of the present input conditions and the previous conditions of the inputs and/or outputs. The output depends on the sequence in which the inputs are applied. We will begin our study of sequential circuits by examining the two most basic sequential circuit elements: the latch and the ip-op, both of which are part of the general class of circuits called bistable multivibrators. These are similar devices, each being used to store a single bit of information indenitely. The difference between a latch and a ipop is the condition under which the stored bit is allowed to change. Latches and ip-ops are also used as integral parts of more complex devices, such as programmable logic devices (PLDs), usually when an input or output state must be stored. I 7.1 Latches KEY TERMS Sequential circuit A digital circuit whose output depends not only on the present combination of inputs, but also on the history of the circuit. Latch A sequential circuit with two inputs called SET and RESET, which make the latch store a logic 0 (reset) or 1 (set) until actively changed. SET 1. The stored HIGH state of a latch circuit. 2. A latch input that makes the latch store a logic 1. RESET 1. The stored LOW state of a latch circuit. 2. A latch input that makes the latch store a logic 0. All the circuits we have seen up to this point have been combinational circuits. That is, their present outputs depend only on their present inputs. The output state of a combinational circuit results only from a combination of input logic states. The other major class of digital circuits isthe sequential circuit. The present outputs of a sequential circuit depend not only on its present inputs, but also on its past input states. The simplest sequential circuit is the SR latch, whose logic symbol is shown in Figure 7.1a. The latch has two inputs, SET (S) and RESET (R), and two complementary outputs, Q and Q. If the latch is operating normally, the outputs are always in opposite logic states. FIGURE 7.1 SR Latch (Active HIGH Inputs) The latch operates like a momentary-contact pushbutton with START and STOP functions, shown in Figure 7.2. A momentary-contact switch operates only when it is held down. When released, a spring returns the switch to its rest position. Suppose the switch in Figure 7.2 is used to control a motor starter. When you push the START button, the motor begins to run. Releasing the START switch does not turn the motor off; that can be done only by pressing the STOP button. If the motor is running, 7.1 Latches 277 pressing the START button again has no effect, except continuing to let the motor run. If the motor is not running, pressing the STOP switch has no effect, since the motor is already stopped. There is a conict if we press both switches simultaneously. In such a case we are trying to start and stop the motor at the same time. We will come back to this point later. The latch SET input is like the START button in Figure 7.2. The RESET input is like the STOP button. FIGURE 7.2 Industrial Pushbutton (e.g., Motor Starter) NOTE By denition: A latch is set when Q 1 and Q 0. A latch is reset when Q 0 and Q 1. The latch in Figure 7.1 has active-HIGH SET and RESET inputs. To set the latch, make R 0 and make S 1. This makes Q 1 until the latch is actively reset, as shown in the timing diagram in Figure 7.1b. To activate the reset function, make S 0 and make R 1. The latch is now reset (Q 0) until the set function is next activated. Combinational circuits produce an output by combining inputs. In sequential circuits, it is more accurate to think in terms of activating functions. In the latch described, S and R are not combined by a Boolean function to produce a particular result at the output. Rather, the set function is activated by making S 1, and the reset function is activated by making R 1, much as we would activate the START or STOP function of a motor starter by pressing the appropriate pushbutton. The timing diagram in Figure 7.1b shows that the inputs need not remain active after the set or reset functions have been selected. In fact, the S or R input must be inactive before the opposite function can be applied, in order to avoid conict between the two functions. EXAMPLE 7.1 FIGURE 7.3 Example 7.1 SR Latch Latches can have active-HIGH or active-LOW inputs, but in each case Q 1 after the set function is applied and Q 0 after reset. For each latch shown in Figure 7.3, complete the timing diagram shown. Q is initially LOW in both cases. (The state of Q before the rst active SET or RESET is unknown unless specied, since the present state depends on previous history of the circuit.) 278 C H A P T E R 7 Introduction to Sequential Logic SOLUTION The Q and Q waveforms are shown in Figure 7.3. Note that the outputs respond only to the rst set or reset command in a sequence of several pulses. EXAMPLE 7.2 Figure 7.4 shows a latching HOLD circuit for an electronic telephone. When HIGH, the HOLD output allows you to replace the handset without disconnecting a call in progress. FIGURE 7.4 Example 7.2 Latching HOLD Button The two-position switch is the telephones hook switch (the switch the handset pushes down when you hang up), shown in the off-hook (in-use) position. The normally closed pushbutton is a momentary-contact switch used as a HOLD button. The circuit is such that the HOLD button does not need to be held down to keep the HOLD active. The latch remembers that the switch was pressed, until told to forget by the reset function. Describe the sequence of events that will place a caller on hold and return the call from hold. Also draw timing diagrams showing the waveforms at the HOLD input, hook switch inputs, S input, and HOLD output for one hold-and-return sequence. (HOLD output 1 means the call is on hold.) SOLUTION To place a call on hold, we must set the latch. We can do so if we press and hold the HOLD switch, then the hook switch. This combines two HIGHsone from the HOLD switch and one from the on-hook position of the hook switchinto the AND gate, making S 1 and R 0. Note the sequence of events: press HOLD, hang up, release HOLD. The S input is HIGH only as long as the HOLD button is pressed. The handset can be kept on-hook and the HOLD button released. The latch stays set, as S R 0 (neither SET not RESET active) as long as the handset is on-hook. To restore a call, lift the handset. This places the hook switch into the off-hook position and now S 0 and R 1, which resets the latch and turns off the HOLD condition. Figure 7.5 shows the timing diagram for the sequence described. FIGURE 7.5 Example 7.2 HOLD Timing Diagram 7.2 NAND/NOR Latches 279 SECTION 7.1 REVIEW PROBLEM 7.1 A latch with active-HIGH S and R inputs is initially set. R is pulsed HIGH three times, with S 0. Describe how the latch responds. 7.2 NAND/NOR Latches An SR latch is easy to build with logic gates. Figure 7.6 shows two such circuits, one made from NOR gates and one from NANDs. The NAND gates in the second circuit are drawn in DeMorgan equivalent form. FIGURE 7.6 SR Latch Circuits The two circuits both have the following three features: 1. OR-shaped gates 2. Logic level inversion between the gate input and output 3. Feedback from the output of one gate to an input of the opposite gate During our examination of the NAND and NOR latches, we will discover why these features are important. A signicant difference between the NAND and NOR latches is the placement of SET and RESET inputs with respect to the Q and Q outputs. Once we dene which output is Q and which is Q, the locations of the SET and RESET inputs are automatically dened. In a NOR latch, the gates have active-HIGH inputs and active-LOW outputs. When the input to the Q gate is HIGH, Q 0, since either input HIGH makes the output LOW. Therefore, this input must be the RESET input. By default, the other is the SET input. In a NAND latch, the gate inputs are active LOW (in DeMorgan equivalent form) and the outputs are active HIGH. A LOW input on the Q gate makes Q 1. This, therefore, is the SET input, and the other gate input is RESET. Since the NAND and NOR latch circuits have two binary inputs, there are four possible input states. Table 7.1 summarizes the action of each latch for each input combination. The functions are the same for each circuit, but they are activated by opposite logic levels. Table 7.1 NOR and NAND Latch Functions S R Action (NOR Latch) S R Action (NAND Latch) 0 0 Neither SET nor RESET active; output does not change from previous state 0 0 Both SET and RESET active; forbidden condition 0 1 1 0 RESET input active SET input active 0 1 1 0 SET input active RESET input active 1 1 Both SET and RESET active; forbidden condition 1 1 Neither SET nor RESET active; output does not change from previous state 280 C H A P T E R 7 Introduction to Sequential Logic We will examine the NAND latch circuit for each of the input conditions in Table 7.1. The analysis of a NOR latch is similar and will be left as an exercise. NAND Latch Operation Figure 7.7 shows a NAND latch in its two possible stable states. In each case the inputs S and R are both HIGH (inactive). S 1 Q S 1 1 0 0 Q 1 1 1 R Q Q 1 0 0 R 1 b. Reset a. Set FIGURE 7.7 NAND Latch Stable States Figure 7.7a shows the latch in its SET condition (Q 1). The feedback connections from each gate output to the input of the opposite gate keep the latch in a stable condition. The upper gate has a LOW on the inner input. Since, for a NAND gate, either input LOW makes the output HIGH, this makes Q 1. This HIGH value is fed to the gate on the other side of the latch. The lower gate has both inputs HIGH, thus keeping its output LOW. The LOW at Q feeds back to the upper gate, forming a closed loop of consistent logic levels. There is no tendency for the outputs to change under these conditions. Figure 7.7b shows a similar state for the latch in a RESET condition (Q 0). As with the SET state, the stability of the latch depends on the feedback connections. The logic values of the latch gate inputs are the same as before, except that the LOW input is on the lower gate, not the upper gate as in the SET condition. Figure 7.8 shows a NAND latch as a Graphic Design File created with MAX PLUS II. The inputs are labeled nS and nR and one output as nQ as we cannot enter input names with bars over them. (BOR2 Bubbled OR, 2-inputs.) INPUT BOR2 OUTPUT nS Q BOR2 INPUT nR OUTPUT nQ FIGURE 7.8 Graphic Design File representation of a NAND Latch. NOTE The documentation for MAX PLUS II recommends that you do not create your own latch circuits or similar cross-coupled structures. Rather, you should use primitives such as LATCH, or components such as lpm_latch, which can be used in gdf or vhd les. We will use the design in Figure 7.8 only to illustrate the function of a NAND latch and to generate some timing data with the MAX PLUS II simulator. In order to make MAX PLUS II synthesize this circuit as we have drawn it in Figure 7.8, we must select Global Project Logic Synthesis from the Assign Menu (Figure 7.9). 7.2 NAND/NOR Latches 281 In the resulting dialog box (Figure 7.10), we must choose the WYSIWYG (What You See Is What You Get) synthesis style and check the box that says Multi-Level Synthesis for MAX5000/7000 Devices. nd_latch.gdf FIGURE 7.10 Choosing WYSIWYG Synthesis Style FIGURE 7.9 Assign Menu When we compile the graphic le, MAX PLUS II synthesizes the following equations, which we can read in the project report le: ** EQUATIONS ** nR nS : INPUT; : INPUT; Node name is nQ :3 Equation name is nQ, type is output nQ LCELL( _EQ001 $ GND); _EQ001 !nR # !Q; Node name is Q :2 Equation name is Q, type is output Q LCELL ( _EQ002 $ GND); _EQ002 !nS # !nQ; We can rewrite the synthesized latch equations as: Q nQ nS nR nQ Q 282 C H A P T E R 7 Introduction to Sequential Logic When we run the MAX PLUS II Timing Analyzer, we get the delay matrix shown in Figure 7.11. The delays are symmetrical for this circuit. The delay from nS to Q (7.5 ns) is through one gate; from nS to nQ (12.5 ns) is through two gates. These values are the same for the path from nR to nQ (7.5 ns; one gate) and from nR to Q (12.5 ns; two gates). We can see these changes on simulation waveforms for the SET and RESET functions. FIGURE 7.11 NAND Latch Delay Matrix (WYSIWYG Synthesis) Figures 7.12 and 7.13 show the transition of a NAND latch from the RESET to the SET condition. In Figure 7.12a, the latch is stable in the RESET condition (Q 0) at time t 0 (i.e., before a SET pulse is applied to the latch). At time t 0, the S input goes LOW (Figure 7.12b) and 7.5 ns later, the output Q goes HIGH (Figure 7.12c). This applies a HIGH to the lower gate in the latch and at t 12.5 ns (Figure 7.12d), the Q output goes LOW, closing the loop. The latch is now in a new stable conguration and the S input can go back HIGH, as shown in Figure 7.12e. www.electronictech.com S 1 Q S 0 0 Q 1 S 0 Q 1 R Q 1 1 1 0 1 Q 1 a. Stable (t 1 R b. Initiate set (t 0) S Q 1 0 Q 1 Q 0 0 R 1 0) S 1 R 1 c. t Q 1 Q 0 0 1 R 1 d. t FIGURE 7.12 RESET-to-SET transition 12.5ns e. Stable (t 12.5ns) 7.5ns 7.2 NAND/NOR Latches 283 FIGURE 7.13 NAND Latch SET function simulation The waveforms in Figure 7.13 also show this transition. The simulation window has a 2.5 ns grid, so three grid spaces are equivalent to 7.5 ns and ve grid spaces to 12.5 ns. The waveforms show Q going HIGH 7.5 ns after nS goes LOW, followed by nQ going LOW at 12.5 ns after nS. Figures 7.14 and 7.15 show the same thing for the RESET function. The latch is in a 0 (Figure stable SET condition at time t 0 (Figure 7.14a). Input R goes LOW at t 7.14b). At time t 7.5 ns, Q goes HIGH, which is transferred to the upper gate in the latch circuit Figure 7.14c). Since both inputs of the upper gate are now HIGH, Q goes LOW at time t 12.5 ns (Figure 7.14d). At this point the latch is stable in the RESET condition and the input R can return to the HIGH (inactive) state, as shown in Figure 7.14e. Figure 7.15 shows the simulation waveforms for this transition. S 1 Q S 1 1 Q 0 R S 1 1 Q 1 a. Stable (t 0 R 0) S Q 0 b. Initiate reset (t 1 S 1 0 1 d. t FIGURE 7.14 SET-to-RESET Transition FIGURE 7.15 NAND latch RESET function simulation Q 0 12.5ns 1 Q 1 R 0 c. t Q 0 Q 1 1 0 R 0 0) Q Q 1 1 0 1 1 1 0 R 1 e. Stable (t 12.5ns) 7.5ns 284 C H A P T E R 7 Introduction to Sequential Logic Note that the latch is not stable in its new condition until the new logic levels have propagated through both gates. Figure 7.16 shows the result of a RESET pulse that only lasts for 7.5 ns. This pulse is too short to allow both gates to change states. The outputs both oscillate, since the changing logic levels never catch up as they move around the latch. This is due to the fact that both paths (nS-Q-nQ and nR-nQ-Q) are the same length. If one path were slightly longer, the logic level controlled by the longer path would dominate and the latch would stabilize in one state or the other. FIGURE 7.16 NAND latch oscillation due to a RESET pulse that is too short S 0 Q 1 Q 1 1 1 R 0 FIGURE 7.17 NAND Latch Forbidden State Figure 7.17 shows a NAND latch with S R 0. This implies that both SET and RESET functions are active. Since a NAND gate requires at least one input LOW to make the output HIGH, both outputs respond by going HIGH. This condition is not unstable in and of itself, but instability can result when the inputs change. There are three possible results when the outputs go back to the HIGH state. 1. The SET input goes HIGH before the RESET input. In this case the latch resets, as RESET is the last input active. This is shown in the simulation in Figure 7.18. FIGURE 7.18 SET goes HIGH before RESET FIGURE 7.19 RESET goes HIGH before SET 2. The RESET input goes HIGH before SET. In this case, the latch sets, as shown in Figure 7.19. 7.2 NAND/NOR Latches 285 3. The SET and RESET inputs go HIGH at the same time. This is an unstable case. Figure 7.20 shows how the latch will oscillate under this condition. When the inputs S and R are both LOW (Figure 7.20a), both latch outputs are HIGH. When S and R go HIGH (Figure 7.20b), all gate inputs are HIGH. This makes both outputs LOW (Figure 7.20c). The LOWs transfer across the latch to the opposite gates and, after a delay, make both outputs HIGH (Figure 7.20d). At this point, oscillations will be sustained until the latch is SET or RESET. The simulation waveforms in Figure 7.21 show the oscillatory condition of the latch outputs. S 0 Q S 1 1 1 1 S 1 1 1 R Q Q 0 a. t R Q 1 0 b. t S 1 Q 1 1 Q 0 R 1 0 c. t S 1 Q 1 0 0 Q 0 7.5ns 0 0 1 R 0 0 1 1 Q Q 1 d. t 1 R 1 12.5ns e. t 17.5ns FIGURE 7.20 NAND Latch Forbidden State Transition In practice, the oscillatory condition of Figure 7.21 is unlikely to be sustained for very long. One of the two gates is likely to be slightly faster than the other, which will allow one state or the other to dominate. FIGURE 7.21 SET and RESET go HIGH simultaneously The operation of the NAND latch can be summarized in a function table, shown in Table 7.2. The notation Qt 1 indicates that the column shows the value of Q after the specied input is applied. Qt indicates the present state of the Q input.* Thus, the entry for the no change state indicates that after the inputs S 0, R 0 are applied, the next state of the output is the same as its present state. *Many sources (such as data sheets) use the notation Q0 to refer to the previous state of Q. We will use the notation indicated (Qt for present state and Qt 1 for next state) so as to be able to reserve Q0 for the least signicant bit of a circuit requiring multiple Q outputs. 286 C H A P T E R 7 Introduction to Sequential Logic Table 7.2 NAND Latch Function Table S R 0 0 1 1 0 1 0 1 Qt 1 1 0 Qt 1 Qt 1 1 0 1 Qt Table 7.3 NOR Latch Function Table Function S R Forbidden Set Reset No Change 0 0 1 1 0 1 0 1 Qt Qt 1 Qt 0 1 0 Qt 1 0 0 1 Function No Change Reset Set Forbidden Table 7.3 shows the function table for the NOR latch. Practical Synthesis in MAX PLUS II The NAND latch shown previously (Figure 7.8) was synthesized in MAX PLUS II, using the WYSIWYG synthesis style. We did this so as to be able to use the MAX PLUS II simulation tool to get waveforms for a standard NAND latch. However, if we allow MAX PLUS II to synthesize the latch circuit in the Normal synthesis style, the software will choose a more stable conguration, shown in Figure 7.22. FIGURE 7.22 NAND Latch as synthesized by MAX PLUS II (NORMAL synthesis) nS Q nR nQ Vcc The equations for the circuit in Figure 7.22 from the MAX PLUS II report le are given as: ** EQUATIONS ** nR nS : INPUT; : INPUT; Node name is nQ Equation name is nQ, location is LC117, type is output. nQ LCELL( _EQ001 $ VCC); _EQ001 nR & Q; Node name is Q 2 1 Equation name is Q, location is LC115, type is output. Q LCELL( _EQ002 $ !ns); _EQ002 nR & nS & Q; We can rewrite the above equations as: Q nQ (nR nS Q) (nR Q) 1 nS nR Q Without going into a detailed analysis, we will just note that the latching occurs through a combination of the XOR gate at Q and the feedback from the Q output to the 3input AND. The lower AND/XOR structure simply serves to invert the Q output to provide a complementary value at nQ. This conguration is more stable because both SET and RESET functions go through the same path (the 3-input AND gate). Delay is the same from nS to Q and from nR to Q. In the WYSIWYG version, the path is equal from nS to nQ and from nR to Q, but not from nS to Q and nR to Q. The SET and RESET pulses thus go through different paths in the 7.2 NAND/NOR Latches 287 WYSIWYG synthesis, resulting in unequal delays from the inputs to the Q output, which can lead to instability. Latch as a Switch Debouncer Pushbutton or toggle switches are sometimes used to generate pulses for digital circuit inputs, as illustrated in Figure 7.23. However, when a switch is operated and contact is made on a new terminal, the contact, being mechanical, will bounce a few times before settling into the new position. Figure 7.23d shows the effect of contact bounce on the waveform for a pushbutton switch. The contact bounce is shown only on the terminal where contact is being made, not broken. FIGURE 7.23 Switches as Pulse Generators Contact bounce can be a serious problem, particularly when a switch is used as an input to a digital circuit that responds to individual pulses. If the circuit expects to receive one pulse, but gets several from a bouncy switch, it will behave unpredictably. A latch can be used as a switch debouncer, as shown in Figure 7.24a. When the pushbutton is in the position shown, the latch is set, since S 0 and R 1. (Recall that the NAND latch inputs are active LOW.) When the pushbutton is pressed, the R contact FIGURE 7.24 NAND Latch as a Switch Debouncer 288 C H A P T E R 7 Introduction to Sequential Logic bounces a few times, as shown in Figure 7.24b. However, on the rst bounce, the latch is reset. Any further bounces are ignored, since the resulting input state is either S R 1 (no change) or S 1, R 0 (reset). Similarly, when the pushbutton is released, the S input bounces a few times, setting the latch on the rst bounce. The latch ignores any further bounces, since they either do not change the latch output (S R 1) or set it again (S 0, R 1). The resulting waveforms at Q and Q are free of contact bounce and can be used reliably as inputs to digital sequential circuits. EXAMPLE 7.3 A NOR latch can be used as a switch debouncer, but not in the same way as a NAND latch. Figure 7.25 shows two NOR latch circuits, only one of which works as a switch debouncer. Draw a timing diagram for each circuit, showing R, S, Q, and Q, to prove that the circuit in Figure 7.25b eliminates switch contact bounce but the circuit in Figure 7.25a does not. FIGURE 7.25 Example 7.3 NOR Latch Circuits SOLUTION Figure 7.26 shows the timing diagrams of the two NOR latch circuits. In the circuit in Figure 7.25a, contact bounce causes the latch to oscillate in and out of the forbidden state of the latch (S R 1). This causes one of the two outputs to bounce for each contact closure. (Use the function table of the NOR latch to examine each part of the timing diagram to see that this is so.) By making the resistors pull down rather than pull up, as in Figure 7.25b, the latch oscillates in and out of the no change state (S R 0) as a result of contact bounce. The rst FIGURE 7.26 Example 7.3 NOR Latch Circuits 7.3 Gated Latches 289 bounce on the SET terminal sets the latch, and other oscillations are disregarded. The rst bounce on the RESET input resets the latch, and further pulses on this input are ignored. The principle illustrated here is that a closed switch must present the active input level to the latch, since switch bounce is only a problem on contact closure. Thus, a closed switch must make the input of a NOR latch HIGH or the input of a NAND latch LOW to debounce the switch waveform. NOTE The NOR latch is seldom used in practice as a switch debouncer. The pull-down resistors need to be about 500 or less to guarantee a logic LOW at the input of a TTL NOR gate. In such a case, a constant current of about 10 mA ows through the resistor connected to the normally closed portion of the switch. This value is unacceptably high in most circuits, as it draws too much idle current from the power supply. For this reason, the NAND latch, which uses higher-value pull-up resistors (about 1 k or larger) and therefore draws less idle current, is preferred for a switch debouncer. SECTION 7.2 REVIEW PROBLEM 7.2 Why is the input state S R 1 considered forbidden in the NOR latch? Why is the same state in the NAND latch the no change condition? 7.3 Gated Latches KEY TERMS Gated SR latch An SR latch whose ability to change states is controlled by an extra input called the ENABLE input. Steering gates Logic gates, controlled by the ENABLE input of a gated latch, that steer a SET or RESET pulse to the correct input of an SR latch circuit. Transparent latch (gated D latch) A latch whose output follows its data input when its ENABLE input is active. Gated SR Latch It is not always desirable to allow a latch to change states at random times. The circuit shown in Figure 7.27, calleda gated SR latch, regulates the times when a latch is allowed to change state. The gated SR latch has two distinct subcircuits. One pair of gates is connected as an SR latch. A second pair, called the steering gates, can be enabled or inhibited by a control signal, called ENABLE, allowing one or the other of these gates to pass a SET or RESET signal to the latch gates. The ENABLE input can be used in two principal ways: (1) as an ON/OFF signal, and (2) as a synchronizing signal. Figure 7.27b shows the ENABLE input functioning as an ON/OFF signal. When ENABLE 1, the circuit acts as an active-HIGH latch. The upper gate converts a HIGH at S to a LOW at S, setting the latch. The lower gate converts a HIGH at R to a LOW at R, thus resetting the latch. When ENABLE 0, the steering gates are inhibited and do not allow SET or RESET signals to reach the latch gate inputs. In this condition, the latch outputs cannot change. 290 C H A P T E R 7 Introduction to Sequential Logic FIGURE 7.27 Gated SR Latch Figure 7.27c shows the ENABLE input as a synchronizing signal. A periodic pulse waveform is present on the ENABLE line. The S and R inputs are free to change at random, but the latch outputs will change only when the ENABLE input is active. Since the ENABLE pulses are equally spaced in time, changes to the latch output can occur only at xed intervals. The outputs can change out of synchronization if S or R change when ENABLE is HIGH. We can minimize this possibility by making the ENABLE pulses as short as possible. Table 7.4 represents the function table for a gated SR latch. Table 7.4 Gated SR Latch Function Table EN S R 1 1 1 1 0 0 0 1 1 X 0 1 0 1 X Qt Qt 0 1 0 Qt 1 Qt Qt 1 0 0 Qt 1 Function No change Reset Set Forbidden Inhibited 7.3 EXAMPLE 7.4 Gated Latches 291 Figure 7.28 shows two gated latches with the same S and R input waveforms but different ENABLE waveforms. EN1 has a 50% duty cycle. EN2 has a duty cycle of 16.67%. Draw the output waveforms, Q1 and Q2. Describe how the length of the ENABLE pulse affects the output of each latch, assuming that the intent of each circuit is to synchronize the output changes to the beginning of the ENABLE pulse. FIGURE 7.28 Example 7.4 Effect of ENABLE Pulse Width SOLUTION Figure 7.28b shows the completed timing diagram. The longer ENABLE pulse at latch 1 allows the output to switch too soon during pulses 1 and 4. (Too soon means before the beginning of the next ENABLE pulse.) In each of these cases, the S and R inputs change while the ENABLE input is HIGH. This premature switching is eliminated in latch 2 because the S and R inputs change after the shorter ENABLE pulse is nished. A shorter pulse gives less chance for synchronization error, since the time for possible output changes is minimized. Transparent Latch (Gated D Latch) Figure 7.29 shows the equivalent circuit of a gated D (data) latch, or transparent latch. This circuit has two modes. When the ENABLE input is HIGH, the latch is transparent because the output Q goes to the level of the data input, D. (We say, Q follows D.) When the ENABLE input is LOW, the latch stores the data that was present at D when ENABLE was last HIGH. In this way, the latch acts as a simple memory circuit. 292 C H A P T E R 7 Introduction to Sequential Logic FIGURE 7.29 Transparent Latch The latch in Figure 7.29 is a modication of the gated SR latch, congured so that the S and R inputs are always opposite. Under these conditions, the states S R 0 (no change) and S R 1 (forbidden) can never occur. However, the equivalent of the no change state happens when the ENABLE input is LOW, when the latch steering gates are inhibited. Figure 7.30 shows the operation of the transparent latch in the inhibit (no change), set, and reset states. When the latch is inhibited, the steering gates block any LOW pulses to the latch gates; the latch does not change states, regardless of the logic level at D. FIGURE 7.30 Operation of Transparent Latch If EN 1, Q follows D. When D 1, the upper steering gate transmits a LOW to the SET input of the latch and Q 1. When D 0, the lower steering gate transmits a LOW to the RESET input of the output latch and Q 0. Table 7.5 shows the function table for a transparent latch. Table 7.5 Function Table of a Transparent Latch EN D Qt 0 X Qt 1 1 0 1 0 1 1 Qt Function Comment Qt No Change Store 1 0 Reset Set Transparent 1 7.3 Gated Latches 293 Implementing D Latches in MAX PLUS II A D latch can be implemented in MAX PLUS II as a primitive in a Graphic Design File or in a VHDL design entity. It can also be created with a behavioral or structural description in a VHDL le. Figure 7.31 shows a D latch primitive in a MAX PLUS II Graphic Design File. Figure 7.32 shows a simulation of the latch. From 0 to 500 ns, ENABLE is HIGH and the latch is in the transparent mode (Q follows D). When ENABLE goes LOW, the last value of D (0) is stored until ENABLE goes high again, just before 800 ns. When ENABLE goes LOW again, a new value of D (1) is stored until the end of the simulation. LATCH d_latch.gdf d_latch.scf D ENA INPUT INPUT D Q ENA OUTPUT Q FIGURE 7.31 D-Latch in a MAX PLUS II Graphic Design File FIGURE 7.32 Simulation for a D Latch In VHDL, a PROCESS statement is concurrent, but the statements inside the PROCESS are sequential. In other words, anything described by a PROCESS acts like a separate component in a design entity. However, the interior of the component so described acts as a sequential circuit. Since the behavior of a D latch is sequential, its description can be created inside a PROCESS. (You can pull a latch out of a bin of parts and connect it in a circuit, but the inside of the part is sequential.) The following VHDL code describes a D latch. d_lch.vhd d_lch.scf d_lch.vhd D latch with active-HIGH level-sensitive enable ENTITY d_lch IS PORT( d, ena : IN q : OUT END d_lch; BIT; BIT); ARCHITECTURE a OF d_lch IS BEGIN PROCESS (d, ena) BEGIN IF (ena 1) THEN q d; END IF; END PROCESS; END a; 294 C H A P T E R 7 Introduction to Sequential Logic Another method, recommended by the MAX PLUS II documentation, is to instantiate a LATCH primitive in a VHDL le. The primitive is contained in the altera library, in a package called maxplus2. The component declaration for this primitive is: COMPONENT LATCH PORT (d : IN STD_LOGIC; ena : IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT; Since the component declaration is in the maxplus2 package, you do not have to declare it in the le in which you are using it. A VHDL le that uses the latch primitive is listed next. The component declaration uses STD LOGIC types, so we must include the type denitions in the ieee library (std_logic_1164 package). lch_prim.vhd lch_prim.vhd D latch with active-HIGH level-sensitive enable LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY lch_prim IS PORT( d_in, enable q_out END lch_prim; : IN : OUT STD_LOGIC; STD_LOGIC); ARCHITECTURE a OF lch_prim IS BEGIN Instantiate a latch from a MAX PLUS II primitive latch_primitive: latch PORT MAP (d d_in, ena enable, q q_out); END a; More information about MAX PLUS II primitives can be found in MAX PLUS II Help. In the Help menu, select Primitives. By clicking on the name of a particular primitive, you can determine whether it can be instantiated in a VHDL le and what its component declaration is, if available. EXAMPLE 7.5 FIGURE 7.33 Example 7.5 Sensor Placement in a Trafc Intersection A system for monitoring automobile trafc is set up at an intersection, with four sensors, placed as shown in Figure 7.33. Each sensor monitors trafc for a particular direction. When a car travels over a sensor, it produces a logic HIGH. The status of the sensor system 7.3 FIGURE 7.34 Example 7.5 D Latch Collection of Data 295 Data Logging System Sensors 1 Gated Latches D1 Q1 Q1 ENA 2 D2 Q2 Q2 ENA 3 D3 Q3 Q3 ENA 4 D4 Q4 Q4 ENA Timing Pulse is captured for later analysis by a set of D latches, as shown in Figure 7.34. A timing pulse enables the latches once every ve seconds and thus stores the system status as a snapshot of the trafc pattern. Figure 7.35 shows the timing diagram of a typical trafc pattern at the intersection. The D inputs show the cars passing through the intersection in the various lanes. Complete this timing diagram by drawing the Q outputs of the latches. How should we interpret the Q output waveforms? FIGURE 7.35 Example 7.5 Latch Conguration and Timing Diagram 296 C H A P T E R 7 Introduction to Sequential Logic SOLUTION Figure 7.35 shows the completed timing diagram. The ENABLE input synchronizes the random sensor pattern to a 5-second standard interval. A HIGH on any Q output indicates a car over a sensor at the beginning of the interval. For example, at the beginning of the rst interval, there is a car in the northbound lane (Q1) and one in the southbound lane (Q2). Similar interpretations can be made for each interval. Multi-bit Latches in VHDL KEY TERMS Library of Parameterized Modules (LPM) A standardized set of components for which certain properties can be specied when the component is instantiated. Parameter (in an LPM component) A property of a component that can be specied when the component is instantiated. Generic map A VHDL construct that maps one or more parameters of a component to a value for that instance of the component. Port map A VHDL construct that maps the name of a port in a component to the name of a port, variable, or signal in a design entity that uses the component. We can easily use VHDL to implement latches with multiple D inputs and Q outputs, but with a common ENABLE line, as in Figure 7.34. Three approaches are: 1. Use a behavioral description, as we did earlier for a single latch (d_lch.vhd). Use STD_LOGIC_VECTOR types for D and Q, rather than STD_LOGIC. 2. Altera recommends using a latch primitive or predened component, rather than creating your own latch structures. We can use multiple LATCH primitives, instantiated by a GENERATE statement, as we did for multiple instances of a full adder in Chapter 6. 3. Use a latch component from the Library of Parameterized Modules (LPM). These components are specied in the lpm_components package in the lpm library. Certain properties of an LPM component, such as the number of inputs or outputs, can be specied when the component is instantiated. These properties are referred to as parameters, and are listed in a generic map. For example, to make the latch output and input four bits wide, we set the parameter called LPM_WIDTH to a value of 4. The various parameters of an LPM component can be found in the LPM Quick Reference on the CD that accompanies this book or in the MAX PLUS II Help menu under Megafunctions/LPM. An input or output of an LPM component is called a port. A port map is used to make a correspondence between the port names in the component declaration and the port names used in the le containing the component. Since LPM components are declared in a separate package, we must refer to the MAX PLUS II Help or the LPM Quick Reference to determine the port names for a component. LPM components are instantiated the same as any other component. The three VHDL les that follow each specify a 4-bit latch with common enable, each using one of the above methods. Behavioral Description: ltch4bhv.vhd D latch with active-HIGH level-sensitive enable LIBRARY ieee; USE ieee.std_logic_1164.ALL; 7.3 ENTITY ltch4bhv PORT(d : enable : q : END ltch4bhv; ltch4bhv.vhd IS IN IN OUT Gated Latches 297 STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC; STD_LOGIC_VECTOR (3 downto 0)); ARCHITECTURE a OF ltch4bhv IS BEGIN PROCESS (enable, d) BEGIN IF (enable 1) THEN q d; END IF; END PROCESS; END a; 4 LATCH Primitives and a GENERATE Statement: ltch4prm.vhd D latch with active-HIGH level-sensitive enable ltch4prm.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY ltch4prm PORT(d_in : enable : q_out : END ltch4prm; IS IN IN OUT STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC; STD_LOGIC_VECTOR (3 downto 0)); ARCHITECTURE a OF ltch4prm IS BEGIN Instantiate a latch from a MAX PLUS II primitive latch4: FOR i IN 3 downto 0 GENERATE latch_primitive: latch PORT MAP (d d_in (i), ena enable, q q_out (i)); END GENERATE; END a; LPM Latch: ltch4lpm.vhd ltch4lpm.scf ltch4lpm.vhd 4-BIT D latch with active-HIGH level-sensitive enable Uses a latch component from the Library of Parameterized Modules (LPM) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY ltch4lpm PORT(d_in : enable : q_out : END ltch4lpm; IS IN IN OUT STD_LOGIC_VECTOR (3 downto 0); STD_LOGIC; STD_LOGIC_VECTOR (3 downto 0) ); 298 C H A P T E R 7 Introduction to Sequential Logic ARCHITECTURE a OF ltch4lpm IS BEGIN Instantiate latch from an LPM component latch4: lpm_latch GENERIC MAP (LPM_WIDTH 4) PORT MAP (data d_in, gate enable, q q_out); END a; All three les can be tested with the same simulation, shown in Figure 7.36. The inputs, d_in, represent a 4-bit group of signals, as do the outputs, q_out. An increasing count, from 5 to C (0101 to 1100) is applied to d_in. This count contains both states (0 and 1) for each input bit. For each applied input state, the output bus, q_out, does not change until the enable line goes HIGH. FIGURE 7.36 Simulation of a 4-bit D Latch SECTION 7.3 REVIEW PROBLEM 7.3 Write the VHDL code for a 16-bit latch with common active-HIGH enable, using MAX PLUS II latch primitives. 7.4 Edge-Triggered D Flip-Flops KEY TERMS Edge The HIGH-to-LOW (negative edge) or LOW-to-HIGH (positive edge) transition of a pulse waveform. CLOCK An enabling input to a sequential circuit that is sensitive to the positiveor negative-going edge of a waveform. Edge-triggered Enabled by the positive or negative edge of a digital waveform. Edge-sensitive Edge-triggered. Level-sensitive Enabled by a logic HIGH or LOW level. Flip-op A sequential circuit based on a latch whose output changes when its CLOCK input receives an edge. In Example 7.4, we saw how a shorter pulse width at the ENABLE input of a gated latch increased the chance of the output being synchronized to the ENABLE pulse waveform. This is because a shorter ENABLE pulse gives less chance for the SET and RESET inputs to change during the time the latch is enabled. A logical extension of this idea is to enable the latch for such a small time that the width of the ENABLE pulse is almost zero. The best approximation we can make to this is to allow changes to the circuit output only when an enabling, or CLOCK, input receives the edge of an input waveform. An edge is the part of a waveform that is in transition from 7.4 Edge-Triggered D Flip-Flops 299 LOW to HIGH (positive edge) or HIGH to LOW (negative edge), as shown in Figure 7.37. We can say that a device enabled by an edge is edge-triggered or edge-sensitive. FIGURE 7.37 Edges of a CLOCK Waveform Since the CLOCK input enables a circuit only while in transition, we can refer to it as a dynamic input. This is in contrast to the ENABLE input of a gated latch, which is levelsensitive or static, and will enable a circuit for the entire time it is at its active level. Latches vs. Flip-Flops KEY TERM Edge detector A circuit in an edge-triggered ip-op that converts the active edge of a CLOCK input to an active-level pulse at the internal latchs SET and RESET inputs. FIGURE 7.38 D Flip-Flop Logic Symbol A gated latch with a clock input is called a ip-op. Although the distinction is not always understood, we will dene a latch as a circuit with a level-sensitive enable (e.g., gated D latch) or no enable (e.g., NAND latch) and a ip-op as a circuit with an edge-triggered clock (e.g., D ip-op). A NAND or NOR latch is sometimes called an SR ip-op. By our denition this is not correct, since neither of these circuits has a clock input. (An SR ip-op would be like the gated SR latch of Figure 7.27 with a clock instead of an enable input.) The symbol for the D, or data, ip-op is shown in Figure 7.38. The D ip-op has the same behavior as a gated D latch, except that the outputs change only on the positive edge of the clock waveform, as opposed to the HIGH state of the enable input. The triangle on the CLK (clock) input of the ip-op indicates that the device is edge-triggered. Table 7.6 shows the function table of a positive edge-triggered D ip-op. Figure 7.39 shows the equivalent circuit of a positive edge-triggered D ip-op. The circuit is the same as the transparent latch of Figure 7.29, except that the enable input (called CLK in the ip-op) passes through an edge detector, a circuit that converts a positive edge to a brief positive-going pulse. (A negative edge detector converts a negative edge to a positive-going pulse.) Table 7.6 Function Table for a Positive Edge-Triggered D Flip-Flop CLK 0 1 FIGURE 7.39 D Flip-Flop Equivalent Circuit D 0 1 X X X Qt 0 1 Qt Qt Qt 1 Qt 1 0 Qt Qt Qt 1 Function Reset Set Inhibited Inhibited Inhibited 300 C H A P T E R 7 Introduction to Sequential Logic Figure 7.40 shows a circuit that acts as a simplied positive edge detector. Edge detection depends on the fact that a gate output does not switch immediately when its input switches. There is a delay of about 3 to 10 ns from input change to output change, called propagation delay. FIGURE 7.40 Positive Edge Detector When input x, shown in the timing diagram of Figure 7.40, goes from LOW to HIGH, the inverter output, x, goes from HIGH to LOW after a short delay. This delay causes both x and x to be HIGH for a short time, producing a high-going pulse at the circuit output immediately following the positive edge at x. When x returns to LOW, x goes HIGH after a delay. However, there is no time in this sequence when both AND inputs are HIGH. Therefore, the circuit output stays LOW after the negative edge of the input waveform. Figure 7.41 shows how the D ip-op circuit operates. When D 0 and the edge detector senses a positive edge at the CLK input, the output of the lower NAND gate steers a low-going pulse to the RESET input of the latch, thus storing a 0 at Q. When D 1, the upper NAND gate is enabled. The edge detector sends a high-going pulse to the upper steering gate, which transmits a low-going SET pulse to the output latch. This action stores a 1 at Q. FIGURE 7.41 Operation of a D Flip-Flop 7.4 EXAMPLE 7.6 Edge-Triggered D Flip-Flops 301 Figure 7.42 shows a MAX PLUS II Graphic Design File with a D latch and a D ipop connected to the same data input and clock. Create a MAX PLUS II simulation that illustrates the difference between the latch (level-sensitive enable) and the ip-op (edgetriggered clock). LATCH D CLK INPUT INPUT D Q ENA OUTPUT Q_latch DFF D PRN Q OUTPUT Q_flip_flop CLRN FIGURE 7.42 D Latch and D Flip-Flop SOLUTION The simulation, shown in Figure 7.43, has a 200 ns grid. Several points on the waveform indicate the similarities and differences between the latch and ip-op operation. FIGURE 7.43 Simulation showing the Difference between D Latch and D Flip Flop latch_ff.gdf latch_ff.scf 1. At 1.2 s, D goes HIGH. The latch output (Q_latch) and the ip-op output (Q_ ip_ op) both go HIGH at 1.4 s, since the beginning of the enable HIGH state and the positive edge of the CLK both correspond to this time. 2. D goes LOW at 2 s. Both Q outputs go LOW at 2.8 s since the positive edge of the CLK and its HIGH level occur at the same time. 3. The D input goes HIGH at 4.4 s, in the middle of a CLK pulse. Since the CLK line is HIGH, Q_ latch changes immediately. Q_ ip_ op does not change until the next positive edge, at 6 s. 4. D goes LOW at 7.8 s. Q_latch also changes at this time, since CLK is HIGH. Q_ ip_ op changes on the next positive edge, at 9.2 s. 302 C H A P T E R 7 Introduction to Sequential Logic Note that the latch output is in an unknown state until the rst CLK pulse, whereas the ip-op output is LOW, even before the rst CLK pulse. This is because Altera CPLDs have power-on reset circuitry that ensures that ip-op outputs in a CPLD are LOW immediately after power is applied to the device. The MAX PLUS II simulator accounts for this condition. EXAMPLE 7.7 Two positive edge-triggered D ip-ops are connected as shown in Figure 7.44a. Inputs D0 and CLK are shown in the timing diagram. Complete the timing diagram by drawing the waveforms for Q0 and Q1, assuming that both ip-ops are initially reset. FIGURE 7.44 Example 7.7 Circuit and Timing Diagram SOLUTION Figure 7.44b shows the output waveforms. Q0 follows D0 at each point where the clock input has a positive edge. One result of this is that the HIGH pulse on D0 between clock pulses 5 and 6 is ignored, since D0 0 on positive edges 5 and 6. Since D1 Q0 and Q1 follows D1, the waveform at Q1 is the same as at Q0, but delayed by one clock cycle. If Q0 changes due to CLK, we assume that the value of D1 is the same as Q0 just before the clock pulse. This is because delays within the circuitry of the ip-ops ensure that their outputs will not change for several nanoseconds after an applied clock pulse. Therefore, the level at D1 remains constant long enough for it to be clocked into the second ip-op. The data entering the circuit at D0 are moved, or shifted, from one ip-op to the next. This type of data movement, called serial shifting, is frequently used in data communication and digital arithmetic circuits. SECTION 7.4 REVIEW PROBLEM 7.4 Which part of a D ip-op accounts for the difference in operation between a D ipop and a D latch? How does it work? 7.5 Edge-Triggered JK Flip-Flops 303 7.5 Edge-Triggered JK Flip-Flops KEY TERM Toggle Alternate between opposite binary states with each applied clock pulse. A versatile and widely used sequential circuit is the JK ip-op. Figure 7.45 shows the logic symbols of a positive- and a negative-edge triggered JK ip-op. J acts as a SET input and K acts as a RESET input, with the output changing on the active clock edge in response to J and K. When J and K are both HIGH, the ip-op will toggle between opposite logic states with each applied clock pulse. The function tables of the devices in Figure 7.45 are shown in Table 7.7. Figure 7.46 shows the simplied circuit of a negative-edge triggered JK ip-op. The circuit is like that of a gated SR latch with an edge detector (an SR ip-op), except that there are two extra feedback lines from the latch outputs to the steering gate inputs. This extra feedback is responsible for the ip-ops toggling action. Figure 7.47 illustrates how the additional two lines cause the ip-op to toggle. The cross-feedback from Q to K and from Q to J enables one, but not both, of the steering gates. The edge detector just after the CLK input produces a short positive-going pulse upon detecting a negative edge on the CLK waveform. The enabled steering gate complements and transmits this pulse to the latch, activating either the set or reset function. This in turn changes the latch state and enables the opposite steering gate. Since all inputs of the steering gates must be HIGH to enable one of the latch functions, J and K must both be HIGH to sustain a repeated toggling action. Under these conditions, Q and Q alternately enable one of the steering gates. FIGURE 7.45 Edge-Triggered JK Flip-Flops Table 7.7 Function Tables for Edge-Triggered JK Flip-Flops CLK J K Qt 0 0 1 1 0 1 0 1 Qt 0 1 Qt 0 1 X X X X X X Qt Qt Qt 1 Qt Function CLK J K Qt 1 0 Qt No change Reset Set Toggle 0 0 1 1 0 1 0 1 Qt 0 1 Qt Qt 1 0 Qt No change Reset Set Toggle Qt Qt Qt Inhibited Inhibited Inhibited 0 1 X X X X X X Qt Qt Qt Qt Qt Qt Inhibited Inhibited Inhibited 1 Positive Edge-Triggered FIGURE 7.46 JK Flip-Flop Circuit (Simplied) Qt 1 Qt 1 Negative Edge-Triggered Function 304 C H A P T E R 7 Introduction to Sequential Logic FIGURE 7.47 Toggle Action of a JK Flip-Flop EXAMPLE 7.8 The J, K, and CLK inputs of a negative edge-triggered JK ip-op are as shown in the timing diagram in Figure 7.48. Complete the timing diagram by drawing the waveforms for Q and Q. Indicate which function (no change, set, reset, or toggle) is performed at each clock pulse. The ip-op is initially reset. FIGURE 7.48 Example 7.8 Timing Diagram (Negative-Edge-Triggered JK Flip-Flop) SOLUTION The completed timing diagram is shown in Figure 7.48. The outputs change only on the negative edges of the CLK waveform. Note that the same output sometimes results from different inputs. For example, the function at clock pulse 4 is reset and the function at pulses 5 and 6 is no change, but the Q waveform is LOW in each case. EXAMPLE 7.9 The toggle function of a JK ip-op is often used to generate a desired output sequence from a series of ip-ops. The circuit shown in Figure 7.49 is congured so that all ipops are permanently in toggle mode. Assume that all ip-ops are initially reset. Draw a timing diagram showing the CLK, Q0, Q1, and Q2 waveforms when eight clock pulses are applied. Make a table showing each 7.5 Edge-Triggered JK Flip-Flops 305 FIGURE 7.49 Example 7.9 Circuit combination of Q2, Q1, and Q0. What pattern do the outputs form over the period shown on the timing diagram? SOLUTION The circuit timing diagram is shown in Figure 7.50. All ip-ops are in toggle mode. Each time a negative clock edge is applied to the ip-op CLK input, the Q output will change to the opposite state. Table 7.8 Sequence of Outputs for Circuit in Figure 7.49 Clock Pulse Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 FIGURE 7.50 Example 7.9 Timing Diagram For ip-op 0, this happens with every clock pulse, since it is clocked directly by the CLK waveform. Each of the other ip-ops is clocked by the Q output waveform of the previous stage. Flip-op 1 is clocked by the negative edge of the Q0 waveform. Flip-op 2 toggles when Q1 goes from HIGH to LOW. Table 7.8 shows the ip-op outputs after each clock pulse. The outputs form a 3-bit number that counts from 000 to 111 in binary sequence, then returns to 000 and repeats. This ip-op circuit is called a 3-bit asynchronous counter. Synchronous versus Asynchronous Circuits KEY TERMS Synchronous Synchronized to the system clock. Asynchronous Not synchronized to the system clock The asynchronous counter in Figure 7.49 has the advantage of being simple to construct and analyze. However, because it is asynchronous (that is, not synchronized to a single clock), it is seldom used in modern digital designs. The main problem with this and other asynchronous circuits is that their outputs do not change at the same time, due to delays in the ip-ops. This yields intermediate states that are not part of the desired output sequence. 306 C H A P T E R 7 Introduction to Sequential Logic Figure 7.51 shows a simulation of a circuit similar to that in Figure 7.49. The outputs are shown separately, and also as a group labeled Q[2..0] that shows the combined binary value of the outputs. asynch3.gdf asynch3.scf FIGURE 7.51 Simulation of a 3-bit Asynchronous Counter Figure 7.52 shows a detail of the simulation at the point where the output goes from 7 to 0 (111 to 000). At 300 ns, the circuit output is 111. A negative clock edge, applied to ip-op 0, makes Q0 toggle after a short delay. The output is now 110 ( 610). The resulting negative edge on Q0 clocks ip-op 1, making it toggle, and yields a new output of 100 ( 410). The negative edge on Q1 clocks ip-op 2, making the output equal to 000 after a short delay. FIGURE 7.52 Detail of simulation for a 3-bit Asynchronous Counter Thus, the output goes through two short intermediate states that are not in the desired output sequence. Instead of going directly from 111 to 000, as in Figure 7.50, the output goes in the sequence 111110100000. We see in Figure 7.51 that the counter output goes through one or more intermediate transitions after each negative edge of the Q0 waveform. In other words, intermediate states arise whenever a change propagates through more than one ip-op. This happens because the ip-ops are clocked from different sources. VCC JKFF JKFF sync3.gdf J sync3.scf K CLK AND2 JKFF PRN PRN Q CLRN J K PRN Q CLRN J K Q CLRN INPUT OUTPUT OUTPUT OUTPUT FIGURE 7.53 3-bit Synchronous Counter Q2 Q1 Q0 7.5 Edge-Triggered JK Flip-Flops 307 Figure 7.53 shows the circuit of a 3-bit synchronous counter. Unlike the circuit in Figure 7.49, the ip-ops in this circuit are clocked from a common source. Therefore, ip-op delays do not add up through the circuit, and all the outputs change at the same time. Figure 7.54 shows a simulation of the circuit of Figure 7.53. Note that the outputs progress in a binary sequence, and there are no intermediate states. FIGURE 7.54 Simulation of a 3-bit Synchronous Counter The circuit works as follows: 1. Flip-op 0 is congured for toggle mode (J0K0 11). Since the ip-ops in Figure 7.53 are positive edge-triggered, Q0 toggles on each positive clock edge. 2. Q0 is connected to inputs J1 and K1. Since these inputs are tied together, only two states are possible: no change (JK 00) or toggle (JK 11). If Q0 1, Q1 toggles. Otherwise, it does not change. This results in a Q1 waveform that toggles at half the rate of Q0. 3. J2 and K2 are both tied to the output of an AND gate. The AND gate output is HIGH if both Q1 and Q0 are HIGH. This makes Q2 toggle, since J2K2 11. In all other cases, there is no change on Q2. The result of this is that Q2 toggles every fourth clock pulse, the only times when Q1 and Q0 are both HIGH. Asynchronous Inputs (Preset and Clear) KEY TERMS Synchronous inputs The inputs of a ip-op that do not affect the ip-ops Q outputs unless a clock pulse is applied. Examples include D, J, and K inputs. Asynchronous inputs The inputs of a ip-op that change the ip-ops Q outputs immediately, without waiting for a pulse at the CLK input. Examples include preset and clear inputs. Preset An asynchronous set function. Clear An asynchronous reset function. The D, J, and K inputs of the ip-ops examined so far are called synchronous inputs. This is because any effect they have on the ip-op outputs is synchronized to the CLK input. Another class of input is also provided on many ip-ops. These inputs, called asynchronous inputs, do not need to wait for a clock pulse to make a change at the output. The two functions usually provided are preset, an asynchronous set function, and clear, an asynchronous reset function. These functions are generally active LOW, and are abbreviated PRE and CLR. Figure 7.55 shows a modication to the JK ip-op of Figure 7.46. The PRE and CLR inputs have direct access to the latch gates of the ip-op and thus are not affected by the 308 C H A P T E R 7 Introduction to Sequential Logic FIGURE 7.55 PRE and CLR Inputs CLK input. They act exactly the same as the SET and RESET inputs of an SR latch and will override any synchronous input functions currently active. EXAMPLE 7.10 The waveforms for the CLK, J, K, PRE, and CLR inputs of a negative edge-triggered JK ip-op are shown in the timing diagram of Figure 7.56. Complete the diagram by drawing the waveform for output Q. FIGURE 7.56 Example 7.10 Waveforms SOLUTION The Q waveform is shown in Figure 7.56. The asynchronous inputs cause an immediate change in Q, whereas the synchronous inputs must wait for the next negative clock edge. If asynchronous and synchronous inputs are simultaneously active, the asynchronous inputs have priority. This occurs in two places: pulse 3 (K, PRE) and pulse 10 (J, CLR). The diagram shows the synchronous functions (no change, reset, set, and toggle) at each clock pulse and the asynchronous functions (preset and clear) at the corresponding transition points. The function table of a negative edge-triggered JK ip-op with preset and clear functions is shown in Table 7.9. 7.5 Edge-Triggered JK Flip-Flops 309 Table 7.9 Function Table of a Negative Edge-Triggered JK Flip-Flop with Preset and Clear Functions PRE CLR CLK J K Synchronous Functions 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Qt 0 1 Qt Qt 1 0 Qt No change Reset Set Toggle Asynchronous Functions 0 1 0 1 0 0 X X X X X X X X X 1 0 1 0 1 1 Preset Clear Forbidden 1 1 1 1 1 1 0 1 X X X X X X Qt Qt Qt Qt Qt Qt Inhibited Inhibited Inhibited X Qt Qt Dont care Present state of Q Next state of Q 1 Qt 1 Qt 1 Function HIGH-to-LOW transition LOW-to-HIGH transition NOTE If preset and clear functions are not used, they should be disabled by connecting them to logic HIGH (for active-LOW inputs). This prevents them from being activated inadvertently by circuit noise. The synchronous functions of some ip-ops will not operate properly unless PRE and CLR are HIGH. In MAX PLUS II, the asynchronous inputs of all ip-op primitives are set to a default level of HIGH. Using Asynchronous Reset in a Synchronous Circuit KEY TERM Master Reset An asynchronous reset input used to set a sequential circuit to a known initial state. Figure 7.57 shows an application of asynchronous clear inputs in a 3-bit synchronous counter. An input called RESET is tied to the asynchronous CLR inputs of all ipops. The counter output is set to 000 when the RESET line goes LOW. VCC JKFF PRN J K CLK RESET AND2 JKFF PRN PRN Q CLRN INPUT INPUT FIGURE 7.57 Synchronous Counter with Asynchronous Reset J K JKFF Q CLRN J K Q CLRN OUTPUT OUTPUT OUTPUT Q2 Q1 Q0 310 C H A P T E R 7 Introduction to Sequential Logic Figure 7.58 shows a set of simulation waveforms that illustrate the asynchronous clear function. When RESET is HIGH, the count proceeds normally. The positive clock edge at 440 ns drives the counter to state 011. The reset pulse at 460 ns sets the counter to 000 as soon as it goes LOW. On the next clock edge, the count proceeds from 000. FIGURE 7.58 Simulation of Synchronous Counter with Asynchronous Reset The function that sets all ip-ops in a circuit to a known initial state is sometimes called Master Reset. SECTION 7.5 REVIEW PROBLEM 7.5 What is the main difference between synchronous and asynchronous circuits, such as the two counters in Figures 7.49 and 7.53? What disadvantage is there to an asynchronous circuit? 7.6 Edge-Triggered T Flip-Flops KEY TERM T (toggle) ip-op A ip-op whose output toggles between HIGH and LOW states on each applied clock pulse when a synchronous input, called T, is active. In the section on the JK ip-op, we saw how that device can be set to toggle between HIGH and LOW output states. Other types of ip-ops can perform this function, as well. For example, Figure 7.59 shows a D ip-op congured for toggle operation. Since Q follows D and D Q in this circuit, then the ip-op output must change to its opposite state with each clock pulse. Figure 7.60 shows a MAX PLUS II simulation of this circuit. notg2d.gdf DFF notg2d.scf NOT PRN D CLK INPUT FIGURE 7.59 D Flip-Flop Congured for Toggle Function Q CLRN OUTPUT Q 7.6 Edge-Triggered T Flip-Flops 311 FIGURE 7.60 Simulation of D Flip-Flop in Toggle Mode It is seldom useful for ip-ops in synchronous circuits to be permanently congured in toggle mode. What made the JK ip-ops suitable elements for the synchronous counter in Figure 7.53 was the fact that sometimes they toggled and sometimes they didnt, depending on the current point in the output sequence of the counter. Figure 7.61 shows a D ip-op congured for a switchable toggle function. FIGURE 7.61 Switchable Toggle Function for a D Flip-Flop XOR DFF PRN T d_toggle.gdf CLK INPUT Q D INPUT OUTPUT Q CLRN d_toggle.scf The XOR gate acts as an inverter when the T input is HIGH and as a noninverting buffer when T is LOW. Thus, when T is LOW, the Q output is circulated back to the D input of the ip-op and the current value of Q is reloaded on the next clock pulse. When T is HIGH, the circuit acts like that of Figure 7.59 and toggles. A T ip-op has this equivalent function. Figure 7.62 shows the symbol of a T ipop in a MAX PLUS II Graphic Design File. A MAX PLUS II simulation in Figure 7.63 shows the operation of this device. The Q output toggles on each clock pulse when FIGURE 7.62 T Flip-Flop TFF T INPUT CLK INPUT t_ipop.gdf t_ipop.scf FIGURE 7.63 Simulation of T Flip-Flop PRN T Q CLRN OUTPUT Q 312 C H A P T E R 7 Introduction to Sequential Logic T is HIGH; otherwise Q retains its last value. A function table for the T ip-op is shown in Table 7.10. Table 7.10 Function Table for a T Flip-Flop CLK T 0 1 0 1 X X X Qt Qt Qt Qt Qt Qt 1 Function No Change Toggle Inhibited Inhibited Inhibited SECTION 7.6 REVIEW PROBLEM 7.6 Draw a circuit showing how the JK ip-ops in Figure 7.53 can be replaced by T ipops. 7.7 Timing Parameters KEY TERMS Setup time (tsu) The time required for the synchronous inputs of a ip-op to be stable before a CLK pulse is applied. Hold time (th) The time that the synchronous inputs of a ip-op must remain stable after the active CLK transition is nished. Pulse width (tw) Minimum time required for an active-level pulse applied to a CLK, CLR, or PRE input, as measured from the midpoint of the leading edge of the pulse to the midpoint of the trailing edge. Recovery time (trec) Minimum time from the midpoint of the trailing edge of a CLR or PRE pulse to the midpoint of an active CLK edge. Propagation delay The time required for the output of a digital circuit to change states after a change at one or more of its inputs. Flip-ops are electrical devices with inherent internal switching delays. As such, they have specic requirements for the timing of the input and output waveforms in order for them to operate reliably. We will examine the basic timing requirements for two small scale integration (SSI) devices: the 74LS107A JK ip-op (LSTTL family) and the 74HC107 JK ip-op (high-speed CMOS family). Figure 7.64 shows some of the basic timing requirements of a JK ip-op. Figure 7.64a illustrates the denitions of setup time (tsu), hold time (th), and pulse width (tW). The notation used for the J or K waveform indicates that the J or K input could be at either logic level and makes a transition to the opposite level at some point. The setup time is measured from the midpoint of the J or K transition to the midpoint of the active CLK edge. The logic level on the J or K input must be steady for at least this time for the ip-op to operate correctly. Setup time for both LSTTL and high-speed CMOS ipops is about 20 ns. Similarly, the hold time is measured from the midpoint of the CLK transition to the midpoint of the next J or K transition. The J or K level must be held steady for at least this time to ensure dependable operation. Hold time is 0 for LSTTL and 3 ns for a high-speed CMOS ip-op. The pulse width, tw, shows how long the CLK needs to be held LOW after an active CLK edge. Although the LOW level does not itself latch data into the ip-op, internal logic levels must reach a steady state before the device can accept a new clock pulse. This 7.7 Timing Parameters 313 FIGURE 7.64 Timing Parameters of a JK Flip-Flop minimum pulse width allows the necessary time for these internal transitions. The data sheet for a 74HC107 ip-op (high-speed CMOS) gives the clock pulse width as 16 ns; a data sheet for a 74LS107A device gives the value as 20 ns. Figure 7.64b shows the pulse width required at the CLR input, the propagation delay from CLR to Q and Q, and the recovery time that must be allowed from the end of a CLR pulse to the beginning of a CLK pulse. These times also apply to a pulse on the PRE input of a ip-op. Propagation delay is the result of internal electrical delays, primarily the charging and discharging of internal capacitances of the gate transistor junctions. The practical result of this is that a pulse at the CLR input makes Q go LOW, but not immediately; there is a delay of several nanoseconds between input pulse and output response. Propagation delay is dened by the direction of the output transition. The delay at Q, which goes from HIGH to LOW, is called tpHL. The delay at Q, which goes from LOW to HIGH when cleared, is called tpLH. Values for propagation delay from CLR to Q or Q are about 20 ns for LSTTL and 31 ns for high-speed CMOS. The recovery time, trec, allows the internal logic levels of the ip-op to reach a steady state after a CLR pulse. When the internal levels are stable, the device is ready to accept an active CLK edge. The recovery time for high-speed CMOS is 20 ns and 25 ns for an LSTTL device. (The LSTTL data sheet treats this parameter as a species of setup time; it is shown as setup time after the CLR is inactive. Same thing.) Finally, Figure 7.64c shows the propagation delay from CLK to Q. This is the time from the midpoint of an active CLK edge to the midpoint of a transition at Q caused by that CLK edge. The parameters are dened, as before, by the direction of the output transition. Propagation delays tpLH and tpHL are 20 ns, maximum, for a 74LS107A device and 25 ns for a 74HC107 ip-op. 314 C H A P T E R 7 Introduction to Sequential Logic The timing restrictions of a ip-op imply that there is a maximum CLK frequency beyond which the device will not operate reliably. Data sheets give these values as about 30 MHz for both LSTTL and high-speed CMOS devices. Table 7.11 summarizes the timing parameters of a 74LS107A ip-op and a 74HC107 device. The values for the latter device are for Vcc 4.5 V and a temperature range of 55C to 25C; they increase with a higher temperature range or a lower supply voltage. Table 7.11 Timing Parameters of an LSTTL and a High-Speed CMOS Flip-Flop Symbol Parameter 74LS107A 74HC107 tsu th tw Setup time Hold time CLR pulse width CLK pulse width Recovery time Propagation delay (from CLR) (from CLK) Maximum frequency 20 ns 0 ns 25 ns 20 ns 25 ns 20 ns 3 ns 16 ns 16 ns 20 ns 20 ns 20 ns 30 MHz 31 ns 25 ns 30 MHz trec tpHL tpLH fmax EXAMPLE 7.11 The timing diagrams in Figure 7.65 represent some of the timing parameters of a JK ipop. From these diagrams, determine the setup and hold times and the propagation delays from CLK and CLR to Q and Q. FIGURE 7.65 Example 7.11 Timing Parameters SOLUTION The values are as follows: Setup time 15 ns Hold time 5 ns Propagation delays (from CLK): 25 ns (tpLH and tpHL) (from CLR): 20 ns(tpLH and tpHL) Summary 315 SECTION 7.7 REVIEW PROBLEM 7.7 An active edge on the clock input of a JK ip-op makes Q go from HIGH-to-LOW. Name the timing parameter that measures the delay between the input and output change. Write the symbol for the parameter. SUMMARY 1. A combinational circuit combines inputs to generate a particular output logic level that is always the same, regardless of the order in which the inputs are applied. A sequential circuit might generate different outputs for the same inputs, depending on the sequence in which the inputs were applied. 2. An SR latch is a sequential circuit with SET (S) and RESET (R) inputs and complementary outputs (Q and Q). By denition, a latch is set when Q 1 and reset when Q 0. 3. A latch sets when its S input activates. When S returns to the inactive state, the latch remains in the set condition until explicitly reset by activating its R input. 4. A latch can have active-HIGH inputs (designated S and R) or active-LOW inputs (designated S and R). 5. Two basic SR latch circuits are the NAND latch and the NOR latch, each consisting of two gates with cross-coupled feedback. In the NAND form, we draw the gates in their DeMorgan equivalent form so that each circuit has ORshaped gates, inversion from input to output, and feedback to the opposite gate. 6. A NOR latch has active-HIGH inputs. It is described by the following function table: S R 0 0 1 1 0 1 0 1 Qt 1 Qt 0 1 0 Qt 1 Qt 1 0 0 Function No change Reset Set Forbidden 7. A NAND latch has active-LOW inputs and is described by the following function table: S R 0 0 1 1 0 1 0 1 Qt 1 1 0 Qt 1 Qt 1 0 1 Qt 1 Function Forbidden Set Reset No change 8. A NAND latch can be used as a switch debouncer for a switch with a grounded common terminal, a normally open, and a normally closed contact. When the switch operates, one contact closes, resetting the latch on the rst bounce. Further bounces are ignored. When the switch returns to its normal position, it sets the latch on the rst bounce and further bounces are ignored. 9. A gated SR latch controls the times when a latch can switch. The circuit consists of a pair of latch gates and a pair of steering gates. The steering gates are enabled or inhibited by a control signal called ENABLE. When the steering gates are enabled, they can direct a set or reset pulse to the latch gates. When inhibited, the steering gates block any set or reset pulses to the latch gates so the latch output cannot change. 10. A gated D (data) latch can be constructed by connecting opposite logic levels to the S and R inputs of an SR latch. Since S and R are always opposite, the D latch has no forbidden state. The no change state is provided by the inhibit property of the ENABLE input. 11. In a gated D latch (or transparent latch), Q follows D when ENABLE is active. This is the transparent mode of the latch. When ENABLE is inactive, the latch stores the last value of D. 12. A D latch can be described in VHDL by an IF statement within a PROCESS. The PROCESS statement in VHDL is concurrent, but the statements inside the PROCESS are sequential. 13. A D latch can also be implemented in VHDL by instantiating a LATCH primitive as a component in a VHDL design entity or by instantiating a component called lpm_latch from the Library of Parameterized Modules (LPM). 14. An LPM component is a standard component with certain properties, called parameters, that can be specied when the component is instantiated. The inputs and outputs of an LPM component are called ports. Parameter values are assigned in the generic map of a component instantiation statement. Component port names are associated with user port names in the port map of a component instantiation statement. 15. A ip-op is like a gated latch that responds to the edge of a pulse applied to an enable input called CLOCK. A ip-op output will change only when the input makes a transition from LOW to HIGH (for a positive edge-triggered device) or HIGH to LOW (for a negative edge-triggered device). 16. In a positive edge-triggered D ip-op, Q follows D when there is a positive edge on the clock input. 17. D ip-ops are used primarily for data storage and transfer. 18. A JK ip-op has two synchronous inputs, called J and K. J acts as an active-HIGH set input. K acts as an active-HIGH reset function. When both inputs are asserted, the ip-op toggles between 0 and 1 with each applied clock pulse. 19. The toggle function in a JK ip-op is implemented with additional cross-coupled feedback from the latch gate outputs to the steering gate inputs. 20. A chain of JK ip-ops can implement an asynchronous binary counter if the Q of each ip-op is connected to the 316 21. 22. 23. 24. C H A P T E R 7 Introduction to Sequential Logic clock input of the next. Although this is an easy way to create a counter, it is seldom used because internal ip-op delays result in unwanted intermediate states in the count sequence. JK ip-ops can be combined with a network of logic gates to make a synchronous binary counter. The gates are connected in such a way that each ip-op toggles when all previous bits are HIGH; otherwise the ip-ops are in a no change state. Although more complex than an asynchronous counter, a synchronous counter is free of unwanted intermediate states. Many ip-ops are provided with asynchronous preset (set) and clear (reset) functions. Since these functions are connected directly to the latch gates of a ip-op, they act immediately, without waiting for the clock. In most cases, these functions are active-LOW. Asynchronous inputs, such as preset and clear, are usually designed so that they will override the synchronous inputs, such as D or JK. Unused asynchronous inputs should be disabled by tying them to a logic HIGH (for an active-LOW input). Flip-op primitives in MAX PLUS II automatically have their asyn- 25. 26. 27. 28. 29. 30. chronous inputs connected to HIGH unless otherwise specied by a design entry le. The outputs of a T (toggle) ip-op toggle with each clock pulse when the T input is HIGH and do not change when T is LOW. Several important timing parameters for a ip-op include: setup and hold time, propagation delay, minimum pulse width, and recovery time. Setup time is the time before a clock edge that a synchronous input must be held steady. Hold time is the time after an applied clock edge that an input level must be held constant. Propagation delay is the time for an input change, such as on CLK or CLR, to have an effect on an output, such as Q. Propagation time is always indicated with respect to the change in output level: tpLH for a LOW-to-HIGH output transition and tpHL for a HIGH-to-LOW output change. Minimum pulse width, tw, indicates how long a CLK or CLR input must be held after an active edge or level is applied before returning to the original level. Recovery time is the minimum time required from the end of an active level on one input (such as CLR) to an active CLK edge. GLOSSARY Asynchronous Not synchronized to the system clock. Asynchronous inputs The inputs of a ip-op that change the ip-ops Q outputs immediately, without waiting for a pulse at the CLK input. Examples include preset and clear inputs. Library of Parameterized Modules (LPM) A standardized set of components for which certain properties can be specied when the component is instantiated. Clear An asynchronous reset function. Master Reset An asynchronous reset input used to set a sequential circuit to a known initial state. CLOCK An enabling input to a sequential circuit that is sensitive to the positive- or negative-going edge of a waveform. Parameter (in an LPM component) A property of a component that can be specied when the component is instantiated. Edge The HIGH-to-LOW (negative edge) or LOW-to-HIGH (positive edge) transition of a pulse waveform. Preset An asynchronous set function. Edge detector A circuit in an edge-triggered ip-op that converts the active edge of a CLOCK input to an active-level pulse at the internal latchs SET and RESET inputs. Edge-sensitive Edge-triggered. Edge-triggered Enabled by the positive or negative edge of a digital waveform. Flip-op A sequential circuit based on a latch whose output changes when its CLOCK input receives either an edge or a pulse, depending on the device. Gated SR latch An SR latch whose ability to change states is controlled by an extra input called the ENABLE input. Generic map A VHDL construct that maps one or more parameters of a component to a value for that instance of the component. Port map A VHDL construct that maps the name of a port in a component to the name of a port, variable, or signal in a design entity that uses the component. Propagation delay The time required for the output of a digital circuit to change states after a change at one or more of its inputs. Pulse width (tw) Minimum time required for an active-level pulse applied to a CLK, CLR, or PRE input, as measured from the midpoint of the leading edge of the pulse to the midpoint of the trailing edge. Recovery time (trec) Minimum time from the midpoint of the trailing edge of a CLR or PRE pulse to the midpoint of an active CLK edge. Reset 1. The stored LOW state of a latch circuit. 2. A latch input that makes the latch store a logic 0. Hold time (th) The time that the synchronous inputs of a ip-op must remain stable after the active CLK transition is nished. Sequential circuit A digital circuit whose output depends not only on the present combination of inputs, but also on the history of the circuit. Latch A sequential circuit with two inputs called SET and RESET, which make the latch store a logic 0 (reset) or 1 (set) until actively changed. Set 1. The stored HIGH state of a latch circuit. 2. A latch input that makes the latch store a logic 1. Level-sensitive Enabled by a logic HIGH or LOW level. Setup time (tsu) The time required for the synchronous inputs of a ip-op to be stable before a CLK pulse is applied. Problems Steering gates Logic gates, controlled by the ENABLE input of a gated latch, that steer a SET or RESET pulse to the correct input of an SR latch circuit. Synchronous Synchronized to the system clock. Synchronous inputs The inputs of a ip-op that do not affect the ip-ops Q outputs unless a clock pulse is applied. Examples include D, J, and K inputs. 317 Toggle Alternate between binary states with each applied clock pulse. T (toggle) ip-op A ip-op whose output toggles between HIGH and LOW states on each applied clock pulse when a synchronous input, called T, is active. Transparent latch (gated D latch) A latch whose output follows its data input when its ENABLE input is active. PROBLEMS Section 7.1 Latches 7.1 7.2 Complete the timing diagram in Figure 7.66 for the active-HIGH latch shown. The latch is initially set. Repeat Problem 7.1 for the timing diagram shown in Figure 7.67. FIGURE 7.66 Problem 7.1 Timing Diagram FIGURE 7.67 Problem 7.2 Timing Diagram FIGURE 7.68 Problem 7.3 Timing Diagram FIGURE 7.69 Problem 7.4 Latch for Motor Starter 7.3 Complete the timing diagram in Figure 7.68 for the active-LOW latch shown. 7.4 Figure 7.69 shows an active-LOW latch used to control a motor starter. The motor runs when Q 1 and stops when Q 0. (Problem continues . . .) 318 C H A P T E R 7 Introduction to Sequential Logic The motor is housed in a safety enclosure that has an access hatch for service. A safety interlock prevents the motor from running when the hatch is open. The HATCH switch opens when the hatch opens, supplying a logic HIGH to the circuit. The START switch is a normally open momentary-contact pushbutton (LOW when pressed). The STOP switch is a normally closed momentary-contact pushbutton (HIGH when pressed). 7.8 Figure 7.71 shows the input waveforms to a NOR latch. Draw the corresponding output waveforms. 7.9 Figure 7.72 represents two input waveforms to a latch circuit. a. Draw the outputs Q and Q if the latch is a NAND latch. b. Draw the output waveforms if the latch is a NOR latch. Draw the timing diagram of the circuit, showing START, STOP, HATCH, S, R, and Q for the following sequence of events: (Note that in each case, the waveforms will produce the forbidden state at some point. Even under this condition, it is still possible to produce unambiguous output waveforms. Refer to Figures 7.18 and 7.19 for guidance.) a. START is pressed and released. b. The hatch cover is opened. c. START is pressed and released. 7.10 a. Draw a timing diagram for a NAND latch showing each of the following sequences of events: d. The hatch cover is closed. i. S and R are both LOW; S goes HIGH before R. e. START is pressed and released. ii. S and R are both LOW; R goes HIGH before S. f. STOP is pressed and released. iii. S and R are both LOW; S and R go HIGH simultaneously. Briey describe the functions of the three switches and how they affect the motor operation. b. State why S R NAND latch. Section 7.2 NAND/NOR Latches 7.5 7.6 7.7 Draw a NAND latch, correctly labeling the inputs and outputs. Describe the operation of a NAND latch for all four possible combinations of S and R. Draw a NOR latch, correctly labeling the inputs and outputs. Describe the operation of a NOR latch for all four possible combinations of S and R. The timing diagram in Figure 7.70 shows the input waveforms of a NAND latch. Complete the diagram by showing the output waveforms. FIGURE 7.70 Problem 7.7 Timing Diagram FIGURE 7.71 Problem 7.8 Input Waveforms to a NOR Latch FIGURE 7.72 Problem 7.9 Input Waveforms to a Latch 0 is a forbidden state for the c. Briey explain what the nal result is for each of the above transitions. 7.11 a Draw a timing diagram for a NOR latch showing each of the following sequences of events: i. S and R are both HIGH; S goes LOW before R. ii. S and R are both HIGH, R goes LOW before S. iii. S and R are both HIGH, S and R go LOW simultaneously. Problems b. Draw a NAND latch circuit that can be used to eliminate this mechanical bounce, and briey explain how it does so. b. Briey explain what the nal result is for each of the transitions listed in part a of this question. c. State why S latch. 7.12 R 1 is a forbidden state for the NOR Figure 7.73 shows the effect of mechanical bounce on the switching waveforms of a single-pole double-throw (SPDT) switch. a. Briey explain how this effect arises. FIGURE 7.73 Problem 7.12 Effect of Mechanical Bounce on a SPDT Switch FIGURE 7.74 Problem 7.13 Gated Latch FIGURE 7.75 Problem 7.14 Gated Latch 319 Section 7.3 Gated Latches 7.13 Complete the timing diagram for the gated latch shown in Figure 7.74. 7.14 Complete the timing diagram for the gated latch shown in Figure 7.75. 320 7.15 C H A P T E R 7 Introduction to Sequential Logic A pump motor can be started at two different locations with momentary-contact pushbuttons S1 and S2. It can be stopped by momentary-contact pushbuttons ST1 and ST2. As in Problem 7.4, a RUN input on the motor controller must be kept HIGH to keep the motor running. After the motor is stopped, a timer prevents the motor from starting for 5 minutes. Draw a circuit block diagram showing how an SR latch and some additional gating logic can be used in FIGURE 7.76 Problem 7.16 Waveforms FIGURE 7.77 Problem 7.17 Waveforms such an application. The timer can be shown as a block activated by the STOP function. Assume that the timer output goes HIGH for 5 minutes when activated. 7.16 The S and R waveforms in Figure 7.76 are applied to two different gated latches. The ENABLE waveforms for the latches are shown as EN1 and EN2. Draw the output waveforms Q1 and Q2, assuming that S, R, and EN are all active HIGH. Which output is least prone to synchronization errors? Why? Problems 7.17 7.18 S SSW SW WSW W WNW NW NNW Figure 7.77 represents the waveforms of the EN and D inputs of a 4-bit transparent latch. Complete the timing diagram by drawing the waveforms for Q1 to Q4. An electronic direction nder aboard an aircraft uses a 4bit number to distinguish 16 different compass points as follows: Direction N NNE NE ENE E ESE SE SSE Degrees 0/360 22.5 45 67.5 90 112.5 135 157.5 Gray Code 0000 0001 0011 0010 0110 0111 0101 0100 180 202.5 225 247.5 270 295.5 315 337.5 1100 1101 1111 1110 1010 1011 1001 1000 The output of the direction nder is stored in a 4-bit latch so that the aircraft ight path can be logged by a computer. The latch is periodically updated by a continuous pulse on the latch enable line. Figure 7.78 shows a sample reading of the direction nders output as presented to the latch. (Problem continues . . .) EN D1 D2 D3 D4 Q1 Q2 Q3 Q4 4-bit Latch Q1 W NN WN W Q4 W D4 W WS Q3 E D3 N W E S S SSW FIGURE 7.78 Problem 7.18 Direction Finder and Sample Output EN E SS EN S W ESE Q2 NNE E EN D2 Data converter N E N D1 Compass 321 322 C H A P T E R 7 Introduction to Sequential Logic count for any differences between the Q1 and Q2 waveforms. a. Complete the timing diagram by lling in the data for the Q outputs. b. Based on the completed timing diagram of Figure 7.78, make a rough sketch of the aircrafts ight path for the monitored time. 7.22 Complete the timing diagram for a positive edge-triggered D ip-op if the waveforms shown in Figure 7.80 are applied to the ip-op inputs. 7.19 Write a VHDL le for an 8-bit latch, using LATCH primitives. Create a simulation le that demonstrates the operation of all eight bits. 7.23 Repeat Problem 7.22 for the waveforms shown in Figure 7.81. 7.20 Write a VHDL le for an 8-bit latch, using a component from the Library of Parameterized Modules. Create a simulation le that tests the latch for all eight bits. 7.24 Repeat Problem 7.22 for the waveforms shown in Figure 7.82. 7.25 Draw a logic diagram of a D ip-op congured for toggle mode. (Hint: The D input must always be the opposite of the Q output.) 7.26 Write a VHDL le that denes a 12-bit D ip-op with a clock common to all ip-ops, using MAX PLUS II primitives. The component declaration for the DFF component is as follows: Section 7.4 Edge-Triggered D Flip-Flops 7.21 The waveforms in Figure 7.79 are applied to the inputs of a positive edge-triggered D ip-op and a gated D latch. Complete the timing diagram where Q1 is the output of the ip-op and Q2 is the output of the gated latch. Ac- FIGURE 7.79 Problem 7.21 Waveforms FIGURE 7.80 Problem 7.22 Waveforms FIGURE 7.81 Problem 7.23 Waveforms Problems 323 FIGURE 7.82 Problem 7.24 Waveforms 7.27 COMPONENT DFF PORT (d : IN STD_LOGIC; clk : IN STD_LOGIC; clrn : IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC; END COMPONENT; Section 7.5 Edge-Triggered JK Flip-Flops 7.28 The waveforms in Figure 7.83 are applied to a negative edge-triggered JK ip-op. Complete the timing diagram by drawing the Q waveform. 7.29 Repeat Problem 7.28 for the waveforms in Figure 7.84. 7.30 Disregard the clrn (active-LOW clear) and prn (active-LOW preset) ports for this problem. (Hint: you may have to use a component declaration in your le that only declares the ports d, clk, and q.) FIGURE 7.83 Problem 7.28 Waveforms Write a VHDL le that creates a 12-bit D ip-op, using the LPM component lpm_ff. (This component is instantiated as a D ip-op by default. The required LPM component port names are: data, clock, and q.) Given the inputs x, y, and z to the circuit in Figure 7.85, draw the waveform for output Q. CLK J K Q FIGURE 7.84 Problem 7.29 Waveforms CLK J K Q FIGURE 7.85 Problem 7.30 Inputs to Circuit x y CLK z CLK x y z Q Q J CLK K Q 324 C H A P T E R 7 Introduction to Sequential Logic FIGURE 7.86 Problem 7.31 Flip-Flops 7.31 7.32 Assume that all ip-ops in Figure 7.86 are initially set. Draw a timing diagram showing the CLK, Q0, Q1, and Q2 waveforms when eight clock pulses are applied. Make a table showing each combination of Q2, Q1, and Q0. What pattern do the outputs form over the period shown on the timing diagram? Refer to the JK ip-op circuit in Figure 7.87. Is the circuit synchronous or asynchronous? Explain your answer. teen clock pulses are applied by making a table showing the sequence of states of Q3Q2Q1Q0, beginning at 0000. 7.34 Draw a timing diagram showing the sequence of states from the table derived in Problem 7.33. 7.35 The waveforms shown in Figure 7.88 are applied to a negative edge-triggered JK ip-op. The ip-ops Preset and Clear inputs are active LOW. Complete the timing diagram by drawing the output waveforms. 7.33 Assume all flip-flops in the circuit in Figure 7.87 are reset. Analyze the operation of the circuit when six- AND2 AND3 VCC JKFF JKFF PRN J K CLK J Q K CLRN INPUT JKFF PRN Q CLRN J K PRN Q CLRN J K Q CLRN OUTPUT OUTPUT OUTPUT OUTPUT FIGURE 7.87 Problem 7.32 Flip-Flop Circuit FIGURE 7.88 Problem 7.35 Waveforms JKFF PRN CLK J K PRE CLR Q Q q3 q2 q1 q0 Problems 7.36 Create a MAX PLUS II Graphic Design File for the synchronous circuit in Figure 7.87. Modify the circuit to add an asynchronous Master Reset function. Create a simulation le to verify the circuit operation. and preset (PRN) inputs. Create a simulation le to verify the operation of your design. Repeat Problem 7.35 for the waveforms in Figure 7.89. 7.37 7.38 The term asynchronous is sometimes used to refer to the conguration of a circuit (e.g., a 3-bit asynchronous counter) and sometimes to a type of input to a device (e.g., an asynchronous clear input). Briey explain how these two usages are similar and how they are different. 7.41 Modify the gdf created in Problem 7.37 to include a Master Reset function and an asynchronous preset function that will set the state of the circuit to Q3Q2Q1Q0 1010 when activated. Create a simulation le to verify the circuit operation. 7.39 7.40 Write a VHDL le for a 12-bit D ip-op that uses MAX PLUS II DFF primitives, similar to that in Problem 7.26. Include active-LOW asynchronous clear (CLRN) FIGURE 7.89 Problem 7.36 Waveforms CLK J K PRE CLR Q CLK T Q FIGURE 7.90 Problem 7.42 Timing Diagram CLK T Q FIGURE 7.91 Problem 7.43 Timing Diagram 325 Write a VHDL le for a 12-bit D ip-op with asynchronous preset and clear, using the LPM component lpm_ff, similar to that in Problem 7.27. Required ports: data, clock, aclr (asynchronous clear), aset (asynchronous set), and q. Ports aset and aclr are active-HIGH. Add two signals to the VHDL design to make them active-LOW. Create a simulation le to verify the operation of your design. Section 7.6 Edge-Triggered T Flip-Flops 7.42 The T and CLK waveforms for a positive-edge triggered T ip-op is shown in Figure 7.90. Complete the timing diagram. 7.43 The T and CLK waveforms for a positive-edge triggered T ip-op is shown in Figure 7.91. Complete the timing diagram. 326 C H A P T E R 7 Introduction to Sequential Logic 7.44 Refer to the synchronous circuit in Figure 7.87. Create a MAX PLUS II Graphic Design File for a circuit with the same function, using T ip-ops rather than JK ipops. Include an asynchronous reset input in the circuit. Create a simulation le to test the operation of the circuit. 7.45 Write a VHDL le that implements the circuit you drew in Problem 7.44. Use TFF primitives in the design. Section 7.7 Timing Parameters 7.46 Use a TTL or high-speed CMOS data sheet, as appropriate, to look up the setup and hold times of the following devices: a. 74LS74A b. 74HC76 7.49 Write names and values of the JK ip-op timing parameters illustrated in Figure 7.92. FIGURE 7.92 Problem 7.49 Timing Parameters 7.50 Repeat Problem 7.49 for the timing diagram in Figure 7.93. c. 74LS76A d. 74LS107A e. 74ALS112A f. 74HC112 7.47 Draw a timing diagram showing the setup and hold times for a 74LS76A ip-op. 7.48 Draw timing diagrams (to scale) showing setup and hold times, minimum CLK and CLR pulse widths, recovery time, and propagation delay times from CLK and CLR for both 74LS107A and 74HC107 ip-ops. FIGURE 7.93 Problem 7.50 Timing Diagram ANSWERS TO SECTION REVIEW PROBLEMS Section 7.1 7.1 The latch resets (i.e., Q goes LOW) upon receiving the rst reset pulse. At that point, the latch is already reset, so further pulses are ignored. Section 7.2 7.2 The NOR latch has active-HIGH inputs. If you make both inputs HIGH, you are attempting to set and reset the latch at the same time, which is a contradictory action. A NAND latch has active-LOW inputs. Therefore, if both inputs are HIGH, neither the set nor reset function activates and there is no change on the latch output. Section 7.3 7.3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY lch16prm PORT(d_in enable q_out END lchl6prm; IS : IN STD_LOGIC_VECTOR (15 downto 0); : IN STD_LOGIC; : OUT STD_LOGIC_VECTOR (15 downto 0) ); ARCHITECTURE a OF lch16prm IS BEGIN Instantiate a latch from a MAX PLUS II primitive latch4: FOR i IN 15 downto 0 GENERATE latch_primitive: latch PORT MAP (d d in (i), ena enable, q q out (i) ); END GENERATE; END a; Section 7.4 7.4 The edge detector circuit in the clock circuit accounts for the operational difference between a D ip-op and a D latch. It works by using the difference in internal delay times between the gates that comprise the ip-ops clock input circuit. Section 7.5 7.5 The ip-ops in asynchronous circuits are not all clocked at the same time; they are asynchronous with respect to the system clock. The ip-ops in a synchronous circuit have a common clock connection, which makes them synchronous to the system clock. The disadvantage to asynchronous circuits is that the internal delays of ip-ops can lead to unwanted intermediate states, since the ip-ops do not all change at the same time. Answers to Review Section 327 Section 7.6 Section 7.7 7.6 The circuit is shown in Figure 7.94. 7.7 The parameter is called propagation delay. For the specied output transition, the symbol is tpHL. AND2 VCC TFF TFF PRN T Q CLRN CLK TFF PRN T PRN Q CLRN T Q CLRN INPUT OUTPUT OUTPUT OUTPUT FIGURE 7.94 Solution to Section Review Problem 7.6 Q2 Q1 Q0 CHAPTER 8 Introduction to Programmable Logic Architectures OUTLINE CHAPTER OBJECTIVES 8.1 Upon successful completion of this chapter, you will be able to: Draw a diagram showing the basic hardware conventions for a sum-ofproducts-type programmable logic device. Describe the structure of a programmable array logic (PAL) AND matrix. Draw fuses on the logic diagram of a PAL to implement simple logic functions. Describe the structures of combinational, programmable polarity, and registered PAL outputs. Determine the number and type of outputs from a PAL/GAL part number. Explain the structure of an output logic macrocell (OLMC). State differences between Universal PAL and generic array logic (GAL) and standard PAL. Interpret the logic diagrams of Universal PAL and GAL devices to determine the number of outputs and product terms and the type of control signals available in a device. Interpret block diagrams to determine the basic structure of an Altera MAX7000S CPLD, including macrocell conguration, Logic Array Blocks (LABs), control signals, and product term expanders. State the differences between PLDs based on sum-of-products (SOP) architecture versus look-up table (LUT) architecture. Interpret block diagrams to determine the basic structure of a logic element in an Altera FLEX10K CPLD, including look-up tables, cascade chains, carry chains, and control signals. Interpret block diagrams to determine how a logic element in a FLEX10K device relates to the overall structure of the device. Interpret block diagrams to determine how logic array blocks and embedded array blocks relate to the overall structure of a FLEX10K CPLD. 8.2 8.3 8.4 8.5 8.6 8.7 Programmable Sum-of-Products Arrays PAL Fuse Matrix and Combinational Outputs PAL Outputs with Programmable Polarity PAL Devices with Programmable Polarity Universal PAL and Generic Array Logic MAX7000S CPLD FLEX10K CPLD I n the past several chapters, we have been using Alteras MAX PLUS II software to make circuit designs for downloading into a complex programmable logic device (CPLD). We have treated this device as a black boxsomething whose function we design, but whose structure we do not really understand. In this chapter, we will look inside the box. I 329 330 C H A P T E R 8 Introduction to Programmable Logic Architectures Before we examine the structure of an Altera MAX7000S CPLD, we will look at the internal structure of several simpler devices that are based on similar technologies, such as the PAL16L8 and PAL16R8 low-density PLDs (largely for an historical overview), the PALCE16V8, and the GAL22V10. These devices are based on programmable matrices of sum-of-products (SOP) circuits, as is the Altera MAX series of devices. The main programming element is the EEPROM (electrically erasable programmable read-only memory) cell. EEPROM-based devices will retain their programmed data when power is removed from the device. The Altera FLEX series of CPLDs is based on another technology altogether. It stores logic functions in look-up tables (LUTs) that act as truth tables with four input bits. The main logic element of the FLEX series is the SRAM (static random access memory) cell. SRAM-based CPLDs must have their programming data loaded every time they are powered up. They have the advantage of being faster than EEPROM devices, with a higher bit capacity. 8.1 Programmable Sum-of-Products Arrays KEY TERMS Product line A single line on a logic diagram used to represent all inputs to an AND gate (i.e., one product term) in a PLD sum-of-products array. Input line A line that applies the true or complement form of an input variable to the AND matrix of a PLD. PAL Programmable array logic. Programmable logic with a xed OR matrix and a programmable AND matrix. The original programmable logic devices (PLDs) consisted of a number of AND and OR gates organized in sum-of-products (SOP) arrays in which connections were made or broken by a matrix of fuse links. An intact fuse allowed a connection to be made; a blown fuse would break a connection. Figure 8.1a shows a simple fuse matrix connected to a 4-input AND gate. True and complement forms of two variables, A and B, can be connected to the AND gate in any combination by blowing selected fuses. In Figure 8.1a, fuses for A and B are blown. The output of the AND gate represents the product term AB, the logical product of the intact fuse lines. Figure 8.1b shows a more compact notation for the AND-gate fuse matrix. Rather than showing each AND input individually, a single line, called the product line, goes into the AND gate, crossing the true and complement input lines. An intact connection to an input line is shown by an X on the junction between the input line and the product line. A symbol convention similar to Figure 8.1b has been developed for programmable logic. Figure 8.2 shows an example. The circuit shown in Figure 8.2 is a sum-of-products network whose Boolean expression is given by: F ABC ABC The product terms are accumulated by the AND gates as in Figure 8.1b. A buffer having true and complement outputs applies each input variable to the AND matrix, thus producing two input lines. Each product line can be joined to any input line by leaving the corresponding fuse intact at the junction between the input and product lines. If a product line, such as for the third AND gate, has all its fuses intact, we do not show the fuses on that product line. Instead, this condition is indicated by an X through the gate. The output of the third AND gate is a logic 0, since (A A B B C C) 0. This is necessary to enable the OR gate output: ABC ABC 0 ABC ABC 8.1 FIGURE 8.1 Crosspoint Fuse Matrix A Programmable Sum-of-Products Arrays A B 331 B Intact AB Blown a. Crosspoint fuse matrix ( A and B intact ) A A B B AB b. PLD notation for fuse matrix Unconnected inputs are HIGH (e.g., A 1 B 1 1 C A B C for the the rst product line). If the unused AND output was HIGH, the function F would be: ABC+ABC+1=1 The conguration in Figure 8.2, with a programmable AND matrix and a hardwired OR connection, is called PAL (programmable array logic) architecture.1 Since any combinational logic function can be written in SOP form, any Boolean function can be programmed into these PLDs by blowing selected fuses. The programming FIGURE 8.2 PLD Symbology 1 PAL is a registered trademark of Vantis Semiconductor. 332 C H A P T E R 8 Introduction to Programmable Logic Architectures is done by special equipment and its associated software. The hardware and software selects each fuse individually and applies a momentary high-current pulse if the fuse is to be blown. The main problem with fuse-programmable PLDs is that they can be programmed one time only; if there is a mistake in the design and/or programming or if the design is updated, we must program a new PLD. More recent technology has produced several types of erasable PLDs, based not on fuses but on oating-gate metal-oxidesemiconductor transistors. These transistors also form the basis of memory technologies such as electrically erasable programmable read-only memory (EEPROM or E2PROM). 8.2 PAL Fuse Matrix and Combinational Outputs KEY TERMS JEDEC Joint Electron Device Engineering Council JEDEC le An industry-standard form of text le indicating which fuses are blown and which are intact in a programmable logic device. Text le An ASCII-coded document stored on disk. Checksum An error-checking code derived from the accumulated sum of the data being checked. Cell A programmable location in a PLD, specied by the intersection of an input line and a product line. Product line rst cell number The lowest cell number on a particular product line in a PAL AND matrix where all cells are consecutively numbered. Input line number A number assigned to a true or complement input line in a PAL AND matrix. Multiplexer A circuit that selects one of several signals to be directed to a single output. Figure 8.3 shows the logic diagram of a PAL16L8 PAL circuit. This device can produce up to eight different sum-of-products expressions, one for each group of AND and OR gates. The device has active-LOW tristate outputs, as indicated by the L in the part number. Each is controlled by a product line from the related AND matrix. The pins that can be used only as inputs or outputs are marked I or O, respectively. Six of the pins can be used as inputs or outputs and are marked I/O. The I/O pins can also feed back a derived Boolean expression into the matrix, where it can be employed as part of another function. A detail of an I/O section is shown in Figure 8.4. The part number of a PAL device gives the designer information about the number of inputs and outputs and their congurations, as follows: Number of inputs Output type: H Active HIGH L Active LOW P Programmable polarity R Registered (D ip-op) X XOR registered C Complementary (both HIGH and LOW) Number of (registered) outputs PAL 16 R 8 8.2 PAL Fuse Matrix and Combinational Outputs 333 FIGURE 8.3 Unprogrammed PAL16L8 The numbering system has some potential ambiguities. For example, it is not possible to use 16 inputs and 8 outputs in a PAL16L8 device at the same time; 6 of the inputs are actually input/output pins. Some possible congurations are as follows: 16 inputs (10 dedicated 6 I/O) and 2 dedicated outputs 10 dedicated inputs and 8 outputs (2 dedicated 6 I/O) 12 inputs (10 dedicated 2 I/O) and 6 outputs (2 dedicated 4 I/O) Each of the outputs of the PAL16L8 is buffered by a tristate inverter, whose ENABLE input is controlled by its own product line. When the ENABLE line of the tristate inverter is 334 C H A P T E R 8 Introduction to Programmable Logic Architectures FIGURE 8.4 PAL16L8 I/O Section I/O HIGH, the inverter output is the same as it would normally bea logic HIGH or LOW, determined by the state of the corresponding OR gate output. When the ENABLE line is LOW, the inverter output is in the high-impedance state. The output acts as an open circuit, neither HIGH nor LOW; it is as though the output was completely disconnected from the circuit. The inverter is permanently enabled if all fuses on the ENABLE product line are blown, and permanently disabled if these fuses are all intact. Published logic diagrams of PAL devices generally do not have fuses drawn on them. This allows us to draw fuses for any application. In practice, PLDs have become too complex to manually draw fuse maps for most applications. Historically, PLD programming would begin with fuses drawn on a logic diagram, and each fuse would be selected and blown individually by someone operating a hardware device constructed for such a purpose. Fuse assignment is now done with special software such as ABEL, CUPL, or PALASM. These programs will take inputs such as Boolean equations, truth tables, or other forms and produce the simplest SOP solution to the particular problem. (MAX PLUS II is not congured to generate programming data for low-density PALs, although it can generate data for similar devices in the Altera Classic PLD series.) The end result of such software is a JEDEC le, an industry-standard way of listing which fuses in the PLD should remain intact and which should be blown. The JEDEC le is stored on disk as an ASCII text le. Most PLD programmers will accept the JEDEC le and use it as a template for blowing fuses in the target device. Fuse locations, called cells, are specied by two numbers: the product line rst cell number, shown along the left side of the diagram, and the input line number, shown along the top. The address of any particular fuse is the sum of its product line rst cell number and its input line number. The fuses on the PAL16L8 device are numbered from 0000 to 2047 ( 2016 31). Figure 8.5 shows an example of a JEDEC le for a PAL16L8 application. The le starts with an ASCII Start Text character (^B). Next is some information required by the PAL programmer about the type of device (PAL16L8), number of fuses (2048), and so forth. The fuse information starts with the line L0000, which is the rst product line. The 1s and 0s which follow show the programmed state of each cell in each product line; a 1 is a blown fuse and a 0 is an intact fuse. In other words, each 0 in the JEDEC le represents an X in the same position on the PAL logic diagram. The product terms for rst sum-of-products output are set by the states of fuses 0000 to 0255 (eight product lines). In the le shown, all fuses are blown in the rst product 8.2 PAL Fuse Matrix and Combinational Outputs 335 FIGURE 8.5 Sample JEDEC File line, the second product line shows three intact fuses, and so forth. Since all fuses are intact in the last three lines, they need not be shown in the JEDEC le. Whenever some unprogrammed product lines are omitted from the fuse map, the last fuse line shown ends with an asterisk (*). The next line with programmed fuses is indicated by a new fuse number. For example, the second group of fuses (0256 to 0511) in Figure 8.5 begins after the line marked L0256 in the JEDEC le. The remaining fuse lines are similarly indicated. The JEDEC le in Figure 8.5 ends with a hexadecimal checksum (C8DCF), an errorchecking code derived from the programming data, and an ASCII End Text code (^C). 336 C H A P T E R 8 Introduction to Programmable Logic Architectures FIGURE 8.6 4-to-1 Multiplexer Circuits In order to examine the general principle of fuse programming, let us develop the programmed logic diagram for a common combinational circuit: a 4-to-1 multiplexer. (After developing the fuse maps for several examples, we will not refer to this technique again.) This circuit, shown in Figure 8.6a, directs one of four input logic signals, D0 to D3, to output Y, depending on the state of two select inputs S0 and S1. The circuit works on the enable/inhibit principle; each AND gate is enabled by a different combination of S1 S0. The binary state of the select inputs is the same as the decimal subscript of the selected data input. For instance, S1 S0 10 selects data input D2; the AND gate corresponding to D2 is enabled and the other three ANDs are inhibited. The logic equation for output Y is given by: Y D0 S 1 S 0 D1 S1 S0 D2 S1 S0 D3 S1 S0 Since the outputs of the PAL16L8 are active LOW, as illustrated in Figure 8.6b, we should rewrite the equation as follows: Y D0 S1 S0 D1 S1 S0 D2 S1 S0 D3 S1 S0 The D inputs must be complemented to reverse the effect of the active-LOW output. The output is enabled when the EN input is HIGH. Figure 8.7 shows the PAL16L8A logic diagram with fuses for the multiplexer application. 8.3 PAL Outputs With Programmable Polarity The multiplexer application developed in the previous section uses a PAL device whose output is always xed at the active-LOW polarity. This xed polarity is suitable for most applications, but Boolean functions that would normally have active-HIGH outputs must be implemented in DeMorgan equivalent form, which is not always very straightforward. Some applications require both active-HIGH and active-LOW outputs. In such cases, it is useful to have a device whose output polarity is fuse programmable. Figure 8.8 shows the logic diagram of a PAL20P8 PAL device. This device is the same as a PAL16L8, except that there are four more dedicated inputs, and the polarity of each output is programmable. The Exclusive OR gate on each output is programmed to act as either an inverter or a buffer. When its associated fuse is intact, the XOR input is grounded and passes the output of its related SOP network in true form. When combined with the output inverter, this produces an active-LOW output. When the polarity fuse is blown, the fused XOR input oats to the HIGH state, inverting the SOP output; the output pin becomes active HIGH. 8.3 PAL Outputs With Programmable Polarity 337 FIGURE 8.7 Programmed Logic Diagram for a 4-to-1 Multiplexer The polarity fuses are given numbers higher than those of the main fuse array. In this case, the product line fuses are numbered 0000 to 2559 and the output polarity fuses are numbered 2560 to 2567. Figure 8.9 illustrates the selection of output polarity. Two Boolean functions, F1 and F2, are programmed into the fuse array, with outputs at pins (17) and (15), respectively. The equations are: F1 F2 AB AB AB AB 338 C H A P T E R 8 Introduction to Programmable Logic Architectures FIGURE 8.8 PAL20P8 Logic Diagram We could, if we chose, rewrite F2 to show the output as active LOW: F2 AB AB The portion of the PAL20P8 logic diagram shown in Figure 8.9 represents the fuses required to program F1 and F2. Pins (14) and (16) supply inputs A and B to the matrix. The ENABLE lines of the tristate output buffers oat HIGH, since all fuses are blown on the corresponding product lines, thus permanently enabling the output buffers. The fuses numbered 2565 and 2567 select the polarity at pins (15) and (17). Fuse 2565 is blown. The fused input to the corresponding XOR gate oats HIGH, thus making the gate into an inverter. Combined with the tristate buffer, this makes pin (17) active HIGH. Fuse 2567 is intact. This grounds the input to the corresponding XOR gate, making the gate into a noninverting buffer. Combined with the tristate output buffer, this makes pin (15) active LOW. 8.3 PAL Outputs With Programmable Polarity 339 FIGURE 8.9 PAL Outputs With Programmable Polarity EXAMPLE 8.1 Show how a PAL20P8 device can be used to implement the following logic functions by drawing fuses on the devices logic diagram. NOT: AND: OR: NAND: NOR: XOR: XNOR: F1 F2 F3 F4 F5 F6 F7 A BC DE FG HJ K L KL KL M N MN MN How would the implementation of these logic functions differ if only active-LOW outputs were available, as in a PAL16L8? SOLUTION The PAL20P8 has 14 dedicated inputs, 2 dedicated outputs, and 6 lines that can be used as inputs or outputs. Our functions need 13 input variables and 7 output variables. We will use six I/O pins (pins (16) through (21)) and one dedicated output (pin (15)) for the output variables. 340 C H A P T E R 8 Introduction to Programmable Logic Architectures All functions must be in SOP form. Outputs for NOT, AND, OR, Exclusive OR, and Exclusive NOR are active HIGH. Therefore, polarity fuses on the outputs for F1, F2, F3, F6, and F7 are blown. NAND and NOR outputs are active LOW; the polarity fuses for F4 and F5 remain intact. Figure 8.10 shows the logic diagram of the programmed PAL. If only active-LOW outputs were available, we would need to rewrite some of the equations to make the outputs correspond to their DeMorgan equivalent forms, as follows: AND: OR: XOR: XNOR: F2 F3 F6 F7 BC DE K L KL KL M N MN MN FIGURE 8.10 Programmed Logic Diagram for Seven Logic Functions 8.4 PAL Devices With Registered Outputs 341 8.4 PAL Devices With Registered Outputs KEY TERMS Register A digital circuit such as a ip-op or array of ip-ops that stores one or more bits of digital information. Registered output An output of a programmable array logic (PAL) device having a ip-op (usually D-type) that stores the output state. Flip-ops are generally found in programmable logic devices as registered outputs. A register is one or more ip-ops used to store data. Registered outputs in programmable array logic (PAL) devices can be used for the same functions as individual ip-ops. Figure 8.11 shows the logic diagram of a PAL device with eight registered outputs: a PAL16R8. The fuse matrix is identical to that of a PAL16L8 device; the differences FIGURE 8.11 PAL16R8 Logic Diagram 342 C H A P T E R 8 Introduction to Programmable Logic Architectures between the two devices are the registered outputs, a dedicated clock input (pin 1), and a pin for enabling all registered outputs (pin 11). With Registered PAL, the number of outputs shown in the part number indicates the number of registered outputs. For example, a PAL16R4 device has four registered outputs and four combinational I/O pins, a PAL16R6 device has six registered outputs and two combinational I/O pins, and a PAL16R8 has eight registered outputs. EXAMPLE 8.2 A common data operation is that of rotation. Figure 8.12 illustrates how a 4-bit number can be rotated to the right by 0, 1, 2, or 3 places by a circuit called a barrel shifter. To rotate the data, move all bits the required number of places to the right. As data reach the rightmost position, move them to the beginning so that they are transferred in a closed loop. FIGURE 8.12 Example 8.2 Rotation to the Right (4-bit Data) This operation is usually performed by serially shifting the data the required number of places and feeding back the last output to the rst input of a serial shift register. Rotation can also be accomplished by a parallel transfer operation. We can load the bits of the input into four D ip-ops in the order determined by two select inputs, S1 and S0. Assume that the binary number S1 S0 is the same as the rotation number in Figure 8.12. Table 8.1 summarizes the contents of the circuit after one clock pulse is applied. Table 8.1 Rotation to the Right by a Selectable Number of Bits S1 S0 QA QB QC QD 0 0 1 1 0 1 0 1 A D C B B A D C C B A D D C B A Rotation 0 1 2 3 Sketch a circuit, using gates and ip-ops, that can accomplish this rotation as a parallel transfer function. Briey explain its operation. Write the Boolean expression(s) for the circuit. Show how the circuit can be implemented by a PAL16R4 device by drawing fuses on its logic diagram. SOLUTION Figure 8.13 shows a parallel transfer circuit (barrel shifter) that will perform the specied rotation. The circuit works by enabling one AND gate in each group of four for each combination of S1 and S0. For example, when S1 S0 00, the rotation is 0 and the leftmost AND gate of each group is enabled, transferring the parallel data into the ip-ops so that DA A, DB B, DC C, and DD D. After one clock pulse, QA QB QC QD ABCD. 8.4 PAL Devices With Registered Outputs 343 FIGURE 8.13 Example 8.2 Rotation by Parallel Transfer (Barrel Shifter) Similarly, if S1 S0 10, we select a rotation of 2. The third AND gate from the left is selected in each group of four. This makes the data DA C, DB D, DC A, and DD B appear at the ip-op inputs. After one clock pulse, QA QB QC QD CDAB. The same principle governs the circuit operation for the other two select codes. The Boolean equations for the circuit are: QA QB QC QD S1 S0 A S1 S0 B S1 S0 C S1 S0 D S1 S0 D S1 S0 A S1 S0 B S1 S0 C S1 S0 C S1 S 0 D S1 S 0 A S1 S0 B S1 S0 B S1 S0 C S1 S0 D S1 S0 A 344 C H A P T E R 8 Introduction to Programmable Logic Architectures FIGURE 8.14 Example 8.2 Programmed PLD for Selectable Bit Rotation These equations imply that each registered output requires us to use four product lines, one for each product term. The programmed logic diagram is shown in Figure 8.14. 8.5 Universal PAL and Generic Array Logic (GAL) 345 8.5 Universal PAL and Generic Array Logic (GAL) KEY TERMS One-time programmable (OTP) A property of some PLDs that allows them to be programmed, but not erased. Generic array logic (GAL) A type of programmable logic device whose outputs can be congured as combinational or registered and whose programming matrix is based on electrically erasable logic cells. Universal PAL A PLD based on erasable cells and congurable outputs, much like GAL, but primarily designed to emulate PAL devices, such as PAL16L8. Output logic macrocell (OLMC) An input/output circuit that can be programmed for a variety of input or output congurations, such as active HIGH or active LOW, combinational or registered. Often just called a macrocell. In-system programmability (ISP) The ability of a PLD to be programmed through a standard four-wire interface while installed in a circuit. JTAG port A four-wire interface specied by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit. Architecture cell A programmable cell that, in combination with other architecture cells, sets the conguration of a macrocell. Global architecture cell An architecture cell that affects the conguration of all macrocells in a device. Local architecture cell An architecture cell that affects the conguration of one macrocell only. Global clock A clock signal in a PLD that clocks all registered outputs in the device. There are several limitations of standard low-density PALs. First, these devices are one-time programmable (OTP). Since the AND matrix of a PAL is programmable by blowing metal fuse links, programming is permanent; there is no opportunity to correct or update a design. In development of a new design, where many modications must be made to the original design, this can be particularly wasteful. Second, standard PAL outputs are permanently congured either as combinational or registered. A given PAL has a certain number of each type of output, which may not be optimum for the design. Third, a standard PAL cannot be programmed while it is installed in a circuit. A number of low-density PLDs have been developed to address these concerns. Devices such as the PALCE16V8 U niversal PAL (Vantis Corporation), and the GAL16V8 and GAL22V10 Generic Array Logic (Lattice Semiconductor)* are based on sum-of-products fuse matrices, just as the earlier-version PALs. However, these devices are based on electrically erasable read only memory (EEPROM or E2PROM) cells, rather than fuses, which allow them to be erased and reprogrammed about 10,000 times. A programmed device will hold its data for about 20 years. Universal PALs and GALs also have programmable input/output configurations. An I/O pin can be configured as a registered output, a combinational output, or a dedicated input, as required. Additionally, an output can be specied as active-HIGH or active-LOW. *Vantis has recently been acquired by Lattice, so these devices are really produced by the same company 346 C H A P T E R 8 Introduction to Programmable Logic Architectures Devices such as the ispGAL22V10 or the Altera MAX7000S series can be programmed while installed in a circuit via a standard four-wire interface called a JTAG port. This property is known as in-system programmability (ISP). PALCE16V8 Figure 8.15 shows one I/O pin and its associated circuitry for a PALCE16V8 Universal PAL. (The V stands for variable or versatile architecture.) It consists of a programmable SOP array with 8 product terms and an output logic macrocell (OLMC), or just macrocell, which determines the I/O conguration for that pin. The various conguration options are selected by a network of four multiplexers that are programmed by a set of architecture cells that set the MUX select inputs HIGH or LOW. 24 27 28 31 CLK OE Select output enable term Select eighth product term 11 VCC 0X 10 SL03 1 1 0 0 1 0 0 1 Select registered or combinational output 11 0X SG1 15 I/O3 D Select active high or low SL13 10 Q Q 10 11 0X Select input or feedback type SG1 SL03 FIGURE 8.15 Output Logic Macrocell for a PALCE16V8 PLD A global architecture cell, SG1, selects conguration options for all macrocells in the device. Two local conguration cells, SL0n and SL1n, select congurations for I/On only. (In this case, the cells shown are SL03 and SL13 for conguration of I/O3.) Figure 8.16 shows the different macrocell congurations for a PALCE16V8 Universal PAL. Most of these congurations are designed to emulate an I/O of a standard PAL, so that an old-style PAL can be replaced by a Universal PAL, and can be programmed by data for the older PAL. The macrocells can also be congured in a pattern that does not conform to an older device. Figure 8.17 shows the logic diagram of a PALCE16V8 Universal PAL. The device has eight dedicated inputs, eight macrocells, a Clock pin and an Output Enable pin. The latter two signals are shown in the macrocell diagram of Figure 8.15 as the lines labeled CLK and OE. If there are registered outputs, the clock input (pin 1) provides a global clock function. That is, all registered outputs are clocked simultaneously by this signal. (Some other PLDs provide an option to clock a registered output from a product term in the AND matrix, allowing several clock functions in one chip.) If there are no registered outputs used in the PLD, pin 1 can be used as an input. 8.5 Universal PAL and Generic Array Logic (GAL) 347 OE OE D CLK D Q Q CLK Q Q a. Registered active low b. Registered active high c. Combinatorial I/O active low d. Combinatorial I/O active high VCC VCC Note 1 e. Combinatorial output active low Notes: 1. Feedback is not available on pins 15 and 16 in the combinatorial output mode. 2. This configuration is not available on pins 15 and 16. Note 1 f. Combinatorial output active high Adjacent I/O pin Note 2 g. Dedicated input FIGURE 8.16 Macrocell Congurations for a PALCE16V8 PLD (Courtesy of Lattice Semiconductor Corporation) Pin 11 provides an active-LOW Output Enable function. This is selected by local architecture cells to provide control of the output tristate buffer, either from the OE pin or from a product term in theAND matrix. If the OE function is unused, the pin can be used as an input. GAL22V10 Figure 8.18 shows the logic diagram of a GAL22V10 generic array logic device. This industry-standard device has a number of features that make it superior to the PALCE16V8. 348 C H A P T E R 8 Introduction to Programmable Logic Architectures 0 CLK/I0 34 78 11 12 15 16 19 20 23 24 27 28 31 1 11 VCC 0X 10 0 SL07 D I1 1 0 0 1 SL17 Q I/O7 10 11 0X 2 VCC 0X 10 8 SL06 SL07 D 15 1 1 0 0 1 0 0 1 10 0X SG1 SL16 Q 18 10 I/O6 Q 10 11 0X 3 SL06 SG1 11 VCC 0X 10 16 SL05 D 23 1 1 0 0 1 0 0 1 10 0X SG1 SL15 Q 17 10 I/O5 Q 10 11 0X 4 SG1 11 VCC 0X 10 24 SL04 D 31 SL14 SL05 1 1 0 0 1 0 0 1 10 0X SG1 I4 19 Q 11 I3 VCC 10 SG0 I2 20 10 0X SG1 7 1 1 0 0 Q 16 10 Q 10 11 0X 5 0 34 78 11 12 15 16 19 20 23 24 27 28 31 FIGURE 8.17 (a) PALCE16V8 Logic Diagram (Courtesy of Lattice Semiconductor Corporation) CLK OE SG1 SL04 I/O4 8.5 0 34 78 CLK OE 11 12 15 16 19 20 23 24 27 28 31 11 VCC 0X 10 32 SL03 D 39 1 1 0 0 1 0 0 1 10 0X SG1 I5 SL13 Q 10 11 0X SG1 11 VCC 0X 10 40 SL02 D 47 SL03 1 1 0 0 1 0 0 1 10 0X SG1 SL12 Q 14 13 11 VCC 0X 10 48 SL01 12 I/O0 SL02 D 55 1 1 0 0 1 0 0 1 10 0X SG1 SL11 Q 10 Q 10 11 0X 8 SG1 11 VCC 0X 10 56 SL00 D 63 SL10 SL01 1 1 0 0 1 0 0 1 10 0X SG1 GND I/O1 10 11 0X SG1 I8 I/O2 10 Q 7 I7 15 I/O3 10 Q 6 I6 349 Universal PAL and Generic Array Logic (GAL) Q 10 Q 10 11 0X 9 10 0 34 78 11 12 15 16 19 20 23 24 27 28 31 SG0 SL00 13 FIGURE 8.17 (b) (PALCE16V8 Logic Diagram OE/19 350 C H A P T E R 8 Introduction to Programmable Logic Architectures FIGURE 8.18 GAL22V10 Logic Diagram 1. There are more outputs (10 as opposed to 8 for the 16V8). 2. There are more inputs (11 dedicated inputs, plus any I/O lines used as inputs). 3. The output logic macrocells are of different sizes, allowing expressions with larger numbers of product terms in some OLMCs than others. There are two OLMCs with each of the following numbers of product lines: 8, 10, 12, 14, and 16. This allows more exibility in design, while minimizing the number of product lines. 8.6 MAX7000S CPLD 351 FIGURE 8.19 GAL22V10 OLMC Congurations 4. OLMC conguration is much simpler than that of a PALCE16V8. Two architecture cells per macrocell, S0 and S1, select the output type, as shown in Figure 8.19. 5. There are product lines for Synchronous Preset (SP) and Asynchronous Reset (AR). The SP line sets all ip-ops HIGH on the rst clock pulse after it becomes active. The AR line sets all ip-ops LOW as soon as it activates, without waiting for the clock pulse. (Note that these lines set or reset the Q output of each ip-op. An active-LOW registered output inverts this state at the output pin.) 8.6 MAX7000S CPLD KEY TERMS CPLD Complex programmable logic device. A programmable logic device consisting of several interconnected programmable blocks. Logic Array Block (LAB) A group of macrocells that share common resources in a CPLD. Programmable Interconnect Array (PIA) An internal bus with programmable connections that link together the Logic Array Blocks of a CPLD. 352 C H A P T E R 8 Introduction to Programmable Logic Architectures Buried logic Logic circuitry in a PLD that has no connection to the input or output pins of the PLD, but is used solely as internal logic. I/O Control Block A circuit in an Altera CPLD that controls the type of tristate switching used in a macrocell output. Parallel logic expanders Product terms that are borrowed from neighboring macrocells in the same LAB. Shared logic expanders Product terms that are inverted and fed back into the programmable AND matrix of an LAB for use by any other macrocell in the LAB. Figure 8.20 shows the block diagram of an Altera MAX7000S Complex PLD (CPLD). A device of this typethe EPM7128SLC84is one of the two devices installed on the Altera UP-1 University Program board, so we will use it as a specic example of the MAX7000S family of devices. INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT INPUT/GCLRn 6 Output Enables 6 Output Enables LAB B 6 to 16 6 to 16 LAB A 6 to 16 I/O Pins I/O Control Block 6 to 16 36 36 Macrocells 1 to 16 16 16 PIA 6 to 16 6 Macrocells 17 to 32 6 to 16 I/O Control Block 6 to 16 36 Macrocells 33 to 48 16 6 to 16 6 36 6 Macrocells 49 to 64 16 6 to 16 FIGURE 8.20 MAX 7000E and MAX 7000S Device Block Diagram (Courtesy of Altera) The part number breaks up as follows: EPM7 128 S LC84 6 to 16 I/O Pins LAB D 6 to 16 6 to 16 LAB C 6 to 16 I/O Pins I/O Control 6 to 16 Block MAX7000 family number of macrocells in-system programmable 84-pin PLCC package I/O Control 6 to 16 Block 6 6 to 16 I/O Pins 8.6 MAX7000S CPLD 353 The main structure of the MAX7000S is a series of Logic Array Blocks (LABs), linked by a Programmable Interconnect Array (PIA). Each LAB is a group of 16 macrocells that can share common product terms and lend or borrow unused product terms among each other. A single LAB has similar I/O and programming capability to a low-density PLD, so a CPLD like the MAX7000S can be thought of as an array of interconnected PALs or GALs on a single chip. An EPM7128S has 8 LABs, for a total of 8 16 128 macrocells. However, these are not all available to the user as I/Os; the number of available I/O pins depends on the device package. Figure 8.20 indicates that each LAB in a MAX7000S device has from 6 to 16 I/O pins. For an EPM7128S in a 160-pin PQFP package, there are 12 I/Os per LAB, for a total of 96 available pins. For the same device in an 84-pin PLCC package, there are only 8 I/Os per LAB, for a total of 64 pins. In practice, if an EPM7128SLC84 is to be programmed in-circuit (i.e., while installed on a circuit board), there are only 60 I/Os available, as four pins are required for the programming interface. The macrocells that are not connected to user I/O pins can only be used for buried logic, or logic that is internal to the chip only. As implied in Figure 8.20, all I/O pins connect to and from their associated LAB via an I/O Control Block (a circuit that controls the tristate switching of signals at an I/O pin). The I/O pin signals also connect directly to the PIA, where they are available for use in other LABs. Sixteen lines connect the macrocell outputs of each LAB to the PIA, again for use throughout the device. The PIA communicates to each LAB via 36 product lines to provide connections from other LABs. The MAX7000S family has four pins that can be congured as control signals or inputs. GCLK1 is a global clock that is common to all macrocells in the device and can be used to synchronously clock all registers. OE1 is an output enable that can globally activate or disable the tristate outputs of the device macrocells. GCLRn is an activeLOW global clear function. The fourth control pin can be congured as an input, as can the other three pins, or as a second global clock (GCLK2) or output enable (OE2). If the control functions are not used, these pins add four inputs to the available total. These assignments can be made by the MAX PLUS II software during the design process. Figure 8.21 shows a macrocell from a MAX7000S device. The macrocell is similar to that of a GAL or Universal PAL in that it provides a sum-of-products function with activeHIGH or -LOW options and the choice of registered or combinational output. Registered outputs can be clocked with one of two global clocks or by a product term from the AND matrix. The register can be cleared globally or by a product term and preset with a product term. The macrocell has ve dedicated product terms, which is fewer than found in the PAL and GAL matrices we examined earlier. This is generally sufcient to implement most logic functions. If more terms are required, they can be supplied by a set of shared logic expanders or parallel logic expanders. Shared logic expanders do not add more product terms to a given macrocell. They do make the programming of the entire LAB more efcient by allowing a product term to be programmed once and used in several macrocells of the same LAB. One product term per macrocell is inverted and fed back into the shared expander pool of product terms. Since there are 16 macrocells per LAB, the shared logic expander pool has up to 16 product terms. Parallel logic expanders allow a macrocell to borrow up to 15 product terms from its three lower-numbered neighbors (5 product terms per neighboring macrocell). For example, macrocell 4 can borrow up to 5 terms each from macrocells 3, 2, and 1. By using its 5 dedicated product terms and the maximum number of parallel expanders, a macrocell can have up to 20 product terms at its disposal. These borrowed terms are not usable by the macrocell from which they were borrowed. The parallel expanders are set up so that a lower-number cell lends product terms to a higher-number cell, so the number of available terms depends on how close to the end of a chain a macrocell is. Expander assignments are done automatically by MAX PLUS II at compile time. 354 C H A P T E R 8 Introduction to Programmable Logic Architectures Global Clear LAB Local Array Parrellel Logic Expanders (from other macrocells) Global Clocks 2 Fast Input Select Programmable Register from I/O pin Register Bypass PRN DQ Clock/ Enable Select ProductTerm Select Matrix to I/O Control Block ENA CLRN VCC Clear Select 36 Signals from PIA Shared Logic Expanders to PIA 16 Expander Product Terms FIGURE 8.21 MAX 7000E and MAX 7000S Device Macrocell (Courtesy of Altera) 8.7 FLEX10K CPLD KEY TERMS Look-up table (LUT) A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations. Logic element (LE) A circuit internal to a CPLD used to implement a logic function as a look-up table. Cascade chain A circuit in a CPLD that allows the input width of a Boolean function to expand beyond the width of one logic element. Carry chain A circuit in a CPLD that is optimized for efcient operation of carry functions between logic elements. Embedded array block (EAB) A relatively large block of storage elements in a CPLD (2048 bits in a FLEX10K device), used for implementing complex logic functions in look-up table format. All programmable logic devices we have seen until now have been based on sum-ofproducts arrays. Another major type of PLD is based on look-up table (LUT) architecture. In this architecture, a number of storage elements are used to synthesize logic functions by storing each function as a truth table. To illustrate the look-up table concept, let us use the truth table of a 2-bit equality comparator, shown in Table 8.2. The comparator examines inputs A1A0 and B1B0 and makes output AEQB equal to logic 1 if A1A0 B1B0. If we were to implement the circuit as an SOP array, we would rst nd the Boolean expression by combining the four product terms from the truth table and then program the appropriate cells in a CPLD AND matrix. The look-up table implementation of this function is based on a totally different concept. 8.7 Table 8.2 Truth Table for a 2-bit Equality Comparator FLEX10K CPLD 355 LUT A1 A0 B1 B0 Decimal AEQB 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 2 3 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 4 5 6 7 0 1 0 0 A1 A0 AEQB B1 B0 a. 2-bit comparator look-up table AEQB Q0 DQ 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 9 10 11 12 13 14 15 0 0 1 0 0 0 0 1 ADDR0 Q1 DQ ADDR1 Storage Elements Q15 DQ ADDR15 Address decoder ADDR0 ADDR1 A1 A0 B1 B0 ADDR15 b. Stuctural concept of a look-up table FIGURE 8.22 Look-up Table Figure 8.22 shows the structural concept of a 4-bit look-up table circuit. An array of 16 ip-ops (Q0 through Q15) contain data for all possible combinations of A1A0B1B0, one ip-op per combination. The LUT inputs A1A0B1B0 are decoded by an internal address decoder. Each decoder output activates a tristate buffer that passes or blocks the output of one ip-op. The active buffer passes the contents of the ip-op to AEQB; all other buffers are in the high-impedance state, blocking the data from the other ip-ops. The contents of the ip-ops are loaded when the look-up table is congured (programmed) with the required function. After that the ip-ops retain their information until they are recongured. For our comparator example, ip-ops 0, 5, 10, and 15 are all set (Q 1). All other ip-ops are reset (Q 0). Examine Table 8.2 to conrm that this is true. The 16-bit storage element in Figure 8.22, combined with switching to choose a combinational or registered output and to interconnect with other parts of the chip, is called a logic element (LE). A logic element performs a function similar to that of a macrocell in SOP-type PLDs. Figure 8.23 shows the structure of a logic element in an Altera FLEX10K CPLD. In addition to the LUT, the LE has circuitry to select various control functions, such as clock and reset, a ip-op for registered output, some expansion circuitry (cascade and carry), and interconnections to local and global busses. The cascade chain circuit, shown in Figure 8.24 allows the user to program Boolean functions with more than four inputs, thus requiring more than one LUT. The 356 C H A P T E R 8 Introduction to Programmable Logic Architectures Carry-In Cascade-In Carry Chain Cascade Chain Register Bypass Programmable Register DATA1 Look-Up Table (LUT) DATA2 DATA3 to FastTrack Interconnect PRN D Q DATA4 ENA CLRN LABCTRL1 to LAB local Interconnect Clear/ Preset Logic LABCTRL2 Chip-Wide Reset Clock Select LABCTRL3 LABCTRL4 Carry-Out Cascade-Out FIGURE 8.23 FLEX10K Logic Element (Courtesy of Altera) AND Cascade Chain d[3..0] OR Cascade Chain d[3..0] LUT LUT LE1 d[7..4] LE1 d[7..4] LUT LUT LE2 d[(4n-1)..(4n-4)] d[(4n-1)..(4n-4)] LUT LEn FIGURE 8.24 Cascade Chain Operation (Courtesy of Altera) LE2 LUT LEn 8.7 FIGURE 8.25 Carry Chain Operation (n-bit Full Adder) (Courtesy of Altera) FLEX10K CPLD 357 Carry-In a1 LUT Register s1 b1 Carry Chain LE1 a2 LUT Register s2 b2 Carry Chain LE2 an LUT Register sn bn Carry Chain LEn LUT Register Carry-Out Carry Chain LEn + 1 cascade chain can be AND- or OR-type, depending on what DeMorgan equivalent form is most appropriate. The carry chain, shown in Figure 8.25 allows for efcient fast-carry implementation of adders, comparators, and other circuits that depend on the combination of low-order bits to dene high-order functions (i.e., circuits whose inputs become wider with higherorder bits). Figure 8.25 shows the carry chain as implemented by an n-bit adder. A Logic Array Block (LAB), shown in Figure 8.26, consists of eight logic elements and a local interconnect. The LAB is connected to the rest of the device by a series of row and column interconnects, which Altera calls a FastTrack Interconnect. Figure 8.27 shows the overall structure of a FLEX10K device, with several LABs and a number of 358 C H A P T E R 8 Introduction to Programmable Logic Architectures Dedicated Inputs and Global Signals Row Interconnect 6 LAB Local Interconnect 4 4 16 Carry-In and Cascade-In 2 24 8 4 4 LE1 4 LE2 4 LAB Control Signals LE3 Column-to-Row Interconnect 16 8 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 8 2 Column Interconnect Carry-Out and Cascade-Out FIGURE 8.26 FLEX10K LAB (Courtesy of Altera) Embedded Array Blocks (EABs). An EAB is an array of 2048 storage elements that can be used to efciently implement complex logic functions. The FLEX10K device found on the Altera UP-1 boardthe EPF10K20RC240-4 has an array of 6 rows by 24 columns of LABs, which gives a total of 144 LABs ( 8 144 1152 logic elements). The device also has 6 EABs (6 2048 12288 bits of EAB storage). Note that one EAB has signicantly more storage capacity than all LABs combined. The FLEX10K series of CPLDs (and LUT-based devices generally) are based on static random access memory (SRAM) technology. The advantage of this conguration is that it can be manufactured with a very high density of storage cells and it programs quickly compared to an EEPROM-based SOP device. The disadvantage is that SRAM cells are volatile; that is, they do not retain their data when power is removed from the circuit. An SRAM-based device must be recongured every time it is powered up. 1. Programmable logic devices (PLDs) are congured in two basic architectures: sum-of-products (SOP), which usually consist of a se- Summary 359 Embedded Array Block (EAB) I/O Element (IOE) IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE Column Interconnect Logic Array EAB Logic Array Block (LAB) IOE IOE IOE IOE Logic Element (LE) Row Interconnect EAB Local Interconnect Logic Array IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE Embedded Array FIGURE 8.27 FLEX10K Device Block Diagram (Courtesy of Altera) SUMMARY 2. 3. 4. 5. 6. ries of programmable AND/OR circuits, and look-up table (LUT), that stores the truth table of a Boolean function in a small memory. Programmable array logic (PAL) is an SOP-type architecture in which there are a series of programmable AND gates that have a xed connection to an OR-gate output. Connections from PLD inputs to PAL AND arrays were historically made by leaving intact selected fuses in a crosspoint fuse array. In modern PLDs, these connections are made by programming EEPROM (electrically erasable programmable read only memory) cells. An AND-gate input in a PAL array is called a product line. A PAL16L8 PLD is an SOP device with up to 16 inputs and up to 8 outputs. There are 10 dedicated inputs, 2 dedicated outputs, and 6 pins that can be congured as input or output. All outputs in the PAL16L8 are active-LOW. A PAL is programmed by a computer and programming hardware that uses a JEDEC le as a template for determin- ing which fuses to blow and which to leave intact. Some PAL devices have programmable-polarity outputs. This is achieved with an XOR gate that has a programmable cell or fuse on one input to switch the output between inverting and noninverting levels. 8. A registered PLD output consists of a ip-op (usually D-type) on the output of an SOP matrix. 9. A PAL part number indicates the number of registered outputs (e.g., a PAL16R8 has eight registered outputs). 10. Early-version standard PALs are limited in that they are one-time programmable (OTP), their outputs are permanently congured as combinational or registered, and they cannot be programmed in-system. Later-version PALs (e.g., PAL16CE16V8 Universal PAL) and GALs (generic array logic such as GAL22V10) overcome these limitations. 11. PALs and GALs with congurable architecture have outputs that can be combinational or registered, with various input or 7. 360 C H A P T E R 8 Introduction to Programmable Logic Architectures feedback options. 12. Congurable output circuits in a PLD are called output logic macrocells (OLMCs) or just macrocells. 13. Macrocells are congured by programming architecture cells. Global architecture cells affect all macrocells in a device. A local architecture cell affects only the macrocell in which it is found. 14. GALs and Universal PALs have global control signals, such as clock, clear, and output enable, that can be applied to all macrocells in the device. 15. A GAL22V10 has ten macrocells, a global clock that can be used as a combinational input for nonclocked designs, and eleven dedicated inputs. 16. The GAL22V10 macrocells are not all the same size. There are two macrocells with each of the following numbers of product terms: 8, 10, 12, 14, 16. 17. PLDs that can be programmed while installed in a circuit are called in-system programmable (ISP). They are programmed by a 4-wire interface that complies to a standard published by the Joint Test Action Group (JTAG) and the IEEE (Std. 1149.1). 18. An Altera MAX7000S CPLD consists of groups of 16 macrocells, called Logic Array Blocks (LABs), that are interconnected by an internal bus called a Programmable Interconnect Array (PIA). 19. The number of macrocell outputs in an LAB that are connected to I/O pins depends on the CPLD package type. Macrocells that do not have external connections can still be used for buried logic function. 20. MAX7000S devices have four programmable control pins: global clock (GCLK1), Global Output Enable (OE1), Global Clear (GCLRn), and a pin that can be congured as a second global clock (GCLK2) or as a second global output enable (OE2). If these functions are not used, the associated pins can be used as standard I/Os. 21. If the ISP capability of a CPLD is to be used, there are four fewer pins available on the CPLD for user I/O. 21. If the ISP capability of a CPLD is to be used, there are four fewer pins available on the CPLD for user I/O. 22. Each MAX7000S macrocell has ve dedicated product lines and capability to borrow or share additional product terms with neighboring macrocells in the same LAB. 23. Shared logic expanders allow one product term per macrocell to be shared with other macrocells in the LAB, totaling 16 product terms per LAB. The expander inverts the product term and feeds it back into the LAB AND matrix. 24. Parallel logic expanders allow a macrocell to borrow product lines from neighboring macrocells. These borrowed product lines are only available to one macrocell. 25. Expander assignments are done automatically by MAX PLUS II at compile time. 26. MAX7000S devices are based on EEPROM cells and are thus nonvolatile. 27. The Altera FLEX10K series of CPLDs is based on a look-up table (LUT) architecture. A look-up table consists of a 16-bit array of storage elements that are selected by four logic inputs. 28. An LUT combined with switching, conguration, and expansion circuitry comprises a logic element (LE), whose function is equivalent to a macrocell in an SOP-type device. 29. Eight logic elements and a local interconnect make up a Logic Array Block (LAB). 30. LABs in a FLEX10K device are interconnected by global row and column busses. 31. The number of inputs in a logic function can be expanded beyond the capacity of one logic element by using cascade chains. 32. Carry chains can be used to more efciently implement carry functions in adders, counters, and comparators. 33. FLEX10K devices are based on SRAM technology and are therefore volatile; they must be recongured each time power is applied to the circuit. GLOSSARY Architecture cell A programmable cell that, in combination with other architecture cells, sets the conguration of a macrocell. Buried logic Logic circuitry in a PLD that has no connection to the input or output pins of the PLD, but is used solely as internal logic. Carry chain A circuit in a CPLD that is optimized for efcient operation of carry functions between logic elements. Cascade chain A circuit in a CPLD that allows the input width of a Boolean function to expand beyond the width of one logic element. Cell A fuse location in a programmable logic device, specied by the intersection of an input line and a product line. Checksum An error-checking code derived from the accumulating sum of the data being checked. CPLD Complex programmable logic device. A programmable logic device consisting of several interconnected programmable blocks. Embedded array block (EAB) A relatively large block of storage elements in a CPLD (2048 bits in a FLEX10K device), used for implementing complex logic functions in look-up table format. Generic array logic (GAL) A type of programmable logic device whose outputs can be congured as combinational or registered and whose programming matrix is based on electrically erasable logic cells. Global architecture cell An architecture cell that affects the conguration of all macrocells in a device. Global clock A clock signal in a PLD that clocks all registered outputs in the device. I/O Control Block A circuit in an Altera CPLD that controls the type of tristate switching used in a macrocell output. Input line A line which applies the true or complement form of an input variable to the AND matrix of a PLD. Input line number A number assigned to a true or complement input line in a PAL AND matrix. 361 Problems In-system programmability (ISP) The ability of a PLD to be programmed through a standard four-wire interface while installed in a circuit. JEDEC Joint Electron Device Engineering Council JEDEC le An industry standard form of text le indicating which fuses are blown and which are intact in a programmable logic device. JTAG Port A four-wire interface specied by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit. Local architecture cell An architecture cell that affects the conguration of one macrocell only. Parallel logic expanders Product terms that are borrowed from neighboring macrocells in the same LAB. Product line A single line on a logic diagram used to represent all inputs to an AND gate (i.e., one product term) in a PLD sum-of-products array. Product line rst cell number The lowest cell number on a particular product line in a PAL AND matrix where all cells are consecutively numbered. Programmable Interconnect Array (PIA) An internal bus with programmable connections that link together the Logic Array Blocks of a CPLD. Logic Array Block (LAB) A group of macrocells that share common resources in a CPLD. Programmable logic device (PLD) A logic device whose function can be programmed by the user, usually in sum-ofproducts form. Logic element (LE) A circuit internal to a CPLD used to implement a logic function as a look-up table. Register A digital circuit such as a ip-op that stores one or more bits of digital information. Look-up table (LUT) A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations. Registered output An output of a programmable array logic (PAL) device having a ip-op (usually D-type) which stores the output state. Multiplexer A circuit which selects one of several signals to be directed to a single output. Shared logic expanders Product terms that are inverted and fed back into the programmable AND matrix of an LAB for use by any other macrocell in the LAB. One-time programmable (OTP) A property some of PLDs that allows them to be programmed, but not erased. Output logic macrocell (OLMC) An input/output circuit that can be programmed for a variety of input or output congurations, such as active HIGH or active LOW, combinational, or registered. Often just called a macrocell. Text le An ASCII-coded document stored on a magnetic disk. Universal PAL A PLD based on erasable cells and congurable outputs, much like GAL, but primarily designed to emulate PAL devices, such as PAL16L8. PAL Programmable array logic. Programmable logic with a xed OR matrix and a programmable AND matrix. PROBLEMS Problem numbers set in color indicate more difcult problems; those with underlines indicate most difcult problems. Section 8.1 Introduction to Progammable Logic Section 8.2 PAL Fuse Matrix and Combinational Outputs 8.4 Make a photocopy of Figure 8.8 (PAL20P8 logic diagram). Draw fuses on the PAL20P8 logic diagram showing how to make a BCD-to-2421 code converter, as developed in Example 3.22. Table 8.3 shows how the two codes relate to each other. The equations are listed on page 362. Section 8.3 PAL Outputs With Programmable Polarity 8.1 Draw a diagram showing the basic conguration and symbology for a PLD sum-of-products array. 8.2 Draw a basic PAL circuit having four inputs, eight product terms, and one active-LOW combinational output. Draw fuses on your diagram showing how to make the following Boolean expression: F 8.3 ABC BCD ACD ACD Modify the PAL circuit drawn in Problem 8.2 to make two outputs having eight product terms and programmable polarity. Draw fuses on the diagram for each of the following functions: F1 ABC BCD ACD ACD F2 ABC BCD ACD ACD Table 8.3 BCD and 2421 Code BCD Code 2421 Code Decimal Equivalent D4 D3 D2 D1 Y4 Y3 Y2 Y1 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 362 C H A P T E R 8 Introduction to Programmable Logic Architectures The Boolean equations for the BCD-to-2421 decoder are: Y4 D3D2 D4 D3D2 D4 D3D2 D1 Which of the CPLDs listed in Problem 8.17 are in-system programmable? What does it mean when a device is insystem programmable? 8.19 How many logic array blocks (LABs) are there in an Altera MAX7000S CPLD? D3D2D1 Y1 8.18 D3D1 Y2 How many macrocells are available in the following CPLDs: a. EPM7032 b. EPM7064 c. EPM7128S d. EPM7160S D3D1 Y3 8.5 D4 8.17 Repeat Problem 8.4 for a 2421-to-BCD code converter. 8.4 PAL Devices with Registered Outputs 8.6 What is a registered output? 8.20 8.7 State the number of registered outputs for each of the following PAL devices: How many user I/O pins are there in an EPM7128SLC84 CPLD? How many pins per LAB does this represent? 8.21 What can be done with the macrocells in an LAB that do not connect to I/O pins? 8.22 State the possible clock congurations of a MAX7000S macrocell. 8.23 Name two features of a PALCE16V8 that make it superior to a PAL16L8. State the possible reset congurations of a MAX7000S macrocell. 8.24 State the difference between a global architecture cell and a local architecture cell in a PALCE16V8. State the possible preset congurations of a MAX7000S macrocell. 8.25 How many dedicated product terms are available in a MAX7000S macrocell? How can this number of product terms be supplemented? What is the maximum number of product terms available to a macrocell? How many shared logic expanders are available in an LAB? a. PAL16R4 b. PAL16R6 c. PAL16R8 8.5 Universal PAL and Generic Array Logic (GAL) 8.8 8.9 8.10 How many macrocells are there in a GAL22V10? How many product lines do these macrocells have? 8.11 State the four congurations possible with a macrocell in a GAL22V10. 8.26 8.12 Is there a global output enable function available for a PALCE16V8? For a GAL22V10? 8.7 FLEX10K CPLD 8.13 Can the registered outputs of a PALCE16V8 be clocked by a product term function from the PAL AND matrix? 8.27 Briey state the difference between CPLDs having sumof-products architecture and look-up table architecture. 8.14 Can the registered outputs of a GAL22V10 be clocked by a product term function from the GAL AND matrix? 8.28 How many inputs can a look-up table accept in an Altera FLEX10K logic element? How can this be expanded? 8.15 Are the Asynchronous Reset (AR) and Synchronous Preset (SP) functions in a GAL22V10 global or local? Explain your answer in one sentence. 8.29 What is the purpose of the carry chain in a FLEX10K CPLD? 8.30 How many logic elements are there in a FLEX10K LAB? 8.31 How many bits of storage are there in an Embedded Array Block in a FLEX10K CPLD? 8.6 MAX7000S CPLD 8.16 State one way in which a Complex PLD, such as an Altera MAX7000S, differs from a low-density PAL or GAL. CHAPTER 9 Counters and Shift Registers OUTLINE CHAPTER OBJECTIVES 9.1 Upon successful completion of this chapter you will be able to: Determine the modulus of a counter. Determine the number of outputs required by a counter for a given modulus. Determine the maximum modulus of a counter, given the number of circuit outputs. Draw the count sequence table, state diagram, and timing diagram of a counter. Determine the recycle point of a counters sequence. Calculate the frequencies of each counter output, given the input clock frequency. Draw a circuit for any full sequence synchronous counter. Determine the count sequence, state diagram, timing diagram, and modulus of any synchronous counter. Complete the state diagram of a synchronous counter to account for unused states. Design the circuit of a truncated sequence synchronous counter, using ipops and logic gates. Use MAX PLUS II to create a graphic design le for any synchronous counter circuit. Use behavioral descriptions in VHDL to design synchronous counters of any modulus. Use a parameterized counter from the Library of Parameterized Modules in a VHDL le. Use the MAX PLUS II simulation tool to verify the operation of synchronous counters. Implement various counter control functions, such as parallel load, clear, count enable, and count direction, both in Graphic Design Files and in VHDL. Design a circuit to decode the output of the counter, both in a MAX PLUS II Graphic Design File or in VHDL. Draw a logic circuit of a serial shift register and determine its contents over time given any input data. 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Basic Concepts of Digital Counters Synchronous Counters Design of Synchronous Counters Programming Binary Counters in VHDL Control Options for Synchronous Counters Programming Presettable and Bidirectional Counters in VHDL Shift Registers Programming Shift Registers in VHDL Shift Register Counters 363 364 C H A P T E R 9 Counters and Shift Registers Draw a timing diagram showing the operation of a serial shift register. Draw the logic circuit of a general parallel-load shift register. Draw a timing diagram showing the operation of a parallel-load shift register. Draw the general logic circuit of a bidirectional shift register and explain the concepts of right-shift and left-shift. Use timing diagrams to explain the operation of a bidirectional shift register. Describe the operation of a universal shift register. Design shift registers, ring counters, and Johnson counters with the MAX PLUS II Graphic Editor or VHDL. Verify the operation of shift registers, ring counters, and Johnson counters using the MAX PLUS II simulation tool. Design a decoder for a Johnson counter. Use a ring counter or a Johnson counter as an event sequencer. Compare binary, ring, and Johnson counters in terms of the modulus and the required decoding for each circuit. C ounters and shift registers are two important classes of sequential circuits. In the simplest terms, a counter is a circuit that counts pulses. As such, it is used in many circuit applications, such as event counting and sequencing, timing, frequency division, and control. A basic counter can be enhanced to incorporate functions such as synchronous or asynchronous parallel loading, synchronous or asynchronous clear, count enable, directional control, and output decoding. In this chapter, we will design counters using schematic entry, VHDL, and counters from the Library of Parameterized Modules and verify their operation using the MAX PLUS II simulator. Shift registers are circuits that store and move data. They can be used in serial data transfer, serial/parallel conversion, arithmetic functions, and delay elements. As with counters, many shift registers have additional functions such as parallel load, clear, and directional control. We can implement these circuits using schematic entry, VHDL, and LPM components. I 9.1 Basic Concepts of Digital Counters KEY TERMS Counter A sequential digital circuit whose output progresses in a predictable repeating pattern, advancing by one state for each clock pulse. Recycle To make a transition from the last state of the count sequence to the rst state. Count sequence The specic series of output states through which a counter progresses. State diagram A diagram showing the progression of states of a sequential circuit. Modulus The number of states through which a counter sequences before repeating. Modulo-n (or mod-n) counter A counter with a modulus of n. UP counter A counter with an ascending sequence. DOWN counter A counter with a descending sequence. 9.1 Basic Concepts of Digital Counters 365 The simplest denition of a counter is a circuit that counts pulses. Knowing only this, let us look at an example of how we might use a counter circuit. EXAMPLE 9.1 FIGURE 9.1 Example 9.1 10-bit Counter Figure 9.1 shows a 10-bit binary counter that can be used to count the number of people passing by an optical sensor. Every time the sensor detects a person passing by, it produces a pulse. Briey describe the counters operation. What is the maximum number of people it can count? What happens if this number is exceeded? CTR DIV 1024 Optical sensor CLK Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Solution The counter has a 10-bit output, allowing a binary number from 00 0000 0000 to 11 1111 1111 (0 to 1023) to appear at its output. The sensor causes the counter to advance by one binary number for every pulse applied to the counters clock (CLK) input. If the counter is allowed to register no people (i.e., 00 0000 0000), then the circuit can count 1023 people, since there are 1024 unique binary combinations of a 10-bit number, including 0. (This is because 210 1024.) When the 1024th pulse is applied to the clock input, the counter rolls over to 0 (or recycles) and starts counting again. (After this point, the counter would not accurately reect the number of people counted.) The counter is labeled CTR DIV 1024 to indicate that one full cycle of the counter requires 1024 clock pulses (i.e., the frequency of the MSB output signal (Q9) is the clock frequency divided by 1024). A counter is a digital circuit that has a number of binary outputs whose states progress through a xed sequence. This count sequence can be ascending, descending, or nonlinear. The output sequence of a counter is usually dened by its modulus, that is, the number of states through which the counter progresses. An UP counter with a modulus of 12 counts through 12 states from 0000 up to 1011 (0 to 11 in decimal), recycles to 0000, and continues. A DOWN counter with a modulus of 12 counts from 1011 down to 0000, recycles to 1011, and continues downward. Both types of counter are called modulo-12, or just mod-12 counters, since they both have sequences of 12 states. State Diagram The states of a counter can be represented by a state diagram. Figure 9.2 compares the state diagram of a mod-12 UP counter to an analog clock face. Each counter state is illustrated in the state diagram by a circle containing its binary value. The progression is shown by a series of directional arrows. Both the clock face and the state diagram represent a closed system of counting. In each case, when we reach the end of the count sequence, we start over from the beginning of the cycle. For instance, if it is 10:00 a.m. and we want to meet a friend in four hours, we know we should turn up for the appointment at 2:00 p.m. We arrive at this gure by starting at 10 on the clock face and counting 4 digits forward in a clockwise circle. This takes us two digits past 12, the recycle point of the clock face. Similarly, if we want to know the 8th state after 0111 in a mod-12 UP counter, we start at state 0111 and count 8 positions in the direction of the arrows. This brings us to state 0000 (the recycle point) in 5 counts and then on to state 0011 in another 3 counts. 366 C H A P T E R 9 Counters and Shift Registers FIGURE 9.2 Mod-12 State Diagram and Analog Clock Face Number of Bits and Maximum Modulus KEY TERMS Maximum modulus (mmax) The largest number of counter states that can be represented by n bits (mmax 2n). Full-sequence counter A counter whose modulus is the same as its maximum modulus (m 2n for an n-bit counter). Binary counter A counter that generates a binary count sequence. Truncated-sequence counter A counter whose modulus is less than its maximum modulus (m 2n for an n-bit counter). The state diagram of Figure 9.2 represents the states of a mod-12 counter as a series of 4bit numbers. Counter states are always written with a xed number of bits, since each bit represents the logic level of a physical location in the counter circuit. A mod-12 counter requires four bits because its highest count value is a 4-bit number: 1011. The maximum modulus of a 4-bit counter is 16 ( 24). The count sequence of a mod16 UP counter is from 0000 to 1111 (0 to 15 in decimal), as illustrated in the state diagram of Figure 9.3. In general, an n-bit counter has a maximum modulus of 2n and a count sequence from 0 to 2n 1 (i.e., all 0s to all 1s). Since a mod-16 counter has a modulus of 2n ( mmax), we say that it is a full-sequence counter. We can also call this a binary counter if it generates the sequence in binary order. A counter, such as a mod-12 counter, whose modulus is less than 2n, is called a truncated sequence counter. Count-Sequence Table and Timing Diagram KEY TERMS Count-sequence table A list of counter states in the order of the count sequence. Two ways to represent a count sequence other than a state diagram are by a count sequence table and by a timing diagram. The count sequence table is simply a list of counter states in the same order as the count sequence. Tables 9.1 and 9.2 show the count sequence tables of a mod-16 UP counter and a mod-12 UP counter, respectively. 9.1 FIGURE 9.3 State Diagram of a Mod-16 Counter Basic Concepts of Digital Counters 367 Table 9.1 Mod-16 Count Sequence Table Q3Q2Q1Q0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 9.2 Mod-12 Count-Sequence Table Q3Q2Q1Q0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 We can derive timing diagrams from each of these tables. We know that each counter advances by one state with each applied clock pulse. The mod-16 count sequence shows us that the Q0 waveform changes state with each clock pulse. Q1 changes with every two clock pulses, Q2 with every four, and Q3 with every eight. Figure 9.4 shows this pattern for the mod-16 UP counter, assuming the counter is a positive edgetriggered device. CLK Q0 Q1 Q2 Q3 FIGURE 9.4 Mod-16 Timing Diagram 368 C H A P T E R 9 Counters and Shift Registers CLK Q0 Q1 Q2 Q3 FIGURE 9.5 Mod-12 Timing Diagram A divide-by-two ratio relates the frequencies of adjacent outputs of a binary counter. For example, if the clock frequency is fc 16 MHz, the frequencies of the output waveforms are: 8 MHz ( f0 fc/2); 4 MHz ( f1 fc/4); 2 MHz ( f2 fc/8); 1 MHz ( f3 fc/16). We can construct a similar timing diagram, illustrated in Figure 9.5, for a mod-12 UP counter. The changes of state can be monitored by noting where Q0 (the least signicant bit) changes. This occurs on each positive edge of the CLK waveform. The sequence progresses by 1 with each CLK pulse until the outputs all go to 0 on the rst CLK pulse after state Q3Q2Q1Q0 1011. The output waveform frequencies of a truncated sequence counter do not necessarily have a simple relationship to one another as do binary counters. For the mod-12 counter the relationships between clock frequency, fc, and output frequencies are: f0 fc/2; f1 fc/4; f2 fc/12; f3 fc/12. Note that both Q2 and Q3 have the same frequencies ( f2 and f3), but are out of phase with one another. EXAMPLE 9.2 Draw the state diagram, count sequence table, and timing diagram for a mod-12 DOWN counter. Solution Figure 9.6 shows the state diagram for the mod-12 DOWN counter. The states are identical to those of a mod-12 UP counter, but progress in the opposite direction. Table 9.3 shows the count sequence table of this circuit. FIGURE 9.6 Example 9.2 State Diagram of a Mod-12 DOWN Counter 9.2 Synchronous Counters 369 Table 9.3 CountSequence Table for a Mod-12 DOWN Counter Q3Q2Q1Q0 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 CLK Q0 Q1 Q2 Q3 FIGURE 9.7 Example 9.2 Timing Diagram of a Mod-12 DOWN Counter The timing diagram of this counter is illustrated in Figure 9.7. The output starts in state Q3Q2Q1Q0 1011 and counts DOWN until it reaches 0000. On the next pulse, it recycles to 1011 and starts over. SECTION 9.1 REVIEW PROBLEM 9.1 How many outputs does a mod-24 counter require? Is this a full-sequence or a truncated sequence counter? Explain your answer. 9.2 Synchronous Counters KEY TERMS Synchronous counter A counter whose ip-ops are all clocked by the same source and thus change in synchronization with each other. Present state The current state of ip-op outputs in a synchronous sequential circuit. Next state The desired future state of ip-op outputs in a synchronous sequential circuit after the next clock pulse is applied. Memory section A set of ip-ops in a synchronous circuit that hold its present state. 370 C H A P T E R 9 Counters and Shift Registers Control section The combinational logic portion of a synchronous circuit that determines the next state of the circuit. Status lines Signals that communicate the present state of a synchronous circuit from its memory section to its control section. Command lines Signals that connect the control section of a synchronous circuit to its memory section and direct the circuit from its present to its next state. In Chapter 7, we briey examined the circuits of a 3-bit and a 4-bit synchronous counter (Figures 7.53 and 7.87, respectively). A synchronous counter is a circuit consisting of ipops and control logic, whose outputs progress through a regular predictable sequence, driven by a clock signal. The counter is synchronous because all ip-ops are clocked at the same time. Figure 9.8 shows the block diagram of a synchronous counter, which consists of a memory section to keep track of the present state of the counter and a control section to direct the counter to its next state. The memory section is a sequential circuit (ip-ops) and the control section is combinational (gates). They communicate through a set of status lines that go from the Q outputs of the ip-ops to the control gate inputs and command lines that connect the control gate outputs to the synchronous inputs (J, K, D, or T) of the ip-ops. Outputs can be tied directly to the status lines or can be decoded to give a sequence other than that of the ip-op output states. The circuit might have inputs to implement one or more control functions, such as changing the count direction, clearing the counter, or presetting the counter to a specic value. Input lines Control section (gates) Command lines Status lines Output decoder (optional) Output lines Memory section (flip-flops) CLK FIGURE 9.8 Synchronous Counter Block Diagram Analysis of Synchronous Counters A 3-bit synchronous binary counter based on JK ip-ops is shown in Figure 9.9. Let us analyze its count sequence in detail so that we can see how the J and K inputs are affected by the Q outputs and how transitions between states are made. Later we will look at the function of truncated sequence counter circuits and counters that are made from ip-ops other than JK. The synchronous input equations are given by: J2 J1 J0 K2 K1 K0 Q1 Q0 Q0 1 9.2 Synchronous Counters 371 VCC JKFF J JKFF PRN Q J K CLRN CLK JKFF AND2 PRN Q J K CLRN PRN Q K CLRN INPUT OUTPUT OUTPUT OUTPUT Q2 Q1 Q0 FIGURE 9.9 3-bit Synchronous Binary Counter For reference, the JK ip-op function table is shown in Table 9.4: Table 9.4 Function Table of a JK Flip-Flop J K 0 0 1 1 0 1 0 1 Qt Function 1 Qt 0 1 Qt No change Reset Set Toggle Qt indicates the state of Q before a clock pulse is applied. Qt 1 indicates the state of Q after the clock pulse. Assume the counter output is initially Q2Q1Q1 000. Before any clock pulses are applied, the J and K inputs are at the following states: J2 J1 J0 K2 Q1 Q0 00 K1 K0 0 Q0 0 1 (Constant) (No change) (No change) (Toggle) The transitions of the outputs after the clock pulse are: Q2: 0 0 Q1: 0 0 Q0: 0 1 (No change) (No change) (Toggle) The output goes from Q2Q1Q1 000 to Q2Q1Q1 001 (see Figure 9.10). The transition is dened by the values of J and K before the clock pulse, since the propagation delays of the ip-ops prevent the new output conditions from changing the J and K values until after the transition. The new conditions of the J and K inputs are: J2 J1 J0 K2 K1 K0 Q1 Q0 0 1 Q0 1 1 (Constant) 0 (No change) (Toggle) (Toggle) 372 C H A P T E R 9 Counters and Shift Registers The transitions of the outputs generated by the second clock pulse are: Q2: 0 0 Q1: 0 1 Q0: 1 0 (No change) (Toggle) (Toggle) The new output is Q2Q1Q0 010, since both Q0 and Q1 change and Q2 stays the same. The J and K conditions are now: J2 J1 J0 K2 K1 K0 Q1 Q0 1 0 Q0 0 1 (Constant) 0 (No change) (No change) (Toggle) The output transitions are: Q2: 0 0 Q1: 1 1 Q0: 0 1 The output is now Q2Q1Q0 J2 J1 J0 K2 K1 K0 (No change) (No change) (Toggle) 011, which results in the JK conditions: Q1 Q0 1 1 Q0 1 1 (Constant) 1 (Toggle) (Toggle) (Toggle) The above conditions result in output transitions: Q2: 0 1 Q1: 1 0 Q0: 1 0 (Toggle) (Toggle) (Toggle) All the outputs toggle and the new output state is Q2Q1Q0 100. The J and K values repeat the above pattern in the second half of the counter cycle (states 100 to 111). Go through the exercise of calculating the J, K, and Q values for the rest of the cycle. Compare the result with the timing diagram in Figure 9.10. Recycle point CLK Q0 0 1 0 Q1 0 1 0 Q2 0 1 0 FIGURE 9.10 Timing Diagram for a Synchronous 3-bit Binary Counter In the counter we have just analyzed, the combinational circuit generates either a toggle (JK 11) or a no change (JK 00) state at each point through the count sequence. We could use any combination of JK modes (no change, reset, set, or toggle) to make the transitions from one state to the next. For instance, instead of using only the no change and toggle modes, the 000 001 transition could also be done by making Q0 set (J0 1, 9.2 Synchronous Counters 373 K0 0) and Q1 and Q2 reset (J1 0, K1 1 and J2 0, K2 1). To do so we would need a different set of combinational logic in the circuit. The simplest synchronous counter design uses only the no change (JK 00) or toggle (JK 11) modes, since the J and K inputs of each ip-op can be connected together. The no change and toggle modes allow us to make any transition (i.e., not just in a linear sequence), even though for truncated sequence and nonbinary counters this is not usually the most efcient design. There is a simple progression of algebraic expressions for the J and K inputs of a synchronous binary (full sequence) counter, which uses only the no change and toggle states: J0 J1 J2 J3 J4 etc. K0 K1 K2 K3 K4 1 Q0 Q1 Q0 Q2 Q1 Q0 Q3 Q2 Q1 Q0 The J and K inputs of each stage are the ANDed outputs of all previous stages. This implies that a ip-op toggles only when the outputs of all previous stages are HIGH. For example, Q2 doesnt change unless both Q1 AND Q0 are HIGH (and therefore J2 K2 1) before the clock pulse. In a 3-bit counter, this occurs only at states 011 and 111, after which Q2 will toggle, along with Q1 and Q0, giving transitions to states 100 and 000 respectively. Look at the timing diagram of Figure 9.10 to conrm this. Determining the Modulus of a Synchronous Counter We can use a more formal technique to analyze any synchronous counter, as follows. 1. Determine the equations for the synchronous inputs (JK, D, or T) in terms of the Q outputs for all ip-ops. (For counters other than straight binary full sequence types, the equations will not be the same as the algebraic progressions previously listed.) 2. Lay out a table with headings for the Present State of the counter (Q outputs before CLK pulse), each Synchronous Input before CLK pulse, and Next State of the counter (Q outputs after the clock pulse). 3. Choose a starting point for the count sequence, usually 0, and enter the starting point in the Present State column. 4. Substitute the Q values of the initial present state into the synchronous input equations and enter the results under the appropriate columns. 5. Determine the action of each ip-op on the next CLK pulse (e.g., for a JK ip-op, the output either will not change (JK 00), or will reset (JK 01), set (JK 10), or toggle (JK 11) ). 6. Look at the Q values for every ip-op. Change them according to the function determined in Step 5 and enter them in the column for the counters next state. 7. Enter the result from Step 6 on the next line of the column for the counters present state (i.e., this lines next state is the next lines present state). 8. Repeat the above process until the result in the next state column is the same as the initial state. EXAMPLE 9.3 Find the count sequence of the synchronous counter shown in Figure 9.11 and, from the count sequence table, draw the timing diagram and state diagram. What is the modulus of the counter? 374 C H A P T E R 9 Counters and Shift Registers AND2 NOT JKFF VCC J JKFF PRN Q J K CLRN CLK JKFF PRN Q J VCC K CLRN PRN Q K CLRN INPUT OUTPUT Q2 OUTPUT Q1 OUTPUT Q0 FIGURE 9.11 Synchronous Counter of Unknown Modulus Solution The J and K equations are: J2 K2 Q1 Q0 1 J1 K1 Q0 Q0 J0 K0 Q2 1 The output transitions can be determined from the values of the J and K functions before each clock pulse, as shown in Table 9.5. Table 9.5 State Table for Figure 9.11 Present State Synchronous Inputs Q2Q1Q0 J2K2 000 001 010 011 100 J1K1 01 01 01 11 01 (R) (R) (R) (T) (R) 00 11 00 11 00 Next State J0K0 (NC) (T) (NC) (T) (NC) 11 11 11 11 01 Q2Q1Q0 (T) (T) (T) (T) (R) 001 010 011 100 000 Since there are ve unique output states, the counters modulus is 5. The timing diagram and state diagram are shown in Figure 9.12. Since this circuit produces one pulse on Q2 for every 5 clock pulses, we can use it as a divide-by-5 circuit. FIGURE 9.12 Example 9.3 Timing Diagram and State Diagram of a Mod-5 Counter 000 Recycle 001 100 CLK Q0 0 0 0 Q1 0 0 0 Q2 0 1 0 010 011 a. Timing diagram b. State diagram 9.2 Synchronous Counters 375 The analysis in Example 9.3 did not account for the fact that the counter uses only 5 of a possible 8 output states. In any truncated sequence counter, it is good practice to determine the next state for each unused state to ensure that if the counter powers up in one of these unused states, it will eventually enter the main sequence. EXAMPLE 9.4 Extend the analysis of the counter in Example 9.3 to include its unused states. Redraw the counters state diagram to show how these unused states enter the main sequence (if they do). Solution The synchronous input equations are: J2 K2 Q1 Q0 1 J1 K1 Q0 Q0 J0 K0 Q2 1 The unused states are Q2Q1Q0 101, 110, and 111. Table 9.6 shows the transitions made by the unused states. Figure 9.13 shows the completed state diagram. Table 9.6 State Table for Mod-5 Counter Including Unused States Present State Synchronous Inputs J1K1 Next State Q2Q1Q0 J2K2 J0K0 Q2Q1Q0 000 001 010 011 100 01 01 01 11 01 (R) (R) (R) (T) (R) 00 11 00 11 00 (NC) (T) (NC) (T) (NC) 11 11 11 11 01 (T) (T) (T) (T) (R) 001 010 011 100 000 101 110 111 01 01 11 (R) (R) (T) 11 00 11 (T) (NC) (T) 01 01 01 (R) (R) (R) 010 010 000 FIGURE 9.13 Example 9.4 Complete State Diagram SECTION 9.2 REVIEW PROBLEM 9.2 A 4-bit synchronous counter based on JK ip-ops is described by the following set of equations: J3 K3 Q2Q1Q0 Q0 J2 K2 Q1Q0 Q1Q0 J1 K1 Q3Q0 Q0 J0 K0 1 1 376 C H A P T E R 9 Counters and Shift Registers Assume the counter output is at 1000 in the count sequence. What will the output be after one clock pulse? After two clock pulses? 9.3 Design of Synchronous Counters KEY TERMS Excitation table A table showing the required input conditions for every possible transition of a ip-op output. State machine A synchronous sequential circuit. A synchronous counter can be designed using established techniques that involve the derivation of Boolean equations for the counters next state logic. Alternatively, several VHDL structures can be used to dene counters; we can use a behavioral description of the counter, or we can use a state machine denition in VHDL that species each present and next state explicitly. In addition to the classical counter design techniques, we will examine the design of a counter through a behavioral description in VHDL. We will leave the state machine design for the following chapter. Classical Design Technique There are several steps involved in the classical design of a synchronous counter. 1. Dene the problem. Before you can begin design of a circuit, you have to know what its purpose is and what it should do under all possible conditions. 2. Draw a state diagram showing the progression of states under various input conditions and what outputs the circuit should produce, if any. 3. Make a state table which lists all possible Present States and the Next State for each one. List the present states in binary order. 4. Use ip-op excitation tables to determine at what states the ip-op synchronous inputs must be to make the circuit go from each Present State to its Next State. 5. The logic levels of the synchronous inputs are Boolean functions of the ip-op outputs and the control inputs. Simplify the expression for each input and write the simplied Boolean expression. 6. Use the Boolean expressions found in step 5 to draw the required logic circuit. Flip-op Excitation Tables In the synchronous counter circuits we examined earlier in this chapter, we used JK ipops that were congured to operate only in toggle or no change mode. We can use any type of ip-op for a synchronous sequential circuit. If we choose to use JK ip-ops, we can use any of the modes (no change, reset, set, or toggle) to make transitions from one state to another. A ip-op excitation table shows all possible transitions of a ip-op output and the synchronous input levels needed to effect these transitions. Table 9.7 is the excitation table of a JK ip-op. If we want a ip-op to make a transition from 0 to 1, we can use either the toggle function (JK 11) or the set function (JK 10). It doesnt matter what K is, as long as J 1. This is reected by the variable pair (JK 1X) beside the 0 1 entry in Table 9.7. The X is a dont care state, a 0 or 1 depending on which is more convenient for the simplication of the Boolean function of the J or K input affected. Table 9.8 shows a condensed version of the JK ip-op excitation table. 9.3 Table 9.7 JK Flip-Flop Excitation Table Transition Function No change or reset 00 Table 9.8 Condensed Excitation Table for a JK Flip-Flop JK 00 01 10 11 Toggle or set 0X Transition JK 1X 00 01 10 11 0X 1X X1 X0 01 11 10 Toggle or reset 11 No change or set 00 377 Design of Synchronous Counters X1 01 X0 10 Design of a Synchronous Mod-12 Counter We will follow the procedure outlined above to design a synchronous mod-12 counter circuit, using JK ip-ops. The aim is to derive the Boolean equations of all J and K inputs and to draw the counter circuit. 1. Dene the problem. The circuit must count in binary sequence from 0000 to 1011 and repeat. The output progresses by 1 for each applied clock pulse. Since the outputs are 4-bit numbers, we require 4 ip-ops. 2. Draw a state diagram. The state diagram for this problem is shown in Figure 9.14. 3. Make a state table showing each present state and the corresponding next state. 4. Use ip-op excitation tables to ll in the J and K entries in the state table. Table 9.9 shows the combined result of steps 3 and 4. Note that all present states are in binary order. We assume for now that states 1100 to 1111 never occur. If we assign their corresponding next states to be dont care states, they can be used to simplify the J and K expressions we derive from the state table. FIGURE 9.14 State Diagram for a Mod-12 Counter 378 C H A P T E R 9 Counters and Shift Registers Table 9.9 State Table for a Mod-12 Counter Present State Next State Synchronous Inputs Q3Q2Q1Q0 Q3Q2Q1Q0 J3K3 J2K2 J1K1 J0K0 0000 0001 0010 0011 00 01 00 10 00 11 01 00 0X 0X 0X 0X 0X 0X 0X 1X 0X 1X X0 X1 1X X1 1X X1 0100 0101 0110 0111 01 01 01 10 01 11 10 00 0X 0X 0X 1X X0 X0 X0 X1 0X 1X X0 X1 1X X1 1X X1 1000 1001 1010 1011 10 01 10 10 10 11 00 00 X0 X0 X0 X1 0X 0X 0X 0X 0X 1X X0 X1 1X X1 1X X1 1100 1101 1110 1111 XXXX XXXX XXXX XXXX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX Let us examine one transition to show how the table is completed. The transition from Q3Q2Q1Q0 0101 to Q3Q2Q1Q0 0110 consists of the following individual ipop transitions. Q3: 0 0 Q2: 1 1 Q1: 0 1 Q0: 1 0 (No change or reset; (No change or set; (Toggle or set; (Toggle or reset; J3K3 J2K2 J1K1 J0K0 0X) X0) 1X) X1) The other lines of the table are similarly completed. 5. Simplify the Boolean expression for each input. Table 9.9 can be treated as eight truth tables, one for each J or K input. We can simplify each function by Boolean algebra or by using a Karnaugh map. Figure 9.15 shows K-map simplication for all 8 synchronous inputs. These maps yield the following simplied Boolean expressions. J0 K0 1 1 J1 K1 Q0 Q0 J2 K2 Q3Q1Q0 Q1Q0 J3 K3 Q2Q1Q0 Q1Q0 6. Draw the required logic circuit. Figure 9.16 shows the circuit corresponding to the above Boolean expressions. We have assumed that states 1100 to 1111 will never occur in the operation of the mod-12 counter. This is normally the case, but when the circuit is powered up, there is no guarantee that the ip-ops will be in any particular state. If a counter powers up in an unused state, the circuit should enter the main sequence after one or more clock pulses. To test whether or not this happens, let us make a state 9.3 FIGURE 9.15 K-Map Simplication of Table 9.9 Design of Synchronous Counters 379 380 INPUT PRN Q K CLRN J JKFF FIGURE 9.16 Synchronous Mod-12 Counter CLK VCC PRN Q K CLRN J JKFF NOT AND2 AND3 PRN Q K CLRN J JKFF AND3 PRN Q K CLRN J JKFF OUTPUT OUTPUT OUTPUT OUTPUT Q0 Q1 Q2 Q3 9.3 Design of Synchronous Counters 381 Table 9.10 Unused States in a Mod-12 Counter Present State Synchronous Inputs Next State Q3Q2Q1Q0 J3K3 J2K2 J1K1 J0K0 Q3Q2Q1Q0 0000 1101 1110 1111 00 00 00 11 00 00 00 01 00 11 00 11 11 11 11 11 1101 1110 1111 0000 table, applying each unused state to the J and K equations as implemented, to see what the Next State is for each case. This analysis is shown in Table 9.10. Figure 9.17 shows the complete state diagram for the designed mod-12 counter. If the counter powers up in an unused state, it will enter the main sequence in no more than four clock pulses. If we want an unused state to make a transition directly to 0000 in one clock pulse, we have a couple of options: 1. We could reset the counter asynchronously and otherwise leave the design as is. 2. We could rewrite the state table to specify these transitions, rather than make the unused states dont cares. Option 1 is the simplest and is considered perfectly acceptable as a design practice. Option 2 would yield a more complicated set of Boolean equations and hence a more complex circuit, but might be worthwhile if a direct synchronous transition to 0000 were required. FIGURE 9.17 Complete State Diagram of Mod-12 Counter in Figure 9.16 382 C H A P T E R 9 Counters and Shift Registers EXAMPLE 9.5 Derive the synchronous input equations of a 4-bit synchronous binary counter based on D ip-ops. Draw the corresponding counter circuit. Solution The rst step in the counter design is to derive the excitation table of a D ipop. Recall that Q follows D when the ip-op is clocked. Therefore the next state of Q is the same as the input D for any transition. This is illustrated in Table 9.11. Table 9.11 Excitation Table of a D Flip-Flop Transition D 00 01 10 11 0 1 0 1 Next, we must construct a state table, shown in Table 9.12, with present and next states for all possible transitions. Note that the binary value of D3D2D1D0 is the same as the next state of the counter. Table 9.12 State Table for a 4-bit Binary Counter Present State Next State Synchronous Inputs Q3Q2Q1Q0 Q3Q2Q1Q0 D3D2D1D0 0000 0001 0010 0011 0001 0010 0011 0100 0001 0010 0011 0100 0100 0101 0110 0111 0101 0110 0111 1000 0101 0110 0111 1000 1000 1001 1010 1011 1001 1010 1011 1100 1001 1010 1011 1100 1100 1101 1110 1111 1101 1110 1111 0000 1101 1110 1111 0000 This state table yields four Boolean equations, for D3 through D0, in terms of the present state outputs. Figure 9.18 shows four Karnaugh maps used to simplify these functions. The simplied equations are: D3 D2 D1 D0 Q3Q2Q1Q0 Q3Q2 Q3Q1 Q2Q1Q0 Q2Q1 Q1Q0 Q1Q0 Q1Q0 Q0 Q3Q0 9.3 Design of Synchronous Counters 383 FIGURE 9.18 Example 9.5 K-Maps for a 4-bit Counter Based on D Flip-Flops These equations represent the maximum SOP simplications of the input functions. However, we can rewrite them to make them more compact. For example the equation for D3 can be rewritten, using DeMorgans theorem ( x y z xyz) and our knowledge of Exclusive OR (XOR) functions ( xy xy x y). D3 Q3Q2Q1Q0 Q3Q2 Q3Q1 Q3(Q2Q1Q0) Q3(Q2 Q1 Q3(Q2Q1Q0) Q3(Q2Q1Q0) Q3 Q2Q1Q0 Q3Q0 Q0) We can write similar equations for the other D inputs as follows: D2 D1 D0 Q2 Q1 Q0 Q1Q0 Q0 1 These equations follow a predictable pattern of expansion. Each equation for an input Dn is simply Qn XORed with the logical product (AND) of all previous Qs. Figure 9.19 shows the circuit for the 4-bit counter, including an asynchronous reset. 384 C H A P T E R 9 Counters and Shift Registers FIGURE 9.19 Example 9.5 4-bit Counter Using D Flip-Flops DFF AND3 XOR D PRN Q OUTPUT Q3 CLRN DFF AND2 XOR D PRN Q OUTPUT Q2 CLRN DFF XOR D PRN Q OUTPUT Q1 CLRN DFF NOT D CLOCK RESET INPUT PRN Q OUTPUT Q0 CLRN INPUT In Section 7.6 (Edge-Triggered T Flip-Flops) of Chapter 7, we saw how a D ip-op could be congured for a switchable toggle function (refer to Figure 7.59). The ip-ops in Figure 9.19 are similarly congured. Each ip-op output, except Q0, is fed back to its input through an Exclusive OR gate. The other input to the XOR controls whether this feedback is inverted (for toggle mode) or not (for no change mode). Recall that x 0 x and x 1 x. For example, Q3 is fed back to D3 through an XOR gate. The feedback is inverted only if the 3-input AND gate has a HIGH output. Thus, the Q3 output toggles only if all previous bits are HIGH (Q3Q2Q1Q0 0111 or 1111). The ip-op toggle mode is therefore controlled by the states of the XOR and AND gates in the circuit. SECTION 9.3 REVIEW PROBLEM 9.3 A 4-bit synchronous counter must make a transition from state Q3Q2Q1Q0 1011 to Q3Q2Q1Q0 1100. Write the required states of the synchronous inputs for a set of four JK ip-ops used to implement the counter. Write the required states of the synchronous inputs if the counter is made from D ip-ops. 9.4 Programming Binary Counters in VHDL 385 9.4 Programming Binary Counters in VHDL KEY TERMS If statement A VHDL construct in which statements within the IF statement are executed only when a specied Boolean condition is satised. Attribute A property associated with a named identier in VHDL. (For example, the attribute EVENT, when associated with the identier clk (written clkEVENT), indicates, when true, that a transition has occurred on the input called clk.) When using VHDL to create a counter, we can take several approaches. We can encode the Boolean equations of the counter directly with concurrent signal assignment statements; we can use VHDL code to describe the behavior of the counter; we can use a CASE statement to implement the state diagram of the counter; or we can use a predened counter, such as those found in the MAX PLUS II Library of Parameterized Modules (LPM) and map its ports to the ports of a VHDL design entity. If we chose to use concurrent signal assignments to encode the Boolean equations of a counter, we could derive the following equations for a 4-bit counter with D ip-ops. d(3)<= d(2)<= d(1)<= d(0)<= q(3)xor(q(2)and q(1)and q(0));, q(2)xor(q(1)and q(0)); q(1)xor q(1);, not q(0);, In Chapter 5, we saw that using concurrent signal assignment statements is an inefcient way to code many digital functions. (For one thing, if we use this procedure, we must know what the equations are. Getting to that point requires a lot of work that can be done by the VHDL compiler.) While acknowledging this as a possible option, we will not examine this method any further for the count logic of binary counters. In this section, we will design a counter using a behavioral description and using an LPM counter. The design of a counter as a state machine will be examined in the next chapter. Behavioral Description of Counters The following VHDL code shows the behavioral description of a simple 8-bit counter (ct_simp.vhd) with asynchronous clear. ct_simp.vhd ENTITY ct_simp IS PORT( clk : IN clear : IN q : OUT END ct_simp; BIT; BIT; INTEGER RANGE 0 TO 255); ARCHITECTURE a OF ct_simp IS BEGIN PROCESS (clk, clear) VARIABLE count : INTEGER RANGE 0 TO 255; BEGIN If (clear = 0) THEN count := 0; ELSE IF (clkEVENT AND clk = 1) THEN count := count + 1; END IF; 386 C H A P T E R 9 Counters and Shift Registers END IF; q <= count; END PROCESS; END a; Recall that the PROCESS statement has the following syntax: PROCESS (sensitivity list) [VARIABLE variable name :type [range]; ] BEGIN Process statements END PROCESS; Square brackets [ ] indicate an optional part of the code. When there is a change in an item in the sensitivity list, the process statements are executed. For a synchronous counter, the list would often only include clock, since any action in a synchronous circuit depends on a clock transition. Since the clear function in this counter is asynchronous, the clear input must also be monitored for any changes. To hold the accumulating output value of the counter, we dene a variable called count, presumed to have an initial value of 0, but dened for the range of 0 to 255. (This 8bit value rolls over to 0 when the count exceeds 255.) The variable (any variable) is local to the process in which it is dened. We update the value of count by an IF statement, with the form: IF (condition) THEN Statement[s]; [ELSIF (condition) THEN statement[s];] [ELSE statement[s];] END IF; The clause (IF (clear=0) THEN) monitors the asynchronous clear function independently of the clock and executes the variable assignment that sets the output to 0 if the Boolean condition (clear=0) is true. Otherwise, the clock is monitored for a positive edge by the condition (clkEVENT AND clk = 1). The clause clkEVENT (pronounced clock tick event) is a predened attribute of the clock signal and is true if there has just been a change on clock. The combination of this and the condition clk = 1 indicates that a positive edge has just occurred. If this is true, the count is incremented. As a nal step, the accumulated count must be assigned to an output port. This is done in the concurrent signal assignment q <= count at the end of the process. Note the difference in types of assignments. A variable is assigned by the : operator (e.g., count := count + 1;). A signal is assigned by the <= operator (eg., q <= count). LPM Counters in VHDL lpm_simp.vhd We can use a component (lpm_counter) from the Library of Parameterized Modules (LPM) to instantiate a counter in VHDL. When using an LPM counter, we dont need to describe the behavior of the counter, as this has been done for us in the module itself. All we need to do is map the ports and parameters of the LPM component to the ports of the VHDL design entity. We do this by using a generic map to specify the parameters we need and a port map to map the ports of the LPM device either to an external port or an internal signal. The VHDL code below shows the VHDL implementation (lpm_simp.vhd) of the same 8-bit counter as in the previous behavioral example. lpm_simp.vhd Eight-bit binary counter based on a component 9.4 Programming Binary Counters in VHDL 387 from the Library of Parameterized Modules (LPM) Counter has an active-LOW asynchronous clear. LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY lpm_simp IS PORT( clk, clear : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (7 downto 0)); END lpm_simp; ARCHITECTURE count OF lpm_simp IS SIGNAL clrn : STD_LOGIC; BEGIN count8: lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP ( clock => clk, aclr => clrn, q => q(7 downto 0)); clrn <= not clear; END count; LPM components require us to use two packages: the std_logic_1164 package in the ieee library to dene STD_LOGIC types used in the LPM components and the lpm_components package in the lpm library to dene the components themselves. Since LPM components are dened using STD_LOGIC and STD_LOGIC_VECTOR types, we should use these types for our other identiers as well. The entity declaration denes the inputs and outputs of our counter and need not correspond to the port names for the LPM counter. That correspondence is dened in the architecture body, where we instantiate the counter module. The counter is dened in a component instantiation statement, which takes the following form: __instance_name: __component_name GENERIC MAP (__parameter_name => __parameter_value, __parameter_name => __parameter_value) PORT MAP (__component_port => __connect_port, __component_port => __connect_port); The component name is the name of the LPM component. Parameter names are those dened in the LPM component, such as LPM_WIDTH. Parameter values are those values assigned in the instance of the component. Component ports are the LPM port names. Connect ports are the names of identiers declared in the entity or as signals or variables. If we want to invert the active level of an LPM input port, we must use a signal assignment statement. (e.g., clrn <= not clear;) We need to do this because a VHDL input port cannot be updated (modied); only an output can be assigned a new value as a result of a Boolean expression. Thus, we create a signal called clrn that maps to the aclr (asynchronous clear) port of the LPM counter. This is connected to the clear input of the counter circuit via an inverter. Figure 9.20 shows the graphic equivalent of this mapping. SECTION 9.4 REVIEW PROBLEM 9.4 Write a VHDL code segment that increments a variable called count upon detection of a negative edge of an input called clock. 388 C H A P T E R 9 Counters and Shift Registers FIGURE 9.20 Graphic Equivalent of an LPM Counter with Active-Low Clear LPM_COUNTER q[] OUTPUT qd[7..0] INPUT aclr clock LPM_AVALUE= LPM_DIRECTION= LPM_MODULUS= LPM_SVALUE= LPM_WIDTH=8 NOT clear INPUT clrn 9.5 Control Options for Synchronous Counters KEY TERMS Parallel load A function that allows simultaneous loading of binary values into all ip-ops of a synchronous circuit. Parallel loading can be synchronous or asynchronous. Presettable counter A counter with a parallel load function. Clear Reset (synchronous or asynchronous). Count enable A control function that allows a counter to progress through its count sequence when active and disables the counter when inactive. Bidirectional counter A counter that can count up or down, depending on the state of a control input. Terminal count The last state in a count sequence before the sequence repeats (e.g., 1111 is the terminal count of a 4-bit binary UP counter; 0000 is the terminal count of a 4-bit binary DOWN counter). Ripple carry out or ripple clock out (RCO) An output that produces one pulse with the same period as the clock upon terminal count. Synchronous counters can be designed with a number of features other than just straight counting. Some of the most common features include: Synchronous or asynchronous parallel load, which allows the count to be set to any value whenever a LOAD input is asserted Synchronous or asynchronous clear (reset), which sets all of the counter outputs to zero Count enable, which allows the count sequence to progress when asserted and inhibits the count when deasserted Bidirectional control, which determines whether the counter counts up or down Output decoding, which activates one or more outputs when detecting particular states on the counter outputs Ripple carry out or ripple clock out (RCO), a special case of output decoding that produces a pulse upon detecting the terminal count, or last state, of a count sequence. 9.5 Control Options for Synchronous Counters 389 We will examine the implementation of these functions, rst as Graphic Design Files in MAX PLUS II, and then, in the next section, in VHDL, both as behavioral descriptions and as functions of LPM counters. Parallel Loading Figure 9.21 shows the symbol of a 4-bit presettable counter (i.e., a counter with a parallel load function). The parallel inputs, P3 to P0, have direct access to the ip-ops of the counter. When the LOAD input is asserted, the values at the P inputs are loaded directly into the counter and appear at the Q outputs. NOTE Parallel loading requires at least two sets of inputs: the load data (P3 to P0) and the load command (LOAD). If the load function is synchronous, as described below, it also requires a clock input. FIGURE 9.21 4-bit Counter with Parallel Load P3 P2 P1 P0 LOAD CTR DIV 16 CLOCK Q3 Q2 Q1 Q0 MSB 4b_al_sl.scf LSB Parallel loading can be synchronous or asynchronous. The MAX PLUS II simulation in Figure 9.22 shows the difference. Two waveforms, QS[3..0] and QA[3..0], represent the outputs of two 4-bit counters with synchronous and asynchronous load, respectively. Both counters have the same clock, load, and P inputs. The count is already in progress at the beginning of the simulation window and shows both counters advancing with each clock pulse: 4, 5, 6. When LOAD goes HIGH at 500 ns, the value of P[3..0] ( AH) is loaded into the asynchronously loading counter (QA[3..0]) immediately after a short propagation delay (12.5 ns). The counter with synchronous load (QS[3..0]) is not loaded until the next positive clock edge, shown at 560 ns. FIGURE 9.22 Synchronous vs. Asynchronous Load Synchronous Load The logic diagram of Figure 9.23 shows the concept of synchronous parallel load. Depending on the status of the LOAD input, the ip-op will either count according to its 390 C H A P T E R 9 Counters and Shift Registers Count_Logic LOAD INPUT INPUT AND2 NOT DFF OR2 D AND2 P3 CLOCK PRN Q OUTPUT Q3 INPUT CLRN INPUT FIGURE 9.23 Count/Load Selection count logic (the next-state combinational circuit) or load an external value. The ip-op shown is the most signicant bit of a 4-bit binary counter, such as shown in Figure 9.19, but with the count logic represented only by an input pin. (For the fourth bit of a counter, the Boolean equation of the count logic is given by D3 Q3 Q2Q1Q0. It is left out in order to more clearly show the operation of the count/load function select circuit.) The LOAD input selects whether the ip-op synchronous input will be fed by the count logic or by the parallel input P3. When LOAD 0, the upper AND gate steers the count logic to the ip-op, and the count progresses with each clock pulse. When LOAD 1, the lower AND gate loads the logic level at P3 directly into the ip-op on the next clock pulse. Count logic Q2 Q1 Q0 INPUT XOR AND3 INPUT INPUT AND2 LOAD INPUT NOT OR2 AND2 P3 CLOCK RESET DFF D PRN Q OUTPUT Q3 INPUT INPUT CLRN INPUT FIGURE 9.24 Counter Element with Synchronous Load and Asynchronous Clear sl_count.gdf 4bit_sl.gdf 4bit_sl.scf Figure 9.24 shows the same circuit, but includes the count logic. If we leave out the 3-input AND gate, as in Figure 9.25, we have a circuit that can be used as a general element (called sl_count) in a synchronous presettable counter. Figure 9.26 shows the logic diagram of a 4-bit synchronously presettable counter consisting of four instances of the counter element of Figure 9.25 and appropriate AND gates for a synchronous counter. This diagram implements a synchronous counter like that of Figure 9.19, but also incorporates a synchronous load function. Figure 9.27 shows a simulation of the counter in Figure 9.26. The rst 19 clock pulses drive the counter through its normal 4-bit cycle from 0H to FH, then up to 2H. At this point, we set the LOAD input HIGH and the value at the P inputs (9H) is loaded into the counter on the rising edge of the next clock pulse. An asynchronous RESET pulse at 880 ns drives the counter outputs to 0H, after which the count resumes. 9.5 391 Control Options for Synchronous Counters XOR INPUT COUNT AND2 INPUT LOAD NOT OR2 DFF D AND2 PRN Q OUTPUT Q INPUT P CLRN INPUT CLOCK INPUT RESET FIGURE 9.25 Counter Element with Synchronous Load and Asychronous Reset (sl_count) sl_count AND3 COUNT LOAD P3 INPUT Q P OUTPUT Q3 CLOCK RESET sl_count AND2 COUNT LOAD P2 INPUT Q P OUTPUT Q2 CLOCK RESET sl_count COUNT LOAD P1 INPUT Q P OUTPUT Q1 CLOCK RESET VCC sl_count COUNT LOAD P0 CLOCK RESET INPUT INPUT INPUT INPUT FIGURE 9.26 4-bit Counter with Synchronous Load and Asynchronous Reset LOAD P CLOCK RESET Q OUTPUT Q0 392 C H A P T E R 9 Counters and Shift Registers FIGURE 9.27 Simulation of 4-bit Counter with Synchronous Load and Asynchronous Reset Asynchronous Load The asynchronous load function of a counter makes use of the asynchronous preset and clear inputs of the counters ip-ops. Figure 9.28 shows the circuit implementation of the asynchronous load function, without any count logic. When ALOAD (Asynchronous LOAD) is HIGH, both NAND gates in Figure 9.28 are enabled. If the P input is HIGH, the output of the upper NAND gate goes LOW, activating the ip-ops asynchronous PRESET input, thus setting Q 1. The lower NAND gate has a HIGH output, thus deactivating the ip-ops CLEAR input. If P is LOW the situation is reversed. The upper NAND output is HIGH and the lower NAND has a LOW output, activating the ip-ops CLEAR input, resetting Q. Thus, Q will be the same value as P when the ALOAD input is asserted. When ALOAD is not asserted ( 0), both NAND outputs are HIGH and thus do not activate either the preset or clear function of the ip-op. Figure 9.29 shows the asynchronous load circuit with an asynchronous clear (reset) function added. The ip-op can be cleared by a logic LOW either from the P input (via the lower NAND gate) or the CLEAR input pin. The clear function disables the upper NAND gate when it is LOW, preventing the ip-op from being cleared and preset simultaneously. This extra connection also ensures that the clear function has priority over the load function. P ALOAD COUNT CLK NAND2 INPUT INPUT DFF INPUT D INPUT NAND2 NOT FIGURE 9.28 Asynchronous LOAD Element PRN Q CLRN OUTPUT Q 9.5 INPUT ALOAD DFF INPUT D 393 NAND3 INPUT P Control Options for Synchronous Counters D PRN OUTPUT Q Q INPUT CLK NAND2 NOT CLRN BNOR2 INPUT CLEAR FIGURE 9.29 Asynchronous LOAD Element with Asynchronous Clear EXAMPLE 9.6 Use MAX PLUS II to redraw the circuit in Figure 9.29 to create a general element called al_count that can be used in a synchronous counter with asynchronous load and clear. (Refer to Figure 9.25 for a similar element with synchronous load.) al_count.gdf Solution Figure 9.30 shows the modied circuit, which includes an XOR gate for part of the count logic. The remainder of the count logic must be supplied externally to this element for each bit of the counter. P ALOAD NAND3 INPUT INPUT XOR COUNT CLK INPUT D INPUT NAND2 NOT CLEAR DFF PRN Q OUTPUT Q CLRN BNOR2 INPUT FIGURE 9.30 Example 9.6 Counter Element with Asynchronous Load and Clear (al_count) EXAMPLE 9.7 4bit_al.gdf 4bit_al.scf Draw a circuit with four instances of al_count (from Example 9.6) to make a 4-bit synchronous counter with asynchronous load and reset. Create a simulation that tests the function of the counter. Solution Figure 9.31 shows the circuit. (Compare this circuit to the counter with synchronous load in Figure 9.26. This difference between the two is in the load function, not the count logic.) The Boolean function applied to the COUNT input of each instance of al_count consists of the logical product of all previous output bits. (COUNT3 Q2Q1Q0, COUNT2 Q1Q0, COUNT1 Q0, COUNT0 1.) When combined with the XOR at the COUNT input 394 C H A P T E R 9 Counters and Shift Registers AND3 al_count COUNT ALOAD P3 INPUT P Q OUTPUT Q3 CLK CLEAR AND2 al_count COUNT ALOAD P2 INPUT P Q OUTPUT Q2 CLK CLEAR al_count COUNT ALOAD P1 INPUT P Q OUTPUT Q1 CLK CLEAR al_count VCC P0 LOAD INPUT INPUT COUNT ALOAD P CLOCK RESET INPUT INPUT Q OUTPUT Q0 CLK CLEAR FIGURE 9.31 Example 9.7 4-bit Counter with Asynchronous Load and Reset of each element, this yields the Boolean equations for a binary counter based on D ipops, as derived in Example 9.5. The circuitry inside each instance of al_count also generates the asynchronous load and clear functions. Figure 9.32 shows a MAX PLUS II simulation of the counter. The counter cycles through its full range and continues. A pulse at 700 ns loads the counter with the value 9H ( 10012), after which the count continues from that point. FIGURE 9.32 Example 9.7 Simulation of a 4-bit Counter with Asynchronous Load and Reset 9.5 Control Options for Synchronous Counters 395 The reset pulse at 900 ns clears the counter. The LOAD pulse starting at 1.02 s shows how the load function has precedence over the count function. When LOAD is asserted, 9H is loaded and the count does not increase until LOAD is deasserted. The RESET pulse at 1.08 s overrides both load and count functions. When RESET is deasserted, 9H is asynchronously reloaded. Count Enable 4bit_sle.gdf 4bit_sle.scf The counter elements in Figures 9.25 (sl_count) and 9.30 (al_count) are just D ip-ops congured for switchable toggle operation with additional circuitry for load and clear functions. Normally, when these elements are used in synchronous counters, the count progresses when the input to the elements XOR gate goes HIGH. In other words, the count progresses when the counter element is switched from a no change to a toggle mode. In order to arrest the count sequence, we must disable the count logic of the counter circuit. Figure 9.33 shows a simple modication to the 4-bit counter circuit of Figure 9.26 that can achieve this function. Each AND gate has an extra input which is used to enable or inhibit the count logic function to each ip-op. Figure 9.34 shows a simulation of the counter. Note that the count progresses normally when COUNT_ENA is HIGH and stops when COUNT_ENA is LOW, even though the clock pulses remain constant throughout the simulation. Also note that the count enable has no effect on the synchronous load and asynchronous reset functions. In the latter part of the simulation, the count stops at AH (Q3Q2Q1Q0 10102), when COUNT_ENA goes LOW. At 760 ns, the synchronous load function loads the value of 9H into the counter. The counter stays at this value, even after LOAD is no longer active, since the count is still disabled. At 880 ns, an asynchronous reset pulse clears the counter. The count resumes on the rst clock pulse after COUNT_ENA goes HIGH again. Bidirectional Counters element.gdf Figure 9.35 shows the logic diagram of a 4-bit synchronous DOWN counter. Its count sequence starts at 1111 and counts backwards to 0000, then repeats. The Boolean equations for this circuit will not be derived at this time, but will be left for an exercise in an end-ofchapter problem. We can intuitively analyze the operation of the counter if we understand that the upper three ip-ops will each toggle when their associated XOR gates have a HIGH input from the rest of the count logic. Q0 is set to toggle on each clock pulse. Q1 toggles whenever Q0 is LOW (every second clock pulse, at states 1110, 1100, 1010, 1000, 0110, 0100, 0010, and 0000). Q2 toggles when Q1 AND Q0 are LOW (1100, 1000, 0100, and 0000). Q3 toggles when Q2 AND Q1 AND Q0 are LOW (1000 and 0000). The result of this analysis can be represented by a timing diagram, such as the simulation shown in Figure 9.36. As we expect, the counter will count down from 1111 (FH) to 0000 (0H) and repeat. We can create a bidirectional counter by including a circuit to select count logic for an UP or DOWN sequence. Figure 9.37 shows a basic synchronous counter element that can be used to create a synchronous counter. The element is simply a D ip-op congured for switchable toggle mode. Four of these elements can be combined with selectable count logic to make a 4-bit bidirectional counter, as shown in Figure 9.38. Each counter element has a pair of AND-shaped gates and an OR gate to steer the count logic to the XOR in the element. When DIR 1, the upper gate in each pair is enabled and the lower gates disabled, 396 C H A P T E R 9 Counters and Shift Registers AND4 sl_count COUNT LOAD P3 INPUT P Q OUTPUT Q3 CLOCK RESET AND3 sl_count COUNT LOAD P2 INPUT P Q OUTPUT Q2 CLOCK RESET AND2 sl_count COUNT LOAD P1 INPUT P Q OUTPUT Q1 CLOCK RESET VCC AND2 COUNT_ENA LOAD P0 CLOCK RESET INPUT INPUT INPUT INPUT INPUT FIGURE 9.33 4-bit Counter with Synchronous Load, Asynchronous Reset, and Count Enable FIGURE 9.34 Simulation of 4-bit Counter with Synchronous Load, Asynchronous Reset, and Count Enable sl_count COUNT LOAD P CLOCK RESET Q OUTPUT Q0 9.5 Control Options for Synchronous Counters DFF BAND3 XOR D PRN Q OUTPUT Q3 CLRN DFF BAND2 XOR D PRN Q OUTPUT Q2 CLRN DFF XOR NOT D PRN Q OUTPUT Q1 CLRN DFF NOT D CLOCK RESET FIGURE 9.35 4-bit Synchronous DOWN Counter FIGURE 9.36 4-bit DOWN Counter Simulation INPUT INPUT PRN Q CLRN OUTPUT Q0 397 398 C H A P T E R 9 Counters and Shift Registers XOR COUNT CLOCK DFF INPUT D INPUT PRN OUTPUT Q Q CLRN RESET INPUT FIGURE 9.37 Synchronous Counter Element (T Flip-Flop) AND4 DIR OR2 INPUT element COUNT BAND4 CLOCK Q OUTPUT Q3 RESET AND3 OR2 BAND3 element COUNT CLOCK Q OUTPUT Q2 RESET AND2 OR2 BAND2 element COUNT CLOCK Q OUTPUT Q1 RESET VCC element COUNT CLOCK RESET INPUT INPUT CLOCK Q OUTPUT Q0 RESET FIGURE 9.38 4-bit Bidirectional Counter steering the UP count logic to the counter element. When DIR 0, the lower gate in each pair is enabled, steering the DOWN count logic to the counter element. The directional function can also be combined with the load and count enable functions, as was shown for unidirectional UP counters. Figure 9.39 shows a simulation of the bidirectional counter of Figure 9.38. The waveforms show the UP count when DIR is HIGH and the DOWN count when DIR is LOW. 9.5 Control Options for Synchronous Counters 399 4bit_dir.gdf 4bit_dir.scf FIGURE 9.39 Simulation of 4-bit Bidirectional Counter Decoding the Output of a Counter Figure 9.40 shows a graphic design le of a 4-bit bidirectional counter with an output decoder. The counter is the one shown in Figure 9.38, represented as a logic circuit symbol. The decoder component decode16 is a module written in VHDL, as listed below. 4bit_dir DIR CLOCK RESET INPUT DIR INPUT Q3 CLOCK INPUT RESET Q2 Q1 Q0 Q3 Q3 Q2 OUTPUT Q1 OUTPUT Q0 OUTPUT Q2 Q1 Q0 DECODE16 Q [3..0] sel [3..0] y [0..15] FIGURE 9.40 4-bit Bidirectional Counter with Output Decoder decode16.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode16 IS PORT( sel : IN INTEGER RANGE 0 to 15; y : OUT BIT_VECTOR (0 to 15)); END decode16; ARCHITECTURE a OF decode16 BEGIN WITH sel SELECT y <= x7FFF WHEN xBFFF WHEN xDFFF WHEN xEFFF WHEN xF7FF WHEN xFBFF WHEN IS 0, 1, 2, 3, 4, 5, OUTPUT Y [0..15] 400 C H A P T E R 9 Counters and Shift Registers xFDFF xFEFF xFF7F xFFBF xFFDF xFFEF xFFF7 xFFFB xFFFD xFFFE XFFFF CD: decode16.vhd 4bit_dcd.gdf 4bit_dcd.scf WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, others; END a; The decoder has 16 outputs, one for each state of the counter. For each state, one and only one output will be low. (Refer to the section on binary decoders in Chapter 5 for a more detailed description of n-line-to-m-line binary decoders.) Figure 9.41 shows a portion of the simulation waveforms (i.e., only the count value and the decoder outputs) for the circuit in Figure 9.40. As the count progresses up or down, as shown by the waveform for Q[3..0], the decoder outputs respond by going LOW in sequence. Output decoders for binary counters can also be congured to have active HIGH outputs. In this case, one and only one output would be HIGH for each output state of the counter. Terminal Count and RCO A special case of output decoding is a circuit that will detect the terminal count, or last state, of a count sequence and activate an output to indicate this state. The terminal count depends on the count sequence. A 4-bit binary UP counter has a terminal count of 1111; a 4-bit binary DOWN counter has a terminal count of 0000. A circuit to detect these conditions must detect the maximum value of an UP count and the minimum value of a DOWN count. FIGURE 9.41 Simulation of 4-bit Decoder 9.5 Control Options for Synchronous Counters 401 VCC AND6 INPUT INPUT Q3 Q2 INPUT INPUT Q1 Q0 OR2 INPUT DIR OUTPUT BAND6 MAX_MIN GND FIGURE 9.42 Terminal Count Decoder for a 4-bit Bidirectional Counter term_dcd.gdf 4bit_rco.gdf 4bit_rco.scf The decoder shown in Figure 9.42 fullls both of these conditions. The directional input DIR enables the upper gate when HIGH and the lower gate when LOW. Thus, the upper gate generates a HIGH output when DIR 1 AND Q3Q2Q1Q0 1111. The lower gate generates a HIGH when DIR 0 AND Q3Q2Q1Q0 0000. Figure 9.43 shows the terminal count decoder combined with a 4-bit bidirectional counter. The decoder is also used to enable a NAND gate output that generates an RCO signal. RCO stands for ripple carry out or ripple clock out. The purpose of RCO is to produce exactly one clock pulse upon terminal count and have the positive edge of RCO at the end of the counter cycle, for a counter that has a positive edge-triggered clock. 4bit_dir DIR CLOCK RESET INPUT INPUT INPUT DIR OUTPUT Q3 OUTPUT RESET Q2 OUTPUT CLOCK Q1 OUTPUT Q0 Q3 Q2 Q1 Q0 term_dcd Q3 Q2 Q1 Q0 DIR NOT MAX_MIN OUTPUT MAX_MIN NAND2 OUTPUT RCO FIGURE 9.43 4-bit Bidirectional Counter with Terminal Count Detection This function is generally found in counters with a xed number of bits (i.e., xedfunction counter chips, not PLDs) and is used to asynchronously clock a further counter stage, as in Figure 9.44. This allows us to extend the width of the counter beyond the number of bits available in the xed-function device. This is not necessary when designing synchronous counters in programmable logic, but is included for the sake of completeness. 402 C H A P T E R 9 Counters and Shift Registers DIR CTR DIV 16 DIR CLK CTR DIV 16 DIR RCO Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FIGURE 9.44 Counter Expansion Using RCO The NAND gate in Figure 9.43 is enabled upon terminal count and passes the clock signal through to RCO. The NAND output sits HIGH when inhibited. The clock is inverted in the RCO circuit so that when the NAND gate inverts it again, the circuit generates a clock pulse in true form. Figure 9.45 shows the simulation of the circuit of Figure 9.43. In the rst half of the simulation, the counter is counting DOWN. The terminal count decoder output, MAX_MIN, goes HIGH when Q3Q2Q1Q0 0000. RCO generates a pulse at that time. For the second half, the counter is counting UP. MAX_MIN is HIGH when Q3Q2Q1Q0 1111 and RCO generates a pulse at that time. FIGURE 9.45 Simulation of a 4-bit Bidirectional Counter with Terminal Count Detection Note that the RCO pulse appears to be half the width of the MAX_MIN pulse. Although the NAND gate that generates RCO is enabled for the whole MAX_MIN pulse, the clock input is HIGH for the rst half-period, which is the same as the RCO inhibit level. The positive edge of RCO is at the end of the pulse. The idea is to synchronize the positive edge of the clock with the positive edge of RCO. However, since the RCO decoder is combinational, a propagation delay of about 7 ns is introduced. SECTION 9.5 REVIEW PROBLEM 9.5 Figure 9.46 shows two presettable counters, one with asynchronous load and clear, the other with synchronous load and clear. The counter with asynchronous functions has a 4-bit output labeled QA. The synchronously loaded counter has a 4-bit output labeled QS. The load and reset inputs to both counters are active LOW. 9.6 Programming Presettable and Bidirectional Counters in VHDL 403 4bit_al P3 INPUT P3 INPUT P1 P2 P1 INPUT P0 Q2 P0 INPUT Q3 Q1 LOAD P2 Q0 OUTPUT QA3 OUTPUT QA2 OUTPUT QA1 OUTPUT QA0 RESET CLOCK 4bit_sl P3 P2 CLOCK RESET Q1 P0 INPUT Q2 LOAD INPUT LOAD Q3 P1 Q0 QS3 OUTPUT QS2 OUTPUT QS1 OUTPUT QS0 RESET INPUT CLOCK FIGURE 9.46 Section Review Problem 9.5 Two Presettable Counters LOAD RESET CLOCK 0 P 8 QA 0 1 2 3 QS 0 1 2 5 3 FIGURE 9.47 Timing Diagram for Counters in Figure 9.46 Figure 9.47 shows a partial timing diagram for the counters. Complete the diagram. 9.6 Programming Presettable and Bidirectional Counters in VHDL The presettable counters and bidirectional counters described in the previous section can be easily implemented in VHDL, either as behavioral descriptions or as LPM components. We will initially examine the behavioral descriptions of two counters, one with asynchronous load and clear and one with synchronous load and clear. We will then examine some options available in the module lpm_counter. 404 C H A P T E R 9 Counters and Shift Registers Behavioral Description The following lists the VHDL code for an 8-bit bidirectional counter with count enable, terminal count decoding, and asynchronous load and clear: ENTITY pre_ct8a IS PORT ( clk, count_ena clear, load, direction p max_min qd END pre_ct8a; pre_ct8a.vhd : : : : : IN IN IN OUT OUT BIT; BIT; INTEGER RANGE 0 TO 255; BIT; INTEGER RANGE 0 TO 255); ARCHITECTURE a OF pre_ct8a IS BEGIN PROCESS (clk, clear, load) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clear = 0) THEN Asynchronous clear cnt := 0; ELSIF (load = 1 and clear = 1) THEN Asynchronous load cnt := p; ELSE IF (clkEVENT AND clk = 1) THEN IF (count_ena = 1 and direction = 0) THEN cnt := cnt - 1; ELSIF (count_ena = 1 and direction = 1) THEN cnt := cnt + 1; END IF; END IF; END IF; qd <= cnt; Terminal count decoder IF (cnt = 0 and direction = 0) THEN max_min <= 1; ELSIF (cnt = 255 and direction = 1) THEN max_min <= 1; ELSE max_min <= 0; END IF; END PROCESS; END a; The load and clear functions of this counter are asynchronous, so these identiers are part of the sensitivity list of the PROCESS statement; the statements in the process will execute if there is a change on the clear, load, or clock inputs. Load and clear are checked by IF statements, independently of the clock. Since load and clear are checked rst, they have precedence over the clock. Clear has precedence over load since load can only activate if clear is not active. If clear and load are not asserted, the clock status is checked by a clause in an IF statement: ( IF (clkEVENT and CLK = 1) THEN). If this condition is true, then a count variable is incremented or decremented, depending on the states of a count enable input and a directional control input. If the count enable input is not asserted, the count is neither incremented nor decremented. 9.6 Programming Presettable and Bidirectional Counters in VHDL 405 The count value is assigned to the counter outputs by the signal assignment statement (qd <= cnt;) after the clear, load, clock, count enable, and direction inputs have been evaluated. Possible results from the signal assignment are: qd 0 (clear 0), qd p (load 1 AND clear 1), increment qd (count_ena 1 AND direction decrement qd (count_ena 1 AND direction no change on qd (count_ena 0). 1), 0), or The terminal count is decoded by determining the count direction and value of the count variable. If the count is UP and the count value is maximum (25510 FFH) or the count is DOWN and the count value is minimum (0 00H), a terminal count decoder output called max_min goes HIGH. The code for the same 8-bit counter, but with synchronous clear and load, is shown next. ENTITY pre_ct8s IS PORT ( clk, count_ena clear, load, direction p max_min qd END pre_ct8s; pre_ct8s.vhd : : : : : IN BIT; IN BIT; IN INTEGER RANGE 0 TO 255; OUT BIT; OUT INTEGER RANGE 0 TO 255); ARCHITECTURE a OF pre_ct8s IS BEGIN PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clkEVENT AND clk = 1) THEN IF (clear = 0) THEN Synchronous clear cnt := 0; ELSIF (load = 1) THEN Synchronous load cnt := p; ELSIF (count_ena = 1 and direction = 0) THEN cnt := cnt - 1; ELSIF (count_ena 1 and direction = 1) THEN cnt := cnt + 1; END IF; END IF; qd <= cnt; Terminal count decoder IF (cnt = 0 and direction = 0) THEN max_min <= 1; ELSIF (cnt = 255 and direction = 1) THEN max_min <= 1; ELSE max_min <= 0; END IF; END PROCESS; END a; The PROCESS statement in the synchronous counter has only one identier in its sensitivity listthat of the clock input. Load and clear status are not evaluated until after the 406 C H A P T E R 9 Counters and Shift Registers pre_ct8a.scf FIGURE 9.48 Simulation Detail of 8-bit VHDL Counter (Bidirectional with Terminal Count Detection) process checks for a positive clock edge. Otherwise the code is the same as for the asynchronously loading counter. Figure 9.48 shows a detail of a simulation of the asynchronously loading counter. It shows the point where the count rolls over from FFH to 00H and activates the max_min output. The directional output changes shortly after this point and shows the terminal count decoding for a DOWN count, the point where the counter rolls over from 00H to FFH. In the UP count, max_min is HIGH when the counter output is FFH, but not 00H. In the DOWN count, max_min goes HIGH when the counter output is 00H, but not FFH. Figure 9.49 shows the operation of the asynchronous load and clear functions. Figure 9.50 show the synchronous load and clear. The inputs are identical for each simulation; each has two pairs of load pulses and a pair of clear pulses. The rst pulse of each pair is arranged so that it immediately follows a positive clock edge; the second pulse of each pair immediately precedes a positive clock edge. In the counter with asynchronous load and clear, these functions are activated by the rst pulse of each pair and again on the second pulse. For the counter with synchronous load and clear, only the second pulse of each pair has an effect, since the load and clear functions must be active during or just prior to an active clock edge, in order to satisfy FIGURE 9.49 Simulation Detail of 8-bit VHDL Counter with Asynchronous Load and Clear 9.6 Programming Presettable and Bidirectional Counters in VHDL 407 FIGURE 9.50 Simulation Detail of 8-bit VHDL Counter with Synchronous Load and Clear setup-time requirements of the counter ip-ops. The end of the load and clear pulse can correspond to the positive clock edge, as the ip-op hold time is zero. Also note that the counter with synchronous load and clear has no intermediate glitch states on its outputs. (The simulation for the asynchronously loading counter shows glitch states on output qd at 21.04 s, 21.10 s, 21.22 s, and 21.44 s. Refer to the section on Synchronous versus Asynchronous Circuits in Chapter 7 for further discussion of intermediate states in asynchronous circuits.) Figures 9.51 and 9.52 show further simulation details for our two VHDL counters. Both show the priority of the load, clear, and count enable functions. Both diagrams show that load and clear are independent of count enable and that clear has precedence over load. Again note that the counter with synchronous load and clear is free of intermediate glitch states. FIGURE 9.51 Simulation Detail of 8-bit VHDL Counter Showing Priority of Count Enable, Asynchronous Load, and Asynchronous Clear FIGURE 9.52 Simulation Detail of 8-bit VHDL Counter Showing Priority of Count Enable, Synchronous Load, and Synchronous Clear 408 C H A P T E R 9 Counters and Shift Registers LPM Counters Earlier in this chapter, we saw how a parameterized counter from the Library of Parameterized Modules (LPM) could be used as a simple 8-bit counter. The component lpm_counter has a number of other functions that can be implemented using specic ports and parameters. These functions are indicated in Table 9.13. Table 9.13 Available Functions of an LPM counter Function Ports Parameters Description Basic count operation clock, q [] LPM_WIDTH Output q[] increases by one with each positive clock edge. LPM_WIDTH is the number of output bits. Synchronous load sload, data [] none When sload 1, output q[] goes to the value at input data[] on the next positive clock edge. data[] has the same width as q[]. Synchronous clear sclr none When sclr edge. Synchronous set sset LPM_SVALUE When sset 1, output goes to value of LPM_SVALUE on positive clock edge. If LPM_SVALUE is not specied, q[] goes to all 1s. Asynchronous load aload, data[] none Output goes to value at data[] when aload Asynchronous clear aclr none Output goes to zero when aclr Asynchronous set aset LPM_AVALUE Output goes to value of LPM_AVALUE when aset 1. If LPM_AVALUE is not specied, outputs all go HIGH when aset 1. Directional control updown LPM_DIRECTION Optional direction control. Default direction is UP. Only one of updown and LPM_DIRECTION can be used. updown 1 for UP count, updown 0 for DOWN count. LPM_DIRECTION UP, DOWN, or DEFAULT Count enable cnt_en none When cnt_en 1, count proceeds upon positive clock edges. No effect on other synchronous functions (sload, sclr, sset). Defaults to enabled when not specied. Clock enable clk_en none All synchronous functions are enabled when clk_en Defaults to enabled when not specied. Modulus control none LPM_MODULUS Modulus of counter is set to value of LPM_MODULUS Output decoding (GDF or AHDL only; not available in VHDL) eq[15..0] none Sixteen active-HIGH decoded outputs, one for each internal counter value from 0 to 15. 1, output q[] goes to zero on positive clock 1. 1. 1. The only ports that are required by an LPM counter are clock, and one of q[] (counter outputs) or eq[] (decoder outputs). The only required parameter is LPM_WIDTH, which species the number of counter output bits. All other ports and parameters are optional, although certain ones must be used together. (For instance, ports sload and data[] are optional, but both must be used for the synchronous load function.) If unused, a port or parameter will be held at a default logic level. To use any of the functions of an LPM component in a VHDL le, we use a component instantiation statement and specify the required parameters in a generic map and the ports in a port map. 9.6 Programming Presettable and Bidirectional Counters in VHDL 409 NOTE The VHDL component declaration, shown below, indicates that all parameters except LPM_WIDTH are dened as having type STRING, which requires the parameter value to be written in double quotes, even if numeric. (e.g, LPM_MODULUS => 12). Since LPM_WIDTH is dened as type POSITIVE (i.e., any integer 0) it must be written without quotes (e.g., LPM_WIDTH => 8). Default values of all ports and parameters are also included in the component declaration (e.g., clk_en: IN STD_LOGIC := 1; the default value of the clock enable input is 1). The LPM component declaration can also be found in the MAX PLUS II Help menu (Help; Megafunctions/LPM; lpm_counter). VHDL Component Declaration for lpm_counter: COMPONENT lpm_counter GENERIC (LPM_WIDTH: POSITIVE; LPM_MODULUS: STRING := UNUSED; LPM_AVALUE: STRING:= UNUSED; LPM_SVALUE: STRING := UNUSED; LPM_DIRECTION: STRING := UNUSED; LPM_TYPE: STRING := L_COUNTER; LPM_PVALUE: STRING := UNUSED; LPM_HINT : STRING := UNUSED); PORT (data: IN STD_LOGIC_VECTOR (LPM_WIDTH-1 DOWNTO 0) := (OTHERS => 0); clock: IN STD_LOGIC; cin: IN STD_LOGIC := 0; clk_en: IN STD_LOGIC := 1; cnt_en: IN STD_LOGIC := 1; updown: IN STD_LOGIC := 1 sload: IN STD_LOGIC := 0; sset: IN STD_LOGIC := 0; sclr: IN STD_LOGIC := 0; aload: IN STD_LOGIC := 0; aset: IN STD_LOGIC := 0; aclr: IN STD_LOGIC := 0; cout: OUT STD_LOGIC; q: OUT STD_LOGIC_VECTOR (LPM_WIDTH-1 DOWNTO 0) ); END COMPONENT; EXAMPLE 9.8 Write a VHDL le for an 8-bit LPM counter with ports for the following functions: asynchronous load, asynchronous clear, directional control, and count enable. Solution The required VHDL le is shown below. Note that no behavioral descriptions are required for the functions, only a mapping from the dened port names to the entity inputs and outputs. pre_lpm8 8-bit presettable counter with asynchronous clear and load, count enable, and a directional control port LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; 410 C H A P T E R 9 Counters and Shift Registers pre_lpm8.vhd ENTITY pre_lpm8 IS PORT ( clk, count_ena : IN clear, load, direction p : IN qd : OUT END pre_lpm8; STD_LOGIC; : IN STD_LOGIC; STD_LOGIC_VECTOR(7 downto 0); STD_LOGIC_VECTOR(7 downto 0)); ARCHITECTURE a OF pre_lpm8 IS BEGIN counter1: lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP ( clock => clk, updown => direction, cnt_en => count_ena, data => p, aload => load, aclr => clear, q => qd); END a; EXAMPLE 9.9 Write a VHDL le that uses an LPM counter to generate a DOWN counter with a modulus of 500. Create a MAX PLUS II simulation le to verify the counters operation. Solution A mod-500 counter requires nine bits since 28 500 29. Since the counter always counts DOWN, we can use the parameter LPM_DIRECTION to specify the DOWN counter rather than using an unnecessary port. The required VHDL code is given below. Note that the value of LPM_WIDTH is written without quotes, since it is dened as type POSITIVE in the component declaration. LPM_MODULUS and LPM_DIRECTION are written in double quotes, since the component declaration denes them as type STRING. mod5c_lpm.vhd mod5c_lpm.scf LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; Use lpm.lpm_components.ALL; ENTITY mod5c_lpm IS PORT ( clk : IN q : OUT END mod5c_lpm; STD_LOGIC; STD_LOGIC_VECTOR (8 downto 0) ); ARCHITECTURE a OF mod5c_lpm IS BEGIN counter1: lpm_counter GENERIC MAP(LPM_WIDTH => 9, LPM_DIRECTION => DOWN, LPM_MODULUS => 500) PORT MAP ( clock => clk, q => q); END a; Figure 9.53 shows a partial simulation of the counter, indicating the point at which the output rolls over from 0 to 499 (decimal). 9.6 Programming Presettable and Bidirectional Counters in VHDL 411 FIGURE 9.53 Example 9.9 Partial Simulation of a Mod-500 LPM DOWN Counter If we are designing a counter for the Altera UP-1 circuit board, we can simulate the on-board oscillator by choosing a clock period of 40 ns, which corresponds to a clock frequency of 25 MHz. The default simulation period is from 0 to 1 s, which only gives 1 s 40 ns/clock period 25 clock periods. This is not enough time to show the entire count cycle. The minimum value for the end of the simulation time is: 40 ns/clock period 500 clock periods 20000 ns 20 s. If we wish to see a few clock cycles past the recycle point, we can set the simulation end time to 20.1 s. (In the MAX PLUS II Simulator window, select File menu; End Time. Enter the value 20.1us (no spaces) into the Time window and click OK.) To view the count waveform, q, in decimal rather than hexadecimal, select the waveform by clicking on it. Either right-click to get a pop-up menu or select Enter Group from the simulator Node menu, as in Figure 9.54. This will bring up the Enter Group dialog box shown in Figure 9.55. Select DEC (for decimal) and click OK. FIGURE 9.54 Selecting a Group in a MAX PLUS II Simulation FIGURE 9.55 Changing the Name or Radix of a Group 412 C H A P T E R 9 Counters and Shift Registers EXAMPLE 9.10 Write a VHDL le that instantiates a 12-bit LPM counter with asynchronous clear and synchronous set functions. Design the counter to set to 2047 (decimal). Create a simulation to verify the counter operation. Solution The required VHDL le is: sset_lpm.vhd 12-bit LPM counter with sset and aclr LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY sset_lpm IS PORT( clk : IN STD_LOGIC; clear, set : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (11 downto 0) ); END sset_lpm; sset_lpm.vhd sset_lpm.scf ARCHITECTURE a OF sset_lpm IS BEGIN counter1: lpm_counter GENERIC MAP (LPM_WIDTH => 12, LPM_SVALUE => 2047) PORT MAP ( clock => clk, sset => set, aclr => clear, q => q); END a; Figure 9.56 shows the simulation le of the counter. The full count sequence would take over 160 s, so we will assume the count portion of the design works properly. Only the set and clear functions are fully simulated. The count waveform is shown in decimal. FIGURE 9.56 Example 9.10 Simulation of a 12-bit Counter with Synchronous Set to 2047 and Asynchronous Clear SECTION 9.6 REVIEW PROBLEM 9.6 The rst part of a VHDL process statement includes a sensitivity list: PROCESS (sensitivity list). How should this be written for a counter with asynchronous clear and for a counter with synchronous clear? 9.7 Shift Registers 413 9.7 Shift Registers KEY TERMS Shift register A synchronous sequential circuit that will store and move n-bit data, either serially or in parallel, in n ip-ops. SRGn Abbreviation for an n-bit shift register (e.g., SRG4 indicates a 4-bit shift register). Serial shifting Movement of data from one end of a shift register to the other at a rate of one bit per clock pulse. Parallel transfer Movement of data into all ip-ops of a shift register at the same time. Rotation Serial shifting of data with the output(s) of the last ip-op connected to the synchronous input(s) of the rst ip-op. The result is continuous circulation of the same data. Right shift A movement of data from the left to the right in a shift register. (Right is dened in MAX PLUS II as toward the LSB.) Left shift A movement of data from the right to the left in a shift register. (Left is dened in MAX PLUS II as toward the MSB.) Bidirectional shift register A shift register that can serially shift bits left or right according to the state of a direction control input. Parallel-load shift register A shift register that can be preset to any value by directly loading a binary number into its internal ip-ops. Universal shift register A shift register that can operate with any combination of serial and parallel inputs and outputs (i.e., serial in/serial out, serial in/parallel out, parallel in/serial out, parallel in/parallel out). A universal shift register is often bidirectional, as well. A shift register is a synchronous sequential circuit used to store or move data. It consists of several ip-ops, connected so that data are transferred into and out of the ip-ops in a standard pattern. Figure 9.57 represents three types of data movement in three 4-bit shift registers. The circuits each contain four ip-ops, congured to move data in one of the ways shown. Figure 9.57a shows the operation of serial shifting. The stored data are taken in one at a time from the input and moved one position toward the output with each applied clock pulse. Parallel transfer is illustrated in Figure 9.57b. As with the synchronous parallel load function of a presettable counter, data move simultaneously into all ip-ops when a clock pulse is applied. The data are available in parallel at the register outputs. Rotation, depicted in Figure 9.57c, is similar to serial shifting in that data are shifted one place to the right with each clock pulse. In this operation, however, data are continuously circulated in the shift register by moving the rightmost bit back to the leftmost ipop with each clock pulse. Serial Shift Registers srg4_sr.gdf srg4_sr.scf Figure 9.58 shows the most basic shift register circuit: the serial shift register, so called because data are shifted through the circuit in a linear or serial fashion. The circuit shown consists of four D ip-ops connected in cascade and clocked synchronously. For a D ip-op, Q follows D. The value of a bit stored in any ip-op after a clock pulse is the same as the bit in the ip-op to its left before the pulse. The result is that when a clock pulse is applied to the circuit, the contents of the ip-ops move one position to the 414 C H A P T E R 9 Counters and Shift Registers Q3 Q2 Q1 Q0 a. Serial shifting Q3 Q2 Q1 Q0 b. Parallel transfer Q3 Q2 Q1 Q0 c. Rotation FIGURE 9.57 Data Movement in a 4-bit Shift Register DFF Serial_in INPUT D DFF PRN Q3 Q CLRN Clock D DFF PRN Q2 Q CLRN D DFF PRN Q1 Q CLRN D PRN Q0 Q CLRN INPUT OUTPUT OUTPUT OUTPUT OUTPUT Q0 Q1 Q2 Q3 FIGURE 9.58 4-bit Serial Shift Register Congured to Shift Right right and the bit at the circuit input is shifted into Q3. The bit stored in Q0 is overwritten by the former value of Q1 and is lost. Since the data move from left to right, we say that the shift register implements a right shift function. (Data movement in the other direction, requiring a different circuit connection, is called left shift.) Let us track the progress of data through the circuit in two cases. All ip-ops are initially cleared in each case. Case 1: A 1 is clocked into the shift register, followed by a string of 0s, as shown in Figure 9.59. The ip-op containing the 1 is shaded. Before the rst clock pulse, all ip-ops are lled with 0s. Data In goes to a 1 and on the rst clock pulse, the 1 is clocked into the rst ip-op. After that, the input goes to 0. The 1 moves one position right with each clock pulse, the register lling up with 0s behind it, fed by the 0 at Data In.After four clock pulses, the 1 reaches the Data Out ip-op. On the fth pulse, the 0 coming behind overwrites the 1 at Q0, leaving the register lled with 0s. 9.7 FIGURE 9.59 Shifting a 1 Through a Shift Register (Shift Right) 0 0 0 Q D Data in Q3 0 Q D Q Shift Registers Q2 0 Q D Q1 Q D Q0 Data out Q Q Q 415 Clock 1 0 1 Q D Data in Q3 0 Q D Q Q2 0 Q D Q1 Q D Data out Q Q Q Q0 Clock 0 1 0 Q D Data in Q3 0 Q D Q Q2 0 Q D Q1 Q D Data out Q Q Q Q0 Clock 0 0 0 Q D Data in Q3 1 Q D Q Q2 0 Q D Q1 Q D Data out Q Q Q Q0 Clock 0 0 0 Q D Data in Q3 0 Q D Q Q2 1 Q D Q1 Q D Data out Q Q Q Q0 Clock 0 0 0 Data in D Q Q Q3 D 0 Q Q Q2 D 0 Q Q Q1 D Q Q0 Data out Q Clock Case 2: Figure 9.60 shows a shift register, initially cleared, being lled with 1s. As before, the initial 1 is clocked into the shift register and reaches the Data Out line on the fourth clock pulse. This time, the register lls up with 1s, not 0s, because the Data input remains HIGH. Figure 9.61 shows a MAX PLUS II simulation of the 4-bit serial shift register in Figure 9.58 through 9.60. The rst half of the simulation shows the circuit operation for Case 416 C H A P T E R 9 Counters and Shift Registers FIGURE 9.60 Filling a Shift Register with 1s (Shift Right) 0 0 0 Q D Data in Q3 0 Q D Q Q2 0 Q D Q1 Q D Data out Q Q Q Q0 Clock 1 0 1 Q D Data in Q3 0 Q D Q Q2 0 Q D Q1 Q D Data out Q Q Q Q0 Clock 1 1 1 Q D Data in Q3 0 Q D Q Q2 0 Q D Q1 Q D Data out Q Q Q Q0 Clock 1 1 1 Q D Data in Q3 1 Q D Q Q2 0 Q D Q1 Q D Data out Q Q Q Q0 Clock 1 1 1 Data in D Q Q Clock FIGURE 9.61 Simulation of a 4-bit Shift Register (Shift Right) Q3 D 1 Q Q Q2 D 1 Q Q Q1 D Q Q Q0 Data out 9.7 Shift Registers 417 1, above. The 1 enters the register at Q3 on the rst clock pulse after serial_in (Data In) goes HIGH. The 1 moves one position for each clock pulse, which is seen in the simulation as a pulse moving through the Q outputs. Case 2 is shown in the second half of the simulation. Again, a 1 enters the register at Q3. The 1 continues to be applied to serial_in, so all Q outputs stay HIGH after receiving the 1 from the previous ip-op. NOTE Conventions differ about whether the rightmost or leftmost bit in a shift register should be considered the most signicant bit. The Altera Library of Parameterized Modules uses the convention of the leftmost bit being the MSB, so this is the convention we will follow. The convention has no physical meaning; the concept of right or left shift only makes sense on a logic diagram. The actual ip-ops may be laid out in any conguration at all in the physical circuit and still implement the right or left shift functions as dened on the logic diagram. (That is to say, wires, circuit board traces, and internal programmable logic connections can run wherever you want; left and right are dened on the logic diagram.) EXAMPLE 9.11 Use the MAX PLUS II Graphic Editor to create the logic diagram of a 4-bit serial shift register that shifts left, rather than right. Solution Figure 9.62 shows the required logic diagram. The ip-ops are laid out the same way as in Figure 9.58, with the MSB (Q3) on the left. The D input of each ip-op is connected to the Q output of the ip-op to its right, resulting in a looped-back connection. A bit at D0 is clocked into the rightmost ip-op. Data in the other ip-ops are moved one place to the left. The bit in Q2 overwrites Q3. The previous value of Q3 is lost. srg4_sl.gdf srg4_sl.scf Serial_in INPUT DFF D3 D DFF PRN Q3 D2 Q CLRN Clock D DFF PRN Q2 Q CLRN D1 D DFF PRN Q1 Q CLRN D0 D PRN Q0 Q CLRN INPUT OUTPUT OUTPUT OUTPUT OUTPUT Q0 Q1 Q2 Q3 FIGURE 9.62 4-bit Serial Shift Register Congured to Shift Left EXAMPLE 9.12 Draw a diagram showing the movement of a single 1 through the register in Figure 9.62. Also draw a diagram showing how the register can be lled up with 1s. Solution Figures 9.63 and 9.64 show the required data movements. D D 0 0 Q Q Q Q Q Q Data out Q3 Data out Q3 Data out Q3 D D D 0 0 0 Q Q Q Q Q Q Q2 Q2 Q2 FIGURE 9.63 Shifting a 1 Through a Shift Register (Shift Left) Clock Clock Clock D 0 D D D Q Q Q Q 1 Q Q Data in 0 Data in 0 Data in Q1 Q1 Q1 0 1 0 D D D 0 1 0 Q Q Q Q Q Q Q0 Q0 Q0 Clock Clock Clock D D D 0 1 0 Q Q Q Q Q Q Data out Q3 Data out Q3 Data out Q3 D D D 0 0 1 Q Q Q Q Q Q Q2 Q2 Q2 D D D Q Q Q Q 0 Q Q Data in 0 Data in 0 Data in Q1 Q1 Q1 0 0 0 D D D 0 0 0 Q Q Q Q Q Q Q0 Q0 Q0 418 C H A P T E R 9 Counters and Shift Registers D D 0 0 Q3 Data out Q Q Data out Q Q Q3 Data out Q Q Q3 D D D 0 0 0 Q Q Q Q Q Q Q2 Q2 Q2 D D D Q Q Q Q 1 Q Q Data in 0 Data in 0 Q1 Q1 Q1 1 1 0 D D D 1 1 0 Q Q Q Q Q Q Q0 Q0 Q0 Clock Clock D D 1 0 Q3 Q3 Data out Q Q Data out Q Q D D 1 1 Q Q Q Q Q2 Q2 D D Q Q 1 Q Q Data in 1 Data in Q1 Q1 1 1 D D 1 1 Q Q Q Q Q0 Q0 Shift Registers FIGURE 9.64 Filling a Shift Register with 1s (Shift Left) Clock Clock Clock D 0 Data in 9.7 419 420 C H A P T E R 9 Counters and Shift Registers EXAMPLE 9.13 Use the MAX PLUS II simulator to verify the operation of the shift-left serial shift register in Figure 9.62. Solution Figure 9.65 shows the simulation of the shift operations shown in Example 9.12. Compare this simulation to the one in Figure 9.61 to see how the opposite shift direction appears on a timing diagram. FIGURE 9.65 Simulation of a 4-bit Shift Register (Shift Left) Bidirectional Shift Registers srg4_bi.gdf srg4_bi.scf Figure 9.66 shows the logic diagram of a bidirectional shift register. This circuit combines the properties of the right shift and left shift circuits, seen earlier in Figures 9.58 and 9.62. This circuit can serially move data right or left, depending on the state of a control input, called DIRECTION. The shift direction is controlled by enabling or inhibiting four pairs of AND-OR circuit paths that direct the bits at the ip-op outputs to other ip-op inputs. When DIRECTION 0, the right-hand AND gate in each pair is enabled and the ip-op outputs are directed to the D inputs of the ip-ops one position left. Thus the enabled pathway is from Left_Shift_In to Q0, then to Q1, Q2, and Q3. When DIRECTION 1, the left-hand AND gate of each pair is enabled, directing the data from Right_Shift_In to Q3, then to Q2, Q1, and Q0. Thus, DIRECTION 0 selects left shift and DIRECTION 1 selects right-shift. Figure 9.67 shows a MAX PLUS II simulation of the bidirectional shift register in Figure 9.66. The simulation shows the left shift function from 0 to 500 ns and right shift after 500 ns. Both Right_Shift_In and Left_Shift_In are applied in both parts of the simulation, but the circuit responds only to one for each function. For the left shift function, a 1 is applied to Q0 at 140 ns and shifted left. The Right_Shift_In pulse is ignored. Similarly, for the right shift function, a 1 is applied to Q3 at 540 ns and shifted right. Left_Shift_In is ignored. INPUT INPUT INPUT FIGURE 9.66 Bidirectional Shift Register CLOCK Right_Shift_In DIRECTION NOT Q AND2 OR2 D CLRN D DFF AND2 PRN OR2 DFF AND2 Q CLRN PRN OR2 D DFF AND2 Q CLRN PRN OR2 D DFF AND2 Q CLRN PRN INPUT OUTPUT OUTPUT OUTPUT OUTPUT Q3 Q2 Q1 Q0 Left_Shift_In 9.7 Shift Registers 421 AND2 AND2 AND2 422 C H A P T E R 9 Counters and Shift Registers FIGURE 9.67 Simulation of a 4-bit Bidirectional Shift Register Shift Register with Parallel Load srg4_par.gdf srg4_par.scf srg4_uni.gdf srg4_uni.scf Earlier in this chapter, we saw how a counter could be set to any value by synchronously loading a set of external inputs directly into the counter ip-ops. We can implement the same function in a shift register, as shown in Figure 9.68. The circuit is similar to that of the bidirectional shift register in Figure 9.66. The synchronous input of each ip-op is fed by an AND-OR circuit that directs one of two signals to the ip-op: the output of the previous ip-op (shift function) or a parallel input (load function). The circuit is congured such that the shift function is enabled when LOAD 0 and the load function is enabled when LOAD 1. Figure 9.69 shows a simulation of the parallel-load shift register circuit of Figure 9.68. In the rst part of the simulation, the shift function is selected. This is tested by sending a 1 through the circuit in a right-shift pattern. Next, at 400 ns, LOAD goes HIGH, and the parallel input value AH ( 10102) is synchronously loaded into the circuit. The LOAD input goes LOW, thus causing the circuit to revert to the shift function. The data in the register are right-shifted out, followed by 0s. At 640 ns, the value FH ( 11112) is loaded into the circuit, then right-shifted out. Figure 9.70 shows the logic circuit of a universal shift register. This circuit can implement any combination of serial and parallel inputs and outputs. It can also serially shift data left or right or hold data, depending on the states of S1 and S0, which form a 2-bit function select input. Each AND-OR circuit acts as a multiplexer to direct one of several possible data sources to the synchronous inputs of each ip-op. For instance, if we trace the paths through the corresponding AND-OR circuit, we nd that the possible sources of data at D2, the synchronous input of the second ip-op, are Q3 (S1S0 01), P2 (S1S0 11), Q1 (S1S0 10), and Q2(S1S0 00). These are the inputs required for the right-shift, parallel load, left-shift, and hold functions, respectively. All functions are synchronous, including the parallel load and hold functions. The hold function is a synchronous no change function, implemented by feeding back the Q output of a ip-op to its synchronous (D) input. It is necessary to have this function, so that the ip-ops will not synchronously clear when none of the other functions is selected. INPUT INPUT INPUT INPUT INPUT INPUT INPUT NOT Q AND2 OR2 D CLRN D DFF AND2 PRN OR2 DFF AND2 Q CLRN PRN OR2 D DFF AND2 Q CLRN PRN OR2 D DFF AND2 Q CLRN PRN OUTPUT OUTPUT OUTPUT OUTPUT Q3 Q2 Q1 Q0 Shift Registers FIGURE 9.68 Serial Shift Register with Parallel Load CLOCK SERIAL_IN LOAD P3 P2 P1 P0 9.7 423 AND2 AND2 AND2 424 C H A P T E R 9 Counters and Shift Registers FIGURE 9.69 Simulation of a 4-bit Serial Shift Register with Parallel Load Table 9.14 summarizes the various possible inputs to each ip-op as a function of S1 and S0. Table 9.14 Flip-Flop Inputs as a Function of S1S0 in a Universal Shift Register S1 S0 Function D3 D2 D1 D0 0 0 1 1 0 1 0 1 Hold Shift Right Shift Left Load Q3 RSI* Q2 P3 Q2 Q3 Q1 P2 Q1 Q2 Q0 P1 Q0 Q1 LSI** P0 *RSI Right-shift input **LSI Left-shift input EXAMPLE 9.14 Create a simulation le to verify the operation of the universal shift register of Figure 9.70. Solution Figure 9.71 shows a possible solution. The following functions are tested: hold, right shift (LSI ignored), hold, left shift (RSI ignored), load FH, asynchronous clear, load FH, shift right for two clocks, shift left for three clocks. 425 INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT S1 0 0 1 1 NOT NOT FIGURE 9.70 4-bit Universal Shift Register CLEAR CLOCK RSI P3 P2 P1 P0 S0 INPUT S0 0 1 0 1 AND3 D Q CLRN PRN HOLD SHIFT RIGHT SHIFT LEFT LOAD D3 DFF AND3 OR4 AND3 Q3 AND3 D2 D DFF AND3 Q CLRN PRN OR4 AND3 Q2 AND3 D1 D DFF AND3 Q CLRN PRN OR4 AND3 Q1 AND3 D0 D DFF AND3 Q CLRN PRN OR4 S1 Q0 AND3 AND3 AND3 AND3 AND3 OUTPUT OUTPUT OUTPUT OUTPUT INPUT Q3 Q2 Q1 Q0 LSI 426 C H A P T E R 9 Counters and Shift Registers FIGURE 9.71 Example 9.14 Simulation of a 4-bit Universal Shift Register SECTION 9.7 REVIEW PROBLEM 9.7 Can the D ip-ops in Figure 9.58 be replaced by JK ip-ops? If so, what modications to the existing circuit are required? 9.8 Programming Shift Registers in VHDL KEY TERMS Structural design A VHDL design technique that connects predesigned components using internal signals. Dataow design A VHDL design technique that uses Boolean equations to dene relationships between inputs and outputs. Behavioral design A VHDL design technique that uses descriptions of required behavior to describe the design. As with other circuit applications, we can take several approaches to programming shift registers in VHDL. Three basic design techniques are structural, dataow, and behavioral descriptions. We will use each of these techniques to design a 4-bit shift register, such as the one shown in Figure 9.58. Structural Design Structural design is like taking components out of a bin and connecting them together to make a circuit. We can use the DFF component from the MAX PLUS II primitives library and instantiate enough components to make a shift register, with connections made 9.8 Programming Shift Registers in VHDL 427 by internal signals. The code to make a 4-bit shift register using the structural design technique is shown here in the le srg4strc.vhd. srg4strc.vhd srgstrc.scf srg4strc.vhd Structural description of a 4-bit serial shift register LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY srg4strc IS PORT( serial_in, clk : IN qo : BUFFER END srg4strc; STD_LOGIC; STD_LOGIC_VECTOR(3 downto 0) ); ARCHITECTURE right_shift of srg4strc IS COMPONENT DFF PORT (d : IN STD_LOGIC; clk : IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT; BEGIN ip_op_3: dff PORT MAP (serial_in, clk, qo(3) ); dffs: FOR i IN 2 downto 0 GENERATE ip_ops_2_to_0: dff PORT MAP (qo(i + 1), clk, qo(i) ); END GENERATE; END right_shift; The design entity srg4strc.vhd instantiates four D ip-ops from the altera. maxplus2 package and connects them by assigning common inputs and outputs to related components. A different way of writing the component instantiations would be as follows. ip_op_3: dff PORT MAP (serial_in, ip_op_2: dff PORT MAP(qo(3), clk, ip_op_1: dff PORT MAP(qo(2), clk, ip_op_0: dff PORT MAP(qo(1), clk, clk, qo(3) ); qo(2) ); qo(1) ); qo(0) ); Since the component ports are in the sequence (D, clk, Q), the component instantiations shown above imply that the D input of a ip-op is fed by the Q of the previous ip-op. The port identier qo is dened as mode BUFFER, not as OUT, because it is sometimes used as an input and sometimes as an output. A port of mode OUT can only be used as an output. A port of mode BUFFER has a feedback connection so that the output can be reused in the programmed AND matrix of the CPLD macrocell. Figure 9.72 illustrates the difference between these modes. Rather than dening connections in the component instantiations, we would also be able to use an internal signal to connect the ip-ops. This method allows us to use a port of mode OUT, rather than BUFFER. The le srg4str2.vhd shows this alternative way. 428 C H A P T E R 9 Counters and Shift Registers AND Matrix D n PIN Q CLK AND Matrix D n CLK a. Driver of mode OUT PIN Q Feedback to AND matrix b. Driver of mode BUFFER FIGURE 9.72 OUT vs. BUFFER srg4str2.vhd Structural description of a 4-bit serial shift register LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; ENTITY srg4str2 IS PORT ( serial_in, clk : IN STD_LOGIC; qo : OUT STD_LOGIC_VECTOR(3 downto 0) ); END srg4str2; srg4str2.vhd srg4str2.scf ARCHITECTURE right_shift of srg4str2 IS COMPONENT DFF PORT (d : IN STD_LOGIC; clk : IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT; SIGNAL connect : STD_LOGIC_VECTOR(3 downto 0); BEGIN ip_op_3: dff PORT MAP (serial_in, clk, connect(3) ); dffs: FOR i IN 2 downto 0 GENERATE ip_ops_2_to_0: dff PORT MAP (connect(i + 1), clk, connect(i) ); END GENERATE; qo <= connect; END right_shift; In this case, the internal signal connect is used to tie the ip-ops together. The circuit output derives from a signal assignment statement at the end of the le. Since the internal signal connect is used to full the ip-op input/output functions, qo can be dened solely as an output. Dataow Design Dataow design describes a design entity in terms of the Boolean relationships between different parts of the circuit. The Boolean relationships in a 4-bit shift register are dened by the expressions for the ip-op synchronous inputs: 9.8 Programming Shift Registers in VHDL D3 D2 D1 D0 429 serial_in Q3 Q2 Q1 The design entity srg4dw.vhd illustrates the use of the dataow design method for a 4-bit serial shift register. srg4dw.vhd srg4dw.scf srg4dw.vhd Dataow description of a 4-bit serial shift register LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srg4dw IS PORT ( serial_in, clk : IN q : BUFFER END srg4dw; STD_LOGIC; STD_LOGIC_VECTOR(3 downto 0) ); ARCHITECTURE right_shift of srg4dw IS SIGNAL d : STD_LOGIC_VECTOR(3 downto 0); BEGIN PROCESS (clk) BEGIN Dene a 4-bit D ip-op IF clkEVENT and clk = 1 THEN q <= d; END IF; END PROCESS; d <= serial_in & q(3 downto 1); END right_shift; Before the ip-ops can be connected, they must be dened in a PROCESS statement. The statements inside the process are sequential, as they must be to dene a ipop, but the process itself is a concurrent statement. Signals are applied concurrently (simultaneously) to the construct implied by the process (the ip-ops) and all other concurrent constructs in the design entity (the connections between q and d and the serial input). A signal assignment statement implements the Boolean equations for the shift register. It is written as a single statement for efciency, but could also be written as four separate assignment statements, as follows: d(3) d(2) d(1) d(0) <= <= <= <= serial_in; q(3); q(2); q(1); We must dene q as mode BUFFER, since we are using it as both input and output. Behavioral Design Table 9.15 Next States of Flip-Flops in a Serial Shift Register Q3 Q2 Q1 Q0 serial_in Q3 Q2 Q1 We can create a VHDL design entity from the description of its desired behavior. In the case of a shift register, we know that after a clock pulse all data move over one position and the rst ip-op in the chain accepts a bit from a serial input, as indicated in Table 9.15. We can use this behavioral description to implement a serial shift register, as shown in the VHDL le srg4behv.vhd. 430 C H A P T E R 9 Counters and Shift Registers srg4behv.vhd Behavioral description of a 4-bit serial shift register LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srg4behv IS PORT ( serial_in, clk : IN q : BUFFER END srg4behv; srg4behv.vhd srg4behv.scf STD_LOGIC; STD_LOGIC_VECTOR(3 downto 0) ); ARCHITECTURE right_shift of srg4behv IS BEGIN PROCESS (clk) BEGIN IF (clkEVENT and clk = 1) THEN q <= serial_in & q(3 downto 1); END IF; END PROCESS; END right_shift; In the behavioral design, we are not concerned with the ip-op inputs or other internal connections; the behavioral description is sufcient for the VHDL compiler to synthesize the required hardware. Compare this to the dataow description, where we created a set of ip-ops, then assigned Boolean functions to the D inputs. In this case, the behavioral design method combines these two steps into one. EXAMPLE 9.15 Write the code for a VHDL design entity that implements a 4-bit bidirectional shift register with asynchronous clear. Create a simulation that veries the design function. Solution The VHDL code for the bidirectional shift register, srg4bidi.vhd, follows. A CASE statement monitors the directional control of the shift register. We require the others clause of the CASE statement since the identier direction is of type STD_LOGIC; the cases 0 and 1 do not cover all possible values of STD_LOGIC. Since we want no action to be taken in the default case, we use the keyword NULL. www.electronictech.com LIBRARY ieee; USE ieee.std_logic_1164.ALL; srg4bidi.vhd srg4bidi.scf ENTITY srg4bidi IS PORT ( clk, clear rsi, lsi direction q END srg4bidi; : : : : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; BUFFER STD_LOGIC_VECTOR(3 downto 0) ); ARCHITECTURE bidirectional_shift of srg4bidi IS BEGIN PROCESS (clk, clear) BEGIN IF clear = 0 THEN q <= 0000; asynchronous clear ELSIF (clkEVENT and clk = 1) THEN CASE direction IS WHEN 0 => q <= q(2 downto 0) & lsi; left shift 9.8 Programming Shift Registers in VHDL 431 WHEN 1 => q <= rsi & q(3 downto 1); right shift WHEN others => NULL; END CASE; END IF; END PROCESS; END bidirectional_shift; Figure 9.73 shows the simulation of the shift register, with the left shift function in the rst half of the simulation and the right shift function in the second half. FIGURE 9.73 Example 9.15 4-bit Bidirectional Shift Register Shift Registers of Generic Width KEY TERM GENERIC A clause in the entity declaration of a VHDL component that lists the parameters that can be specied when the component is instantiated. All multibit VHDL components we have examined until now have been of a specied width (e.g., 2-to-4 decoder, 8-bit MUX, 8-bit adder, 4-bit counter). VHDL allows us to create components having a generic, or unspecied, width or other parameter which is specied when the component is instantiated. In the entity declaration of such a component, we indicate an unspecied parameter (such as width) in a GENERIC clause. The unspecied parameter must be given a default value in the GENERIC clause, indicated by : value. When we instantiate the component, we specify the parameter value in a generic map, as we have done with components from the Library of Parameterized Modules. The design entity srt_bhv.vhd below behaviorally denes an n-bit right-shift register, with a default width of four bits given by the statement ( GENERIC (width : POSITIVE := 4);). The entity srt8_bhv.vhd instantiates the n-bit register as an 8-bit circuit by specifying the bit width in a generic map. If no value is specied, the component is presumed to have a default width of four, as dened in the components entity declaration. srt_bhv.vhd 432 C H A P T E R 9 Counters and Shift Registers Behavioral description of an n-bit shift register LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srt_bhv IS GENERIC (width : POSITIVE := 4); PORT ( serial_in, clk : IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR(width-1 downto 0) ); END srt_bhv; srt_bhv.vhd srt8_bhv.vhd srt8_bhv.scf ARCHITECTURE right_shift of srt_bhv IS BEGIN PROCESS (clk) BEGIN IF (clkEVENT and clk = 1) THEN q(width-1 downto 0) <= serial_in & q(width-1 downto 1); END IF; END PROCESS; END right_shift; srt8_bhv.vhd 8-bit shift register that instantiates srt_bhv LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srt8_bhv IS PORT( data_in, clock : IN qo : BUFFER END srt8_bhv; STD_LOGIC; STD_LOGIC_VECTOR(7 downto 0) ); ARCHITECTURE right_shift of srt8_bhv IS COMPONENT srt_bhv GENERIC (width : POSITIVE); PORT ( serial_in, clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(7 downto 0) ); END COMPONENT; BEGIN Shift_right_8: srt_bhv GENERIC MAP (width=> 8) PORT MAP (serial_in => data_in, clk => clock, q => qo); END right_shift; EXAMPLE 9.16 Write the code for a VHDL design entity that denes a universal shift register with a generic width. (The default width is eight bits.) Instantiate this entity as a component in a le for a 16-bit universal shift register. Solution srg_univ.vhd Universal shift register with generic width Default width = 8 bits 9.8 Programming Shift Registers in VHDL 433 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY srg_univ IS GENERIC (width : POSITIVE := 8); PORT ( clk, clear : IN STD_LOGIC; rsi, lsi : IN STD_LOGIC; function_select : IN STD_LOGIC_VECTOR(1 downto 0); p : IN STD_LOGIC_VECTOR(width-1 downto 0); q : BUFFER STD_LOGIC_VECTOR(width-1 downto 0) ); END srg_univ; srg_univ.vhd srg16uni.vhd ARCHITECTURE universal_shift of srg_univ IS BEGIN PROCESS (clk, clear) BEGIN IF clear = 0 THEN -- Conversion function to convert integer 0 to vector -- of any width. Requires ieee.std_logic_arith package. q <= CONV_STD_LOGIC_VECTOR(0, width); ELSIF (clkEVENT and clk = 1) THEN CASE function_select IS WHEN 00 => q <= q; Hold WHEN 01 => q <= rsi & q(width-1 downto 1); -- Shift right WHEN 10 => q <= q(width-2 downto 0) & lsi; -- Shift left WHEN 11 => q <= p; Load WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; END universal_shift; srg16uni.vhd 16-bit universal shift register (instantiates srg_univ) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srg16uni IS PORT ( clock, clr rsi, lsi s parallel_in qo END srg16uni; : : : : : IN IN IN IN BUFFER STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(1 downto 0); STD_LOGIC_VECTOR(15 downto 0); STD_LOGIC_VECTOR(15 downto 0) ); ARCHITECTURE universal_shift of srg16uni IS COMPONENT srg_univ GENERIC (width : POSITIVE); PORT ( clk, clear : IN STD_LOGIC; 434 C H A P T E R 9 Counters and Shift Registers rsi, lsi : IN STD_LOGIC; function_select : IN STD_LOGIC_VECTOR(1 downto 0); p : IN STD_LOGIC_VECTOR(width-1 downto 0); q : BUFFER STD_LOGIC_VECTOR(width-1 downto 0)); END COMPONENT; BEGIN Shift_universal_16: srg_univ GENERIC MAP (width=> 16) PORT MAP (clk => clock, clear => clr, rsi => rsi, lsi => lsi, function_select => s, p => parallel_in, q => qo); END universal_shift; When we are designing the clear function in srg_univ.vhd, we must account for the fact that we must set all bits of a vector of unknown width to 0. To get around this problem, we use a conversion function that changes an INTEGER value of 0 to a STD_LOGIC_VECTOR of width bits and assigns the value to the output. The required conversion function, CONV_STD_LOGIC_VECTOR(value, number_of_bits), is found in the std_logic_arith package in the ieee library. We could also use the construct q <= (others => 0); which states that the default case is to set all bits of q to 0 when clear is 0. Since there is no other case specied, all bits of q are cleared. LPM Shift Registers The Library of Parameterized Modules contains a shift register component, lpm_shiftreg, that we can instantiate in a VHDL design entity. The various functions of lpm_shiftreg are listed in Table 9.16. The following VHDL code instantiates lpm_shiftreg as an 8-bit shift register with serial input and serial output. In this case, the LPM component is declared explicitly, with the component declaration statement listing only the ports and parameters used by the design entity. The component instantiation statement lists the port names from the design entity in the same order as the corresponding component port names. By default the register direction is LEFT (i.e., toward the MSB). srg8_lpm.vhd 8-bit serial shift register (shift left by default) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; 9.8 435 Programming Shift Registers in VHDL Table 9.16 Available Functions for lpm_shiftreg Function Ports Parameters Description Basic serial operation clock, shiftin, shiftout, q[] LPM_WIDTH Data moves serially from shiftin to shiftout. Parallel outputs appear at q[]. Load sload, data[] none When sload 1, q[] goes to the value at input data[] on the next positive clock edge. Data[] has the same width as LPM_WIDTH. Synchronous clear sclr none When sclr Synchronous set sset LPM_SVALUE When sset 1, output goes to value of LPM_SVALUE on positive clock edge. If LPM_SVALUE is not specied q[] goes to all 1s. Asynchronous clear aclr none Output goes to zero when aclr Asynchronous set aset LPM_AVALUE Output goes to value of LPM_AVALUE when aset 1. If LPM_AVALUE is not specied, outputs all go HIGH when aset 1. Directional control none LPM_DIRECTION Optional direction control. Default direction is LEFT. LPM_DIRECTION LEFT or RIGHT. If shiftin and shiftout are used, the serial shift always goes through the entire shift register, in the direction given by LPM_DIRECTION. Clock enable enable none All synchronous functions are enabled when enable Defaults to enabled when not specied. 1, q[] goes to zero on positive clock edge 1. 1. ENTITY srg8_lpm IS PORT ( clk : IN STD_LOGIC; serial_in : IN STD_LOGIC; serial_out : OUT STD_LOGIC); END srg8_lpm; srg8_lpm.vhd srg8_lpm.scf ARCHITECTURE lpm_shift of srg8_lpm IS COMPONENT lpm_shiftreg GENERIC(LPM_WIDTH: POSITIVE); PORT ( clock, shiftin : IN STD_LOGIC; shiftout : OUT STD_LOGIC); END COMPONENT; BEGIN Shift_8: lpm_shiftreg GENERIC MAP (LPM_WIDTH=> 8) PORT MAP (clk, serial_in, serial_out); END lpm_shift; Figure 9.74 shows a simulation of the shift register, with the data shifting from right to left (LSB to MSB). Since there is no parallel output (q[]) instantiated in our design, we would not normally be able to monitor the progress of bits from ip-op to ip-op; we would only see shiftin, and then, eight clock cycles later, shiftout. However, we are able to monitor the ip-op states as buried nodes (Shift_8|dffs[7..0].Q). These buried nodes are the last eight lines in the simulation. 436 C H A P T E R 9 Counters and Shift Registers FIGURE 9.74 Simulation of an 8-bit LPM Shift Register (Shift Left) EXAMPLE 9.17 Modify the VHDL code just shown to make the serial shift register shift right, rather than left. Create a simulation to verify the circuit function. How do the positions of shiftin and shiftout ports relate to the internal ip-ops for the right-shift and left-shift implementations? Solution The modied VHDL code is shown next as design entity srg8lpm2. The only difference is the addition of the parameter LPM_DIRECTION to both the component declaration and component instantiation statements. srg8_lpm2.vhd 8-bit serial shift register (shift right) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY srg8lpm2 IS PORT ( clk : IN STD_LOGIC; serial_in : IN STD_LOGIC; serial_out : OUT STD_LOGIC); END srg8_lpm2; srg8_lpm2.vhd srg8_lpm2.scf ARCHITECTURE lpm_shift of srg8_lpm2 IS COMPONENT lpm_shiftreg GENERIC(LPM_WIDTH: POSITIVE; LPM_DIRECTION: STRING); PORT ( clock, shiftin : IN STD_LOGIC; shiftout : OUT STD_LOGIC); END COMPONENT; BEGIN shift_8: lpm)_shiftreg GENERIC MAP (LPM_WIDTH=> 8, LPM_DIRECTION => RIGHT) PORT MAP (clk, serial_in, serial_out); END lpm_shift; 9.8 Programming Shift Registers in VHDL 437 FIGURE 9.75 Example 9.17 Simulation of an 8-bit LPM Shift Register (Shift Right) The simulation for the right-shift register is shown in Figure 9.75. The inputs are identical to those of Figure 9.74, but the internal shift direction is opposite. The LPM component congures the serial shift input and output such that they allow data to go through the entire register, regardless of shift direction. For left-shift, serial_in (shiftin) is applied to D0, and is shifted toward Q7. For right-shift, the same serial_in is applied to D7 and shifted toward Q0. Thus, there is no right shift input or left shift input in this component, and also no bidirectional shift that can be controlled by an input port. Shift direction can only be set by the value of a parameter and is therefore xed when a component is instantiated. EXAMPLE 9.18 Write the VHDL code for an 8-bit LPM shift register with both parallel and serial outputs, parallel load and asynchronous clear. Create a simulation to verify the design operation. Solution The VHDL code for the parallel load shift register follows as srg8lpm3. LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY srg8lpm3 IS PORT ( clk, ld, clr p q_out serial_out END srg8lpm3; srg8lpm3.vhd srg8lpm3.scf : : : : IN IN OUT OUT STD_LOGIC; STD_LOGIC_VECTOR(7 downto 0); STD_LOGIC_VECTOR(7 downto 0); STD_LOGIC); ARCHITECTURE lpm_shift of srg8lpm3 IS COMPONENT lpm_shiftreg GENERIC(LPM_WIDTH: POSITIVE); PORT ( clock, load : IN STD_LOGIC; aclr : IN STD_LOGIC; data : IN STD_LOGIC_VECTOR (7 downto 0); q : OUT STD_LOGIC_VECTOR (7 downto 0); shiftout : OUT STD_LOGIC); END COMPONENT; BEGIN 438 C H A P T E R 9 Counters and Shift Registers Shift_8: lpm_shiftreg GENERIC MAP (LPM_WIDTH=> 8) PORT MAP (clk, ld, clr, p, q_out, serial_out); END lpm_shift; The simulation for srg8lpm3 is shown in Figure 9.76. The load input is initially HIGH, causing the shift register to load 55H ( 01010101) on the rst clock pulse. Since we have not instantiated the serial input shiftin, the serial input reverts to a default value of 1, causing the register to be lled with 1s. If we did not want this to be the case, we would have to instantiate the shiftin port and set it to 0. FIGURE 9.76 Example 9.18 Simulation of an 8-bit LPM Shift Register with Parallel Load SECTION 9.8 REVIEW PROBLEM 9.8 When a shift register is encoded in VHDL, why are its outputs dened as BUFFER, not OUT? 9.9 Shift Register Counters KEY TERMS Ring counter A serial shift register with feedback from the output of the last ipop to the input of the rst. Johnson counter A serial shift register with complemented feedback from the output of the last ip-op to the input of the rst. Also called a twisted ring counter By introducing feedback into a serial shift register, we can create a class of synchronous counters based on continuous circulation, or rotation, of data. If we feed back the output of a serial shift register to its input without inversion, we create a circuit called a ring counter. If we introduce inversion into the feedback loop, we have a circuit called a Johnson counter. These circuits can be decoded more easily than binary counters of similar size and are particularly useful for event sequencing. Ring Counters 9.9 Shift Register Counters 439 Figure 9.77 shows a 4-bit ring counter made from D ip-ops. This circuit could also be constructed from SR or JK ip-ops, as can any serial shift register. A ring counter circulates the same data in a continuous loop. This assumes that the FIGURE 9.77 4-bit Ring Counter D Q Q Q3 D Q Q Q2 D Q Q Q1 D Q Q0 Q Clock data have somehow been placed into the circuit upon initialization, usually by synchronous or asynchronous preset and clear inputs, which are not shown. Figure 9.78 shows the circulation of a logic 1 through a 4-bit ring counter. If we assume that the circuit is initialized to the state Q3Q2Q1Q0 1000, it is easy to see that the 1 is shifted one place right with each clock pulse. The feedback connection from Q0 to D3 ensures that the input of ip-op 3 will be lled by the contents of Q0, thus recirculating the initial data. The nal transition in the sequence shows the 1 recirculated to Q3. A ring counter is not restricted to circulating a logic 1. We can program the counter to circulate any data pattern we happen to nd convenient. Figure 9.79 shows a ring counter circulating a 0 by starting with an initial state of Q3Q2Q1Q0 0111. The circuit is the same as before; only the initial state has changed. Figure 9.80 shows the timing diagrams for the circuit in Figures 9.78 and 9.79. Ring Counter Modulus and Decoding The maximum modulus of a ring counter is the maximum number of unique states in its count sequence. In Figures 9.78 and 9.79, the ring counters each had a maximum modulus of 4. We say that 4 is the maximum modulus of the ring counters shown, since we can change the modulus of a ring counter by loading different data at initialization. For example, if we load a 4-bit ring counter with the data Q3Q2Q1Q0 1000, the following unique states are possible: 1000, 0100, 0010, and 0001. If we load the same circuit with the data Q3Q2Q1Q0 1010, there are only two unique states: 1010 and 0101. Depending on which data are loaded, the modulus is 4 or 2. Most input data in this circuit will yield a modulus of 4. Try a few combinations. NOTE The maximum modulus of a ring counter is the same as the number of bits in its output. A ring counter requires more ip-ops than a binary counter to produce the same number of unique states. Specically, for n ip-ops, a binary counter has 2n unique states and a ring counter has n. This is offset by the fact that a ring counter requires no decoding. A binary counter used to sequence eight events requires three ip-ops andeight 3-input decoding gates. To perform the same task, a ring counter requires eight ip-ops and no decoding gates. As the number of output states of an event sequencer increases, the complexity of the decoder for the binary counter also increases. A circuit requiring 16 output states can be implemented with a 4-bit binary counter and sixteen 4-input decoding gates. If you need 18 output states, you must have a 5-bit counter (24 18 25) and eighteen 5-input decoding gates. The only required modication to the ring counter is one more ip-op for each addi- 440 C H A P T E R 9 Counters and Shift Registers 1 0 Q D Q3 0 Q D Q Q2 0 Q D Q1 Q D Q Q Q Q0 Clock 0 1 Q D Q3 0 Q D Q Q2 0 Q D Q1 Q D Q Q Q Q0 Clock 0 0 Q D Q3 1 Q D Q Q2 0 Q D Q1 Q D Q Q Q Q0 Clock 0 0 Q D Q3 0 Q D Q Q2 1 Q D Q1 Q D Q Q Q Q0 Clock 1 D 0 Q Q Q3 D 0 Q Q Q2 D 0 Q Q Q1 D Q Q0 Q Clock FIGURE 9.78 Circulating a 1 in a Ring Counter tional state. A 16-state ring counter needs 16 ip-ops and an 18-state ring counter must have 18 ip-ops. No decoding is required for either circuit. Johnson Counters Figure 9.81 shows a 4-bit Johnson counter constructed from D ip-ops. It is the same as a ring counter except for the inversion in the feedback loop where Q0 is connected to D3. The circuit output is taken from ip-op outputs Q3 through Q0. Since the feedback introduces a twist into the recirculating data, a Johnson counter is also called a twisted ring 9.9 0 1 Q D Shift Register Counters Q3 1 Q D Q Q2 1 Q D Q1 Q D Q Q Q Q0 Clock 1 0 Q D Q3 1 Q D Q Q2 1 Q D Q1 Q D Q Q Q Q0 Clock 1 1 Q D Q3 0 Q D Q Q2 1 Q D Q1 Q D Q Q Q Q0 Clock 1 1 Q D Q3 1 Q D Q Q2 0 Q D Q1 Q D Q Q Q Q0 Clock 0 D 1 Q Q Clock FIGURE 9.79 Circulating a 0 in a Ring Counter Q3 D 1 Q Q Q2 D 1 Q Q Q1 D Q Q Q0 441 442 C H A P T E R 9 Counters and Shift Registers FIGURE 9.80 Timing Diagrams for Figures 9.78 and 9.79 0 D 0 Q Q Q3 D 0 Q Q Q2 D 0 Q Q Q1 D Q Q0 Q Clock FIGURE 9.81 4-bit Johnson Counter Table 9.17 Count Sequence of a 4-bit Johnson Counter Q3 Q2 Q1 Q0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 counter. Figure 9.82 shows the progress of data through a Johnson counter that starts cleared (Q3Q2Q1Q0 0000). The shaded ip-ops represents 1s and the unshaded ip-ops are 0s. Every 0 at Q0 is fed back to D3 as a 1 and every 1 is fed back as a 0. The count sequence for this circuit is given in Table 9.17. There are 8 unique states in the count sequence table. 443 D D D 1 1 1 Q Q Q Q Q Q Q Q Q3 Q3 Q3 Q3 D D D D 1 1 0 0 Q Q Q Q Q Q Q Q FIGURE 9.82 Data Circulation in a 4-bit Johnson Counter Clock Clock Clock Clock D 0 Q2 Q2 Q2 Q2 D D D D 1 0 0 0 Q Q Q Q Q Q Q Q Q1 Q1 Q1 Q1 D D D D 0 0 0 0 Q Q Q Q Q Q Q Q Q0 Q0 Q0 Q0 Clock Clock Clock Clock D D D D 0 0 0 1 Q Q Q Q Q Q Q Q Q3 Q3 Q3 Q3 D D D D 0 0 1 1 Q Q Q Q Q Q Q Q Q2 Q2 Q2 Q2 D D D D 0 1 1 1 Q Q Q Q Q Q Q Q Q1 Q1 Q1 Q1 D D D D 1 1 1 1 Q Q Q Q Q Q Q Q Q0 Q0 Q0 Q0 444 C H A P T E R 9 Counters and Shift Registers EXAMPLE 9.19 Write the VHDL code for a Johnson counter of generic width and instantiate it as an 8-bit counter. List the sequence of states in a table, assuming the counter is initially cleared, and create a simulation to verify the circuits operation. Include a clear input (synchronous). Solution The VHDL design entities for the generic-width component and the 8-bit Johnson counter follow. jnsn_ct.vhd Johnson counter of generic width LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY jnsn_ct IS GENERIC (width : POSITIVE := 4); PORT ( clk, clr : IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR(width-1 downto 0) ); END jnsn_ct; jnsn_ct.vhd jnsn_ct8.vhd jnsn_ct8.scf ARCHITECTURE johnson_counter of jnsn_ct IS BEGIN PROCESS (clk) BEGIN IF (clkEVENT and clk = 1) THEN IF clr = 0 THEN q <= (others => 0); n-bit clear function (n = width) ELSE q(width-1 downto 0) <= (not q(0) ) & q(width-1 downto 1); END IF; END IF; END PROCESS; END johnson_counter; jnsn_ct8.vhd 8-bit Johnson counter using component jnsn_ct LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY jnsn_ct8 IS PORT( clock, clear : IN qo : BUFFER END jnsn_ct8; STD_LOGIC; STD_LOGIC_VECTOR(7 downto 0)); ARCHITECTURE johnson_counter of jnsn_ct8 IS COMPONENT jnsn_ct GENERIC (width : POSITIVE); PORT( clk, clr : IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR(7 downto 0) ); END COMPONENT; BEGIN johnson: jnsn_ct GENERIC MAP (width=> 8) PORT MAP (clk => clock clr => clear, q => qo); END johnson_counter; 9.9 Shift Register Counters 445 Table 9.18 Count Sequence of an 8-bit Johnson Counter Q7Q6Q5Q4Q3Q2Q1Q0 00000000 10000000 11000000 11100000 11110000 11111000 11111100 11111110 11111111 01111111 00111111 00011111 00001111 00000111 00000011 00000001 Note that in the component le (jnsn_ct.vhd), the counter is cleared synchronously by the statement ( q <= (others => 0);). Recall that the clause (others => 0) can be used to set all bits of a signal aggregate to the value 0. This is a simple way to clear a vector of unknown width without using a conversion function. Table 9.18 shows the count sequence for the 8-bit Johnson counter. The simulation of the Johnson counter, including one full cycle and a clear, is shown in Figure 9.83. FIGURE 9.83 Example 9.19 Simulation of an 8-bit Johnson Counter Johnson Counter Modulus and Decoding NOTE The maximum modulus of a Johnson counter is 2n for a circuit with n ip-ops. The Johnson counter represents a compromise between binary and ring counters, whose maximum moduli are, respectively, 2n and n for an n-bit counter. 446 C H A P T E R 9 Counters and Shift Registers If it is used for event sequencing, a Johnson counter must be decoded, unlike a ring counter. Its output states are such that each state can be decoded uniquely by a 2-input AND or NAND gate, depending on whether you need active-HIGH or active-LOW indication. This yields a simpler decoder than is required for a binary counter. Table 9.19 shows the decoding of a 4-bit Johnson counter. Table 9.19 Decoding a 4-bit Johnson Counter Q3 Q0 Decoder Outputs 0 0 0 Q3 Q0 1 0 0 0 Q3 Q2 1/0 1 1 0 0 Q2 Q1 Pairs 1 1 1 0 Q1 Q0 1 1 1 1 Q3Q0 0 1 1 1 Q3Q2 0/1 0 0 1 1 Q2Q1 Pairs 0 D Q1 0 0 Q2 0 0 1 Q1Q0 0 Q Q3 Q D 0 Q Q Q2 D Comment MSB MSB LSB 0 LSB 1 0 Q Q Q1 D Q Q0 Q Clock Q3Q0 Q3Q2 Q2Q1 Q1Q0 Q3Q0 Q3Q2 Q2Q1 Q1Q0 FIGURE 9.84 4-bit Johnson Counter with Output Decoding 9.9 Shift Register Counters 447 Decoding a sequential circuit depends on the decoder responding uniquely to every possible state of the circuit outputs. If we want to use only 2-input gates in our decoder, it must recognize two variables for every state that are both active only in that state. A Johnson counter decoder exploits what might be called the 1/0 interface of the count sequence table. Careful examination of Tables 9.17 and 9.18 reveals that for every state, except where the outputs are all 1s or all 0s, there is a side-by-side 10 or 01 pair which exists only in that state. Each of these pairs can be decoded to give unique indication of a particular state. For example, the pair Q3Q2 uniquely indicates the second state since Q3 1 AND Q2 0 only in the second line of the count sequence table. (This is true for any size of Johnson counter; compare the second lines of Tables 9.17 and 9.18. In the second line of both tables, the MSB is 1 and the 2nd MSB is 0.) For the states where the outputs are all 1s or all 0s, the most signicant AND least signicant bits can be decoded uniquely, these being the only states where MSB LSB. Figure 9.84 shows the decoder circuit for a 4-bit Johnson counter. The output decoder of a Johnson counter does not increase in complexity as the modulus of the counter increases. The decoder will always consist of 2n 2-input AND or NAND gates for an n-bit counter. (For example, for an 8-bit Johnson counter, the decoder will consist of sixteen 2-input AND or NAND gates.) EXAMPLE 9.20 Draw the timing diagram of the Johnson counter decoder of Figure 9.84, assuming the counter is initially cleared. Solution Figure 9.85 shows the timing diagram of the Johnson counter and its decoder outputs. FIGURE 9.85 Example 9.20 Johnson Counter Decoder Outputs 448 C H A P T E R 9 Counters and Shift Registers SECTION 9.9 REVIEW PROBLEM 9.9 How many ip-ops are required to produce 24 unique states in each of the following types of counters: binary counter, ring counter, Johnson counter? How many and what type of decoding gates are required to produce an active-LOW decoder for each type of counter? SUMMARY 1. A counter is a circuit that progresses in a dened sequence at the rate of one state per clock pulse. 2. The modulus of a counter is the number of states through which the counter output progresses before repeating. 3. A counter with an ascending sequence of states is called an UP counter. A counter with a descending sequence of states is called a DOWN counter. 4. In general, the maximum modulus of a counter is given by 2n for an n-bit counter. 5. A counter whose modulus is 2n is called a full-sequence counter. The count progresses from 0 to 2n 1, which corresponds to a binary output of all 0s to all 1s. 6. A counter whose output is less than 2n is called a truncated sequence counter. 7. The adjacent outputs of a full-sequence binary counter have a frequency ratio of 2 1. The less signicant of the two bits has the higher frequency. 8. The outputs of a truncated sequence counter do not necessarily have a simple frequency relationship. 9. A synchronous counter consists of a series of ip-ops, all clocked from the same source, that stores the present state of the counter and a combinational circuit that monitors the counters present state and determines its next state. 10. A synchronous counter can be analyzed by a formal procedure that includes the following steps: a. Write the Boolean equations for the synchronous inputs of the counter ip-ops in terms of the present state of the ip-ip outputs. b. Evaluate each Boolean equation for an initial state to nd the states of the synchronous inputs. c. Use ip-op function tables to determine each ip-op next state. d. Set the next state to the new present state. e. Continue until the sequence repeats. 11. The analysis procedure above should be applied to any unused states of the counter to ensure that they will enter the count sequence properly. 12. A synchronous counter can be designed using a formal method that relies on the excitation tables of the ip-ops used in the counter. An excitation table indicates the required logic levels on the ip-op inputs to effect a particular transition. 13. The synchronous counter design procedure is based on the following steps: a. Draw the state diagram of the counter and use it to list the relationship between the counters present and next states. The table should list the counters present states in binary order. b. For the initial design, unused states can be set to a known destination, such as 0, or treated as dont care states. c. Use the ip-op excitation table to determine the synchronous input levels for each present-to-next state transition. d. Use Boolean algebra or Karnaugh maps to nd the simplest equations for the ip-op inputs (JK, D, or T) in terms of Q. e. Unused states should be analyzed by substituting their values into the Boolean equations of the counter. This will verify whether or not an unused state will enter the count sequence properly. 14. If a counter must reset to 0 from an unused state, the ipops can be reset asynchronously to their initial states or the counter can be designed with the unused states always having 0 as their next state. 15. A counter can be designed in VHDL by using a behavioral description or a structural design that uses a component from the Library of Parameterized Modules (LPM). 16. A behavioral counter design requires a PROCESS statement that lists the clock signal and any asynchronous inputs in its sensitivity list. An IF statement inside the PROCESS can monitor the active clock edge by using the predened EVENT attribute (e.g., clk EVENT) and increment a count variable. 17. A variable is local to a PROCESS and is assigned with the : operator. A signal is global to the VHDL design entity and is assigned with the <= operator. (Recall that a signal is like an internal connecting wire and a variable is a piece of working memory.) 18. A structural counter design can use an LPM component (lpm_counter) and instantiate the component in a component instantiation statement. The statements generic map species the component parameters, and its port map indicates the correspondence between the component port names and the user port, signal, or variable names. 19. Some of the most common control features available in synchronous counters include: a. Synchronous or asynchronous parallel load, which allows the count to be set to any value whenever a LOAD input is asserted b. Synchronous or asynchronous clear (reset), which sets all of the counter outputs to zero c. Count enable, which allows the count sequence to progress when asserted and inhibits the count when deasserted d. Bidirectional control, which determines whether the counter counts up or down Glossary e. Output decoding, which activates one or more outputs when detecting particular states on the counter outputs f. Ripple carry out or ripple clock out (RCO), a special case of output decoding that produces a pulse upon detecting the terminal count, or last state, of a count sequence 20. The parallel load function of a counter requires load data (the parallel input values) and a load command input, such as LOAD, that transfer the parallel data when asserted. If the load function is synchronous, a clock pulse is also required. 21. Synchronous load transfers data to the counter outputs on an active clock edge. Asynchronous load operates as soon as the load input activates, without waiting for the clock. 22. Synchronous load is implemented by a function select circuit that selects either the count logic or the direct parallel input to be applied to the synchronous input(s) of a ip-op. 23. Asynchronous load is implemented by enabling or inhibiting a pair of NAND gates, one of which asserts a ip-op clear input and the other of which asserts a preset input for the same ip-op. 24. The count enable function enables or disables the count logic of a counter without affecting other functions, such as clock or clear. This can be done by ANDing the count logic with the count enable input signal. 25. A ip-op in an UP counter toggles when all previous bits are HIGH. A ip-op in a DOWN counter toggles when all previous bits are LOW. A circuit that selects one of these two conditions (a pair of AND-shaped gates, combined in an OR gate; essentially a 2-to-1 multiplexer) can implement a bidirectional count. 26. An output decoder asserts one output for each counter state. A special case is a terminal count decoder that detects the last state of a count sequence. 27. RCO (ripple clock out) generates one clock pulse upon terminal count, with its positive edge at the end of the count cycle. 28. Asynchronous inputs to a behaviorally dened counter in VHDL must be included in the sensitivity list of the process dening the counter. Asynchronous inputs must be checked inside the process before the clock is checked for an active edge. 29. Synchronous inputs to a behaviorally dened counter should not be included in the sensitivity list of the process dening the counter. Synchronous inputs must be checked inside the IF statement that checks the clock edge. 449 30. A shift register is a circuit for storing and moving data. Three basic movements in a shift register are: serial (from one ipop to another), parallel (into all ip-ops at once), and rotation (serial shift with a connection from the last ip-op output to the rst ip-op input). 31. Serial shifting can be left (toward the MSB) or right (away from the MSB). This is the convention used by MAX PLUS II. Some data sheets indicate the opposite relationship between right/left and LSB/MSB. 32. A function select circuit can implement several shift register variations: bidirectional serial shift, parallel load with serial shift, and universal shift (parallel/serial in/out and bidirectional in one device). The circuit directs data to the D inputs of each ip-op from one of several sources, such as from the ip-op immediately to the left or right or from an external parallel input. 33. A shift register can be created in VHDL by the structural, dataow, or behavioral method. 34. A structural design instantiates components, such as D ipops, and connects them with internal signals. 35. A dataow design uses internal Boolean relationships between inputs and outputs. It is similar to a structural model, except that it must contain a process to create the ip-ops. 36. A behavioral design method uses a description of the shift register function to generate the required hardware. 37. A VHDL component can be created with parameters (such as width) that are specied when the component is instantiated. The parameters are listed in a GENERIC clause in the components entity declaration. Each parameter must be given a default value. The parameters are specied in a generic map in the design entity that instantiates the component. 38. A ring counter is a serial shift register with the serial output fed back to the serial input so that the internal data is continuously circulated. The initial value is generally set by asynchronous preset and clear functions. 39. The maximum modulus of a ring counter is n for a circuit with n ip-ops, as compared to 2n for a binary counter. A ring counter output is self-decoding, whereas a binary counter requires m 2n AND or NAND gates with n inputs each. 40. A Johnson counter is a ring counter where the feedback is complemented. A Johnson counter has 2n states for an n-bit counter which can be uniquely decoded by 2n 2-input AND or NAND gates. GLOSSARY Attribute A property associated with a named identier in VHDL. (e.g., the attribute EVENT, when associated with the identier clk (written clk EVENT), indicates whether a transition has occurred on the input called clk.) Clear Reset (synchronous or asynchronous) Behavioral design A VHDL design technique that uses descriptions of required behavior to describe the design. Conditional signal assignment statement A signal assignment statement that is executed only when a Boolean condition is satised. Bidirectional counter A counter that can count up or down, depending on the state of a control input. Bidirectional shift register A shift register that can serially shift bits left or right according to the state of a direction control input. Binary counter A counter that generates a binary count sequence. Command lines Signals that connect the control section of a synchronous circuit to its memory section and direct the circuit from its present to its next state. Control section The combinational logic portion of a synchronous circuit that determines the next state of the circuit. Count enable A control function that allows a counter to progress through its count sequence when active and disables the counter when inactive. 450 C H A P T E R 9 Counters and Shift Registers Count sequence The specic series of output states through which a counter progresses. Counter A sequential digital circuit whose output progresses in a predictable repeating pattern, advancing by one state for each clock pulse. Count-sequence table A list of counter states in the order of the count sequence. Dataow design A VHDL design technique that uses Boolean equations to dene relationships between inputs and outputs. DOWN counter A counter with a descending sequence. Excitation table A table showing the required input conditions for every possible transition of a ip-op output. Full-sequence counter A counter whose modulus is the same as its maximum modulus (m 2n for an n-bit counter). GENERIC A clause in the entity declaration of a VHDL component that lists the parameters that can be specied when the component is instantiated. Johnson counter A serial shift register with complemented feedback from the output of the last ip-op to the input of the rst. Also called a twisted ring counter Presettable counter A counter with a parallel load function. Recycle To make a transition from the last state of the count sequence to the rst state. Right shift A movement of data from the left to the right in a shift register. (Right is dened in MAX PLUS II as toward the LSB.) Ring counter A serial shift register with feedback from the output of the last ip-op to the input of the rst. Ripple carry out or ripple clock out (RCO) An output that produces one pulse with the same period as the clock upon terminal count. Rotation Serial shifting of data with the output(s) of the last ip-op connected to the synchronous input(s) of the rst ipop. The result is continuous circulation of the same data. Serial shifting Movement of data from one end of a shift register to the other at a rate of one bit per clock pulse. Shift register A synchronous sequential circuit that will store and move n-bit data, either serially or in parallel, in n ip-ops. SRGn Symbol for an n-bit shift register (e.g., SRG4 indicates a 4-bit shift register). Left shift A movement of data from the right to the left in a shift register. (Left is dened in MAX PLUS II as toward the MSB.) State diagram A diagram showing the progression of states of a sequential circuit. Maximum modulus (mmax) The largest number of counter states that can be represented by n bits (mmax 2n) State machine A synchronous sequential circuit. Memory section A set of ip-ops in a synchronous circuit that hold its present state. Modulo-n (or mod-n) counter A counter with a modulus of n. Modulus The number of states through which a counter sequences before repeating. Next state The desired future state of ip-op outputs in a synchronous sequential circuit after the next clock pulse is applied. Parallel load A function that allows simultaneous loading of binary values into all ip-ops of a synchronous circuit. Parallel loading can be synchronous or asynchronous. Parallel-load shift register A shift register that can be preset to any value by directly loading a binary number into its internal ip-ops. Parallel transfer Movement of data into all ip-ops of a shift register at the same time. Present state The current state of ip-op outputs in a synchronous sequential circuit. Status lines Signals that communicate the present state of a synchronous circuit from its memory section to its control section. Structural design A VHDL design technique that connects predesigned components using internal signals. Synchronous counter A counter whose ip-ops are all clocked by the same source and thus change in synchronization with each other. Terminal count The last state in a count sequence before the sequence repeats (e.g., 1111 is the terminal count of a 4-bit binary UP counter; 0000 is the terminal count of a 4-bit binary DOWN counter). Truncated-sequence counter A counter whose modulus is less than its maximum modulus (m 2n for an n-bit counter) Universal shift register A shift register that can operate with any combination of serial and parallel inputs and outputs (i.e., serial in/serial out, serial in/parallel out, parallel in/serial out, parallel in/parallel out). A universal shift register is often bidirectional, as well. UP counter A counter with an ascending sequence. diagram which shows how you can use a digital counter to light a LOT FULL sign after 4095 cars have entered. (Assume no cars leave the lot until after the game, so you dont need to keep track of cars leaving the lot.) How many bits should the counter have? PROBLEMS Problem numbers set in color indicate more difcult problems; those with underlines indicate most difcult problems. 9.1 Basic Concepts of Digital Counters 9.1 A parking lot at a football stadium is monitored before a game to determine whether or not there is available space for more cars. When a car enters the lot, the driver takes a ticket from a dispenser which also produces a pulse for each ticket taken. The parking lot has space for 4095 cars. Draw a block 9.2 Figure 9.86 shows a mod-16 which controls the operation of two digital sequential circuits, labeled Circuit 1 and Circuit 2. Circuit 1 is positive edge-triggered and clocked by counter output Q1. Circuit 2 is negative edgetriggered and clocked by Q3. (Q3 is the MSB output of Problems i. The counter is at state 0111. What is the count after 7 clock pulses are applied? CTR DIV 16 CLK 451 ii. After 5 clock pulses, the counter output is at 0001. What was the counter state prior to the clock pulses? CLK Q3 Q2 Q1 Q0 iii. The counter output is at 1000 after 15 clock pulses. What was the original output state? 9.6 What is the maximum modulus of a 6-bit counter? A 7bit? 8-bit? 9.7 Draw the count sequence table and timing diagram of a mod-10 UP counter. 9.8 Draw the state diagram, count sequence table, and timing diagram of a mod-10 DOWN counter. 9.9 A mod-16 counter is clocked by a waveform having a frequency of 48 kHz. What is the frequency of each of the waveforms at Q0, Q1, Q2, and Q3? 9.10 A mod-10 counter is clocked by a waveform having a frequency of 48 kHz. What is the frequency of the Q3 output waveform? The Q0 waveform? Why is it difcult to determine the frequencies of Q1 and Q2? Circuit 1 Circuit 2 FIGURE 9.86 Problem 9.2 Mod-16 Counter Driving Two Sequential Circuits the counter.) a. Draw the timing diagram for one complete cycle of the circuit operation. Draw arrows on the active edges of the waveforms that activate Circuit 1 and Circuit 2. 9.2 Synchronous Counters b. State how many times Circuit 1 is clocked for each time that Circuit 2 is clocked. 9.11 Draw the circuit for a synchronous mod-16 UP counter made from negative edge-triggered JK ip-ops. 9.3 Draw the timing diagram for one complete cycle of a mod-8 counter, including waveforms for CLK, Q0, Q1, and Q2, where Q0 is the LSB. 9.12 Write the Boolean equations required to extend the counter drawn in Problem 9.11 to a mod-64 counter. 9.13 9.4 How many bits are required to make a counter with a modulus of 64? Why? What is the maximum count of such a counter? Write the J and K equations for the MSB of a synchronous mod-256 (8-bit) UP counter. 9.14 Analyze the operation of the synchronous counter in Figure 9.87 by drawing a state table showing all transitions, including unused states. Use this state table to draw a state diagram and a timing diagram. What is the counters modulus? 9.15 a. Write the equations for the J and K inputs of each ip- 9.5 a. Draw the state diagram of a mod-10 UP counter. b. Use the state diagram drawn in part a to answer the following questions: FIGURE 9.87 Problem 9.14 Synchronous Counter 452 C H A P T E R 9 Counters and Shift Registers FIGURE 9.88 Problem 9.15 Synchronous Counter FIGURE 9.89 Problem 9.16 Counter op of the synchronous counter represented in Figure 9.88. b. Assume that Q3Q2Q1Q0 1010 at some point in the count sequence. Use the equations from part a to predict the circuit outputs after each of three clock pulses. 9.16 Analyze the operation of the counter shown in Figure 9.89. Predict the count sequence by determining the J and K inputs and resulting transitions for each counter output state. Draw the state diagram and the timing diagram. Assume that all ip-op outputs are initially 0. 9.3 Design of Synchronous Counters 9.17 Draw the timing diagram and state diagram of a synchronous mod-10 counter with a positive edge-triggered clock. 9.18 Design a synchronous mod-10 counter, using positive edge-triggered JK ip-ops. Check that unused states properly enter the main sequence. Draw a state diagram showing the unused states. 9.19 Design a synchronous mod-10 counter, using positive edge-triggered D ip-ops. Check that unused states properly enter the main sequence. Draw a state diagram showing the unused states. 9.20 Design a synchronous 3-bit binary counter using T ipops. 9.21 Table 9.20 shows the count sequence for a biquinary sequence counter. The sequence has ten states, but does not progress in binary order. The advantage of the sequence is that its most signicant bit has a divide-by-10 ratio, relative to a clock input, and a 50% duty cycle. Design the Problems Table 9.20 Biquinary Sequence 453 load is really synchronous and that the reset is really asynchronous. 9.28 Refer to the 4-bit counter of Figure 9.33 (p. 396). The graphic design les for the counter are found on the accompanying CD as 4bit_sle.gdf and sl_count.gdf in the folder drive:\Student Files\Chapter09. Copy these les to a new folder and modify the synchronous count element sl_count.gdf so that it implements an active-HIGH synchronous load and an active-LOW synchronous clear function, as well as the binary count function. Create a default symbol for the new element and substitute it in 4bit_sle.gdf for the existing counter elements sl_count. The load function should have priority over count enable, and clear (reset) should have priority over both. Save and compile the new le. Hints: (1) The clear function makes Q 0 after a clock pulse. (2) Q follows D. 9.29 Q3Q2Q1Q0 Create a MAX PLUS II simulation to verify the functions of the counter in Problem 9.28. The simulation must include the recycle point of the counter and show that the load and clear really are synchronous and that load has priority over count enable and clear has priority over both. 9.30 Derive the Boolean equations for the synchronous DOWN-counter in Figure 9.35. 9.31 Write the Boolean equations for the count logic of the 4bit bidirectional counter in Figure 9.38. Briey explain how the logic works. 9.32 Draw a MAX PLUS II Graphic Design File for a bidirectional counter, using T ip-ops. Create a simulation of the counter to verify its function 9.33 Use MAX PLUS II to create a synchronous bidirectional counter with synchronous load, asynchronous reset, and count enable. The count enable should not affect the operation of the load and reset functions. The functions should have the following priority: (1) clear; (2) load; and (3) count. Create a MAX PLUS II simulation to verify the operation of your design. 0000 0001 0010 0011 0100 1000 1001 1010 1011 1100 synchronous counter circuit for this sequence, using D ip-ops. Hint: When making the state table, list all present states in binary order. The next states will not be in binary order. 9.4 Programming Binary Counters in VHDL 9.22 Write the VHDL code for a behavioral description of a 6bit binary counter with asynchronous clear. 9.23 Create a simulation le in MAX PLUS II to verify the operation of the counter in Problem 9.22. (Use a 40 ns clock, which approximates the clock period of the oscillator on the Altera UP-1 board.) Note: To make a useful simulation, you must include the recycle point, which may be beyond the default end time of the simulation (1 ms). To change the end time, select End Time from the MAX PLUS II File menu in the Simulator menu. To change the clock period, select Grid Size from the MAX PLUS II Options menu in the Simulator window. The default clock period is two grid spaces. 9.24 Write a VHDL le that instantiates a counter from the Library of Parameterized Modules to make a 12-bit binary counter. Create a MAX PLUS II simulation to verify the operation of the counter. (Refer to the note after Problem 9.23.) 9.5 Control Options for Synchronous Counters 9.25 Refer to the 4-bit counter of Figure 9.26 (p. 391). The graphic design les for the counter are found on the CD accompanying this text as 4bit_sl.gdf and sl_count.gdf in the folder drive:\Student_Files\Chapter09. Copy these les to a new folder and use the MAX PLUS II graphic editor to expand the counter of Figure 9.26 to a 5-bit counter with synchronous load and asynchronous reset. Save and compile the le to make sure that there are no design errors. Create a MAX PLUS II simulation to verify the functions of the counter in Problem 9.26. The simulation must include the recycle point of the counter and show that the 9.34 Write the VHDL code for a counter that uses a behavioral description of the following functions: 12-bit binary UP count; active-LOW asynchronous clear, active-LOW synchronous load, active-LOW count enable, terminal count decoder. The clear function should have the highest priority, followed by load, then count enable. Create a simulation in MAX PLUS II that veries the functions of this counter. 9.35 Write the VHDL code for a behavioral description of a bidirectional counter with a modulus of 24. The counter should also have an active-LOW synchronous clear function that has priority over the count. Create a MAX PLUS II simulation le to verify the counter operation. 9.36 Write the VHDL code for a 4-bit counter with two decoding outputs called eq8 and eq12. Out eq8 goes HIGH when the count equals 8 and eq12 goes HIGH when the count equals 12 (decimal). The counter should also have an active-LOW asynchronous clear function that has pri- Briey explain the difference between asynchronous and synchronous parallel load in a synchronous counter. Draw a partial timing diagram that illustrates both functions for a 4-bit counter. 9.26 9.6 Programming Presettable and Bidirectional Counters in VHDL 9.27 454 C H A P T E R 9 Counters and Shift Registers FIGURE 9.90 Problem 9.44 Timing Diagram ority over the count. Create a MAX PLUS II simulation le to verify the counter operation. 9.37 9.38 9.39 Modify the VHDL code in Example 9.10 (p. 412) so that the counter synchronously sets to all 1s ( 4095), rather than to 2047. Do not use SVALUE 4095. Create a simulation in MAX PLUS II that veries the operation of the counter. State the main difference between the code for Example 9.10 and the solution to this problem. Use a counter from the Library of Parameterized Modules to implement the counter described in Problem 9.35. Create a MAX PLUS II simulation le to verify the operation of the counter. Write a VHDL le that instantiates an 8-bit LPM count with synchronous load and clear, count enable, and directional control. Also include a terminal count decoder. (The LPM counter has no port for the terminal count function, so it must be done separately.) Create a MAX PLUS II simulation to verify the operation of the counter. 9.7 Shift Registers 9.40 Use the MAX PLUS II Graphic Editor to draw the circuit of a serial shift register constructed from JK ipops. Create a simulation to verify the operation of the shift register. 9.41 Use the MAX PLUS II Graphic Editor to create the logic diagram of the 4-bit serial shift register based on JK ip-ops that shifts left, rather than right. Create a simulation to verify the operation of the shift register. 9.42 The following bits are applied in sequence to the input of a 6-bit serial right-shift register: 0111111 (0 is applied rst). Draw the timing diagram. 9.43 After the data in Problem 9.42 are applied to the 6-bit shift register, the serial input goes to 0 for the next 8 clock pulses and then returns to 1. Write the internal states, Q5 through Q0, of the shift register ip-ops after the rst 2 clock pulses. Write the states after 6, 8, and 10 clock pulses. 9.44 Complete the timing diagram of Figure 9.90, which is for a serial shift register (right-shift). Assume the shift register is initially cleared. What happens to the state of the circuit if D7 stays HIGH beyond the end of the diagram and the CLK input continues to pulse? 9.45 An 8-bit right-shift serial-in-serial-out shift register is initially cleared and has the following data clocked into its serial input: 1011001110. Draw a timing diagram of the circuit showing the CLK, Serial Input, and Serial Output. (Assume the individual ip-op outputs are not accessible.) Problems 455 FIGURE 9.91 Problem 9.46 Logic Circuit Complete the logic circuit shown in Figure 9.91 to make a bidirectional shift register. 9.47 9.51 Modify the VHDL code for the left-shift register Problem 9.50 to make a shift register of generic width. Use this component in another VHDL le to make a 32-bit shift register that shifts left. Create a simulation le to verify the operation of this design. 9.52 Write the code for a VHDL design entity that implements a 4-bit universal shift register with asynchronous clear. Create a simulation that veries the design function. 9.53 Use MAX PLUS II to create simulations for the generic-width and the 16-bit universal shift registers in Example 9.16 (p. 432). What is the difference in width between the default value of the generic shift register and the instantiated component in the 16-bit le? Given this difference, why can the generic-width shift register be correctly used as a component in the 16-bit design entity? 9.54 Use an LPM shift register in a VHDL le to instantiate a 48-bit shift register with the following functions: serial input, parallel output, synchronous clear. 9.55 9.46 Use an LPM shift register in a VHDL le to instantiate a 10-bit shift register with the following functions: serial input and output whose internal value can be synchro- Complete the logic circuit shown in Figure 9.92 to make a parallel-in-serial-out shift register. 9.8 Programming Shift Registers in VHDL 9.48 Write the VHDL code for an 8-bit serial shift register using a structural design procedure. Use JK ip-ops. (MAX PLUS II primitive: JKFF.) Create a MAX PLUS II simulation le to verify the operation of your design. 9.49 Repeat Problem 9.48 using a dataow design procedure. 9.50 Modify the VHDL code for the behaviorally designed shift register srg4behv.vhd so that the shift register moves the data left, not right. Hint: The statement q (3 downto 0) <= serial_in & q(3 downto 1); is equivalent to the following two statements: q(3) <= serial_in; q(2 downto 0) <= q(3 downto 1); Create a simulation le to verify the operation of this device. FIGURE 9.92 Problem 9.47 Logic Circuit 456 C H A P T E R 9 Counters and Shift Registers 9.58 A control sequence has ten steps, each activated by a logic HIGH. Use MAX PLUS II to design a counter and decoder in each of the following congurations to produce the required sequence: binary counter, ring counter, and Johnson counter. You may use a Graphic Design File or VHDL. Create a simulation for each counter and decoder. 9.59 nously set to 960. Create a MAX PLUS II simulation to verify the operation of the design. Use the MAX PLUS II Graphic Editor to design a 4-bit ring counter that can be asynchronously initialized to Q3Q2Q1Q0 1000 by using only the clear inputs of its ip-ops. No presets allowed. Hint: use a circuit with a 9.9 Shift Register Counters 9.56 9.57 Write the VHDL code for a ring counter of generic width and instantiate it as an 8-bit ring counter. List the sequence of states in a table, assuming the counter is initially cleared, and create a simulation to verify the circuits operation. Include a clear input (synchronous). Construct the count sequence table of a 5-bit Johnson counter, assuming the counter is initially cleared. What changes must be made to the decoder part of the circuit in Figure 9.84 (p. 446) if it is to decode the 5-bit Johnson counter? double twist in the data path. ANSWERS TO SECTION REVIEW PROBLEMS Section 9.5 9.5 The completed timing diagram is shown in Figure 9.93. Section 9.1 Section 9.6 9.1 A mod-24 UP counter goes from 00000 to 10111 (0 to 23). This requires 5 outputs. The counter is a truncated sequence since its modulus is less than 25 32. 9.6 Asynchronous clear: PROCESS (clock, clear); Synchronous clear: PROCESS (clock) Section 9.7 Section 9.2 9.7 JK ip-ops can be used in the shift register of Figure 9.58. The Q output of any stage connects to the J input of the next stage and the Q output of any stage connects to the K input of the next. The serial_in input connects directly to the J input of the rst ip-op. Serial_in is applied to K of the rst ip-op through an inverter (NOT gate). 9.2 1001, 0000 Section 9.3 9.3 JK ip-ops: J3K3 X0, J2K2 1X, J1K1 D ip-ops: D3 1, D2 1, D1 0, D0 X1, J0K0 0 X1 Section 9.4 Section 9.8 9.4 If (clockEVENT AND clock = 0) THEN 9.8 A shift register output is dened as a port of mode BUFFER because this mode allows a signal to be fed back into the PLD matrix and reused as an input to another part of the circuit. count := count + 1; END IF; Section 9.9 Binary: 5 ip-ops, 24 5-inputs NANDs; Ring: 24 ip-ops, no LOAD RESET CLOCK P 0 8 QA 0 1 2 3 QS 0 1 2 3 4 8 4 FIGURE 9.93 Answer to Section Review Problem 9.5 5 9 8 9 A 1 0 A 0 1 2 5 2 6 5 6 CHAPTER 10 State Machine Design OUTLINE CHAPTER OBJECTIVES 10.1 State Machines 10.2 State Machines with No Control Inputs 10.3 State Machines with Control Inputs 10.4 Switch Debouncer for a Normally Open Pushbutton Switch 10.5 Unused States in State Machines 10.6 Trafc Light Controller Upon successful completion of this chapter you will be able to: Describe the components of a state machine. Distinguish between Moore and Mealy implementations of state machines. Draw the state diagram of a state machine from a verbal description. Use the classical (state table) method of state machine design to determine the Boolean equations of the state machine. Translate the Boolean equations of a state machine into a Graphic Design File in Alteras MAX PLUS II software. Write VHDL code to implement state machines. Create simulations in MAX PLUS II to verify the function of a state machine design. Determine whether the output of a state machine is vulnerable to asynchronous changes of input. Design state machine applications, such as a switch debouncer, a singlepulse generator, and a trafc light controller. 10.1 State Machines KEY TERMS State machine A synchronous sequential circuit, consisting of a sequential logic section and a combinational logic section, whose outputs and internal ip-ops progress through a predictable sequence of states in response to a clock and other input signals. Moore machine A state machine whose output is determined only by the sequential logic of the machine. Mealy machine A state machine whose output is determined by both the sequential logic and the combinational logic of the machine. State variables The variables held in the ip-ops of a state machine that determine its present state. The number of state variables in a machine is equivalent to the number of ip-ops. 457 458 C H A P T E R 1 0 State Machine Design FIGURE 10.1 Moore-Type State Machine The synchronous counters and shift registers we examined in Chapter 9 are examples of a larger class of circuits known as state machines. As described for synchronous counters in Section 9.2, a state machine consists of a memory section that holds the present state of the machine and a control section that determines the machines next state. These sections communicate via a series of command and status lines. Depending on the type of machine, the outputs will either be functions of the present state only or of the present and next states. Figure 10.1 shows the block diagram of a Moore machine. The outputs of a Moore machine are determined solely by the present state of the machines memory section. The output may be directly connected to the Q outputs of the internal ip-ops, or the Q outputs might pass through a decoder circuit. The output of a Moore machine is synchronous to the system clock, since the output can only change when the machines internal state variables change. The block diagram of a Mealy machine is shown in Figure 10.2. The outputs of the Mealy machine are derived from the combinational (control) section of the machine, as FIGURE 10.2 Mealy-Type State Machine 10.2 State Machines with No Control Inputs 459 well as the sequential (memory) part of the machine. Therefore, the outputs can change asynchronously when the combinational circuit inputs change out of phase with the clock. (When we say that the outputs change asynchronously, we generally do not mean a change via a function such as asynchronous reset that directly affects the machines ip-ops.) SECTION 10.1 REVIEW PROBLEM 10.1 What is the main difference between a Moore-type state machine and a Mealy-type state machine? 10.2 State Machines with No Control Inputs KEY TERMS Bubble A circle in a state diagram containing the state name and values of the state variables. A state machine can be designed using a classical technique, similar to that used to design a synchronous counter. We can also use a VHDL design method. We will design several state machines, using both classical and VHDL techniques. As an example of these techniques, we will design a state machine whose output depends only on the clock input: a 3-bit counter with a Gray code count sequence. A 3-bit Gray code, shown in Table 10.1, changes only one bit between adjacent codes and is therefore not a binary-weighted sequence. Table 10.1 3-bit Gray Code Sequence Q2Q1Q0 000 001 011 010 110 111 101 100 Gray code is often used in situations where it is important to minimize the effect of single-bit errors. For example, suppose the angle of a motor shaft is measured by a detected code on a Gray-coded shaft encoder, shown in Figure 10.3. The encoder indicates a 3-bit number for each of eight angular positions by having three concentric circular segments for each code. A dark band indicates a 1 and a transparent band indicates a 0, with the MSB as the outermost band. The dark or transparent bands are detected by three sensors that detect FIGURE 10.3 Gray Code on a Shaft Encoder 100 000 101 001 111 011 110 010 460 C H A P T E R 1 0 State Machine Design light shining through a transparent band. (A real shaft encoder has more bits to indicate an angle more precisely. For example, a shaft encoder that measures an angle of one degree would require nine bits, since there are 360 degrees in a circle and 28 360 29.) For most positions on the encoder, the error of a single bit results in a positional error of only one eighth of the circle. This is not true with binary coding, where single bit errors can give larger positional errors. For example if the positional decoder reads 100 instead of 000, this is a difference of 4 in binary. The same codes differ by only one position in Gray code. Classical Design Techniques We can summarize the classical design technique for a state machine, as follows: 1. Dene the problem. 2. Draw a state diagram. 3. Make a state table that lists all possible present states and inputs and the next state and output state for each present state/input combination. List the present states and inputs in binary order. 4. Use ip-op excitation tables to determine at what states the ip-op synchronous inputs must be to make the circuit go from each present state to its next state. The next state variables are functions of the inputs and present state variables. 5. Write the output value for each present state/input combination. The output variables are functions of the inputs and present state variables. 6. Simplify the Boolean expression for each output and synchronous input. 7. Use the Boolean expressions found in step 6 to draw the required logic circuit. Let us follow this procedure to design a 3-bit Gray code counter. We will modify the procedure to account for the fact that there are no inputs other than the clock and no outputs that must be designed apart from the counter itself. 1. Dene the problem. Design a counter whose outputs progress in the sequence dened in Table 10.1. 2. Draw a state diagram. The state diagram is shown in Figure 10.4. In addition to the values of state variables shown in each circle (or bubble), we also indicate a state name, such as s0, s1, s2, and so on. This name is independent of the value of state variables. We use numbered states (s0, s1, . . .) for convenience, but we could use any names we wanted to. FIGURE 10.4 State Diagram for a 3-bit Gray Code Counter S7 100 S0 000 S1 001 S6 101 S2 011 S5 111 S4 010 S3 010 3. Make a state table. The state table, based on D ip-ops, is shown in Table 10.2. Since there are eight unique states in the state diagram, we require three state variables (23 8), and hence three ip-ops. Note that the present states are in binary-weighted order, even though the count does not progress in this order. In such a case, it is essential to have an accurate state diagram, from which we derive each next state. For example, if 10.2 State Machines with No Control Inputs 461 Table 10.2 State Table for a 3-bit Gray Code Counter Present State Next State Synchronous Inputs Q2Q1Q0 Q2Q1Q0 D2D1D0 000 001 010 011 001 011 110 010 001 011 110 010 100 101 110 111 000 100 111 101 000 100 111 101 the present state is 010, the next state is not 011, as we would expect, but 110, which we derive by examining the state diagram. Why list the present states in binary order, rather than the same order as the output sequence? By doing so, we can easily simplify the equations for the D inputs of the ipops by using a series of Karnaugh maps. This is still possible, but harder to do, if we list the present states in order of the output sequence. 4. Use ip-op excitation tables to determine at what states the ip-op synchronous inputs must be to make the circuit go from each present state to its next state. This is not necessary if we use D ip-ops, since Q follows D. The D inputs are the same as the next state outputs. For JK or T ip-ops, we would follow the same procedure as for the design of synchronous counters outlined in Chapter 9. 5. Simplify the Boolean expression for each synchronous input. Figure 10.5 shows three Karnaugh maps, one for each D input of the circuit. Q0 Q2 Q1 0 00 0 0 01 1 0 11 1 1 10 0 1 Q0 Q2 Q1 1 D2 1 01 1 1 0 10 0 Q1 Q0 1 00 1 1 0 0 11 1 1 10 0 Q2 Q0 0 01 1 11 Q2 Q0 0 Q0 Q2 Q1 1 00 Q1 Q0 0 0 0 Q2 Q1 Q2 Q1 D0 D1 FIGURE 10.5 Karnaugh Maps for 3-bit Gray Code Counter The K-maps yield three Boolean equations: D2 D1 D0 Q1Q0 Q1Q0 Q2 Q1 Q2Q0 Q2Q0 Q2Q1 6. Draw the logic circuit for the state machine. Figure 10.6 shows the circuit for a 3-bit Gray code counter, drawn as a Graphic Design File in MAX PLUS II. A simulation for this circuit is shown in Figure 10.7, with the outputs shown as individual waveforms and as a group with a binary value. 462 INPUT NOT NOT NOT OR2 AND2 FIGURE 10.6 Logic Diagram of a 3-bit Gray Code Counter CLK Q0 Q1 Q2 AND2 D DFF Q CLRN PRN Q2 AND2 D DFF Q CLRN PRN Q1 D DFF AND2 OR2 AND2 OR2 AND2 Q CLRN PRN Q0 OUTPUT OUTPUT OUTPUT Q2 Q1 Q0 10.2 State Machines with No Control Inputs 463 gray_ct3.gof gray_ct3.scf FIGURE 10.7 Simulation of a 3-bit Gray Code Counter (from Graphic Design File) VHDL Design of State Machines KEY TERMS Enumerated type A user-dened type in VHDL in which all possible values of a named identier are listed in a type denition statement. State machines can be dened in VHDL within a CASE statement. The VHDL code below illustrates the principle, using the 3-bit Gray code counter as an example. gray_ct1.vhd 3-bit Gray code counter (state machine with decoded outputs) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY gray_ct1 IS PORT( clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 downto 0)); END gray_ct1; gray_ct1.vhd ARCHITECTURE a OF gray_ct1 IS TYPE STATE_TYPE IS (s0, s1, s2, s3, s4, s5, s6, s7); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN CASE state IS WHEN s0 => state <= s1; WHEN s1 => state <= s2; WHEN s2 => state <= s3; WHEN s3 => state <= s4; WHEN s4 => state <= s5; 464 C H A P T E R 1 0 State Machine Design WHEN s5 => state <= s6; WHEN s6=> state <= s7; WHEN s7 => state <= s0; END CASE; END IF; END PROCESS; WITH state SELECT q <= 000 WHEN 001 WHEN 011 WHEN 010 WHEN 110 WHEN 111 WHEN 101 WHEN 100 WHEN END a; s0, s1, s2, s3, s4, s5, s6, s7; Recall that the format of a CASE statement is: CASE __expression IS WHEN__constant_value => __statement; __statement; WHEN__constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE; The keyword expression in the CASE statement refers to a signal called state that we dene to represent the state variables within the machine. For each possible value of state, we make an assignment indicating the next state of the machine. For example, the clause (WHEN s0 => (state <= s1)); indicates a transition from state s0 to state s1. The actual output values of the counter are assigned in a selected signal assignment statement after the PROCESS statement. Notice that the signal state can have one of eight different values, from s0 to s7. Until now, we have seen signals with values such as 1 (BIT or STD_LOGIC types), 011 (BIT_VECTOR or STD_LOGIC_VECTOR types), or 7 (INTEGER types). The signal state is of type STATE_TYPE, which is a user-dened enumerated type. An enumerated type is simply a list of all values a signal, variable, or port of that type is allowed to have. For example, we could dene a type called DIRECTION with four values, with the statement: TYPE DIRECTION IS (up, down, left, right); We could then dene a signal called position of type DIRECTION: SIGNAL position: DIRECTION: An IF statement or other construct could then assign one of the four dened values of type DIRECTION to the signal called position: 10.3 State Machines with Control Inputs 465 IF (x=0 and y=0) THEN position <= down; ELSIF (x=0 and y=1) THEN position <= left; ELSIF (x=1 and y=0) THEN position <= up; ELSE position <= right; END IF; Thus the named identier position of type DIRECTION can take on only the four values specied in the enumerated type denition. An alternative way to encode the 3-bit counter is to include output assignments within the body of the CASE statement. Each case then has more than one statement, as indicated in the following VHDL code. -- gray_ct2.vhd -- 3-bit Gray code counter -- (outputs dened within states) LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY gray_ct2 IS PORT( clk : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 downto 0)); END gray_ct2; gray_ct2.vhd ARCHITECTURE a OF gray_ct2 IS TYPE STATE_TYPE IS (s0, s1, s2, s3, s4, s5, s6, s7); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN CASE state IS WHEN s0 => state <= s1; q <= 001; WHEN s1 => state <= s2; q <= 011; WHEN s2 => state <= s3; q <= 010; WHEN s3 => state <= s4; q <= 110; WHEN s4 => state <= s5; q <= 111; WHEN s5 => state <= s6; q <= 101; WHEN s6 => state <= s7; q <= 100; WHEN s7 => 466 C H A P T E R 1 0 State Machine Design state <= s0; q <= 000; END CASE; END IF; END PROCESS; END a; The above VHDL code is identical to that of the previous example, except for the way the outputs are assigned. SECTION 10.2 REVIEW PROBLEM 10.2 Write the Boolean equations for the J and K inputs of the ip-ops in a 3-bit Gray code counter based on JK ip-ops. 10.3 State Machines with Control Inputs KEY TERMS Control input A state machine input that directs the machine from state to state. Conditional transition A transition between states of a state machine that occurs only under specic conditions of one or more control inputs. Unconditional transition A transition between states of a state machine that occurs regardless of the status of any control inputs. As an extension of the techniques used in the previous section, we will examine the design of state machines that use control inputs, as well as the clock, to direct their operation. Outputs of these state machines will not necessarily be the same as the states of the machines ip-ops. As a result, this type of state machine requires a more detailed state diagram notation, such as that shown in Figure 10.8. The state machine represented by the diagram in Figure 10.8 has two states, and thus FIGURE 10.8 State Diagram Notation in1/out1, out2 1/00 start 0 X /01 State name Legend State variable Input value Output value 0/10 Unconditional transition continue 1 Conditional transition requires only one state variable. Each state is represented by a bubble (circle) containing the state name and the value of the state variable. For example, the bubble containing the start notation indicates that the state called start corresponds to a state variable with a 0 value of 0. Each state must have a unique value for the state variable(s). Transitions between states are marked with a combination of input and output values 10.3 State Machines with Control Inputs 467 corresponding to the transition. The inputs and outputs are labeled in1, in2, . . . , inx/out1, out2, . . . ,outx. The inputs and outputs are sometimes simply indicated by the value of each variable for each transition. In this case, a legend indicates which variable corresponds to which position in the label. For example, the legend in the state diagram of Figure 10.8 indicates that the inputs and outputs are labeled in the order in1/out1, out2. Thus if the machine is in the start state and the input in1 goes to 0, there is a transition to the state continue. During this transition, out1 goes to 1 and out2 goes to 0. This is indicated by the notation 0/10 beside the transitional arrow. This is called a conditional transition because the transition depends on the state of in1. The other possibility from the start state is a no-change transition, with both outputs at 0, if in1 1. This is shown as 1/00. If the machine is in the state named continue, the notation X/01 indicates that the machine makes a transition back to the start state, regardless of the value of in1, and that out1 0 and out2 1 upon this transition. Since the transition always happens, it is called an unconditional transition. What does this state machine do? We can determine its function by analyzing the state diagram, as follows. 1. There are two states, called start and continue. The machine begins in the start state and waits for a LOW input on in1. As long as in1 is HIGH, the machine waits and the outputs out1 and out2 are both LOW. 2. When in1 goes LOW, the machine makes a transition to continue in one clock pulse. Output out1 goes HIGH. 3. On the next clock pulse, the machine goes back to start. The output out2 goes HIGH and out1 goes back LOW. 4. If in1 is HIGH, the machine waits for a new LOW on in1. Both outputs are LOW again. If in1 is LOW, the cycle repeats. In summary, the machine waits for a LOW input on in1, then generates a pulse of one clock cycle duration on out1, then on out2. A timing diagram describing this operation is shown in Figure 10.9. CLK in1 out1 out2 start start continue FIGURE 10.9 Ideal Operation of State Machine in Figure 10.8 Classical Design of State Machines with Control Inputs We can use the classical design technique of the previous section to design a circuit that implements the state diagram of Figure 10.8. 1. Dene the problem. Implement a digital circuit that generates a pulse on each of two outputs, as described above. For this implementation, let us use JK ip-ops for the state logic. If we so chose, we could also use D or T ip-ops. 2. Draw a state diagram. The state diagram is shown in Figure 10.8. 468 C H A P T E R 1 0 State Machine Design Table 10.3 State Table for State Diagram in Figure 10.8 Present State JK 00 01 10 11 0X 1X X1 X0 Sync. Inputs in1 Q JK out1 out2 0 0 1 1 Transition Next State Q Table 10.4 JK Flip-Flop Excitation Table Input 0 1 0 1 1 0 0 0 1X 0X X1 X1 1 0 0 0 0 0 1 1 Outputs 3. Make a state table. The state table is shown in Table 10.3. The combination of present state and input are listed in binary order, thus making Table 10.3 into a truth table for the next state and output functions. Since there are two states, we require one state variable, Q. The next state of Q, a function of the present state and the input in1, is determined by examining the state diagram. (Thus, if you are in state 0, the next state is 1 if in1 0 and 0 if in1 1. If you are in state 1, the next state is always 0.) 4. Use ip-op excitation tables to determine at what states the ip-op synchronous inputs must be to make the circuit go from each present state to its next state. Table 10.4 shows the ip-op excitation table for a JK ip-op. The synchronous inputs are derived from the present-to-next state transitions in Table 10.4 and entered into Table 10.3. (Refer to the synchronous counter design process in Chapter 9 for more detail about using ip-op excitation tables.) 5. Write the output values for each present state/input combination. These can be determined from the state diagram and are entered in the last two columns of Table 10.3. 6. Simplify the Boolean expression for each output and synchronous input. The following equations represent the next state and output logic of the state machine: J K out1 out2 Q in1 1 Q in1 Q in1 Q in1 in1 Q in1 Q 7. Use the Boolean expressions found in step 6 to draw the required logic circuit. state_x2a.gdf state_x2a.scf Figure 10.10 shows the circuit of the state machine drawn as a MAX PLUS II Graphic Design File. Since out1 is a function of the control section and the memory section of the machine, we can categorize the circuit as a Mealy machine. (All counter circuits that we have previously examined have been Moore machines since their outputs are derived solely from the ip-op outputs of the circuit.) Since the circuit is a Mealy machine, it is vulnerable to asynchronous changes of output due to asynchronous input changes. This is shown in the simulation waveforms of Figure 10.11. JKFF NOT in1 clk INPUT J PRN OUTPUT Q out2 INPUT K VCC CLRN BAND2 OUTPUT FIGURE 10.10 Implementation of State Machine of Figure 10.8 out1 10.3 State Machines with Control Inputs 469 FIGURE 10.11 Simulation of State Machine Circuit of Figure 10.10 Ideally, out1 should not change until the rst positive clock edge after in1 goes LOW. However, since out1 is derived from a combinational output, it will change as soon as in1 goes LOW, after allowing for a short propagation delay. Also, since out2 is derived directly from a ip-op and out1 is derived from the same ip-op via a gate, out1 stays HIGH for a short time after out2 goes HIGH. (The extra time represents the propagation delay of the gate.) If output synchronization is a problem (and it may not be), it can be xed by adding a synchronizing D ip-op to each output, as shown in Figure 10.12. DFF JKFF NOT INPUT in1 J PRN D Q PRN Q OUTPUT out2 VCC K CLRN CLRN DFF BAND2 D PRN Q OUTPUT out1 INPUT clk CLRN FIGURE 10.12 State Machine with Synchronous Outputs state_x3a.gdf state_x3a.scf The state variable is stored as the state of the JK ip-op. This state is clocked through a D ip-op to generate out2 and combined with in1 to generate out1 via another ip-op. The simulation for this circuit, shown in Figure 10.13, indicates that the two outputs are synchronous with the clock, but delayed by one clock cycle after the state change. VHDL Implementation of State Machines with Control Inputs The VHDL code for a state machine with one or more control inputs is similar to that for a machine with no control inputs. The machine states are still dened using a CASE statement, but a case representing a conditional transition will contain an IF statement. 470 C H A P T E R 1 0 State Machine Design FIGURE 10.13 Simulation of the State Machine of Figure 10.12 The VHDL code for the state machine implemented above is as follows. ------ state_x1.vhd state machine example 1 Two states, one input, two outputs Generates a pulse on one output, then the next after receiving a LOW on the input LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY state_x1 IS PORT( clk, in1 : IN out1, out2 : OUT END state_x1; state_x1.vhd state_x1.scf STD_LOGIC; STD_LOGIC); ARCHITECTURE a OF state_x1 IS TYPE PULSER IS (start, continue); SIGNAL sequence: PULSER; BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk = 1 THEN CASE sequence IS WHEN start => IF in1 = 1 THEN sequence <= start; -- no change if in1 1 out1 <= 0; out2 <= 0; ELSE sequence <= continue; -- proceed if in1 0 out1 <= 1; -- pulse on out1 out2 <= 0; END IF; WHEN continue => sequence <= start; out1 <= 0; out2 <= 1; -- pulse on out2 END CASE; END IF; END PROCESS; END a; 10.3 State Machines with Control Inputs 471 The transition from start is conditional, so the case for start contains an IF statement that denes the possible state transitions and their associated output states. The transition from continue is unconditional, so no IF statement is needed in the corresponding case. Figure 10.14 shows the simulation for the VHDL design entity, state_x1.vhd. The values of the state variable, sequence, are also shown in the simulation. This gives us a ready indication of the machines state (start or continue). FIGURE 10.14 Simulation of the State Machine in VHDL Entity state_x1 The design of the state machine is such that if the input in1 is held LOW beyond the end of one pulse cycle, the cycle will repeat, as shown in the simulation of Figure 10.15. FIGURE 10.15 Simulation of VHDL State Machine Showing a Repeated Output Cycle EXAMPLE 10.1 Application A state machine called a single-pulse generator operates as follows: 1. The circuit has two states: seek and nd, an input called sync and an output called pulse. 2. The state machine resets to the state seek. If sync 1, the machine remains in seek and the output, pulse, remains LOW. 3. When sync 0, the machine makes a transition to nd. In this transition, pulse goes HIGH. 4. When the machine is in state nd and sync 0, the machine remains in nd and pulse goes LOW. 5. When the machine is in nd and sync 1, the machine goes back to seek and pulse remains LOW. Use classical state machine design techniques to design the circuit for the single-pulse generator, using D ip-ops for the state logic. Use MAX PLUS II to draw the state 472 C H A P T E R 1 0 State Machine Design machine circuit. Create a simulation to verify the design operation. Briey describe what this state machine does. Solution Figure 10.16 shows the state diagram derived from the description of the state machine. The state table is shown in Table 10.5. Since Q follows D, the D input is the same as the next state of Q. FIGURE 10.16 Example 10.1 State Diagram for a Single-pulse Generator 1/0 sync/pulse seek 0 0/1 1/0 find 1 0/0 Table 10.5 State Table for Single-Pulse Generator Present State Input Next State Sync. Input Output Q sync Q D pulse 0 0 1 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0 The next-state and output equations are: D pulse pulse1.gdf pulse1.scf Q sync Q sync Q sync sync Figure 10.17 shows the state machine circuit derived from the above Boolean equations. The simulation for this circuit is shown in Figure 10.18. The simulation shows that the circuit generates one pulse when the input sync goes LOW, regardless of the length of time that sync is LOW. The circuit could be used in conjunction with a debounced pushbutton to produce exactly one pulse, regardless of how long the pushbutton was held down. Figure 10.19 shows such a circuit. DFF NOT SYNC CLK INPUT D AND2 PRN NOT Q INPUT CLRN FIGURE 10.17 Example 10.1 Single-pulse Generator OUTPUT PULSE 10.3 State Machines with Control Inputs 473 FIGURE 10.18 Example 10.1 Simulation of a Single-pulse Generator (from GDF) Vcc Single-pulse generator Debouncer N.O. SYNC PULSE CLK FIGURE 10.19 Example 10.1 Single-pulse Generator Used with a Debounced Pushbutton EXAMPLE 10.2 The state machine of Example 10.1 is vulnerable to asynchronous input changes. How do we know this from the circuit schematic and from the simulation waveform? Modify the circuit to eliminate the asynchronous behavior and show the effect of the change on a simulation of the design. How does this change improve the design? Solution The output, pulse, in the state machine of Figure 10.17 is derived from the state ip-op and the combinational logic of the circuit. The output can be affected by a change that is purely combinational, thus making the output asynchronous. This is demonstrated on the rst pulse of the simulation in Figure 10.18, where pulse momentarily goes HIGH between clock edges. Since no clock edge was present when either the input, sync, changed or when pulse changed, the output pulse must be due entirely to changes in the combinational part of the circuit. The circuit output can be synchronized to the clock by adding an output ip-op, as in Figure 10.20. A simulation of this circuit is shown in Figure 10.21. With the synchronized output, the output pulse is always the same width: one clock period. This gives a more predictable operation of the circuit. DFF DFF NOT SYNC INPUT D AND2 PRN NOT Q CLRN CLK INPUT FIGURE 10.20 Example 10.2 Single-pulse Generator with Synchronous Output D PRN Q CLRN OUTPUT PULSE 474 C H A P T E R 1 0 State Machine Design pulse1a.gdf pulse1a.scf FIGURE 10.21 Example 10.2 Simulation of a Single-pulse Generator with Synchronous Output (from GDF) EXAMPLE 10.3 Write the VHDL code for a design entity that implements the single-pulse generator, as described in Example 10.1. Create a simulation that veries the operation of the design. Solution The required VHDL code is given here in the design entity sngl_pls. LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY sngl_pls IS PORT( clk, sync : IN STD_LOGIC; pulse : OUT STD_LOGIC); END sngl_pls; sngl_pls.vhd sngl_pls.scf ARCHITECTURE pulser OF sngl_pls IS TYPE PULSE_STATE IS (seek, nd); SIGNAL status: PULSE_STATE; BEGIN PROCESS (clk, sync) BEGIN IF (clkEVENT and clk = 1) THEN CASE status IS WHEN seek => IF (sync = 1) THEN status <= seek; pulse <= 0; ELSE status <= nd; pulse <= 1; END IF; WHEN nd => IF (sync = 1) THEN status <= seek; pulse <= 0; ELSE status <= nd; pulse <= 0; END IF; END CASE; END IF; END PROCESS; END pulser; 10.4 Switch Debouncer for a Normally Open Pushbutton Switch 475 FIGURE 10.22 Example 10.3 Simulation of a Single-pulse Generator (VHDL) The simulation of the VHDL design entity sngl_pls is shown in Figure 10.22 SECTION 10.3 REVIEW PROBLEM 10.3 Briey explain why the single-pulse circuit in Figure 10.20 has a ip-op on its output. 10.4 Switch Debouncer for a Normally Open Pushbutton Switch www.electronictech.com KEY TERMS Form A contact A normally open contact on a switch or relay. Form B contact A normally closed contact on a switch or relay. Form C contact A pair of contacts, one normally open and one normally closed, that operate with a single action of a switch or relay. A useful interface function is implemented by a digital circuit that removes the mechanical bounce from a pushbutton switch. The easiest way to debounce a pushbutton switch is with a NAND latch, as shown in Figure 10.23. Vcc S Q Vcc R Q FIGURE 10.23 NAND Latch as a Switch Debouncer The latch eliminates switch bounce by setting or resetting on the rst bounce of a switch contact and ignoring further bounces. The limitation of this circuit is that the input switch must have Form C contacts. That is, the switch has normally open, normally closed, and common contacts. This is so that the switch resets the latch when pressed (i.e., 476 C H A P T E R 1 0 State Machine Design when the normally open contact closes) and sets the latch when released (normally closed contact recloses). Each switch position activates an opposite latch function. If the only available switch has a single set of contacts, such as the normally open (Form A) pushbuttons on the Altera UP-1 Education Board, a different debouncer circuit must be used. We will look at two solutions using VHDL: one based on an existing device (the Motorola MC14490 Contact Bounce Eliminator) and another that implements a state machine solution to the contact bounce problem. Switch Debouncer Based on a 4-bit Shift Register The circuit in Figure 10.24 is based on the same principle as the Motorola MC14490 Contact Bounce Eliminator, adapted for use in an Altera CPLD, such as the EPM7128S or the EPF10K20 on the Altera UP-1 Education Board. Vcc PBIN External pushbutton Clock divider CTR DIV 216 System clock (25.175 MHZ) CLOCK Load Shift in Q15 D0 D1 SGR4 D2 D3 Shift out PBOUT CLOCK FIGURE 10.24 Switch Debouncer Based on a 4-bit Shift Register The heart of the debouncer circuit in Figure 10.24 is a 2-bit comparator (an Exclusive NOR gate) and a 4-bit serial shift register, with active-HIGH synchronous LOAD. The XNOR gate compares the shift register serial input and output. When the shift register input and output are different, the input data are serially shifted through the register. When input and output of the shift register are the same, the binary value at the serial output is parallel-loaded back into all bits of the shift register. Figure 10.25 shows the timing of the debouncer circuit with switch bounces on both make and break phases of the switch contact. The line labeled 4-bit delay refers to the shift register ip-op outputs. Pushbutton input is pb_in, debounced output is pb_out and clk is the UP-1 system clock, divided by 216. (Time values in Figure 10.25 are not to scale and should be disregarded.) FIGURE 10.25 Simulation of the Shift Register-Based Debouncer 10.4 Switch Debouncer for a Normally Open Pushbutton Switch 477 Assume the shift register is initially lled with 0s. The pushbutton rest state is HIGH. As shown in Figure 10.24, the pushbutton input value is inverted and applied to the shift register input. Therefore, before the switch is pressed, both input and output of the shift register are LOW. Since they are the same, the XNOR output is HIGH, which keeps the shift register in LOAD mode and the LOW at pb_out is reloaded to the register on every positive clock edge. When the switch is pressed, it will bounce, as shown above the second, third, and fourth clock pulses on Figure 10.25. Just before the second clock pulse, pb_in is LOW. This makes the shift register input and output different, so a 1 is shifted in. (Recall that pb_in is at the opposite logic level to the shift register input.) On the next clock pulse, pb_in has bounced HIGH again. The shift register input and output are now the same, so the output value, 0, is loaded in parallel to all ip-ops of the shift register. On the fth pulse, pb_in is stable at logic LOW. Since the shift register input is now HIGH and the output is LOW, the HIGH is shifted through the register. We see this by 4-bit delay increasing in value: 0, 1, 3, 7, F, which in binary is equivalent to 0000, 0001, 0011, 0111, 1111. At this point, the input and output are now the same and the output value, 1, is parallel-loaded into the register on each clock pulse. A similar process occurs when the waveform goes back to the HIGH state. When the input goes HIGH, a LOW is shifted into the shift register. If the input bounces back LOW, the shift register is parallel-loaded with HIGHs and the process starts over. When pb_in is stable at a HIGH level, a LOW is shifted through the register, resulting in the hexadecimal sequence F, E, C, 8, 0, which is equivalent to the binary values 1111, 1110, 1100, 1000, 0000. To produce an output change, the shift register input and output must remain different for at least four clock pulses. This implies that the input is stable for that period of time. If the input and output are the same, this could mean one of two things. Either the input is stable and the shift register ip-ops should be kept at a constant state or the input has bounced back to its previous level and the shift register should be reinitialized. In either case, the output value should be parallel loaded back into the shift register. Serial shifting should only occur if there has been an input change. The debouncer in Figure 10.24 is effective for removing bounce that lasts for no more than 4 clock periods. Since switch bounce is typically about 10 ms in duration, the clock should have a period of about 2.5 ms. At 25.175 MHz (a clock period of about 40 ns), the Altera UP-1 system clock is much too fast. If we divide the oscillator frequency by 65536 ( 216) using a 16-bit counter, we obtain a clock waveform for the debouncer with a period of 2.6 ms. Four clock periods (10.2 ms) are sufcient to take care of switch bounce. We can use VHDL to synthesize the switch debouncer by instantiating a counter and shift register from the Altera Library of Parameterized Modules and connecting them together with internal signals. The VHDL code is as follows. debounce.vhd debounce.scf ----- debounce.vhd Switch Debouncer for a Form A contact, based on a 4-bit shift register. Function is similar to a Motorola MC14490 Contact Bounce Eliminator. -- Use modules from Library of Parameterized Modules (LPM): -LPM_SHIFTREG (Shift Register) -LPM_COUNTER (16-bit counter) LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL; 478 C H A P T E R 1 0 State Machine Design ENTITY debounce IS PORT( clk : IN STD_LOGIC; pb_in : IN STD_LOGIC; pb_out : OUT STD_LOGIC); END debounce; ARCHITECTURE debouncer OF debounce IS -- Internal signals required to interconnect counter and shift register SIGNAL srg_ser_out, srg_ser_in, srg_clk, srg_load : STD_LOGIC; SIGNAL srg_data : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ctr_q : STD_LOGIC_VECTOR (15 DOWNTO 0); BEGIN -- Instantiate 16-bit counter clock_divider: lpm_counter GENERIC MAP (LPM_WIDTH => 16) PORT MAP (clock => clk, q => ctr_q(15 DOWNTO 0)); -- Instantiate 4-bit shift register four_bit_delay: lpm_shiftreg GENERIC MAP (LPM_WIDTH => 4) PORT MAP (shiftin => srg_ser_in, clock => srg_clk, load => srg_load, data => srg_data(3 downto 0), shiftout => srg_ser_out); -- Shift register is clocked by counter output -- (divides system clock by 216) srg_clk <= ctr_q(15); -- Undebounced pushbutton input to shift register srg_ser_in <= not pb_in; ----- Shift register is parallel-loaded with output data if shift register input and output are the same. If input and output are different, data are serial-shifted. srg_data(3) <= srg_ser_out; srg_data(2) <= srg_ser_out; srg_data(1) <= srg_ser_out; srg_data(0) <= srg_ser_out; pb_out <= srg_ser_out; srg_load <= not((not pb_in) xor srg_ser_out); END debouncer; Figure 10.26 shows a fairly easy way to test the switch debouncer. The debouncer output is used to clock an 8-bit counter whose outputs are decoded by two seven-segment decoders. (The decoders are VHDL les developed in a similar way to the seven-segment decoders in Chapter 5.) Pin numbers are given for the EPM7128S CPLD on the Altera UP-1 circuit board. Since the clock and seven segment displays are hardwired on the Altera board, the only external connections required for the circuit are wires for the two pushbutton inputs, reset and pb_in. 479 INPUT VCC reset reset clk pb_in INPUT VCC pb_in pb_out Q[7..0] COUNT_8 clk clock FIGURE 10.26 Test Circuit for a Switch Debouncer 2digit_1@52 2digit_1@51 2digit_1@83 INPUT VCC DEBOUNCE q[7..0] d2 d1 d0 q6 q5 q4 g f e d c b d3 d2 d1 d0 q2 q1 q0 g f e d c b a SEV_SEGV q3 d3 q7 a SEV_SEGV VCC OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT g2 f2 e2 d2 c2 b2 a2 g1 f1 e1 d1 c1 b1 a1 dp2 dp1 2digit_1@77 2digit_1@75 2digit_1@76 2digit_1@74 2digit_1@73 2digit_1@70 2digit_1@69 2digit_1@67 2digit_1@65 2digit_1@64 2digit_1@63 2digit_1@61 2digit_1@60 2digit_1@58 2digit_1@79 2digit_1@68 480 C H A P T E R 1 0 State Machine Design 2digit.gdf count_8.vhd sev_segv.vhd If the debouncer is working properly, the seven-segment display should advance by one each time pb_in is pressed. If the debouncer is not working, the display will change by an unpredictable number with each switch press. The component source les for the debouncer and test circuit components are supplied on the CD accompanying this book in the folder drive:\Student Files\Chapter 10\. To use these les, create a symbol for each one (File menu; Project; Set Project to Current File; then File menu; Create Default Symbol) and draw the Graphic Design File of Figure 10.26. Alternatively, you can instantiate each le as a component in a VHDL design entity (all components are designed in VHDL) and connect them together with internal signals. Behaviorally Designed Switch Debouncer We can also design a switch debouncer by using a behavioral state machine description in VHDL. In order to do so, we need to dene the operation of the circuit with a state diagram, as in Figure 10.27. FIGURE 10.27 State Diagram for a Behaviorally Designed Switch Debouncer pb-in, pb-out/pb-out 01/1 10/0 s0 00 00/0 11/1 01/1 10/0 s1 01 00/0 11/1 01/1 10/0 s2 02 00/0 11/1 01/1 10/0 00/1 11/0 s3 03 Transitions between states are determined by comparing pb_in and pb_out. If they are the same (00 or 11), the machine advances to the next state; if they are different (01 or 10), the machine reverts to the initial state, s0. At any point in the state diagram (including state s3, the last state), the machine will reset if pb_in and pb_out are different, indicating a bounce on the input. If pb_in and pb_out are the same for four clock pulses, the input is deemed to be stable. Only at this point will the output change to its opposite state. NOTE In the shift registerbased debouncer, the circuit advanced to the next state if the shift register input and output were different and reset if they were the same. This might appear to be opposite to our behavioral description, but it is not if you look carefully. The shift register debouncer circuit inverts pb_in before applying the signal to the serial input of the shift register. Therefore, viewed from the circuit input and output terminals, rather than at the shift register input and output, the description is the same in both cases. 10.4 Switch Debouncer for a Normally Open Pushbutton Switch 481 The VHDL code corresponding to the behavioral description of the switch debouncer is given next. The only output change is specied on the transition from state s3 to s0 when pb_in pb_out. Since no change is allowed at any other time, no other output state needs to be specied. -- dbc_behv.vhd -- Behavioral denition of a switch debouncer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY dbc_behv IS PORT( clk, pb_in : IN STD_LOGIC; pb_out : BUFFER STD_LOGIC); END dbc_behv; dbc_behv.vhd dbc_behv.scf ARCHITECTURE debounce of dbc_behv IS TYPE sequence IS (s0, s1, s2, s3); SIGNAL state: sequence; BEGIN PROCESS (clk, pb_in) BEGIN IF (clkEVENT and clk=1) THEN CASE state IS WHEN s0=> IF (pb_in = pb_out) THEN state <= s1; ELSE state <= s0; END IF; WHEN s1=> IF (pb_in = pb_out) THEN state <= s2; ELSE state <= s0; END IF; WHEN S2=> IF (pb_in = pb_out) THEN state <= s3; ELSE state <= s0; END IF; WHEN s3=> IF (pb_in = pb_out) THEN state <= s0; pb_out <= not pb_out; ELSE state <= s0; END IF; WHEN others => state <= s0; END CASE; END IF; END PROCESS; END debounce; Figure 10.28 shows a simulation of the behaviorally-designed switch debouncer. State s1 through s3 are of too short a duration to show properly on the simulation, so further details of the simulation are shown in Figures 10.29 and 10.30. 482 C H A P T E R 1 0 State Machine Design FIGURE 10.28 Simulation of a Behaviorally Designed Switch Debouncer FIGURE 10.29 Simulation Detail (Behaviorally Designed Switch Debouncer) FIGURE 10.30 Simulation Detail (Behaviorally Designed Switch Debouncer) Note that the behaviorally designed switch debouncer does not have a built-in clock divider. If we were to use the circuit on the Altera UP-1 board, we would need to include a divide-by-216 counter to the circuit, as shown in Figure 10.31. SECTION 10.4 REVIEW PROBLEM 10.4 What is the fastest acceptable clock rate for the shift register portion of the debouncer in Figure 10.24 if the pushbutton switch bounces for 15ms? 483 INPUT VCC INPUT VCC pb_in reset clkdiv15 INPUT VCC pb_out Q[7..0] COUNT_8 reset clk Q[15..0] DBC_BEHV pb_in clk clk FIGURE 10.31 Using a Behaviorally Designed Debouncer with a 16-bit Clock Divider 2digit@52 2digit@51 2digit@83 clock COUNT_16 q[7..0] clkdiv[15..0] d2 d1 d0 q6 q5 q4 g f e d c b d3 d2 d1 d0 q2 q1 q0 g f e d c b a SEV_SEGV q3 d3 q7 a SEV_SEGV VCC OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT g2 f2 e2 d2 c2 b2 a2 g1 f1 e1 d1 c1 b1 a1 dp2 dp1 2digit@77 2digit@75 2digit@76 2digit@74 2digit@73 2digit@70 2digit@69 2digit@67 2digit@65 2digit@64 2digit@63 2digit@61 2digit@60 2digit@58 2digit@79 2digit@68 484 C H A P T E R 1 0 State Machine Design 0/00 X /01 in1/out1, out2 start 000 1/00 pulse2 100 wait1 001 X /10 1/00 0/00 wait2 010 pulse1 011 1/00 0/00 FIGURE 10.32 State Diagram for a Two-pulse Generator 10.5 Unused States in State Machines In our study of counter circuits in Chapter 9, we found that when a counter modulus is not equal to a power of two there were unused states in the counters sequence. For example, a mod-10 counter has six unused states, as the counter requires four bits to express ten states and the maximum number of 4-bit states is sixteen. The unused states (1010, 1011, 1100, 1101, 1110, and 1111) have to be accounted for in the design of a mod-10 counter. The same is true of state machines whose number of states does not equal a power of two. For instance, a machine with ve states requires three state variables. There are up to eight states available in a machine with three state variables, leaving three unused states. Figure 10.32 shows the state diagram of such a machine. Unused states can be dealt with in two ways: they can be treated as dont care states, or they can be assigned specic destinations in the state diagram. In the latter case, the safest destination is the rst state, in this case the state called start. EXAMPLE 10.4 Redraw the state diagram of Figure 10.32 to include the unused states of the machines state variables. Set the unused states to have a destination state of start. Briey describe the intended operation of the state machine. Solution Figure 10.33 shows the revised state diagram. The machine begins in state start and waits for a HIGH on in1. The machine then makes a transition to wait1 and stays there until in1 goes LOW again. The machine goes to wait2 and stays there until in1 goes HIGH and then makes an unconditional transition to pulse1 on the next clock pulse. Until this point, there is no change in either output. The machine makes an unconditional transition to pulse2 and makes out1 go HIGH. The next transition, also unconditional, is to start, when out1 goes LOW and out2 goes HIGH. If in1 is LOW, the machine stays in start. Otherwise, the cycle continues as above. In either case, out2 goes LOW again. 10.5 FIGURE 10.33 Example 10.4 State Diagram for Two-pulse Generator Showing Unused States unused3 X /00 111 unused2 110 unused1 101 Unused States in State Machines 0/00 X /00 in1/out1, out2 start 000 X /00 485 1/00 X /01 pulse2 100 wait1 001 X /10 1/00 0/00 wait2 010 pulse1 011 1/00 0/00 Thus the machine waits for a HIGH-LOW-HIGH input sequence and generates a pulse sequence on two outputs. EXAMPLE 10.5 Use classical state machine design techniques to implement the state machine described in the modied state diagram of Figure 10.33. Draw the state machine as a Graphic Design File in Max PLUS II and create a simulation to verify its function. Solution Table 10.6 shows the state table of the state machine represented by Figure 10.33. Table 10.6 State Table for State Machine of Figure 10.33 Present State Input Next State Q2Q1Q0 in1 Q2Q1Q0 out1 out2 000 000 001 001 0 1 0 1 000 001 010 001 0 0 0 0 0 0 0 0 010 010 011 011 0 1 0 1 010 011 100 100 0 0 1 1 0 0 0 0 100 100 101 101 0 1 0 1 000 000 000 000 0 0 0 0 1 1 0 0 110 110 111 111 0 1 0 1 000 000 000 000 0 0 0 0 0 0 0 0 Outputs 486 C H A P T E R 1 0 State Machine Design Figure 10.34 shows the Karnaugh maps used to simplify the next-state equations for the state variable ip-ops. The output equations can be simplied by inspection. The next-state and output equations for the state machine are: Q0 in1 00 Q2 Q1 01 11 10 00 0 0 0 0 01 0 0 1 11 0 0 10 0 0 Q0 in1 00 Q2 Q1 01 11 10 00 0 0 0 1 1 01 1 1 0 0 0 11 0 0 0 0 10 0 0 D2 Q0 in1 00 Q2 Q1 01 11 10 00 0 1 1 0 0 01 0 1 0 0 0 0 11 0 0 0 0 0 0 10 0 0 0 0 D1 D0 FIGURE 10.34 Example 10.5 K-Maps for Two-pulse Generator D2 Q2Q1Q0 D1 Q2Q1Q0 Q2Q1Q0in1 D0 Q2Q0in1 Q2Q1in1 out1 Q2Q1Q0 out2 Q2Q1Q0 Figure 10.35 shows the Graphic Design File schematic for the state machine. Figure 10.36 shows the MAX PLUS II simulation waveforms. We can monitor the state variables in the MAX PLUS II simulation le by adding a group of waveforms for the buried nodes q2, q1, and q0. These are shown on the simulation as q[2..0].Q, meaning the Q outputs of the ip-ops named q2, q1, q0. To add the buried nodes, select Enter Node from SNF from the Node menu in the simulator window. In the dialog box shown in Figure 10.37, check the box that says All, and click on List. Select the nodes q2.Q, q1.Q, and q0.Q from the Available Nodes and Groups and transfer them to the Selected Nodes and Groups. ClickOK. Select the three new waveforms and from the Node menu, select Group. Click OK in the resulting dialog box. 487 INPUT INPUT FIGURE 10.35 Example 10.5 Two-pulse Generator clk in1 D D d0 D DFF d1 DFF d2 DFF Q Q Q CLRN PRN CLRN PRN CLRN PRN q0 q1 q2 q2 q1 q0 NOT NOT NOT NOT AND3 AND3 AND3 AND3 AND4 AND3 AND3 d2 OUTPUT OUTPUT OR2 OR2 out2 out1 d0 d1 488 C H A P T E R 1 0 State Machine Design FIGURE 10.36 Example 10.5 Simulation of a Two-pulse Generator (GDF) FIGURE 10.37 Adding Buried Nodes to a Simulation EXAMPLE 10.6 Write the VHDL code required to implement the two-pulse generator described in Examples 10.4 and 10.5. Create a MAX PLUS II simulation to verify the operation of the design. Based on your examination of the simulations for the VHDL design and the GDF design of the previous example, how do the two designs differ in their operation? What is the reason for the difference? Solution The VHDL code for the state machine in design entity two_pulse.vhd follows. The unused states are accounted for in the others clause. -- two_pulse.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY two_pulse IS PORT( clk, in1 : IN output : OUT END two_pulse; STD_LOGIC; STD_LOGIC_VECTOR (1 to 2)); ARCHITECTURE a OF two_pulse IS TYPE SEQUENCE IS (start, wait1, wait2, pulse1, pulse2); SIGNAL pulse_state : SEQUENCE; BEGIN PROCESS(clk) BEGIN IF (clkEVENT and clk = 1) THEN CASE pulse_state IS 10.6 two_pulse.vhd two_pulse.scf two_pulse.rpt Unused States in State Machines 489 WHEN start => IF in1 = 0 THEN pulse_state <= start; output <= 00; ELSIF in1 = 1 THEN pulse_state <= wait1; output <= 00; END IF; WHEN wait1 => IF in1 0 THEN pulse_state <= wait2; output <= 00; ELSIF in1 = 1 THEN pulse_state <= wait1; output <= 00; END IF; WHEN wait2 => IF in1 = 0 THEN pulse_state <= wait2; output <= 00; ELSIF in1 = 1 THEN pulse_state <= pulse1; output <= 00; END IF; WHEN pulse1 => pulse_state <= pulse2; output <= 10; WHEN pulse2 => pulse_state <= start; output <= 01; WHEN others => pulse_state <= start; output <= 00; END CASE; END IF; END PROCESS; END a; Figure 10.38 shows the MAX PLUS II simulation of the state machine. If you closely examine the simulation waveforms in Figures 10.36 and 10.38, you will note that the pulse outputs in Figure 10.38 (VHDL design) occur one clock cycle later than they do in Figure 10.36 (graphical design). This is because the VHDL compiler has synthesized each output with a D ip-op, as we did for the single-pulse circuit in Figure FIGURE 10.38 Example 10.6 Simulation of a Two-pulse Generator (VHDL) 490 C H A P T E R 1 0 State Machine Design 10.20, in order to ensure synchronous output operation.(We can verify this by examining the EQUATIONS section of the project report le, two_pulse.rpt.) Since the outputs are both derived entirely from ip-op outputs, this synthesis step is not strictly necessary to ensure that the outputs are synchronous with the clock. SECTION 10.5 REVIEW PROBLEM 10.5 Is the state machine designed in Example 10.5 a Moore machine or a Mealy machine? Why? 10.6 Trafc Light Controller A simple trafc light controller can be implemented by a state machine with a state diagram such as the one shown in Figure 10.39. 0/ 011110 X/ 011110 s0 00 1/ 011101 s3 11 TIMER/ nsr,nsy,nsg, ewr,ewy,ewg s1 01 1/ 101011 X/ 110011 s2 10 Q/ 110011 FIGURE 10.39 State Diagram of a Trafc Light Controller The control scheme assumes control over a north-south road and an east-west road. The north-south lights are controlled by outputs called nsr, nsy, and nsg (north-south red, yellow, green). The east-west road is controlled by similar outputs called ewr, ewy, and ewg. A LOW controller output turns on a light. Thus an output 011110 corresponds to the north-south red and east-west green lights. An input called TIMER controls the length of the two green-light cycles. When TIMER 1, a transition from s0 to s1 or from s2 to s3 is possible (s0 represents the EW green; s2 the NS green). This transition accompanies a change from green to yellow on the active road. The light on the other road stays red. An unconditional transition follows, changing the yellow light to red on one road and the red light to green on the other. The cycle can be set to any length by changing the signal on the TIMER input. (The yellow light will always be on for one clock pulse in this design.) For ease of observation, we will use a cycle of ten clock pulses. For either direction, the cycle consists of 4 clocks GREEN, 1 clock YELLOW, 5 clocks RED. This cycle can be generated by the MSB of a mod-5 counter, as shown in Figure 10.40. If we model the trafc controller using the Altera UP-1 board, we require a clock divider to slow down the 25.175 MHz clock to a rate of about 0.75 Hz, making it easy to observe the changes of lights. These blocks can all be instantiated in VHDL, which will be left as part of an exercise in the lab manual accompanying this book. CTR DIV 5 FIGURE 10.40 Trafc Control Demonstration Circuit for the Altera UP-1 Board CTR DIV 2 25 Cycle timer* Q0 Clock divider Q24 CLOCK CLOCK RESET CLOCK RESET Q1 Q2 Output controller NSR TIMER NSY NSG North-south lights EWR RESET CLOCK RESET EWY EWG *Cycle: Red for 5 clocks Green for 4 clocks Yellow for 1 clock East-west lights Trafc Light Controller 491 Figure 10.41 shows the simulation of the mod-5 counter that generates the TIMER control signal. The MSB goes HIGH for one clock period, then LOW for four. When applied to the TIMER input of the output controller, this signal directs the controller from state to state. FIGURE 10.41 Simulation of a Mod-5 Counter Figure 10.42 shows a simulation of the mod-5 counter and output controller. The north-south lights are red for ve clock pulses (shown by 011 in the north_south waveform). At the same time, the east-west lights are green for four clock pulses (east_west 110), followed by yellow for one clock pulse (east_west 101). The cycle continues with an east-west red and north-south green and yellow. According to the state diagram, the yellow light should happen on the transition where TIMER 1. This corresponds to the point on the simulation waveforms where count 4. FIGURE 10.42 Simulation of a Trafc Light Controller 492 C H A P T E R 1 0 State Machine Design However, the yellow light does not come on until count 0. This is because the MAX PLUS II VHDL compiler synthesizes the controller outputs with synchronous outputs (ip-ops). As a result, the output states are delayed by one clock cycle. Since the relative lengths of the cycle proportions are preserved, this does not affect the operation of the controller. SUMMARY 1. 2. 3. 4. 5. 6. A state machine is a synchronous sequential circuit with a memory section (ip-ops) to hold the present state of the machine and a control section (gates) to determine the machines next state. The number of ip-ops in a state machines memory section is the same as the number of state variables. Two main types of state machine are the Moore machine and the Mealy machine. The outputs of a Moore machine are entirely dependent on the states of the machines ip-ops. Output changes will always be synchronous with the system clock. The outputs of a Mealy machine depend on the states of the machines ip-ops and the gates in the control section. A Mealy machines outputs can change asynchronously, relative to the system clock. A state machine can be designed in a classical fashion using the same method as in designing a synchronous counter, as follows: a. Dene the problem and draw a state diagram. 9. 10. 11. 12. 13. b. Construct a table of present and next states. c. Use ip-op excitation tables to determine the ipop inputs for each state transition. d. Use Boolean algebra or K-maps to nd the simplest Boolean expression for ip-op inputs (D, T, or JK) in terms of outputs (Q). e. Draw the logic diagram of the state machine. 7. 8. The state names in a state machine can be named numerically (s0, s1, s2, . . .) or literally (start, idle, read, write), depending on the machine function. State names are independent of the values of the state variables. A state machine can be dened in VHDL by using a CASE statement within a PROCESS to dene the progression of 14. 15. 16. states. The output values can be dened by a separate decoder construct or they can be assigned within each case of the CASE statement. The possible values of the state variables of a machine are dened within an enumerated type denition. An enumerated type is a list of possible values that a port, variable, or signal of that type is allowed to have. Notation for a state diagram includes a series of bubbles (circles) containing state names and values of state variables in state_name . the form state_variable(s) The inputs and outputs of a state machine are labeled in1, in2, . . . , inx/out1, out2, . . . ,outx. Transitions between states can be conditional or unconditional. A conditional transition happens only under certain conditions of a control input and is labeled with the relevant input condition. An unconditional transition happens under all conditions of input and is labeled with an X for each input variable. Conditional transitions in a VHDL state machine are described by an IF statement within a particular case of the CASE statement that describes the machine. Mealy machine outputs are susceptible to asynchronous output changes if a combinational input changes out of synchronization with the clock. This can be remedied by clocking each output through a separate synchronizing ip-op. A maximum of 2n states can be assigned to a state machine that has n state variables. If the number of states is less than 2n, the unused states must be accounted for. Either they can be treated as dont care states, or they can be assigned a specic destination state, usually the reset state. In a VHDL implementation of a state machine, any unused states can be covered with an others clause in the CASE statement that denes the machine. GLOSSARY Conditional transition A transition between states of a state machine that occurs only under specic conditions of one or more control inputs. Form B contact A normally closed contact on a switch or relay. Control input A state machine input that directs the operation of the machine from state to state. Form C contact A pair of contacts, one normally open and one normally closed, that operate with a single action of a switch or relay. Enumerated type A user-dened type in VHDL in which all possible values of a named identier are listed in a type denition statement. Form A contact A normally open contact on a switch or relay. Mealy machine A state machine whose output is determined by both the sequential logic and the combinational logic of the machine. Problems 493 Moore machine A state machine whose output is determined only by the sequential logic of the machine. State variables The variables held in the ip-ops of a state machine that determine its present state. State machine A synchronous sequential circuit, consisting of a sequential logic section and a combinational logic section, whose outputs and internal ip-ops progress through a predictable sequence of states in response to a clock and other input signals. Unconditional transition A transition between states of a state machine that occurs regardless of the status of any control inputs. PROBLEMS Problem numbers set in color indicate more difcult problems: those with underlines indicate most difcult problems. Section 10.1 State Machines 10.1 10.2 Is the state machine in Figure 10.43 a Moore machine or a Mealy machine? Explain your answer. Is the state machine in Figure 10.44 a Moore machine or a Mealy machine? Explain your answer. INPUT in1 DFF XOR D OUTPUT Q PULSE CLRN INPUT clk AND2 PRN FIGURE 10.43 Problem 10.1 State Machine Circuit DFF DFF XOR in1 INPUT D XOR PRN Q CLRN clk INPUT D PRN Q CLRN OUTPUT OUTPUT FIGURE 10.44 Problem 10.2 State Machine Circuit out1 out0 494 C H A P T E R 1 0 State Machine Design Section 10.2 State Machines with No Control Inputs Section 10.3 State Machines with Control Inputs 10.3 10.7 A 4-bit Gray code sequence is shown in Table 10.7. Use classical design methods to design a counter with this sequence, using D ip-ops. Draw the resulting circuit diagram in a MAX PLUS II Graphic Design File. Create a simulation to verify the circuit operation. Table 10.7 4-bit Gray code sequence Use classical state machine design techniques to nd the Boolean next state and output equations for the state machine represented by the state diagram in Figure 10.45. Draw the state machine circuit as a Graphic Design File in MAX PLUS II. Create a simulation le to verify the operation of the circuit. Briey explain the intended function of the state machine. Q3Q2Q1Q0 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 10.4 Use classical state machine design techniques to design a counter whose output sequence is shown in Table 10.8. (This is a divide-by-twelve counter in which the MSB output has a duty cycle of 50%.) Draw the state diagram, derive synchronous equations of the ip-ops, and draw the circuit implementation in MAX PLUS II and create a simulation to verify the circuits function. Table 10.8 Counter Sequence for Problem 10.4 X /0,0 10.5 Write the VHDL code required to implement a 4-bit Gray code counter. Create a simulation in MAX PLUS II to verify the operation of the circuit. 10.6 Write the VHDL code required to implement a counter with the sequence shown in Table 10.8. Create a simulation in MAX PLUS II to verify the operation of the circuit. in1/out1, out2 s3 11 0/1,0 s0 00 0/0,0 s1 01 X /0,0 s2 10 1/0,1 FIGURE 10.45 Problem 10.7 State Diagram 10.8 Referring to the simulation for the state machine in Problem 10.7, briey explain why it is susceptible to asynchronous input changes. Modify the state machine circuit to eliminate the asynchronous behavior of the outputs. Create a MAX PLUS II simulation to verify the function of the modied state machine. 10.9 Write the VHDL code required to implement the state machine in Problem 10.7. Create a simulation to verify the operation of the state machine. 10.10 A state machine is used to control an analog-to-digital converter, as shown in the block diagram of Figure 10.46. Q3Q2Q1Q0 0000 0001 0010 0011 0100 0101 1000 1001 1010 1011 1100 1101 1/0,0 Controller Analog-to-digital converter sc go reset go reset sc oe oe eoc eoc clk FIGURE 10.46 Problem 10.10 Analog-to-Digital Converter and Controller The controller has four states, dened by state variables Q1 and Q0 as follows: idle (00), start (01), waiting (11), and read (10). There are two outputs: sc (Start Conversion; active-HIGH) and oe (Output Enable; active LOW). There are four inputs: clock, go (active-LOW) eoc (End of Conversion), and asynchronous reset (active LOW). The machine operates as follows: Problems 495 a. In the idle state, the outputs are: sc 0, oe 1. The machine defaults to the idle state when the machine is reset. 10.16 Briey explain how the Exclusive NOR gate in the debounce circuit of Figure 10.24 determines if switch bounce has occurred. b. Upon detecting a 0 at the go input, the machine makes a transition to the start state. In this transition, sc 1, oe 1. 10.17 Refer to the section on the behaviorally designed switch debouncer in Section 10.4. For how many clock periods must the input of the debouncer remain stable before the output can change? What is the maximum switch bounce time that can be removed by the circuit of Figure 10.24. if the state machine clock is running at a rate of 480 Hz? c. The machine makes an unconditional transition to the waiting state; sc 0, oe 1. It remains in this state, with no output change, until input eoc 1. d. When eoc 1, the machine goes to the read state; sc 0, oe 0. in1,in2/out1 e. The machine makes an unconditional transition to the idle state; sc 0, oe 1. Use classical state machine design techniques to design the controller. Draw the required circuit in MAX PLUS II and create a simulation to verify its operation. Is this machine vulnerable to asynchronous input change? X,0/1 Section 10.4 Switch Debouncer for a Normally Open Pushbutton Switch X,X /0 1,X /0 X,1/0 s4 110 s1 001 X,X /0 10.11 Use VHDL to implement the controller circuit of Problem 10.10. Create a simulation to verify its operation. 10.12 Write a VHDL le for a state machine that selects a 3-bit binary or Gray code count, depending on the state of an input called gray. If gray 1, count in Gray code. Otherwise count in binary. Create a simulation le that veries the operation of the circuit, clearly showing the full Gray code count, binary count, and reset function. s0 000 0,X /1 s3 010 s2 011 X,X /0 FIGURE 10.47 Problem 10.18 State Diagram Section 10.5 Unused States in State Machines 10.18 Refer to the state diagram in Figure 10.47. 10.13 Why is it not possible to debounce the pushbuttons on the Altera UP-1 board using a NAND latch? a. How many state variables are required to implement this state machine? Why? 10.14 Refer to the switch debouncer circuit in Figure 10.24 (p. 476). For how many clock periods must the input of the debouncer remain stable before the output can change? b. How many unused states are there for this state machine? List the unused states. 10.15 What is the maximum switch bounce time that can be removed by the circuit of Figure 10.24 if the clock at the shift register is running at a rate of 480 Hz? CLK in1 in2 out1 state s0 s1 FIGURE 10.48 Problem 10.18 Partial Timing Diagram c. Complete the partial timing diagram shown in Figure 10.48 to illustrate one complete cycle of the state machine represented by the state diagram of Figure 10.47. 496 C H A P T E R 1 0 State Machine Design 10.19 Write the VHDL code required to implement the state machine described by the state diagram of Figure 10.47. Create a simulation le to verify the operation of the circuit. 10.20 Use classical state machine design techniques to design a state machine described by the state diagram of Figure 10.49. Briey describe the intended operation of the circuit. Create a MAX PLUS II simulation to verify the operation of the state machine design. Unused states may be treated as dont care states, but unspecied outputs should always be assigned to 0. in1/out1,out2 1/0,0 0/0,0 s0 000 0/1,0 s4 110 s1 001 1/0,0 X /0,1 X/1,1 s3 010 s2 011 10.22 Write the VHDL code for the state machine described in Problem 10.20. Create a MAX PLUS II simulation to verify the function of the state machine. 10.23 A state machine is used to control an analog-to-digital converter, as shown in the block diagram of Figure 10.46. (The following description is a modied version of the controller described in Problem 10.10.) Five states are used: idle, start, waiting1, waiting2, and read. There are two outputs: sc (Start Conversion; active-HIGH) and oe (Output Enable; active HIGH). There are four inputs: clock, reset, go, and eoc (End of Conversion). The machine operates as follows: a. In the idle state, the outputs are: sc 0, oe 0. The machine defaults to the idle state when asynchronously reset and remains there until go 0. b. When go 0, the machine makes a transition to the start state. In this transition, sc 1, oe 0. c. The machine makes an unconditional transition to the waiting1 state; sc 0, oe 0. It remains in this state, with no output change, until input eoc 0. d. When eoc 0, the machine goes to the waiting2 state; sc 0, oe 0. It remains in this state, with no output change, until input eoc 1. e. The machine makes a transition to the read state when eoc 1, sc 0, oe 1. X/0,0 f. The machine makes an unconditional transition to the idle state; sc , 0, oe 0. FIGURE 10.49 Problem 10.20 State Diagram After reviewing the block diagram and the states just listed, 10.21 Determine the next state for each of the unused states of the state machine designed in Problem 10.20. Use this analysis to redraw the state diagram of Figure 10.49 so that it properly includes the unused states. (There is more than one right answer, depending on the result of the Boolean simplication process used in Problem 10.20.) a. Draw the state diagram of the controller. b. How many state variables are required for the controller described in this question? 10.24 Write the VHDL code for the state machine described in Problem 10.23. Create a simulation le to verify the function of the design. ANSWERS TO SECTION REVIEW PROBLEMS Section 10.1 Section 10.3 10.1 A Moore state machine has outputs that depend only on the states of the ip-ops in the machine. A Mealy machines outputs depend on the states of its ip-ops as well as the gates of the machines control section. This can result in asynchronous output changes in the Mealy machine outputs. 10.3 The output ip-op synchronizes the output to the system clock, yielding the following advantages: (1) the output is always a known width of one clock cycle; and (2) the output is not vulnerable to change due to asynchronous changes of input. Section 10.2 10.4 Tc 10.2 J2 K2 J1 K1 J0 K0 Q1Q0 Q1Q0 Q2Q0 Q2Q0 Q2Q1 Q2Q1 Section 10.4 3.75 ms; fc 267 Hz Section 10.5 10.5 Moore machine. The outputs are derived entirely from the output states of the state machine and are not vulnerable to asynchronous changes of input. Q2Q1 Q2Q1 Q2 Q2 Q1 Q1 CHAPTER 11 Logic Gate Circuitry OUTLINE CHAPTER OBJECTIVES 11.1 Electrical Characteristics of Logic Gates 11.2 Propagation Delay 11.3 Fanout 11.4 Power Dissipation 11.5 Noise Margin 11.6 Interfacing TTL and CMOS Gates 11.7 Internal Circuitry of TTL Gates 11.8 Internal Circuitry of CMOS Gates 11.9 TTL and CMOS Variations Upon successful completion of this chapter, you will be able to: Name the various logic families most commonly in use today and state several advantages and disadvantages of each. Dene propagation delay. Calculate propagation delay of simple circuits, using data sheets. Dene fanout and calculate its value, using data sheets. Calculate power dissipation of TTL and CMOS circuits. Calculate noise margin of a logic gate from data sheets. Draw circuits that will interface various CMOS and TTL gates. Explain how a bipolar junction transistor can be used as a logic inverter. Describe the function of a TTL input transistor in all possible input states: HIGH, LOW, and open-circuit. Explain the operation of a totem pole output. Illustrate how a totem pole output generates power line noise and describe how to remedy this problem. Illustrate why totem pole outputs cannot be tied together. Explain the difference between open-collector and totem pole outputs of a TTL gate. Illustrate the operation of TTL open-collector inverter, NAND, and NOR gates. Write the Boolean expression of a wired-AND circuit. Design a circuit that uses an open-collector gate to drive a high-current load. Calculate the value of a pull-up resistor at the output of an open-collector gate. Explain the operation of a tristate gate and name several of its advantages. Design a circuit using a tristate bus driver to direct the ow of data from one device to another. Describe the basic structure of a MOSFET and state its bias voltage requirements. Draw the circuit of an CMOS inverter and show how it works. 497 498 C H A P T E R 1 1 Logic Gate Circuitry Draw the circuits of CMOS NAND and NOR gates and explain the operation of each. Design a circuit using a CMOS transmission gate to enable and inhibit digital and analog signals. Interpret TTL data sheets to distinguish between the various TTL families. Describe the use of the Schottky barrier diode in TTL gates. Calculate speed-power products from data sheets. O ur study of logic gates and ip-ops in previous chapters has concentrated on digital logic and has largely ignored digital electronics. Digital logic devices are electronic circuits with their own characteristic voltages and currents. No serious study of digital circuitry is complete without some examination of this topic. It is particularly important to understand the inputs and outputs of logic devices as electronic circuits. Knowing the input and output voltages and currents of these circuits is essential, since gate loading, power dissipation, noise voltages, and interfacing between logic families depend on them. The switching speed of device outputs is also fundamental and may be a consideration when choosing the logic family for a circuit design. Input and output voltages of logic devices are specied in manufacturers data sheets, which allows us to take a black box approach initially. Later in the chapter, we will examine some basic digital circuits at a transistor level, since digital logic is based on transistor switching. Two major types of transistors, the bipolar junction transistor and the metal-oxide-semiconductor eld effect transistor (MOSFET), form the basis of the major logic families in use today. Transistor-transistor logic (TTL) is based on the bipolar transistor. Complementary MOS (CMOS) is based on the MOSFET. We will briey study the operating characteristics of both bipolar transistors and MOSFETs and then see how these devices give rise to the electrical characteristics of simple logic gates. 11.1 Electrical Characteristics of Logic Gates KEY TERMS TTL Transistor-transistor logic. A logic family based on bipolar transistors. CMOS Complementary metal-oxide semiconductor. A logic family based on metal-oxide-semiconductor eld effect transistors (MOSFETs). ECL Emitter coupled logic. A high-speed logic family based on bipolar transistors. When we examine the electrical characteristics of logic circuits, we see them as practical, rather than ideal devices. We look at properties such as switching speed, power dissipation, noise immunity, and current-driving capability. There are several commonly available logic families in use today, each having a unique set of electrical characteristics that differentiates it from all the others. Each logic family gives superior performance in one or more of its electrical properties. CMOS consumes very little power, has excellent noise immunity, and can be used with a wide range of power supply voltages. TTL has a larger current-driving capability than CMOS. Its power consumption is higher than that of CMOS, and its power supply requirements are more rigid. ECL is fast, making it the choice for high-speed applications. It is inferior to CMOS and TTL in terms of noise immunity and power consumption. TTL and CMOS gates come in a wide range of subfamilies. Table 11.1 lists some of the TTL and CMOS variations of the quadruple 2-input NAND gate. All gates listed have 11.1 Electrical Characteristics of Logic Gates 499 Table 11.1 Part Numbers for a Quad 2-input NAND Gate in Different Logic Families Part Number 74LS00 74ALS00 74F00 74HC00 74HCT00 74LVX00 TTL CMOS Logic Family Low-power Schottky TTL Advanced low-power Schottky TTL Fast TTL High-speed CMOS High-speed CMOS (TTL-compatible inputs) Low-voltage CMOS the same logic function but different electrical characteristics. Other gates would be similarly designated, with the last two or three digits indicating the gate function (e.g., a quadruple 2-input NOR gate would be designated 74LS02, 74ALS02, 74F02, etc.). We will examine four electrical characteristics of TTL and CMOS circuits: propagation delay, fanout, noise margin, and power dissipation. The rst of these has to do with speed of output response to a change of input. The last three have to do with input and output voltages and currents. All four properties can be read directly from specications given in a manufacturers data sheet or derived from these specications. Figures 11.1 and 11.2 show how the input and output voltages and currents are dened in a 74XX00 NAND gate. This designation can be generalized to any logic gate input or output. H L L H H L VOL VOH VIH VIL FIGURE 11.1 Input/Output Voltage Parameters H H L L L IOL IIH H IOH IIL FIGURE 11.2 Input/Output Current Parameters The voltages and currents are designated with two subscripts, one that designates an input or output and another that indicates the logic level. For example, VOL is the voltage at the gate output when the output is in the logic LOW state. IIL is the input current when the input is in the LOW state. These voltages and currents are specied in manufacturers published data sheets, which are usually available in print form in a data book or in an electronic format, such as Portable Document Format (pdf) on a CD or internet site. Figure 11.3 shows a data sheet for a 74LS00 NAND gate, which also shows parameter values for a 54LS00 device. A 54-series device is manufactured to military specications, which require a high range of environmental operating conditions. A 74-series device is suitable for general or commercial use. We will limit ourselves to the 74-series devices. The voltage and current parameters indicated in Figures 11.1 and 11.2 are all shown in the 74LS00 data sheet. Some parameters are shown as typical values, as well as maximum or minimum. Typical values should be considered information only as device manufacturers 500 C H A P T E R 1 1 Logic Gate Circuitry SN54/74LS00 QUAD 2-INPUT NAND GATE ESD > 3500 Volts QUAD 2-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 55 0 25 25 125 70 C IOH Output Current High 54, 74 0.4 mA IOL Output Current Low 54 74 4.0 8.0 mA FIGURE 11.3 74LS00 Data (1 of 2) Reprinted with permission of Motorola. 11.1 Electrical Characteristics of Logic Gates 501 SN54/74LS00 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter Typ Max Unit Test Conditions Input HIGH Voltage VIL Input LOW Voltage Input LOW Voltage VIK Input Clamp Diode Voltage VOH 2.0 Input HIGH Current Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) Guaranteed Input LOW Voltage for g All Inputs V VCC = MIN, IIN = 18 mA Output LOW Voltage Output LOW Voltage IIH Guaranteed Input HIGH Voltage for All Inputs Output HIGH Voltage Output HIGH Voltage VOL V V VIH 54 0.7 74 0.8 0.65 1.5 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table 20 VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V 0.4 mA VCC = MAX, VIN = 0.4 V 100 mA VCC = MAX Power Supply Current Total, Output HIGH 1.6 mA VCC = MAX Total, Output LOW ICC A 0.1 4.4 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol Parameter Min Typ Max Unit Test Conditions VCC = 5.0 V CL = 15 pF tPLH Turn-Off Delay, Input to Output 9.0 15 ns tPHL Turn-On Delay, Input to Output 10 15 ns FIGURE 11.3 74LS00 Data (2 of 2) Reprinted with permission of Motorola. do not guarantee these values. An exception to this would be the supply voltage, VCC, whose typical value is simply indicated as the average of maximum and minimum values. Note that IIH and IIL are shown in Figure 11.2 as owing in opposite directions, as are IOH and IOL. On a data sheet, a current entering a gate is indicated as positive and a current leaving the gate is shown as having a negative value. The reason for these current directions will become apparent when we examine the internal circuits of the gates later in the chapter. EXAMPLE 11.1 What is the maximum value of VOL for a 74LS00 NAND gate when the output current is at its maximum value? Solution When the output is in the LOW state, the output current is given by IOL, which has a maximum value of 8 mA. The output voltage, VOL, is specied for a value of 4 mA and for 8 mA. Since the output condition is specied for maximum IOL (8 mA), then VOL 0.5 V. 502 C H A P T E R 1 1 Logic Gate Circuitry The 74XX00 NAND gate data is sufcient to represent any logic functions having normal output current within its particular logic family. This data can be used for most gate or ip-op circuits within the family. Some specialized devices with higher-current outputs (e.g., 74XX244 octal tristate buffers) have a different set of electrical characteristics within their family. In the following sections of the chapter, we will use a NAND gate from each of three device families (74LS00, 74HC00A, and 74HCT00A) for illustrating the general principles of the various electrical characteristics. Devices from other families will also be used in examples and problems. Data sheets for the various devices are included in Appendix C. SECTION 11.1 REVIEW PROBLEM 11.1 What are the maximum values of voltage and current we can expect at the output of a 74LS00 NAND gate when both inputs are LOW? 11.2 Propagation Delay KEY TERMS tpHL tpLH Propagation delay when the device output is changing from HIGH to LOW. Propagation delay when the device output is changing from LOW to HIGH. Propagation delay occurs because the output of a logic gate or ip-op cannot respond instantaneously to changes at its input. There is a short delay, on the order of several nanoseconds, between input change and output response. This is largely due to the charging and discharging of capacitances inherent in the switching transistors of the gate or ipop. Figure 11.4 shows propagation delay in two gates: a 74XX00 NAND gate and a 74XX08 AND gate. Each gate has an identical input waveform, a LOW-HIGH-LOW pulse. After each input transition, the output changes after a short delay, tp. FIGURE 11.4 Propagation Delay in NAND and AND Gates Two delays are shown for each gate: tpLH and tpHL. The LH and HL subscripts show the direction of change at the gate output; LH indicates that the output goes from LOW to HIGH, and HL shows the output changing from HIGH to LOW. Propagation delay is the time between input and output voltages passing through a standard reference value. The reference voltage for standard TTL is 1.5 V. LSTTL and CMOS have different reference voltages, as follows. 11.2 Propagation Delay 503 NOTE Propagation Delay for Various Logic Families: LSTTL: Time from 1.3 V at input to 1.3 V at output. Other TTL: Time from 1.5 V at input to 1.5 V at output. CMOS: Time from 50% of maximum input to 50% of maximum output. EXAMPLE 11.2 Use the data sheet in Figure 11.3, as well as those in Appendix C, to nd the maximum propagation delays for each of the following gates: 74LS00 (quadruple 2-input NAND), 74LS02 (quadruple 2-input NOR), 74LS08 (quadruple 2-input AND), and 74LS32 (quadruple 2-input OR). Solution Table 11.2 Propagation Delays of 74LS Gates 74LS00 tpLH tpHL 74LS02 74LS08 74LS32 15 ns 15 ns 15 ns 15 ns 15 ns 20 ns 22 ns 22 ns Table 11.2 shows the variation of propagation delay among logic gates of the same family (74LS TTL). Since each logic function has a different circuit, its propagation delay will differ from those of gates with different functions. EXAMPLE 11.3 Use data sheets to nd the maximum propagation delays for each of the following logic gates: 74F00, 74AS00, 74ALS00, 74HC00, and 74HCT00. Solution Table 11.3 Propagation Delays of 74LS Gates 74F00* tpLH tpHL 74AS00 74ALS00 74HC00** 74HCT00*** 6 ns 5.3 ns 4.5 ns 4 ns 11 ns 8 ns 15 ns 15 ns 19 ns 19 ns *Temperature range (74F00): 0C to 70C. **VCC 4.5 V, temperature range (74HC00): 55C to 25C. ***VCC 5 V, temperature range (74HCT00): 55C to 25C. As indicated by the notes for Table 11.3, propagation delay (and other parameters) vary with certain operating conditions, such as ambient temperature and power supply voltage. Always make sure that the operating conditions are correctly specied when looking up a data sheet parameter. All gates in Example 11.3 have the same logic function (2-input NAND), but different propagation delay times. We might ask, Why not always use the advanced Schottky TTL gate (74AS00), since it is the fastest? The main reason is that it has the highest power dissipation of the gates shown. We wouldnt know this without looking up other specs on the data sheet. (We will learn how to do this later in the chapter.) Thus, it is important to make design decisions based on complete information, not just one parameter. 504 C H A P T E R 1 1 Logic Gate Circuitry Propagation Delay in Logic Circuits A circuit consisting of two or more gates or ip-ops has a propagation delay that is the sum of delays in the input-to-output path. Delays in gates that do not affect the circuit output are disregarded. Figure 11.5 shows how propagation delay works in a simple logic circuit consisting of a 74HC08 AND gate and a 74HC32 OR gate. Changes at inputs A and B must propagate through both gates to affect the output. The total delay in such a case is the sum of tp1 and tp2. A change at input C must pass only through gate 2. The circuit delay resulting from this change is only tp2. FIGURE 11.5 Propagation Delays in a Logic Gate Circuit The timing diagram in Figure 11.5 shows the changes at inputs A, B, and C and the resulting transitions at all gate outputs. Assume VCC 4.5 V and temperature range is 55C to 25C. 1. When A goes LOW, AB, the output of gate 1, also goes LOW after a maximum delay of tpHL 15 ns. This makes Y go LOW after a further delay of up to tpHL 15 ns. Total delay: tp tpHL1 tpHL2 15 ns 15 ns 30 ns, max. 2. The HIGH-to-LOW transition at input B has no effect, since there is no difference between 0 1 and 0 0. AB is already LOW. 3. The LOW-to-HIGH transition at input C makes Y go HIGH after a maximum delay of tpLH2 15 ns. SECTION 11.2 REVIEW PROBLEM 11.2 Assume the gates in Figure 11.5 are replaced by a 74LS08 AND gate and a 74LS32 OR gate. Repeat the calculations of for the propagation delays if the waveforms of Figure 11.5 are applied to the circuit. The data sheets for the 74LS08 and 74LS32 are found in Appendix C. 11.3 Fanout 505 11.3 Fanout KEY TERMS Fanout The number of load gates that a logic gate output is capable of driving without possible logic errors. Driving gate A gate whose output supplies current to the inputs of other gates. Load gate A gate whose input current is supplied by the output of another gate. Sourcing A terminal on a gate or ip-op is sourcing current when the current ows out of the terminal. Sinking A terminal on a gate or ip-op is sinking current when the current ows into the terminal. IOL Current measured at a device output when the output is LOW. IOH Current measured at a device output when the output is HIGH. IIL Current measured at a device input when the input is LOW. IIH Current measured at a device input when the input is HIGH. We have assumed that logic gates are able to drive any number of other logic gates. Since gates are electrical devices with nite current-driving capabilities, this is obviously not the case. The number of gates (loads) a logic gate can drive is referred to as its fanout. NOTE Fanout is simply an application of Kirchhoffs current law: The algebraic sum of currents at a node must be zero. Thus, the fanout of a logic gate is limited by: a. The maximum current its output can supply safely in a given logic state (IOH or IOL ), and b. The current requirements of the load to which it is connected (IIH or IIL ). Figure 11.6 shows the fanout of an AND gate when its output is in the HIGH and LOW states. The AND gate, or driving gate, supplies current to the inputs of the other four gates, which are called the load gates. Each load gate requires a xed amount of input current, depending on which state it is in. The sum of these input currents equals the current supplied by the driving gate. The FIGURE 11.6 Driving Gates and Load Gates 506 C H A P T E R 1 1 Logic Gate Circuitry fanout is determined by the amount of current the driving gate can supply without damaging its output circuit. The input and output currents of a gate are established by its internal circuitry. These values are usually the same for two gates in the same family, since the input and output circuitry of a gate is common to all members of the family. Exceptions may occur when the output of a particular gate, such as the 74XX244 octal three-state buffer, has additional output buffering or an input of a gate such as a 74LS86 Exclusive OR is equivalent to more than one input load. EXAMPLE 11.4 FIGURE 11.7 Example 11.4 Output Current due to One Load Gate The gates in Figure 11.7a and b are 74LS00 NAND gates. Determine the output current of the driving gate in each gure. H H L IOL IIL a. Low output on driving gate L L IOH IIH H b. High output on driving gate Solution From the 74LS00 data sheet, IIL 0.4 mA and IIH 20 A. (There are two values of IIH given in the data sheet. Choose the one for the condition VIN 2.7 V, which is the minimum output voltage of a driving gate in the HIGH state (VOH). The other value is not appropriate since a gate will never have a 7 V output, as specied in the condition, if its supply voltage is 5 V.) Since the driving gate is driving one load, its output current is the same as the input current of the load gate. Therefore, the driving gate output currents are given by IOL 0.4 mA (positive, since it is entering the driving gate output) and IOH 20 A (negative, since it is leaving the driving gate output). EXAMPLE 11.5 FIGURE 11.8 Example 11.5 Output Current due to Two Load Gates Determine the output current of the driving gate in each of Figures 11.8a and b if the gates are all 74LS00 NAND gates. H H IOL IIL L IIL a. Low output on driving gate L L IOH IIH H IIH b. High output on driving gate 11.3 Fanout 507 Solution Since there are two identical load gates in the circuits of Figure 11.8, the driving gate output current will be twice the load gate input current. IOL IOH 2 2 0.4 mA 0.8 mA. ( 20 A) 40 A. Figure 11.9 shows the extension of the circuits in Figures 11.7 and 11.8, where the number of load gates is the maximum that can be driven by the driving gate. This is the condition used to calculate fanout. IOL H H IIL 1 L IIL 2 IIL nL a. Low output on driving gate IOH L L IIH 1 H IIH 2 IIH nH b. High output on driving gate FIGURE 11.9 Output Current to Fanout Calculation If the load gates each represent the same load, then by Kirchhoffs current law (KCL): IOL and IOH IIL1 IIH1 IIL2 IIH2 IILnL nL IIL IIHnH nH IIH The fanout of the driving gate in the LOW and HIGH states can be calculated as: nL and IOL IIL nH IOH IIH By convention, current entering a gate (IIH, IOL ) is denoted as positive, and current leaving a gate (IIL, IOH) is denoted as negative. When current is leaving a gate, we say the gate is sourcing current. When current is entering a gate, we say the gate is sinking current. Note that the output of a gate does not always source current, nor does an input always sink current. The current direction changes for the HIGH and LOW states at the same terminal. The reason for this will become apparent when we study the circuitry of logic gate inputs and outputs. 508 C H A P T E R 1 1 Logic Gate Circuitry EXAMPLE 11.6 How many 74LS00 inputs can a 74LS00 NAND gate drive? (that is, what is the fanout of a 74LS00 NAND gate?) Solution We must consider the following cases: a. When the output of the driving gate is LOW b. When the output of the driving gate is HIGH Output LOW: IOL IIL nL 8 mA (sinking) 0.4 mA (sourcing) 8 mA/0.4 mA 20 IOH IIH nH 0.4 mA (sourcing) 20 A (sinking) 0.4 mA/20 A 20 Output HIGH: Since nL nH, fanout is 20. We disregard the negative sign in our calculations, since the input current of the load gate and output current of the driving gate are actually in the same direction. For example, even though IOH is leaving the driving gate (negative), IIH is entering the load gates (positive). These currents ow in the same direction. If we include the minus sign in our calculation, we get a negative value of fanout, which is meaningless. The fanout in both HIGH and LOW states is the same in this case, but that is not always so. If the values of HIGH- and LOW-state fanout are different, the smallest value must be used. For example, if a gate can drive four loads in the HIGH state or eight in the LOW state, the fanout of the driving gate is four loads. If we attempt to drive eight loads, we cant guarantee enough driving current to supply all loads in both states. If a gate from one logic family is used to drive gates from another logic family, we must use the output parameters (IOL, IOH) for the driving gate and the input parameters (IIL, IIH) for the load gates. EXAMPLE 11.7 Calculate the maximum number of Schottky TTL loads (74SXX series) that a 74LS86 XOR gate can drive. Solution Driving gate: Load gates: 74LS86 IOH IOL IIH IIL 74SXX 0.4 mA, 8 mA 50 A, 2 mA Output LOW: IOL IIL nL 8 mA (sinking) 2 mA (sourcing) 8 mA/2 mA 4 IOH IIH nH 0.4 mA (sourcing) 50 A (sinking) 0.4 mA/50 A 8 Output HIGH: Since nL nH, fanout nL 4. 11.3 509 What happens if we load a gate output beyond its rated fanout? Adding more load gates will do this by increasing the value of IOL beyond its maximum rating. If enough load is added, the output of the driving gate might be destroyed by the heat generated by the excess current. More likely, the performance of the driving gate will be degraded. Figure 11.10 shows the relationship between output voltage and current for a 74LS00 and a 74F00 NAND gate. Figure 11.10a shows that the output voltage (LOW state) increases with increasing sink current. Figure 11.10b indicates a decrease in HIGH state output voltage with an increase of source current. VOL , OUTPUT VOLTAGE (VOLTS) 1 TA = 25C VCC = 4.5 V LS00 F00 0.5 0 0 20 40 IOL, OUTPUT CURRENT (mA) 60 a. Output low characteristic 4 VOH , OUTPUT VOLTAGE (VOLTS) www.electronictech.com Fanout TA = 25C VCC = 5.5 V 3 2 1 0 LS00 F00 50 100 IOH, OUTPUT CURRENT (mA) 150 b. Output high characteristic FIGURE 11.10 Output Characteristics of 74LS00 and 74F00 Gate. Reprinted with permission of Motorola In other words, a greater load in either state takes the output voltage further away from its nominal value. This has an effect on other performance factors, such as noise margin, which we will examine in a later section of the chapter. NOTE The output voltage of a logic gate is dened in a datasheet for a particular value of output current. We will examine the fanout of CMOS devices in a later section on interfacing between CMOS and TTL. 510 C H A P T E R 1 1 Logic Gate Circuitry SECTION 11.3 REVIEW PROBLEM 11.3 The input and output currents IOH, IOL, IIH, and IIL of a TTL device may be classied as source currents or sink currents. List each input or output current as a source or sink current. 14.4 Power Dissipation KEY TERMS Power dissipation The electrical energy used by a logic circuit in a specied period of time. Abbreviation: PD VCC TTL or high-speed CMOS supply voltage. ICC Total TTL or high-speed CMOS supply current. ICCH TTL supply current with all outputs HIGH. ICCL TTL supply current with all outputs LOW. IT When referring to CMOS supply current, the sum of static and dynamic supply currents. CPD Internal capacitance of a high-speed CMOS device used to calculate its power dissipation. Electronic logic gates require a certain amount of electrical energy to operate. The measure of the energy used over time is called power dissipation. Each of the different families of logic has a characteristic range of values for the power it consumes. For TTL and CMOS, the power dissipation is calculated as follows: TTL: High-Speed CMOS: PD PD VCC ICC VCC IT (IT quiescent current) dynamic supply Figure 11.11 shows the supply voltage and current in a 74XX00 NAND gate. FIGURE 11.11 Power Supply Voltage and Current in a 74XX00 NAND gate. Vcc Icc Icc The main difference between the two families is the calculation of supply current. The supply current in a TTL device is different when its outputs are HIGH than when they are LOW. Thus, supply current, ICC, and therefore power dissipation, depends on the states of the device outputs. If the outputs are switching, ICC is proportional to output duty cycle. In a CMOS device, very little power is consumed when the device outputs are static. Much more current is drawn from the supply when the outputs switch from one state to another. Thus, the power dissipation of a device depends on the switching frequency of its outputs. 11.4 Power Dissipation 511 Power Dissipation in TTL Devices Two values are given for supply current in a TTL data sheet. ICCL is the current drawn from the power supply when all gate outputs are LOW. ICCH is the current drawn from the supply when all outputs are HIGH. If the gate outputs are not all at the same level, the supply current is the sum of currents given by: ICC nH ICCH n nL ICCL n where n is the total number of gates in the package nH is the number of gates whose output is HIGH nL is the number of gates whose output is LOW The power dissipation of a TTL chip also depends on the duty cycle of the gate outputs. That is, it depends on the fraction of time that the chips outputs are HIGH. If we assume that, on average, the outputs of a chip are switching with a duty cycle of 50%, the supply current can be calculated as follows: ICC (ICCH ICCL)/2 If the output duty cycle is other than 50%, the supply current is given by: ICC where DC EXAMPLE 11.8 DC ICCH (1 DC) ICCL duty cycle. Figure 11.12 shows a circuit constructed from the gates in a 74XX00 quadruple 2-input NAND gate package. Use the data sheet shown in Figure 11.3 to determine the maximum power dissipation of the circuit if the input is DCBA 1001 and the gates are 74LS00 NANDs. Refer to the data sheets in Appendix C and repeat the calculation for 74ALS00 and 74AS00 gates. FIGURE 11.12 Power Dissipation of 74XX00 NAND Solution Gate 1: AB 1 Gate 2: CD 1 Gate 3: AB CD 0 Gate 4: AB CD 1 Since three outputs are HIGH and one is LOW, the supply current is given by: ICC nH ICCH n 3 ICCH 4 nL ICCL n 1 ICCL 4 512 C H A P T E R 1 1 Logic Gate Circuitry Maximum supply current for each device is: 74LS00: ICC 74ALS00: ICC 74AS00: ICC 0.75(1.6 mA) 0.25(4.4 mA) 2.3 mA 0.75(0.85 mA) 0.25(3 mA) 1.3875 mA 0.75(3.2 mA) 0.25(17.4 mA) 6.75 mA Maximum power dissipation for each device is: 74LS00: PD 74ALS00: PD 74AS00: PD (1 mW EXAMPLE 11.9 1 milliwatt VCC ICC VCC ICC VCC ICC 10 3 (5 V)(2.3 mA) 11.5 mW (5V)(1.3875 mA) 6.94 mW (5V)(6.75 mA) 33.75 mW W.) Find the maximum power dissipation of the circuit in Figure 11.12 if the gates are 74LS00 and the gate outputs are switching with an average duty cycle of 30%. Solution ICC ICC PD 0.3 ICCH 0.7 ICCL 0.3(1.6 mA) 0.7(4.4 mA) 3.56 mA VCC ICC (5 V)(3.56 mA) 17.8 mW Power Dissipation in High-Speed CMOS Devices CMOS gates draw the most power when their outputs are switching from one logic state to the other. When the outputs are static (not switching), the large internal impedances of the gate limit the supply current. A change of state requires the charging and discharging of internal gate capacitances, resulting in a greater demand on the power supply current. Thus, the faster a CMOS gate switches, the more current, and hence more power, it requires. CMOS supply current has two components: a quiescent current that ows when the gate is in a steady state and a dynamic component that depends on frequency. For relatively high frequencies (about 1 MHz and up), the quiescent component is small compared to the dynamic component and can be neglected. The quiescent current is usually specied for an entire chip package, regardless of the number of gates. It is given by ICC VCC. For a 74HC00A NAND gate, ICC 1 A at room temperature for a supply voltage of VCC 6.0 V. The dynamic component calculation accounts for internal and load capacitance and is given, per gate, by: (CL where EXAMPLE 11.10 2 CPD) V CC f CL is the gate load capacitance CPD is the gate internal capacitance VCC is the supply voltage f is the switching frequency of the gate output The circuit in Figure 11.12 is constructed from 74HC00A high-speed CMOS NAND gates. Calculate the power dissipation of the circuit: a. When the gate inputs are steady at the state DCBA 1010 b. When the outputs are switching at an average frequency of 10 kHz c. When the outputs are switching at an average frequency of 1 MHz Supply voltage is 5 V. Temperature range is 25C to 55C. 11.4 Power Dissipation 513 Solution Refer to the 74HC00A data sheet in Appendix C. a. PD VCC ICC (5 V)(1 A) 5 W. This is the quiescent power dissipation of the circuit. b. The 74HC00A data sheet indicates that each gate has a maximum input capacitance, Cin of 10 pF. Assume that this value represents the load capacitance of gates 1, 2, and 3 of the circuit in Figure 11.12. Further assume that gate 4 has a load capacitance of 0. The total power dissipation of the circuit is given by: 3(22 pF 10 pF)(5 V)2 (0.01 MHz) (22 pF)(5 V)2 (0.01 MHz) 5 W 3(8 W) 5.5 W 5 W 34.5 W PD c. For f 1 MHz, total power dissipation is given by: 3(22 pF 10 pF)(5 V)2 (1 MHz) (22 pF)(5 V)2 (1 MHz) 5 W 3(800 W) 550 W 5 W 2955 W 2.95 mW PD EXAMPLE 11.11 The circuit in Figure 11.12 is constructed using a 74LS00 quad 2-in NAND gate and again with a 74HC00 quad 2-in NAND. Both circuits have identical waveforms applied to their inputs that make all gate outputs switch with a duty cycle of 50%. Calculate the frequency at which the power dissipation of the 74HC00 circuit exceeds that of the 74LS00 circuit. Assume VCC 5 V and temperature 25C for both circuits. Solution The power dissipation of the LSTTL circuit is: PD VCC ICC (VCC) (ICCH ICCL)/2 (5 V) (3.0 mA) 15 mW (5V) (1.6 mA 4.4 mA)/2 Neglect the quiescent current of the high-speed CMOS circuit. Per gate: Total: For PD PD CPD CL PD (CL CPD)VCC2 f 22 pF per gate 10 pF for 3 gates and 0 pF for 1 gate (3(10pF 22 pF) 22 pF)(5 V)2f (3(32 pF) 22 pF) (25 V2) f (96 pF 22 pF) (25 V2) f (118 pF) (25 V2) f 15 mW: f 15mW (118pF)(25V2) 5.08MHz The power dissipation of the 74HC00 circuit exceeds that of the 74LS00 circuit at 5.08 MHz. NOTE The power saving in a high-speed CMOS circuit generally results from the fact that most device outputs are not switching at any given time. The power dissipation of a TTL circuit is independent of frequency and therefore draws some power at all times. This is not the case for CMOS, which draws the majority of its power when switching. 514 C H A P T E R 1 1 Logic Gate Circuitry SECTION 11.4 REVIEW PROBLEM 11.4 Why does CMOS power dissipation increase with frequency? 11.5 Noise Margin KEY TERMS Noise Unwanted electrical signal, often resulting from electromagnetic radiation. Noise margin A measure of the ability of a logic circuit to tolerate noise. VIH Voltage level required to make the input of a logic circuit HIGH. VIL Voltage level required to make the input of a logic circuit LOW. VOH Voltage measured at a device output when the output is HIGH. VOL Voltage measured at a device output when the output is LOW. Electrical circuits are susceptible to noise, or unwanted electrical signals. Such signals are often induced by electromagnetic elds of motors, uorescent lighting, highfrequency electronic circuits, and cosmic rays. They can cause erroneous operation of a digital circuit. Since it is impossible to eliminate all noise from a circuit, it is desirable to build a certain amount of tolerance, or noise margin, into digital devices used in the circuit. In all circuits studied so far, we have assumed that logic HIGH is 5 volts and logic LOW is 0 volts in devices with a 5-volt supply. In practice, there is a certain amount of tolerance on both the logic HIGH and LOW voltages; for TTL devices, a HIGH at a device input is anything above about 2 volts, and a LOW is any voltage below about 0.8 volts. Due to internal voltage drops, the HIGH output of a TTL gate is typically about 3.5 volts. Figure 11.13 shows one inverter driving another. In Figure 11.13a, the output of the rst inverter and the input of the second have the same logic threshold. That is, the input of the second gate recognizes any voltage above 2.7 volts as HIGH (VIH 2.7 V) and any voltage below 0.5 volts as LOW (VIL 0.5 V). The output of the rst inverter produces at least 2.7 volts when HIGH (VOH 2.7 V) and no more than 0.5 volts as LOW (VOL 0.5 V). If there is noise on the line connecting the two gates, it will likely cause the voltage of the second gate input to penetrate into the forbidden region between logic HIGH and LOW levels. This is shown on the graph of the waveform in Figure 11.13a. When the voltage enters the forbidden region, the gate will not operate reliably. Its output may switch states when it is not supposed to. Figure 11.13b shows the same circuit with different logic thresholds at input and output. The output of the rst inverter is guaranteed to be at least 2.7 volts when HIGH (VOH 2.7 V) and no more than 0.5 volts when LOW (VOL 0.5 V). The second gate recognizes any input voltage greater than 2 volts as a HIGH (VIH 2 V) and any input voltage less than 0.8 volts (VIL 0.8 V) a LOW. The difference between logic thresholds allows for a small noise voltage, equal to or less than the difference, to be superimposed on the desired signal. It will not cause the input voltage of the second inverter to penetrate the forbidden region. This ensures reliable operation even in the presence of some noise. For the 74LS04 inverter, the HIGH-state and LOW-state noise margins, VNH and VNL, are: VNH VNL VOH VIL VIH VOL 2.7 V 0.8 V 2.0 V 0.5 V 0.7 V 0.3 V A device with these values of VIH and VIL is deemed to be TTL compatible. 11.5 515 A A A Noise Margin 1 2 GATE 1 OUTPUT A, volts GATE 2 INPUT 5V 5V Noise pushes VIH, VIL into forbidden region HIGH VOH HIGH VIH FORBIDDEN VOL 2.7 V VIL 2.7 V V0H VIH 0.5 V FORBIDDEN 0.5 V LOW LOW 0V V0L VIL 0V t a. Zero noise margin GATE 1 OUTPUT A, volts GATE 2 INPUT 5V 5V HIGH Noise within specs for VIH, VIL HIGH VNH VOH V0H 2.7 V VIH 2.0 V VIH VIL FORBIDDEN 0.8V VIL FORBIDDEN VOL 0.5 V V0L LOW LOW VNH 0V 0V t b. Nonzero noise margin FIGURE 11.13 Noise Margins EXAMPLE 11.12 Use the 74HC00A data sheet in Appendix C to calculate the noise margins for this gate. Assume VCC 4.5 V, ambient temperature (TA) is 25C, and the driving gate is fully loaded (IOUT 4 mA). Solution VNH VNL VOH VIL VIH VOL 3.98 V 1.35 V 3.15 V 0.26 V 0.63 V 1.09 V 516 C H A P T E R 1 1 Logic Gate Circuitry SECTION 11.5 REVIEW PROBLEM 11.5 Calculate the noise margins of a 74HCT00A NAND gate from the data sheet in Appendix C. VCC 4.5 V, TA 25C, IOUT 4 mA 11.6 Interfacing TTL and CMOS Gates KEY TERM TTL Compatible Able to be driven directly by a TTL output. Usually implies voltage compatibility with TTL. Interfacing different logic families is just an extension of the fanout and noise margin problems; you have to know what the load gates of a circuit require and what the driving gates can supply. In practice, this means you must know the specied values of input and output voltages and currents for the gates in question. Table 11.4, which is derived from the manufacturersdata sheets included in Appendix C, gives an overview of input and output parameters for a variety of TTL and CMOS families. Ambient temperature is assumed to be 25C. Table 11.4 TTL and CMOS Input and Output Parameters TTL 74LS VCC (V) VOH (V) VOL (V) VIH (V) VIL (V) IOH (mA) IOL (mA) IIH (mA) IIL (mA) Low-Voltage CMOS High-Speed CMOS 74F 74AS 74ALS 5.0 2.7 0.5 2.0 0.8 0.4 8.0 0.02 0.4 5.0 2.7 0.5 2.0 0.8 1.0 20.0 0.1 0.6 5.5 3.0 0.5 2.0 0.8 2.0 20.0 0.02 0.5 5.5 3.0 0.5 2.0 0.8 0.4 8.0 0.02 0.1 74HC 4.5 3.98 0.26 3.15 1.35 4.0 4.0 0.0001 0.0001 74HCT 74VHC 74VHCT 74LVX 74LCX 4.5 3.98 0.26 2.0 0.8 4.0 4.0 0.0001 0.0001 4.5 3.94 0.36 3.15 1.35 8.0 8.0 0.0001 0.0001 4.5 3.94 0.36 2.0 0.8 8.0 8.0 0.0001 0.0001 3.0 2.58 0.36 2.0 0.8 4.0 4.0 0.0001 0.0001 3.0 2.2 0.55 2.0 0.8 24.0 24.0 0.0001 0.0001 Table 11.4 is useful for comparison of logic families, but it is not a substitute for reading data sheets, as it gives parameters only under a restricted set of conditions. We can, however, make some observations based on the data in Table 11.4. 1. Input currents in a CMOS gate are very low, due to its high input impedance. As a result fanout is generally not a problem with CMOS loads. Interface problems to CMOS loads have to do with input voltage, not current. 2. CMOS devices, such as 74HCT, that have the same values of VIH and VIL as the TTL families in Table 11.4, are considered to be TTL compatible, since they can be driven directly by TTL drivers. 3. LSTTL is usually regarded as the benchmark for measuring TTL loading of a CMOS circuit. For example, a data sheet will claim that a device can drive 10 LSTTL loads. This claim depends on the values of IOH and IOL for the driving gate, which are not listed directly in CMOS data sheets, except as absolute maximum ratings. The values in Table 11.4 are the values of current for which the output voltages, VOH and VOL, are dened. (Recall from the section on fanout in this chapter that increasing output current causes output voltages to migrate away from their nominal values, thus reducing device noise margins.) Let us examine four interfacing problems: high-speed CMOS driving 74LS, 74LS driving 74HC, 74LS driving 74HCT, and 74LS driving low-voltage CMOS. 11.6 Interfacing TTL and CMOS Gates 517 High-Speed CMOS driving 74LS To design an interface between any two logic families, we must examine the output voltages and currents of the driving gate and the input voltages and currents of the load gates. Assume a 74HC00 NAND gate drives one or more 74LS00 NAND gates. From the 74HC00 data sheet, we determine that VOH 3.98 V and VOL 0.26 V for VCC 4.5 V. The 74LS00 requires at least 2.0 V at its input in the HIGH state and no more than 0.8 V in the LOW state. The 74HC00 therefore satises the input voltage requirement of the 74LS00. For the dened output voltages, the 74HC00 gate can source or sink 4 mA. The fanout for the circuit is therefore calculated as follows: nH nL n IOH IIH IOL IIL 4mA 20 A 4mA 0.4A 200 10 10 Therefore a 74HC00 NAND can drive a 74LS00 directly, with a fanout of 10. 74LS Driving 74HC As mentioned earlier, CMOS has a very small input current and therefore does not present a fanout problem to a 74LS driving gate. However, we must also examine the interface for voltage compatibility. From data sheets, we see that a 74LS00 gate is guaranteed to provide at least 2.7 V in the HIGH state and no more than 0.5 V in the LOW state. A 74HC00 gate will recognize anything less than 1.35 V as a logic LOW and anything more than 3.15 V as a logic HIGH. The 74LS00 meets the LOW-state criterion, but it cannot guarantee sufcient output voltage in the HIGH state. In order to properly drive a 74HC input with a 74LS output, we must provide a pull-up resistor to ensure sufcient HIGH-state voltage at the 74HC input. The circuit is illustrated in Figure 11.14. The pull-up resistor should be between 1 k and 10 k . Vcc 74LS00 Rp 74HC00 GND FIGURE 11.14 LSTTL driving 74HC CMOS 74LS Driving 74HCT 74HCT inputs are designed to be compatible with TTL outputs. As with 74HC devices, input currents are sufciently low that fanout is not a problem with the 74LS-to-74HCT interface. 74HCT input voltages are the same as those for TTL (VIH 2.0 V and VIL 0.8 V). Therefore, 74HCT inputs can be driven directly by LSTTL outputs. 74LS Driving Low-voltage CMOS CMOS families with supply voltages less than 5 V are rapidly becoming popular in new applications. Two of the reasons for their increasing prominence are reduced power dissipation (inversely proportional to the square of the supply voltage) and smaller feature size 518 C H A P T E R 1 1 Logic Gate Circuitry (i.e., size of the internal transistors) that allows more efcient packaging and faster operation. Low-voltage logic is particularly popular for battery-powered applications such as laptop computing or cell phones. Low voltage families typically operate at VCC 3.3 V or 2.5 V. Newer devices are available for VCC 1.8 V or 1.65 V. Low-voltage CMOS families such as 74LVX or 74LCX can interface directly with TTL outputs if they are operated with a 3.0 V to 3.3 V power supply. These families are not really suitable for driving 5-volt TTL, as their noise margins are too small when they use a 3.0 V supply voltage. If we wish to use a 74LS device to drive a 74HC device operating at a power supply voltage of less than 4.5 V, we can use a 74HC4049 or 74HC4050 buffer to translate the TTL logic level down to an appropriate value. The 74HC4049 is a package of six inverting buffers. The 74HC4050 has six noninverting buffers. These buffers can tolerate up to 15 V on their inputs. Their output voltages are determined by the value of their supply voltage. Figure 11.15 shows an LSTTL-to-74HC interface circuit with a 74HC4050 buffer. Note that the interface buffer has the same power supply voltage as the load gate. Both sides of the interface are referenced to the same ground. 5V 3V 74LS00 74HC4050 74HC00 GND FIGURE 11.15 74LS-to-74HC Interface Using a 74HC4050 Buffer SECTION 11.6 REVIEW PROBLEM 11.6 A 74LS00 driving gate is to be interfaced to a 74HC00 load using a 74HC4050 noninverting buffer. The 74HC00 has a power supply voltage of 2.5 V. What supply voltage should the 74HC4050 buffer have? Why? 11.7 Internal Circuitry of TTL Gates KEY TERMS Cutoff mode The operating mode of a bipolar transistor when there is no collector current owing and the path from collector to emitter is effectively an open circuit. In a digital application, a transistor in cutoff mode is considered OFF. Saturation mode The operating mode of a bipolar transistor when an increase in base current will not cause a further increase in the collector current and the path from collector to emitter is very nearly (but not quite) a short circuit. This is the ON state of a transistor in a digital circuit. TTL has been around for a long time. The rst transistor-transistor logic ICs were developed by Texas Instruments around 1965. Since then, there have been many improvements in the speed and power consumption of these devices, but the basic logic principles remain largely unchanged. Even though they are seldom used in modern designs, it makes sense to examine the internal circuitry of standard TTL gates such as the 7400 NAND, 7402 NOR, and 7404 inverter because the internal logic concepts are similar to the more advanced types of TTL. The most important parts of the circuit, as far as a designer or technician is concerned, are the input and output circuits, because they are the only parts of the chip to which we have access. It is to these points that we interface other circuits and where we make diag- 11.7 Internal Circuitry of TTL Gates 519 nostic measurements. A basic understanding of the inputs and outputs of logic gate circuitry is helpful when we design or troubleshoot a digital circuit. Bipolar Transistors as Logic Devices FIGURE 11.16 Currents and Voltages in an NPN Bipolar Transistor The basic element of a TTL device is the bipolar junction transistor, illustrated in Figure 11.16. This is not the place to give a detailed analysis of the operation of a bipolar transistor, but a simplied summary of operating modes will be useful. The bipolar transistor is a current amplier having three terminals called the collector, emitter, and base. Current owing into the base controls the amount of current owing from the collector to the emitter. If base current is below a certain threshold, the transistor is in cutoff mode and no current ows in the collector. In this state, the base-emitter voltage is less than 0.6 V and the collector-emitter path acts like an open circuit. We can treat the collector-emitter path as an open switch, as shown in the lefthand diagram in Figure 11.17. FIGURE 11.17 NPN Bipolar Transistor as a Switch If the base current increases, the transistor enters the active region, where the collector current is proportional to the base current by a current gain factor, b. This is the linear, or amplication, region of operation, used by analog ampliers. If the base current increases still further, collector current reaches a maximum value and will no longer increase with base current. This is called the saturation mode of the transistor. The saturated value of collector current, ICS, is determined by (1) the resistance in the collector-emitter current path, (2) the voltage drop across the collector and emitter, VCE, and (3) the collector supply voltage, VCC. Base-emitter voltage is about 0.7 V and will not increase signicantly with increasing base current. The voltage between collector and emitter is in the range from 0.2 V to 0.5 V. In this mode, we can treat the transistor as a closed switch, as shown in the righthand diagram of Figure 11.17. Table 11.5 summarizes the voltages and currents in the cutoff, active, and saturation regions. Table 11.5 Bipolar Transistor Characteristics Cutoff IC VCE VBE Active Saturation 0 Open cct. 0.6 V bIB 0.8 V 0.6 V0.7 V bIB 0.2 V0.5 V 0.7 V 520 C H A P T E R 1 1 Logic Gate Circuitry EXAMPLE 11.13 Figure 11.18 shows an NPN bipolar transistor connected in a common-emitter conguration. With the right choice of input voltages, this circuit acts as a digital inverter. FIGURE 11.18 Example 11.13 Transistor as Inverter Analyze the circuit to show that it acts as an inverter if a logic HIGH is dened as 3 V and a logic LOW is dened as 0.5 V. Assume that b 100, and assume that VBE 0.7 V and VCE 0.2 V in saturation. Solution We will analyze the circuit with two input voltages: 3 V (logic HIGH) and 0.5 V (logic LOW). These two conditions are shown in Figure 11.19. FIGURE 11.19 Example 11.13 Voltage and Current Analysis of Inverter High input. We must prove that VI 3 V is sufcient to saturate the transistor. Let us assume that this is true and nd out if calculations conrm our assumption. Figure 11.19a shows the circuit with VI 3 V. By Kirchhoffs voltage law (KVL): VI IB IBRB VBE, or (VI VBE)/RB If we assume that IB is sufcient to saturate the transistor, then: IB bIB (3 V 0.7 V)/22 k 105 A (100)(105 A) 10.5 mA Collector current wont increase beyond its saturated value, even if base current increases. Therefore, if the transistor is saturated, bIB will be larger than the current actually owing in the collector-emitter path. 11.7 Internal Circuitry of TTL Gates 521 In saturation, the collector current can be calculated by KVL: VCC IC IC IC RC VCE, or (VCC VCE)/RC (5 V 0.2 V)/470 10.2 mA Since bIB IC, the transistor is saturated. Thus, an input voltage of 3 V will produce sufcient base current to saturate the transistor. The output is given by VO VCE 0.2 V, which is within the dened range of a logic LOW. LOW input. Figure 11.19b shows the circuit with VI VI VBE Since VBE must be IB RB 0.5 V 0.5 V. By KVL: VBE IB RB 0.6 V, the transistor is in cutoff mode. Thus, in the collector circuit: VCC IC RC 5V VO (0)(470 ) VCE VCE 5 V (logic HIGH) VCE Table 11.6 summarizes the operation of the circuit as an inverter. Table 11.6 Input and Output of Single-Transistor Inverter Input Output VI Logic Level VO Logic Level 0.5 V 3V LOW HIGH 5V 0.2 V HIGH LOW TTL Open-Collector Inverter and NAND Gate KEY TERM Open-collector output A TTL output where the collector of the LOW-state output transistor is brought out directly to the output pin. There is no built-in HIGHstate output circuitry, which allows two or more open-collector outputs to be connected without possible damage. NOTE The TTL gates (7405, 7401, 7404, 7400, and 7402) used in the following sections to illustrate TTL circuit principles are no longer in general use. They are from the original (standard) TTL family, which has been superceded by faster and more efcient devices. However, the standard TTL devices are easier to understand than devices from the newer TTL subfamilies, since their circuit structure is simpler. The operating principles are similar in both the standard and newer families, so we will use the standard devices to illustrate the general principles of TTL operation. Figure 11.20 shows the circuit of the simplest TTL gate: a 7405 inverter with open-collector outputs. This circuit performs the same function as the single-transistor inverter we examined in Example 11.13. These circuits differ most obviously in their input circuitry. The inverter circuit in Example 11.13 has a resistor as its input; the 7405 inverter has a transistor, 522 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.20 Open-Collector Inverter (7405) Q1, as its input. The input transistor allows faster switching of input states. This conguration is common to all standard TTL gates and will be examined in detail later in this section. The logic function of the 7405 is performed by transistors Q2 and Q3. Output transistor Q3 is switched ON and OFF by current owing in the collector-emitter path of Q2. When Q3 is ON, Y is LOW. However, when Q3 is OFF, Y is oating. There is a high impedance between Y and ground, so the output is not LOW. But there is no connection to VCC to make the output HIGH. In this condition, Y is neither HIGH nor LOW. To enable the output to produce a HIGH state, we need to add an external pull-up resistor. The value of this resistor depends on the current sinking capability of Q3, specied in the data sheet as IOL. We will do such calculations in a later example. TTL Inputs Transistor Q1 and diode D1 make up the input circuit of the TTL inverter of Figure 11.20. The diode protects the input against small negative voltages. If the input goes more negative than about 0.7 V, the diode will conduct, effectively short-circuiting the input to ground plus one diode drop. This clamps the input to 0.7 V. D1 has no logic function. Q1 can be treated as two back-to-back diodes, as shown in Figure 11.21. Figure 11.22 shows how the input responds to logic HIGH and LOW voltages. LOW Input. When a TTL input is made LOW, the base-emitter junction of Q1 acts as a forward-biased diode, creating a current path from VCC to ground via the input pin. This 11.7 Internal Circuitry of TTL Gates 523 FIGURE 11.21 Diode Equivalent of TTL Input Transistor FIGURE 11.22 HIGH and LOW Inputs at a TTL Gate current makes up the majority of current IIL, which has a maximum value of 1.6 mA in standard TTL (0.4mA in LSTTL). At the moment the input is made LOW, the transistor action of Q1 transports charge away from the base of Q2, pulling it LOW and keeping it in cutoff mode. This current dies out when the base charge of Q2 has been depleted, shortly after the LOW is applied to the input pin. The diode formed by the base-collector junction of Q1 does not carry sufcient current to turn on Q2, since the base-emitter path is of much lower impedance. HIGH Input. A HIGH at a TTL input reverse-biases the base-emitter junction of Q1. Only a small leakage current, IIH, ows. The maximum value of IIH is 40 A for standard TTL (20 A for LSTTL). Since the low-impedance current path to the input pin has not been established, current ows to the base of Q2 via the forward-biased base-collector junction of Q1. This current is sufcient to saturate Q2. Open (Floating) TTL Input. An open-circuit TTL input acts as a logic HIGH, as illustrated by Figure 11.23. A TTL input relies on a logic LOW to establish a low-impedance current path from VCC to the input pin. If the input is open, this LOW is not present and current ows in the base-collector junction of the transistor, by default. This is the same current that ows under the HIGH-input condition. This HIGH is not stable; it can be converted to logic LOW by induced noise at the input pin. To avoid this uncertainty, an unused input should always be wired to a logic HIGH or LOW state. 524 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.23 LOW, HIGH, and Open TTL Inputs TTL Open-Collector Inverter Figure 11.24 shows the operation of the 7405 open-collector inverter. FIGURE 11.24 7405 Operation LOW Input. As was described above, a LOW input establishes a low-impedance path to ground, which draws current through the base-emitter junction of Q1. This action also prevents base current from owing in transistor Q2, causing it to be in cutoff mode and making IC2 0. Since IB3 is derived from IC2, IB3 0 and Q3 is cut off, making a high-impedance path between the collector and emitter of Q3. As was the case with the single-transistor inverter in Example 11.13, when IC3 0, then VO VCE VCC. (Since no current ows through the pull-up resistor, the voltage must be the same at both ends.) Output Y is HIGH. HIGH Input. When input A is HIGH, the base-emitter junction of Q1 does not have sufcient voltage across it to be forward-biased. Current ows through the base-collector junction of Q1, saturating Q2. Since Q2 is ON, current ows to the Q2 emitter and splits through the 1-k resistor and the base of Q3. The output transistor, Q3, turns ON, establishing a low-impedance current path from output Y to ground. Current is limited by the external pull-up resistor, which must be chosen to keep IOL at or under its rated value of 16 mA. VCE3 is about 0.2 V to 0.4 V. Output Y is LOW. TTL Open-Collector NAND Figure 11.25 shows one gate of a 7401 quadruple 2-input NAND gate with open-collector outputs. The circuit is the same as that of the 7405 inverter, except that the input transistor has a second emitter. Multiple-emitter transistors of this type are common in TTL circuits and can be modeled by the diode equivalent in Figure 11.25b. Figure 11.26 shows the response of the multiple-emitter input transistor to various combinations of logic levels. 11.7 Internal Circuitry of TTL Gates 525 FIGURE 11.25 TTL NAND with Open Collector Output FIGURE 11.26 Input Response of Multiple-Emitter Transistor If both inputs are LOW, the NAND acts exactly the same as the 7405 inverter with a LOW input. (A low-impedance path is created through a base-emitter junction.) Output Y is HIGH, provided an external pull-up resistor is connected to output. A partial truth table for this condition is: A B Y 0 0 1 If one input is LOW, the input acts the same as the inverter with a LOW input. The lowimpedance current path through the one grounded emitter prevents sufcient basecollector current from owing to forward-bias that junction. Output Y is HIGH if a pull-up resistor is connected to the output. A partial truth table is as follows: A B Y 0 1 1 0 1 1 526 C H A P T E R 1 1 Logic Gate Circuitry If both inputs are HIGH, the NAND circuit acts like the 7405 when its input is HIGH. (There is no base-emitter current path. A collector-emitter path is established by default.) Output Y is LOW. This condition can be represented by: A B Y 1 1 0 Combining all these conditions, we get the standard NAND truth table: A B Y 0 0 1 1 0 1 0 1 1 1 1 0 NOTE If one or more emitters of a TTL multiple-emitter input transistor is LOW, the input is a LOW equivalent. All emitters must be HIGH to make the transistor input a HIGH equivalent. These statements lead to the familiar NAND-gate descriptive sentences, illustrated by the gate symbols in Figure 11.27. a. At least one input LOW makes the output HIGH. b. Both inputs HIGH make the output LOW. FIGURE 11.27 DeMorgan Equivalent Forms of a NAND Gate SECTION 11.7A REVIEW PROBLEM 11.7 What are the two main functions of the pull-up resistor on the output of an opencollector gate? Open-Collector Applications KEY TERM Wired-AND A connection where open-collector outputs of logic gates are wired together. The logical effect is the ANDing of connected functions. A more common TTL output than the open collector is the totem pole output, which we will study later in this chapter. The totem pole output has its own internal pull-up circuit for HIGH outputs. 11.7 Internal Circuitry of TTL Gates 527 Gates with totem pole outputs cannot be used in all digital circuits. For example, opencollector gates are required when several outputs must be tied together, a connection called wired-AND. Totem pole outputs would be damaged by such a connection, since there is the possibility of conict between an output HIGH and LOW state. Open-collector outputs can also be used for applications requiring high current drive and for interfacing to circuits having supply voltages other than TTL levels. A special symbol dened by IEEE/ANSI Standard 91-1984, an underlined square diamond, is shown in Figure 11.28. This symbol is added to a logic gate symbol to indicate that it has an open-collector output. Other symbols, such as a star (*), a dot (), or the initials OC are also used. Wired-AND NOTE A wired-AND connection combines the outputs of the connected gates in an AND function. FIGURE 11.28 Open-Collector Symbols Shown for a NAND Gate (e.g., 7401) FIGURE 11.29 Three Inverters in a Wired-AND Connection Figure 11.29 shows three open-collector inverters connected in a wired-AND conguration. The output transistors of the inverters are shown in Figure 11.30, with different possible ON and OFF states. The only way output Y can remain HIGH is if all the transistors are in their OFF states, as in Figure 11.30c. This can happen only if the outputs of the inverters are all HIGH. This is the same as saying the outputs are ANDed together at Y. The Boolean expression for Y is: Y ABC ABC By DeMorgans theorem, the wired-AND connection of inverter outputs is equivalent to a NOR function. Because of this DeMorgan equivalence, the connection is sometimes called wired-OR. Figure 11.31 shows three NAND gates in a wired-AND connection. Since the output functions are ANDed, the Boolean expression for Y is: Y AB CD EF AB CD EF 528 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.30 Output Transistors of OpenCollector Inverters in a WiredAND Connection The resulting function is called AND-OR-INVERT. Normally this requires at least two types of logic gateAND and NOR. The wired-AND conguration can synthesize any size of AND-OR-INVERT network using only NAND gates. The wired-AND function is sometimes shown as an AND symbol around a soldered connection, as shown in Figure 11.31b. 11.7 Internal Circuitry of TTL Gates 529 FIGURE 11.31 NAND Gates in Wired-AND Connection High-Current Driver Standard TTL outputs have higher current ratings in the LOW state than in the HIGH state. Thus, open-collector outputs are useful for driving loads that need more current than a standard TTL output can provide in the HIGH state. There are special TTL gates with higher ratings of IOL to allow even larger loads to be driven. Typical loads would be LEDs, incandescent lamps, and relay coils, all of which require currents in the tens of milliamperes. EXAMPLE 11.14 Vcc 5V A 24 V Y 690 74LS07 FIGURE 11.32 Example 11.14 74LS07 High-Current Driver A 74LS07 hex buffer/driver contains six noninverting buffers whose outputs are opencollector, rated for IOLmax 40 mA and VOHmax 30 V. That is, even though there is no internal circuit to provide a logic HIGH at the output, the output transistor can withstand a voltage of up to 30 V without damage. Figure 11.32 shows a 74LS07 buffer driving an incandescent lamp rated at 24 V, with a resistance of 690 . Calculate the current that ows when the lamp is illuminated. What logic level at A turns the lamp on? Could the lamp be driven by a 74LS05 inverter? Why or why not? Solution From the 74LS07 data sheet in Appendix C, we see that VOL IOL 16 mA and VOL 0.7 V for IOL 40 mA. Assume the latter value. 0.4 V for By KVL: 24 V (IOL)(690 ) VOL 0 Thus, IOL (24 V 0.7 V)/690 33.8 mA Since the buffer is noninverting, and current ows when the output of the 74LS07 sinks current to ground (LOW), the lamp is on when A is LOW. A 74LS05 open-collector inverter would not be a suitable driver for the circuit for two reasons: its output is only designed to withstand 5.5 V and it can only sink a maximum of 8 mA. Value of External Pull-up Resistor The value of the pull-up resistor required by an open-collector circuit is calculated using manufacturers specications and the basic principles of circuit theory: Kirchhoffs voltage and current laws (KVL and KCL) and Ohms law. Figure 11.33 shows the circuit model for calculating the value of Rext. It accounts for the current requirements of the loads, the LOW-state output voltage, and current-sinking capacity of the open-collector gate. 530 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.33 Circuit Model for Pull-up Resistor Calculation NOTE The main rule in resistor selection is to keep the sum of currents into the open-collector output to less than the maximum rated value of IOL. IOL IR EXAMPLE 11.15 IR nIIL (VCC VOL /Rext Calculate the minimum value of the pull-up resistor for a 74LS05 inverter if the circuit drives ten 74LS00 NAND gate inputs. Solution From 74LS00 specs: For 10 gates: From 74LS05 specs: IIL 0.4 mA nIIL 10IIL 4 mA IOL 8 mA IR For IOL 8 mA, VOL 0.5 V Rext Use a 1.2-k or 1.5-k IOL nIIL 8 mA 4 mA 4 mA (VCC VOL)/IR (5 V 0.5 V)/4 mA 4.5 V/4 mA 1.125 k standard value resistor. SECTION 11.7B REVIEW PROBLEM 11.8 Calculate the minimum value of pull-up resistor required for a 74LS05 inverter if it drives one input of a 74LS00 NAND gate. What is the minimum standard value of this resistor? 11.7 Internal Circuitry of TTL Gates 531 Totem Pole Outputs KEY TERMS Totem pole output A type of TTL output with a HIGH and a LOW output transistor, only one of which is active at any time. Phase splitter A transistor in a TTL circuit that ensures that the LOW- and HIGH-state output transistors of a totem pole output are always in opposite phase (i.e., one ON, one OFF). Figure 11.34 shows one gate of a 7400 quadruple 2-input NAND with totem pole outputs. The circuit is the same as that for a 7401 open-collector NAND except for a transistor, resistor, and diode, which make up the HIGH-state output circuitry of the NAND gate. FIGURE 11.34 NAND Gate With Totem Pole Output The totem pole output, shown in Figure 11.34b, has separate transistors to switch the output to the HIGH state (Q4) and the LOW state (Q3). These transistors are switched by Q2, the phase splitter. Only one of them is ON at a time; the currents IOH and IOL never ow simultaneously. The portion of the circuit consisting of Q4, D3, and the 130- resistor replaces the external pull-up resistor required by the open-collector TTL output. Since the HIGH state is switched by its own transistor, we say that the circuit has an active pull-up. The main advantage of the totem pole output over the open collector is that it can change states faster. The external pull-up resistance needed in an open-collector circuit slows down the output switching by contributing to the RC time constant of the output. The HIGH-state transistor circuit, with its relatively low output impedance, reduces this time constant and thus improves switching speed. 532 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.35 NAND Gate Operation Figure 11.35 shows the operation of the 7400 NAND gate for HIGH and LOW input conditions. HIGH Input. When both inputs are HIGH, there is no low-impedance base-emitter current path in Q1. The base-collector junction of Q1 acts as a forward-biased diode. Base current ows in Q2, saturating the transistor. Sufcient current ows to Q3 to saturate it. Y is connected to ground, via the collector-emitter path of Q3. The output is LOW. LOW Input. Figure 11.35b shows input B of a 7400 NAND gate pulled LOW. The circuit operates the same way if A or both A and B are LOW. In this condition, a low-impedance path to ground is established through one of the base-emitter junctions of Q1. This pulls the base of Q2 LOW, causing it to be in cutoff 11.7 Internal Circuitry of TTL Gates 533 mode. No current ows through the collector-emitter path of Q2, so no base current ows in Q3; it is also cut off. Current ows through the 1.6-k resistor to the base of Q4, turning it ON. This connects the output, via Q4, D3, and the 130- resistor, to VCC. The output is HIGH. Q4 will not turn ON when Q3 is ON. We can nd out why by calculating VBE4 VD3. For Q4 to conduct, two pn junctions (D3 and the base-emitter junction of Q4) must be forward-biased. Thus, (VBE4 VD3) must be greater than 0.6 V 0.6 V 1.2 V. VBE4 VD3 VB4 VCE3 We can calculate VB4 by adding up voltage drops, as follows: VB4 VCE2 VBE3 0.2 V 0.7 V 0.9 V Q3 is saturated, thus: VCE3 0.2 V The difference between these voltages is: VB4 VCE3 0.9 V 0.2 V 0.7 V This is insufcient to forward-bias BE4 and D3. Q4 stays OFF. NOTE Without D3 in the circuit, VBE4 (VCE2 (0.2 V 0.7 V VBE3) VCE3 0.7 V) 0.2 V This is sufcient to saturate Q4, even when Q3 is ON. The diode is therefore necessary to keep Q4 OFF when Q3 is ON. Switching Noise KEY TERM Storage time Time required to transport stored charge away from the base region of a bipolar transistor before it can turn off. A totem pole output is an inherently noisy circuit. Noise is generated on the supply voltage line when the output switches from LOW to HIGH. When the output is in a steady HIGH or LOW state, Q3 and Q4 are always in opposite phase. The design of the totem pole output is such that when Q3 is ON, it is saturated, but when Q4 is ON, it operates in the transistors active, or linear, region. A saturated transistor takes longer to shut off than an unsaturated one due to storage time, the time required to transport stored charge away from the base region of the transistor. Thus, Q3 takes longer to turn off than Q4. When a totem pole output is LOW, Q3 is ON and Q4 is OFF. When the output changes state, Q4 turns ON before Q3 can turn OFF, due to the storage time of Q3. For a few nanoseconds, both transistors are ON. This condition momentarily shorts VCC to ground, causing a surge of supply current, as shown in Figure 11.36. The inductance of the power line produces a corresponding spike proportional to the instantaneous rate of change of the supply current (v L di/dt, where L is the power line inductance and di/dt is the instantaneous rate of change of supply current). These spikes on the supply voltage line can cause real problems, especially in synchronous circuits. They often cause erroneous switching that is nearly impossible to troubleshoot. The best cure for such problems is prevention. 534 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.36 Spikes on Power Line During LOW-to-HIGH Transition of Totem Pole Output Figure 11.37 shows the addition of a decoupling capacitor to a totem pole output to eliminate switching spikes. A low-inductance capacitor of about 0.1 F is placed between the VCC and ground pins of the chip to be decoupled. This capacitor offsets the power line inductance and acts as a low-impedance path to ground for high-frequency noise (i.e., spikes). Since a capacitor is an open circuit for low frequencies, the normal DC supply voltage is not shorted out. FIGURE 11.37 Decoupling the Power Supply 11.7 Internal Circuitry of TTL Gates 535 NOTE It is important that the capacitor be placed physically close to the decoupled chip. Inductance of the power line accumulates with distance, and if the capacitor is far away from the chip (say, at the end of the circuit board), the decoupling effect of the capacitor is lost. FIGURE 11.38 Placement of Decoupling Capacitor (Low-Frequency Designs) It is not necessary to decouple every chip on a circuit board for designs operating at relatively low frequencies ( 1 MHz). In such cases, one capacitor for every two ICs is enough. The capacitor should be connected between VCC and ground of the same chip, as shown in Figure 11.38. For high-frequency designs, use one capacitor per IC, as shown in Figure 11.39. Connect directly to power and ground traces on a printed circuit board, as close as possible to the chip being decoupled. FIGURE 11.39 Placement of Decoupling Capacitors (High-Frequency Designs) Connection of Totem Pole Outputs Totem pole outputs must never be connected together. As shown in Figure 11.40, the problem occurs when two connected outputs are in opposite states. The active pull-up consisting of Q4, D3, and the 130- resistor is designed to supply current to about 10 TTL inputs, each having a large input impedance. It will not withstand the current that ows when the output is forced to ground through the LOW output transistor of another gate. Under this condition about 30 to 55 mA will ow through Q4A and Q3B. This exceeds the ratings of the outputs in both the HIGH and LOW state and will cause damage to the outputs over time. The outputs will probably withstand this sort of abuse for several minutes, but eventually will be damaged. 536 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.40 Totem Poles Connected Together SECTION 11.7C REVIEW PROBLEM 11.9 A totem pole output is likely to be damaged when shorted to ground. Why? Tristate Gates KEY TERM Tristate output An output having three possible states: logic HIGH and LOW, and a high-impedance state, in which the output acts as an open circuit. Figure 11.41 shows the circuits of two TTL inverters with tristate outputs. In addition to the usual binary states of HIGH and LOW, the output of the tristate inverter can also be in a high-impedance (Hi-Z) state. This state occurs when both Q3 and Q4 are OFF. The electrical effect is to produce an open circuit at the output, which is neither HIGH nor LOW. The output of a tristate gate combines advantages of a totem pole output and an opencollector output. Like the totem pole output, it has an active pull-up with lower output impedance and faster switching than an open collector. Like the open collector, we can connect several outputs together, provided only one output is active at a time. Input G, the gating or enable input, controls the gate. When G is active, the gate acts as an ordinary inverter. When inactive, the gate is in the high-impedance state. Table 11.6 summarizes the operation of the tristate inverters in Figure 11.41. The tristate inverter in Figure 11.41a is enabled by a HIGH at the G input. The circuit is the same as a 7400 NAND gate with two exceptions: (1) an extra diode goes from the base of Q4 to G, and (2) G connects directly to one of the emitters of Q1. When G 0, Q1 acts as though there was a LOW at a NAND gate input. In a 7400 NAND circuit, this causes Q2 and Q3 to be in cutoff mode. Due to the opposite states of the emitter and collector in Q2, Q4 would normally be ON. Instead, the LOW at G pulls the base of Q4 LOW through the extra diode. Thus, both Q3 and Q4 are OFF. When G 1, the G emitter of Q1 acts like a HIGH NAND input. By the enable/ inhibit rules of a NAND gate, Y A. The additional diode prevents the HIGH at G from activating Q4. The circuit in Figure 11.41b works the same way, except for the opposite sense of the activating input. This opposite active level is achieved by using an open-collector inverter, consisting of Q5, Q6, and Q7, at input G. 11.7 Internal Circuitry of TTL Gates FIGURE 11.41 Tristate Inverters Table 11.6 Truth Tables of Tristate Inverters G A Y G A Y 0 0 1 1 0 1 0 1 Hi-Z Hi-Z 1 0 0 0 1 1 0 1 0 1 1 0 Hi-Z Hi-Z 537 538 C H A P T E R 1 1 Logic Gate Circuitry SECTION 11.7D REVIEW PROBLEM 11.10 Why is the diode from the base of Q4 necessary in the tristate inverters in Figure 11.41? Other Basic TTL Gates Other TTL gates are similar to the NAND and inverter gates we have already examined. A signicant variation is the OR/NOR circuit, which has a different input conguration than the AND/NAND/inverter type gates. 7402 NOR Gate Figure 11.42 shows one gate of a 7402 quadruple 2-input NOR gate package. The difference between this gate and the 7400 NAND gate is the structure of the inputs. The NOR gate does not use the multiple-emitter transistor, but rather an individual transistor (Q1 or Q2) for each input. There are two phase splitters (Q3 and Q4), which are paralleled, emitterto-emitter and collector-to-collector. FIGURE 11.42 7402 NOR Gate Circuit If either Q3 or Q4 is enabled by a HIGH at its corresponding input, it will turn on Q5, making the output LOW. If both gate inputs are LOW, both Q3 and Q4 are in cutoff mode, and so is Q5. The output is HIGH through Q6. Table 11.7 shows the truth table and the states of the transistors for this gate. It is not strictly correct to refer to Q1 and Q2 as being ON or OFF, since there is current owing in these transistors regardless of whether the inputs are HIGH or LOW. Let us dene the ON 11.8 Internal Circuitry of MOS Gates 539 Table 11.7 7402 NOR Function and Truth Table A B Q1 Q2 Q3 Q4 Q5 Q6 Y 0 0 1 1 0 1 0 1 ON ON OFF OFF ON OFF ON OFF OFF OFF ON ON OFF ON OFF ON OFF ON ON ON ON OFF OFF OFF 1 0 0 0 state of an input transistor as the condition where the base-emitter junction is conducting (LOW input). If the base-collector junction conducts, we will consider the transistor OFF (HIGH input). 7408 AND Gate and 7432 OR Gate It may not be obvious why we would choose to study NAND and NOR gates before AND and OR. After all, AND and OR are the more basic logic functions. Electrically, it works the other way around. The simplest TTL circuit is the NAND/inverter, followed by the NOR. AND and OR gates are more complex since they are based on the NAND and NOR and require an extra inverter stage. FIGURE 11.43 7408 AND Gate Figure 11.43 shows the circuit of a 7408 AND gate, and Figure 11.44 shows a 7432 TTL OR gate circuit. Each of these gates is like its NAND/NOR counterpart, except for an additional inverter, implemented by Q3 in the AND gate and Q5 in the OR gate. Tables 11.8 and 11.9 show the transistor function and truth table for each gate. In keeping with the convention established for the NOR function table, an input transistor with a conducting base-emitter junction is considered ON. 540 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.44 7432 OR Gate Table 11.8 7408 AND Function and Truth Table A B Q1 Q2 Q3 Q4 Q5 Q6 Y 0 0 1 1 0 1 0 1 ON ON ON OFF OFF OFF OFF ON OFF OFF OFF ON ON ON ON OFF ON ON ON OFF OFF OFF OFF ON 0 0 0 1 Table 11.9 7432 OR Function and Truth Table A B Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Y 0 0 1 1 0 1 0 1 ON ON OFF OFF ON OFF ON OFF OFF OFF ON ON OFF ON OFF ON OFF ON ON ON ON OFF OFF OFF ON OFF OFF OFF OFF ON ON ON 0 1 1 1 SECTION 11.7E REVIEW PROBLEM 11.11 Why are noninverting gates more complex than inverting gates? 11.8 Internal Circuitry of MOS Gates KEY TERMS MOSFET Metal-oxide-semiconductor eld effect transistor. A MOSFET has three terminalsgate, source, and drainwhich are analogous to the base, emitter, and collector of a bipolar junction transistor. 11.8 Internal Circuitry of MOS Gates 541 Enhancement-mode MOSFET A MOSFET that creates a conduction path (a channel) between its drain and source terminals when the voltage between gate and source exceeds a specied threshold level. Substrate The foundation of n- or p-type silicon on which an integrated circuit is built. n-channel enhancement-mode MOSFET A MOSFET built on a p-type substrate with n-type drain and source regions. An n-type channel is created in the psubstrate during conduction. p-channel enhancement-mode MOSFET A MOSFET built on an n-type substrate with p-type drain and source regions. During conduction, a p-type channel is created in the n-substrate. CMOS A logic family based on the switching of n- and p-channel (complementary) enhancement-mode MOSFETs. All the logic circuits we have examined so far have been based on the switching of bipolar junction transistors. Another major logic family, CMOS, is based on the switching of metal-oxide-semiconductor eld effect transistors, or MOSFETS. There are two major types of MOSFETs, called depletion-mode and enhancementmode MOSFETs. We will concentrate on the enhancement-mode devices, as they are the type used in the manufacture of digital ICs. Details of the differences between depletionand enhancement-mode transistors can be found in any good textbook on electronic devices. MOSFETs can be categorized in another way: as n-channel and p-channel devices, much as bipolar transistors are classied as NPN or PNP. CMOS logic is constructed from both n- and p-channel MOSFETs. CMOS (Complementary MOS) refers to the opposite, or complementary, operation of n- and p-channel transistors. MOSFET Structure Figure 11.45 shows the structure and symbol of an n-channel enhancement-mode MOSFET in an integrated circuit. The device is built on a substrate of p-type silicon, which has a deciency of electrons in its structure. The drain and source regions are wells of n-type silicon, which has an excess of electrons. The drain and source are roughly equivalent to the emitter and collector of a bipolar transistor. FIGURE 11.45 n-Channel MOSFET The substrate is shown as a terminal with an arrow. The arrow points in for an nchannel device and out for a p-channel device. In nearly all cases, the substrate is shorted to the source terminal. (Some exceptions to this general rule will be examined when we look at circuits of CMOS gates.) 542 C H A P T E R 1 1 Logic Gate Circuitry The gate terminal is similar to the base of a bipolar transistor in that it controls the ow of current between the drain and source. The difference is that a MOSFET uses gate voltage to control drain current, whereas a bipolar transistor uses base current to control collector current. The gate consists of an insulating layer of silicon dioxide (SiO2) and a layer of metal over the substrate between the drain and source. This gate structure is what gives the MOSFET its name (metal-oxide-semiconductor eld effect transistor). NOTE The oxide layer of the gate structure is subject to damage if excessive voltage (greater than about 100 V) is applied. This especially includes static electricity, or electrostatic discharge (ESD). There are standard precautions for working with MOS devices that should be followed carefully. Most important are ensuring that MOS devices are stored in antistatic or conducting material, that work surfaces are not likely to generate static, that unused inputs are not left open or oating, that you avoid touching the pins of a MOS device, and that if you must handle a MOS IC, you discharge any static on your person before touching it. A conductive wrist strap with a high series resistance to ground (about 1 M ) is often worn to reduce static. The high resistance protects the operator from shock injury in the event of a short circuit. A list of handling precautions is included in Appendix D. SECTION 11.8A REVIEW PROBLEM 11.12 Why are MOSFET circuits particularly susceptible to static damage? Bias Requirement for MOS Transistors KEY TERMS Ohmic region The MOSFET equivalent of saturation. When a MOSFET is biased ON, it acts like a relatively low resistance, or ohmically. n-type inversion layer The conducting layer formed between drain and source when an enhancement-mode n-channel MOSFET is biased ON. Also referred to as the channel. Threshold voltage VGS(Th) The minimum voltage between gate and source of a MOSFET for the formation of the conducting inversion layer (channel). When we studied the operation of TTL gate circuits, we discovered that, for the most part, the bipolar transistors in the gates operated either in the saturation or the cutoff regions. In MOStype gates, we make use of two similar operating regions in the constituent MOSFETs: 1. The cutoff region is the same as that for a bipolar transistor. Under this condition, there is a very high impedance between the drain and source terminals of the MOSFET. 2. The ohmic region is analogous to the saturation region of a bipolar transistor. In this state, there is a relatively low resistance between the MOSFETs drain and source. The MOSFET switches between cutoff and ohmic regions when the voltage between gate and source, VGS, is less than or greater than a value called the threshold voltage. The abbreviation for this voltage is VGS(Th); its value is between 1 and 5 volts, typically 1.5 V. Figure 11.46 shows an n-channel MOSFET operating in the cutoff region. The gatesource voltage, VGS is less than VGS(Th). There is no conduction between the drain and source. The resistance, RDS(OFF), between drain and source is very large, typically in the thousands of megohms. 11.8 Internal Circuitry of MOS Gates 543 FIGURE 11.46 n-Channel MOSFET in Cutoff Region When the value of VGS increases and exceeds the threshold voltage, the MOSFET enters the ohmic region. A conduction channel, called the n-type inversion layer, is created in the p-substrate of the transistor, as shown in Figure 11.47. This layer is like an articially created region of n-type silicon, which allows conduction between the drain and source, provided there is sufcient potential difference between them. FIGURE 11.47 Channel Formation in an n-Channel MOSFET Figure 11.48 shows a MOSFET operating in the ohmic region. RDS(ON), the equivalent resistance of a MOSFET in the ohmic region, is typically around 500 to 2 k . The drainsource current, IDS, is determined by Ohms law: IDS VCC/RDS(ON). FIGURE 11.48 n-Channel MOSFET in Ohmic Region 544 C H A P T E R 1 1 Logic Gate Circuitry The operation of a p-channel MOSFET is similar, but with polarities reversed. If VGS(Th) is 1.5 V for an n-channel device, an equivalent p-channel MOSFET has a threshold voltage of 1.5 V. VGS 1.5 V turns ON an n-channel transistor; VGS 1.5 V turns ON a p-channel device. Figure 11.49 summarizes the bias requirements for n- and p-channel enhancementmode MOSFETs. FIGURE 11.49 Bias Requirements of n- and p-Channel MOSFETs CMOS Inverter Figure 11.50 shows the circuit of a CMOS inverter, which consists of one n-channel and one p-channel MOSFET. Recall the bias conditions of the two transistors: n-channel: threshold voltage, VGS(Th) 1.5V ON when VGS VGS(Th) (e.g., VGS VCC) OFF when VGS VGS(Th) (e.g., VGS 0 V) p-channel: threshold voltage, VGS(Th) 1.5 V ON when VGS VGS(Th) (e.g., VGS VCC) OFF when VGS VGS(Th) (e.g., VGS 0 V) 11.8 Internal Circuitry of MOS Gates 545 FIGURE 11.50 CMOS Inverter The operation of the CMOS inverter, and any other CMOS gate, depends on arranging the bias conditions of each complementary pair of transistors so that they are always in opposite states. Whenever Q1 is ON, Q2 is OFF, and vice versa. Figure 11.51 shows how this is accomplished. Assume that a LOW input is at ground potential and that a HIGH input is equal to VCC. FIGURE 11.51 Operation of CMOS Inverter When input A is LOW, the gate voltage of Q2 is the same as its source voltage; VGS2 0 and Q2 is OFF. This places a high-impedance path between output Y and ground. At the same time, the gate voltage of Q1 is 0 V and its source voltage is VCC; VGS1 VG1 VS1 0 VCC VCC. (The p-channel transistor, Q1, is drawn upside down to make the complementary pair symmetrical.) Q1 is ON, forming a low-impedance path from VDD to the output Y. Output Y is HIGH. When input A is HIGH, the gate-source voltage of the n-channel transistor is VCC, causing Q2 to turn ON. The gate of Q1 is also at VCC. Since the source of the p-channel 546 C H A P T E R 1 1 Logic Gate Circuitry transistor is at VCC, VGS1 VG1 VS1 VCC VCC 0 V; Q1 is OFF. This combination creates a high impedance between VCC and output Y and a low-impedance path from output Y to ground, as shown in Figure 15.51b. Output Y is LOW. CMOS NAND/NOR Gates CMOS NAND and NOR gates are constructed from complementary pairs of MOSFETs. Each MOSFET pair has an n-channel transistor that is turned ON by a HIGH input and a p-channel transistor that is turned ON by a LOW input. The n-channel devices switch the output to ground; the p-channel ones switch the output to VCC. NAND and NOR functions are generated by arranging the MOSFET drain-source paths in series (AND) and parallel (OR) congurations. In Figure 11.52, we see the DeMorgan equivalent forms of a NAND gate. Each form illustrates an aspect of NAND operation that can be described with a brief sentence and implemented by a MOSFET circuit. The combination of forms describes the complete operation of the device. Figure 11.52a states that both NAND inputs must be HIGH to make the output LOW. A logic HIGH activates an n-channel MOSFET. The gate output is switched to ground by an n-channel MOSFET. Thus, the drain-source paths of two n-channel transistors must be connected in series to make the output LOW under the stated conditions. Figure 11.52b shows that the NAND output is HIGH if either input is LOW. A pchannel transistor will turn ON when its gate is LOW and will switch a HIGH to the output. A parallel combination of p-channel MOSFETs will satisfy these conditions. FIGURE 11.52 NAND Functions of MOSFETs The stated conditions are combined in the CMOS NAND circuit shown in Figure 11.53. Transistors Q1 and Q4 form a complementary pair, as do Q2 and Q3. When A and B are both HIGH, Q1 and Q2 are both OFF, cutting off the connection between VCC and output Y. Q3 and Q4 are both ON, supplying a low-impedance path from output Y to ground, making the output LOW. This is shown in the partial truth table in Table 11.10. When A is LOW and B is HIGH, Q1 is ON. This creates a path from VCC to output Y. At the same time, Q4 is OFF. This cuts the Y-to-ground path through the n-channel 11.8 Internal Circuitry of MOS Gates 547 FIGURE 11.53 CMOS NAND Gate Table 11.10 Partial CMOS NAND Function and Truth Table Table 11.11 Partial CMOS NAND Function and Truth Table A B Q1 Q2 Q3 Q4 Y A B Q1 Q2 Q3 Q4 Y 1 1 OFF OFF ON ON 0 0 0 1 0 1 0 ON ON OFF ON OFF ON OFF ON OFF OFF OFF ON 1 1 1 MOSFETs; the series path from output to ground is broken. One parallel path from VCC to output has been established. Output Y is HIGH. The remaining input combinations also make the output HIGH, as shown in Table 11.11. They do so by breaking the n-channel path from output to ground and enabling one or both p-channel paths from VCC to output. Each MOSFET in a logic circuit must have its own independent substrate bias. This ensures that the transistor will operate as expected when a logic HIGH or LOW is applied to its gate. Normally, the substrate of a MOSFET is shorted to its source terminal. If a MOSFET source terminal is isolated from VCC or ground, the substrate must be biased separately. For example, in the NAND gate in Figure 11.53, the substrate of Q3 connects directly to ground. NOR gates are similar to NANDs in construction. Figure 11.54 shows the DeMorgan equivalent forms of the NOR function and the MOSFET implementations of each aspect of the gate operation. FIGURE 11.54 NOR Functions of MOSFETs 548 C H A P T E R 1 1 Logic Gate Circuitry When either input is HIGH, the output is LOW. This function is implemented by two parallel n-channel MOSFETs. Both inputs must be LOW to make the output HIGH, which implies a series connection of two p-channel transistors. The complete NOR gate circuit is shown in Figure 11.55. (Note that the substrate of Q2 is connected directly to VCC to ensure that it has its own bias voltage.) FIGURE 11.55 CMOS NOR Gate As was the case with the NAND circuit, transistors Q1 and Q4 form a complementary MOSFET pair. Transistors Q2 and Q3 form the second pair. When both inputs are LOW, both p-channel transistors are ON. This creates a lowimpedance path from VCC to output Y. The n-channel transistors, Q3 and Q4, are both OFF. This isolates the output from ground. Output Y is HIGH. Table 11.12 shows the MOSFET states under this condition. Table 11.12 Partial CMOS NOR Function and Truth Table A B Q1 Q2 Q4 Q4 Y 0 0 ON ON OFF OFF 1 If either input is HIGH, one or both of the p-channel transistors will turn OFF. This action breaks the path from VCC to output Y. The complementary n-channel transistor will turn ON. This creates a low-impedance path from output Y to ground. Output Y is LOW. Table 11.13 summarizes the possible input conditions and MOSFET states when the NOR output is LOW. Table 11.13 Partial CMOS NOR Function and Truth Table A B Q1 Q2 Q3 Q4 Y 0 1 1 1 0 1 ON OFF OFF OFF ON OFF ON OFF ON OFF ON ON 0 0 0 11.8 Internal Circuitry of MOS Gates 549 FIGURE 11.56 CMOS AND Gate FIGURE 11.57 CMOS OR Gate CMOS AND and OR Gates Figures 11.56 and 11.57 show the circuits of CMOS AND and OR gates. The AND gate is the same as the NAND circuit, except for the output inverter section constructed from Q5 and Q6. The OR gate is the same as the NOR with an output inverter section. SECTION 11.8B REVIEW PROBLEM 11.13 Why is the source of a p-channel MOSFET connected to VCC in a CMOS gate? CMOS Transmission Gate Figure 11.58 shows the circuit of a CMOS transmission gate. A CMOS transmission gate, or analog switch, conducts in both directions. This makes it possible to enable or inhibit 550 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.58 CMOS Transmission Gate time-varying analog signals having both positive and negative values. Conduction takes place between the input and output terminals through MOSFETs Q1 and Q2. Positive current (left to right in the diagram) ows through Q2, and negative current (right to left) ows through Q1. Two inverters, consisting of the Q3/Q4 and Q5/Q6 pairs of MOSFETs, control the ON/OFF state of the circuit. When CONTROL 1, the inverters bias both Q1 and Q2 ON, allowing them to conduct. When CONTROL 0, the circuit inhibits conduction between input and output. The substrate terminal of Q1 is connected, not to the source terminal of that transistor, but directly to VCC thus providing the correct bias to Q1 in the ON state. A particular device with this function is the 74HC4066 quad analog switch, whose circuit symbol is shown in Figure 11.59. When the CONTROL input is HIGH, analog and digital signals can pass between the bidirectional input terminals. FIGURE 11.59 One of Four Analog Switches From 74HC4066 EXAMPLE 11.16 Figure 11.60 shows a circuit where the analog switches in a 74HC4066 package are used to control the selection and muting of two pairs of speakers in a stereophonic audio system. Briey explain the circuit operation. Solution The audio signal to each speaker is passed or blocked by a CMOS transmission gate. The speakers are paired into A and B groups. Each pair has a left and a right channel speaker. The same logic gate controls both speakers of each group. The Select A switch enables the A speakers when it is open (logic HIGH). The Select B switch enables the B speakers when it is open. The Mute Toggle ip-op mutes (disables) both sets of speakers when Q is LOW. This action inhibits both AND gates, making all transmission gate CONTROL inputs LOW. The mute function toggles ON and OFF with each push of the Mute ON/OFF switch. 11.9 FIGURE 11.60 Example 11.16 74HC4066 Analog Switches as Audio Selectors TTL and CMOS Variations 551 11.9 TTL and CMOS Variations Standard (74NN) TTL and CMOS represented the two main standards of logic design for many years, and their inuence is still visible in other, more advanced types of logic. The changes that have been made in newer logic families are not fundamental changes in the working concepts, but improvements to the specications, particularly switching speed and power dissipation. 552 C H A P T E R 1 1 Logic Gate Circuitry TTL Logic Families KEY TERMS Schottky barrier diode A specialized diode with a forward drop of about 0.4 V. Schottky transistor A bipolar transistor with a Schottky diode across its basecollector junction, which prevents the transistor from going into deep saturation. Schottky TTL A series of unsaturated TTL logic families based on Schottky transistors. Schottky TTL switches faster than standard TTL due to decreased storage time in its transistors. Speed-power product A measure of a logic circuits efciency, calculated by multiplying its propagation delay by its power dissipation. Unit: picojoule (pJ) Probably the most important development in TTL technology was the introduction, in the early 1970s, of the Schottky barrier diode into circuit designs. This made possible the rst family of nonsaturated bipolar logic, with its resultant improvement in switching speed. Figure 11.61 shows a bipolar transistor with a Schottky diode connected across its base and collector and the equivalent circuit symbol of this combination. We call this conguration a Schottky transistor and logic devices using such transistors Schottky TTL. FIGURE 11.61 Schottky Transistor Normally the base-collector junction of a saturated bipolar transistor has a drop of about 0.5 volts, as shown in Figure 11.62. The Schottky diode clamps this junction voltage to about 0.4 volts. This keeps the transistor out of deep saturation in its ON state. The base region of the Schottky-clamped transistor holds less charge than does a standard bipolar transistor. Its storage time, the time required to dissipate base charge upon turn-off, is substantially reduced. The transistor can switch faster with the Schottky diode than without. FIGURE 11.62 ON-State Operating Voltages of Bipolar Transistors Figure 11.63 shows the circuits of the 74S00 Schottky and 74LS00 low-power Schottky NAND gates. Compare these circuits to each other and to the 7400 standard TTL NAND gate in Figure 11.33. 11.9 TTL and CMOS Variations 553 FIGURE 11.63 Schottky TTL Circuits In the 74S00 circuit, Q1 acts as the input and Q2 as the phase splitter, as in the 7400 gate. The HIGH output circuit consists of Q3 and Q4 connected as a modied Darlington pair. When Q2 is OFF (at least one input is LOW), enough base current ows in Q3 to turn it on. Collector-emitter current in Q3 turns on Q4, making the output HIGH. When Q2 is ON (both inputs are HIGH), the base of Q3 is pulled LOW, turning it OFF. Sufcient current ows in the base of Q5 to turn it ON. The resultant current through Q5 554 C H A P T E R 1 1 Logic Gate Circuitry will turn on Q6, making the output LOW. A similar analysis can be made for the 74LS00 gate. One difference between the 74S00 and 74LS00 circuits is the size of the resistors; the LS device has larger resistors. Less current ows in the gate circuit. This reduces power dissipation of the chip. The larger resistor values also slow down the switching times of the various transistors by increasing the RC time constants of the circuit elements. Speed-Power Product One measure of logic circuit efciency is its speed-power product, calculated by multiplying switching speed and power dissipation, usually expressed in picojoules (pJ). (The joule is the SI unit of energy. Power is the rate of energy used per unit time.) A major goal of logic circuit design is the reduction of a devices speed-power product. Table 11.14 shows the propagation delay, supply current, and speed-power product for a NAND gate in six TTL families: standard TTL (7400), Schottky (74S00), low-power Schottky (74LS00), fast TTL (74F00), advanced Schottky (74AS00), and advanced lowpower Schottky (74ALS00). Table 11.14 TTL Speed and Power Specications 7400 74LS00 74S00 74F00 74ALS00 74AS00 tpLH (max) tpHL (max) 22 ns 15 ns 15 ns 15 ns 4.5 ns 5 ns 6 ns 5.3 ns 11 ns 8 ns 4.5 ns 4 ns ICCH/4 (max) ICCL/4 (max) 2 mA 5.5 mA 0.4 mA 1.1 mA 4 mA 9 mA 0.7 mA 2.6 mA 0.21 mA 0.75 mA 0.8 mA 4.35 mA Speed-power product (per gate) 605 pJ 82.5 pJ 225 pJ 78.0 pJ 41.25 pJ 97.9 pJ The speed-power product shown is the worst-case value. This is calculated by multiplying the largest value of ICC/4 by the slowest switching speed by 5 volts for each family. We use ICC/4 because ICC is specied per chip (four gates). A faster switching speed results in an overall increase in speed-power product, other factors being equal. For example, the speed-power product of either advanced Schottky family is lower than that of the LS and S families. However, the ALS series (the slower advanced Schottky family) has a lower speed-power product than the AS series. The smaller resistors used to speed up output switching imply a proportional drop in propagation delay (higher speed) but an increased supply current. Power dissipation increases in proportion to the square of the supply current, thus offsetting the effect of the increased switching speed. CMOS Logic Families The CMOS gates we have looked at in this chapter are simpler than most gates actually in use. There are two main families of CMOS devices: metal-gate CMOS, and silicon-gate, or high-speed, CMOS. Metal-Gate CMOS There are two main variations on this type of circuit, designated B-series and UB-series CMOS. Most CMOS gates are B-series; UB-series is available in a limited number of inverting-type gates, such as inverters and 2-, 3-, and 4-input NAND and NOR gates. Figure 11.64 shows the difference in the two congurations. Figure 11.64b shows one gate from a 4011UB quadruple 2-input NAND package. Its circuit is the same as the NAND conguration examined in Section 11.8. Power supply voltages in metal-gate CMOS are designated VDD (power) and VSS (ground). High-speed, or silicon-gate, CMOS uses the same power supply designations as TTL: VCC and ground. 11.9 TTL and CMOS Variations 555 FIGURE 11.64 Metal-Gate CMOS Circuits The B-series conguration of this circuit has two additional inverter outputs in cascade with the NAND logic. (The same gate becomes an AND when we add a third output inverter.) The inverter conguration is actually an amplier; extra inverter stages provide additional gain and increase noise margin by allowing the circuit to accept smaller input signals. CMOS gates are sometimes used in analog applications, such as oscillators. The UBseries gates, with their lower gain, are more desirable for such applications. Due to its low switching speed, metal-gate CMOS is rarely used in new designs. High-Speed CMOS KEY TERM High-speed (silicon-gate) CMOS A CMOS logic family with a smaller device structure and thus higher speed than standard (metal-gate) CMOS. Metal-gate CMOS has been considered a nearly ideal family for logic designs, with its high noise immunity, low power consumption, and exible power supply requirements. Unfortunately, its propagation delay times, typically 10 to 20 times greater than those of equivalent TTL devices, are just not fast enough for use in modern microprocessor-based systems. High-speed CMOS was developed to address the problem of switching speed, while striving to keep the other advantages of CMOS. This is achieved by using MOSFETs with a polysilicon material for the gate, rather than metal, as in standard CMOS. Because of advantages gained in this manufacturing process, each transistor is physically smaller and has a lower gate capacitance than metal-gate MOSFETs. Both these factors contribute to a lower propagation delay for the logic gate circuit. Several subfamilies of high-speed CMOS are available for various logic and linear applications, designated by the labels 74HCNN, 74HC4NNN, 74HCTNN, and 74HCUNN. The 74HCNN series duplicates equivalent LSTTL functions in packages having identical pinouts to LSTTL. The 74HC4NNN replaces CMOS functions pin for pin. Both these series have CMOS-equivalent input and output levels, within the power supply limits (2.0 V to 6.0 V) of high-speed CMOS. 556 C H A P T E R 1 1 Logic Gate Circuitry Table 11.15 CMOS Speed and Power Specications Metal-Gate CMOS 4011B 4011UB Advanced High-Speed CMOS High-Speed CMOS 74HC00A 74HCT00A 74HCU04 15 ns 180 ns 74VHC00 74VHCT00 Low-Voltage CMOS 74LVX00 74LCX00 19 ns 14 ns 5.5 ns 6.9 ns 6.2 ns 5.2 ns tpLH, tpHL 250 ns IDD or ICC 0.25 A 0.25 A 0.25 A 0.25 A 0.17 A 0.5 A 0.5 A 0.5 A 0.25 A VDD or VCC 5.0 V 5.0 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 3.3 V 3.3 V PD (1 MHz) 1.5 mW 1.5 mW 446 W 304 W 303 W 385 W 385 W 208 W 272 W Speed-power product (quiescent) 0.31 pJ 0.23 pJ 0.017 pJ 0.021 pJ 0.011 pJ 0.012 pJ 0.015 pJ 0.010 pJ 0.043 pJ Speed-power product (1 MHz) 375 pJ 270 pJ 6.68 pJ 5.77 pJ 4.25 pJ 2.12 pJ 2.65 pJ 1.29 pJ 1.42 pJ The 74HCTNN devices are designed to be directly compatible with LSTTL devices, and thus have LSTTL-equivalent inputs and CMOS-equivalent outputs. 74HCUNN devices have no output buffers, like the 4000 UB-series standard CMOS devices. The 74HCU devices are used, as are the 4000UB devices, for linear applications such as oscillators and multivibrators. Table 11.15 shows the relative performance of the various CMOS families. As in TTL, the 2-input NAND gate is used as the standard, except for the HCU family, where this gate is not available. The quiescent speed-power product of all CMOS families is much smaller than that of any TTL family. The high-speed CMOS families have propagation delays comparable to those of LSTTL. The power dissipation of a CMOS device increases directly with frequency. The speed-power product also goes up with higher frequencies. Table 11.15 shows CMOS speed-power product for a switching speed of 1 MHz. At these speeds, B-series CMOS has no advantage over the common TTL families in terms of its efciency. It still has the edge on TTL with respect to noise immunity and power supply exibility. SECTION 11.9 REVIEW PROBLEM 11.14 Assuming that power dissipation of a 74HC00A NAND gate is directly proportional to its switching frequency, what is the speed-power product of the gate at 2 MHz, 5 MHz, and 10 MHz? SUMMARY 1. TTL (transistor-transistor logic) and CMOS (complementary metal-oxide semiconductor) are two major logic families in use today. TTL is constructed from bipolar junction transistors. CMOS is made from metal-oxide-semiconductor eld effect transistors (MOSFETs). 2. The main CMOS advantages include low power consumption, high noise immunity, and a exibility in choosing a power supply voltage. 3. The main advantages of TTL include relatively high switching speed and an ability to drive loads with relatively high current requirements. 4. TTL and high-speed CMOS logic families are alphabetically designated by a part number having the form 74XXNN, where XX is the family and NN is a numeric logic function designator. (For example, 74HC00 and 74LS00 have the same logic function, but are from different logic families.) Summary 5. 6. 7. 8. 9. 10. 11. Devices from earlier CMOS families are designated by a part number of the form 4NNNB or 4NNNUB. Devices of the same logic family generally have the same electrical characteristics. Data such as input/output voltages and currents are specied in manufacturers datasheets. Only the maximum or minimum values of these parameters should be used as design information. Typical values should be regarded as information only. The time required for an a logic circuit output to change as a result of an input change is called propagation delay. Propagation delay is specied as tpLH when an output changes from LOW to HIGH and tpHL when the output goes from HIGH to LOW. Propagation delay in a circuit is the sum of all delays in the slowest input-to-output path. Gates whose outputs do not change are ignored in the calculation. Fanout is the maximum number of device inputs that can be driven by the output of a logic device. The actual value of output current in a driving gate is the sum of all load currents, which are the input currents of the load gates. For n loads, IOL IIL1 IIL2 IILnL nL IIL and IOH IIH1 IIH2 IIHnH nHIIH 12. The fanout of the driving gate in the LOW and HIGH states can be calculated as: nL IOL IIL and nH IOH IIH 13. If the fanout is unequal for LOW and HIGH states, the smaller value must be used. 14. If the fanout of a gate is exceeded, the output voltage of the driving gate will drop if the output is HIGH and rise if the output is LOW. This move away from the nominal value degrades the general performance of the driving gate. 15. Power supply current (ICC), and therefore power dissipation (PD), of a TTL device depends on the number of outputs in the device that are HIGH or LOW. PD VCC ICC nH nL ICCH ICCL for a device with n outputs, nH of VCC n n which are HIGH and nL of which are LOW. 16. CMOS devices draw most current from the power supply when its outputs are switching and very little when they are static. Power dissipation of a high-speed CMOS device with n outputs has a static and a dynamic component, given by: PD (CL CPD)V2 f CC VCC ICC n At high frequencies ( 1 MHz), the quiescent current can be neglected. 17. Noise margin is a measure of the noise voltage that can be tolerated by a logic device input. In the HIGH state, it is given by VNH VOH VIH. In the LOW state, it is given by VNL VIL VOL. CMOS devices generally have higher noise margins than TTL. 18. When interfacing two devices from different logic families, the driving gate must satisfy the voltage and current requirements of the load gates. 557 19. Input current in a CMOS gate is very low, due to its high input impedance. Thus, fanout is generally not a problem with CMOS loads. 20. CMOS devices that have the same values of VIH and VIL as TTL are considered to be TTL compatible, since they can be driven directly by TTL drivers. 21. A 74HC or 74HCT device can drive 10 LSTTL loads directly. To calculate fanout, we use the output currents for which the driving gate output voltages are dened. 22. A 74LS device can drive one or more 74HC devices, provided each 74HC input has a pull-up resistor (about 1 k to 10 k ) to supply sufcient voltage in the HIGH state. 23. A 74LS device can drive one or more 74HCT inputs directly. 24. Low-voltage CMOS (e.g., 74LVX or 74LCX) can be driven directly by a TTL device if the CMOS device is operated with a 3.3 V power supply. Noise margins are too small for a low-voltage CMOS driver to drive TTL loads. 25. 74HC or 74HCT gates can be operated at a low value of VCC (e.g., 3 volts) and interfaced to a higher-voltage driver by an inverting or noninverting buffer, such as the 74HC4049 or 74HC4050. The interface buffer can tolerate relatively high input voltages (up to 15 V) and, if it shares the same supply voltage as the load gate, can provide correct input voltages to the load. 26. A bipolar transistor with a grounded emitter acts as an inverter or a digital switch. A HIGH at the base causes the transistor to conduct, pulling the collector to near-ground potential. If there is a pull-up resistor on the collector, there will be a HIGH state at the collector when the base is LOW. 27. The simplest TTL input is a transistor with its base connected to VCC through a resistor. It can be treated as two diodes, back-to-back. 28. A TTL LOW input forward-biases the base-emitter junction of the input transistor, supplying a path to ground for input current. 29. A TTL HIGH input reverse-biases the base-emitter junction of the input transistor and forward-biases its base-collector junction. Input current in the HIGH state is restricted to reverse leakage current through the base-emitter junction. 30. An open TTL input is equivalent to a HIGH, as it provides no path to ground. 31. Some types of TTL gates, such as NAND, have multipleemitter input transistors. Any one input LOW acts as a LOW for the whole circuit. 32. Other TTL gates, such as NOR, have separate transistors for each input. Any HIGH input acts as a HIGH for the whole circuit. 33. An open-collector output has one output transistor that switches on a path to ground (logic LOW) when it is turned on. There is no separate internal circuit for a HIGH output. This must be provided by an external pull-up resistor. 34. Open-collector outputs can be used to parallel outputs (wired-AND), drive high-current loads, or interface to a circuit with a different power supply voltage than the driving gate. 35. A totem pole output has a transistor that switches on for a LOW output and another that switches on for a HIGH output. These output transistors are always in opposite states, except briey during times when the output is changing states. 36. Totem pole outputs generate noise spikes on the power line of a circuit when they switch between logic states. These 558 37. 38. 39. 40. 41. C H A P T E R 1 1 Logic Gate Circuitry spikes can be amplied by inductance of the power line. Decoupling capacitors placed close to each device help minimize this problem. TTL outputs should never be connected together, as they can be damaged when the outputs are in opposite states. (Too much output current ows.) The logic level under such conditions is not certain. Gates with tristate outputs can generate logic LOW, logic HIGH, or high-impedance states. A high-impedance state is like an open circuit or electrical disconnection of the gate output from the circuit. In this state, both HIGH- and LOWstate output transistors are off. The operation of a tristate output is controlled by the state of a control input. In one control state, the output is either HIGH or LOW. In the opposite control state, the output is in the high-impedance state. CMOS (complementary MOS) devices are based on nchannel and p-channel MOSFETs (metal-oxide-semiconductor eld effect transistors). A MOSFET consists of a silicon substrate of a particular type of silicon (e.g., p-type), embedded with wells of the opposite type (e.g., n-type) that form the drain and source regions of the MOSFET. A gate electrode can bias the substrate to create a conduction channel between drain and source. 42. An n-channel enhancement mode MOSFET is biased on when its gate voltage exceeds its source voltage by a given amount called the threshold voltage. 43. A p-channel enhancement mode MOSFET is biased on when its gate voltage is less than its source voltage by a given amount called the threshold voltage. 44. An n-channel and p-channel MOSFET can be connected in such a way that one of the pair of MOSFETs is always on and one is always off. This connection is called a complementary pair and forms the basis for CMOS logic. 45. Logic functions, such as NAND and NOR, can be implemented with a complementary pair of MOSFETs for each input, with the MOSFETs in series or parallel to VCC or ground, as required. 46. Many TTL families have been designed to incorporate Schottky barrier diodes, which limit the saturation of their transistors, allowing faster internal and output switching speeds. 47. Metal-gate CMOS has been superceded by high-speed (silicon-gate) CMOS, which has a smaller MOSFET size, resulting in faster switching and lower gate capacitance. 48. Speed-power product is a measure of the energy used by a gate. More advanced logic families have smaller values of speed-power product. GLOSSARY CMOS Complementary metal-oxide semiconductor. A logic family based on the switching of n- and p-channel metal-oxidesemiconductor eld effect transistors (MOSFETs). IOH Current measured at a device output when the output is HIGH. IOL Current measured at a device output when the output is LOW. Cutoff mode The operating mode of a transistor when there is no collector or drain current owing and the path from collector to emitter or drain to source is effectively an open circuit IT When referring to CMOS supply current, the sum of static and dynamic supply currents. Driving gate A gate whose output supplies current to the inputs of other gates. Load gate A gate whose input current is supplied by the output of another gate. ECL Emitter coupled logic. A high-speed logic family based on bipolar transistors. MOSFET Metal-oxide-semiconductor eld effect transistor. A MOSFET has three terminalsgate, source, and drain which are analogous to the base, emitter, and collector of a bipolar junction transistor. Enhancement-mode MOSFET A MOSFET which creates a conduction path (a channel) between its drain and source terminals when the voltage between gate and source exceeds a specied threshold level. Fanout The number of gate inputs that a gate output is capable of driving without possible logic errors. Floating An undened logic state, neither HIGH nor LOW. High-speed (silicon-gate) CMOS A CMOS logic family with a smaller device structure and thus higher speed than standard (metal-gate) CMOS. ICC Total supply current in a TTL or high-speed CMOS device. ICCH TTL supply current with all outputs HIGH. ICCL TTL supply current with all outputs LOW. IDD CMOS supply current under static (nonswitching) conditions. IIH Current measured at a device input when the input is HIGH. IIL Current measured at a device input when the input is LOW. n-channel enhancement-mode MOSFET A MOSFET built on a p-type substrate with n-type drain and source regions. An n-type channel is created in the p-substrate during conduction. Noise Unwanted electrical signal, often resulting from electromagnetic radiation. Noise margin A measure of the ability of a logic circuit to tolerate noise. n-type inversion layer The conducting layer formed between drain and source when an enhancement-mode n-channel MOSFET is biased ON. Also referred to as the channel. Ohmic region The MOSFET equivalent of saturation. When a MOSFET is biased ON, it acts like a relatively low resistance, or ohmically. Open-collector output A TTL output where the collector of the LOW-state output transistor is brought out directly to the output pin. There is no built-in HIGH-state output circuitry which allows two or more open collector outputs to be connected without possible damage. Glossary p-channel enhancement-mode MOSFET A MOSFET built on an n-type substrate with p-type drain and source regions. During conduction, a p-type channel is created in the n-substrate. Phase splitter A transistor in a TTL circuit which ensures that the LOW- and HIGH-state output transistors of a totem pole output are always in opposite phase (i.e., one ON, one OFF). 559 Substrate The foundation of n- or p-type silicon on which an integrated circuit is built. Threshold voltage, VGS(Th) The minimum voltage between gate and source of a MOSFET for the formation of the conducting inversion layer (channel). Totem pole output A type of TTL output with a HIGH and a LOW output transistor, only one of which is active at any time. Power dissipation The electrical energy used by a logic circuit in a specied period of time. Abbreviation: PD tpHL Propagation delay when the device output is changing from HIGH to LOW. Propagation delay The time required for the output of a digital circuit to change states after a change at one or more of its inputs. tpLH Propagation delay when the device output is changing from LOW to HIGH. Saturation mode The operating mode of a bipolar transistor when an increase in base current will not cause a further increase in the collector current and the path from collector to emitter is very nearly (but not quite) a short circuit. This is the ON state of a transistor in a digital circuit. Schottky barrier diode A specialized diode with a forward drop of about 0.4 V. Schottky transistor A bipolar transistor with a Schottky diode across its base-collector junction, which prevents the transistor from going into deep saturation. Schottky TTL A series of unsaturated TTL logic families based on Schottky transistors. Schottky TTL switches faster than standard TTL due to decreased storage time in its transistors. Tristate output An output having three possible states: logic HIGH, logic LOW, and a high-impedance state, in which the output acts as an open circuit. TTL Transistor-transistor logic. A logic family based on bipolar transistors. TTL Compatible Able to be driven directly by a TTL output. Usually implies voltage compatibility with TTL. VCC Supply voltage for TTL and high-speed CMOS devices. VDD Metal-gate CMOS supply voltage. VIH Voltage level required to make the input of a logic circuit HIGH. VIL Voltage level required to make the input of a logic circuit LOW. Sinking A terminal on a gate or ip-op is sinking current when the current ows into the terminal. VOH Voltage measured at a device output when the output is HIGH. Sourcing A terminal on a gate or ip-op is sourcing current when the current ows out of the terminal. VOL Voltage measured at a device output when the output is LOW. Speed-power product A measure of a logic circuits efciency, calculated by multiplying its propagation delay by its power dissipation. Unit: picojoule (pJ) Wired-AND A connection where open-collector outputs of logic gates are wired together. The logical effect is the ANDing of connected functions. Storage time Time required to transport stored charge away from the base region of a bipolar transistor before it can turn off. PROBLEMS Problem numbers set in color indicate more difcult problems: those with underlines indicate most difcult problems. Section 11.1 Electrical Characteristics of Logic Gates 11.1 Briey list the advantages and disadvantages of TTL, CMOS, and ECL logic gates. Section 11.2 Propagation Delay State 1 State 2 State 3 A 1 0 0 B 0 0 0 C 1 1 0 a. Draw a timing diagram that uses the above changes of input state to illustrate the effect of propagation delay in the circuit. 11.2 Explain how propagation delay is measured in TTL devices and CMOS devices. How do these measurements differ? 11.3 Figure 11.65 shows the input and output waveforms of a logic gate. Use the graph to calculate tpHL and tpLH. b. Calculate the maximum time it takes for the output to change when the inputs change from state 1 to state 2. 11.4 The inputs of the logic circuit in Figure 11.66 are in state 1 in the following table. The inputs change to state 2, then to state 3. c. Calculate the maximum time it takes for the output to change when the inputs change from state 2 to state 3. 560 C H A P T E R 1 1 Logic Gate Circuitry FIGURE 11.65 Problem 11.3 Waveforms FIGURE 11.66 Problems 11.4 and 11.5 Logic Circuit 11.5 Section 11.3 Fanout 11.6 Calculate the maximum number of low-power Schottky TTL loads (74LSNN series) that a 74S86 XOR gate can drive. 11.7 What is the maximum number of 74S32 OR gates that a 74LS00 NAND gate can drive? FIGURE 11.67 Problem 11.10 Current Calculations I1 11.8 What is the maximum number of 74LS00 NAND gates that a 74S32 OR gate can drive? 11.9 Repeat Problem 11.4 , parts b and c, for a 74HC00 NAND and a 74HC02 NOR gate. An LSTTL gate is driving seven LSTTL gate inputs, each equivalent to the load presented by a 74LS00 NAND input. Calculate the source and sink currents required from the driving gate. 11.10 Calculate the current values for the circuits shown in Figure 11.67. For each circuit, state the logic level at the output of gate 1. I1 I2 1 2 I2 1 I3 2 I3 3 3 I4 I4 4 4 I5 I5 5 I6 6 5 NAND: 74LS00 NOR : 74LS02 XOR : 74LS86A I6 6 Problems Section 11.4 Power Dissipation 11.11 The circuit in Figure 11.68 is constructed from the gates of a 74LS08 AND device. Calculate the power dissipation of the circuit for the following input logic levels: a. b. c. d. A 0 1 1 1 B 0 1 1 1 C 0 0 1 1 D 0 1 1 1 E 0 1 0 1 561 Calculate the maximum total power dissipation of the circuit when its input state is ABCDE 01100. Include all unused gates. (Connect unused gate inputs so that they will dissipate the least amount of power.) 11.15 a. Calculate the no-load power dissipation of a single gate at 1 MHz for a 74HC00A quad 2-input NAND gate (VCC 5 V). (Neglect quiescent current.) b. Calculate the percent change in power dissipation if the gate in part a of this question is operated with a new value of VCC 3.3 V. (f 1 MHz) Section 11.5 Noise Margin 11.16 Calculate the maximum noise margins, in both HIGH and LOW states, of: a. A 74S00 NAND gate b. A 74LS00 NAND gate c. A 74AS00 NAND gate d. A 74ALS00 NAND gate FIGURE 11.68 Problems 11.11 to 11.13 Logic Circuit e. A 74HC00 NAND gate (VCC f. A 74HCT00 NAND gate (VCC 5 V) 5 V) Section 11.6 Interfacing TTL and CMOS Gates 11.12 The gate outputs in Figure 11.68 are switching at an average frequency of 100 kHz, with an average duty cycle of 60%. Calculate the power dissipation if the gates are all 74S08 AND gates. 11.13 The gates in Figure 11.68 are 74HC08A high-speed CMOS gates. a. Calculate the power dissipation of the circuit if the input state is ABCDE 010101. (VCC 4.5 V, TA 25C) b. Calculate the circuit power dissipation if the outputs are switching at a frequency of 10 kHz, 50% duty cycle. c. Repeat part b for a frequency of 2 MHz. 11.14 The circuit in Figure 11.69 consists of two 74LS00 NAND gates (gates 4 and 5) and three 74LS02 NOR gates (gates 1, 2, and 3). When this circuit is actually built, there will be two unused NAND gates and one unused NOR gate in the device packages. 11.17 Why can an LSTTL gate drive a 74HCT gate directly, but not a 74HC? Show calculations. 11.18 Draw a circuit that allows an LSTTL gate to drive a 74HC gate. Explain briey how it works. 11.19 How many LSTTL loads (e.g., 74LS00) can a 74HC00A NAND gate drive? Use data sheet parameters to support your answer. Assume VCC 4.5 V. Show all calculations. Section 11.7 Internal Circuitry of TTL Gates 11.20 In what logic state is an open TTL input? Why? 11.21 Briey describe the operation of the TTL open-collector inverter shown in Figure 11.20. What is the purpose of the diode? 11.22 Briey explain the operation of a multiple-emitter input transistor used in a TTL NAND gate. Describe how the transistor responds to various combinations of HIGH and LOW inputs. 11.23 Draw a wired-AND circuit consisting of three opencollector NAND gates and an output pull-up resistor. The gate inputs are as follows: Gate 1: Inputs A, B Gate 2: Inputs C, D Gate 3: Inputs E, F Write the Boolean function of the circuit output. FIGURE 11.69 Problem 11.14 Logic Circuit 11.24 Calculate the minimum value of the pull-up resistor if the circuit drawn in Problem 11.23 is to drive a logic gate having input current IIL 0.8 mA and the NAND gates can sink 12 mA in the LOW output state. (Assume that VOL 0.4 V.) 562 C H A P T E R 1 1 Logic Gate Circuitry 11.25 Draw a circuit consisting only of open-collector gates whose Boolean expression is the product-of-sums expression (A B)(C D)(E F)(G 24 V H). LAMP 690 11.26 Is an open-collector TTL output likely to be damaged if shorted to ground? Why or why not? 11.27 Is an open-collector TTL output likely to be damaged if shorted to VCC? Why or why not? 11.28 Draw the totem pole output of a standard TTL gate. FIGURE 11.71 Problem 11.32 Lamp Driver 11.29 Refer to the TTL NAND gate in Figure 11.34. a. Why are Q3 and Q4 never on at the same time (ideally)? b. How does switching noise originate in a totem pole output? How can the problem be controlled? 11.30 Explain briey why two totem pole outputs should not be connected together. 11.31 Two LED driver circuits are shown in Figure 11.70. For each circuit, calculate the current owing when the LED is ON. Calculate the ratio between the LED ON current and IOL or IOH of the inverter, whichever is appropriate for each circuit. State which is the best connection for LED driving and explain why. Section 11.8 Internal Circuitry of CMOS Gates 11.33 State several precautions that should be taken to prevent electrostatic damage to MOSFET circuits. 11.34 a. Draw the circuit symbols for an n-channel and a pchannel enhancement-mode MOSFET. b. Describe the required bias conditions for each type of MOSFET in the cutoff and ohmic regions. c. State the approximate channel resistance for a MOSFET in the cutoff and ohmic regions. 11.35 Draw the circuit diagram of a CMOS AND gate. Derive the truth table of the gate by analyzing the operation of all the transistors under all possible input conditions. 11.36 Repeat Problem 11.35 for a CMOS OR gate. 11.37 Figure 11.72 shows a circuit that can switch two analog signals to an automotive speedometer/tachometer. Each sensor produces an analog voltage proportional to its measured quantity. Briey explain how these analog signals are switched to the display output circuitry. Vcc 74LS04 330 Vf 2V 330 Vf 2V Section 11.9 TTL and CMOS Variations 11.38 Briey explain how a Schottky barrier diode can improve the performance of a transistor in a TTL circuit. 74LS04 FIGURE 11.70 Problem 11.31 LED drivers 11.39 Is the speed-power product of a TTL gate affected by the switching frequency of its output? Explain. 11.40 Use data sheets to calculate the speed-power products of the following gates: a. 74LS00 b. 74S00 c. 74ALS00 11.32 Calculate the current owing when the lamp in Figure 11.71 is illuminated. Choose one of the following devices as a suitable driver: 74LS04, 74LS05 74LS06, 74LS16. Explain your choice. (Data sheets for these devices are found in Appendix C.) d. 74AS00 e. 74HC00A (quiescent and 10 MHz) f. 74HCT00A (quiescent and 10 MHz) g. 74F00 Answers to Section Review Problems 563 FIGURE 11.72 Problem 11.37 Speedometer/Tachometer Switching Circuit 11.41 Briey explain the differences among the following highspeed CMOS logic families: 74HCNN, 74HC4NNN, 74HCTNN, and 74HCUNN. 11.42 Assume that the power dissipation of a metal-gate or high-speed CMOS gate increases in proportion to the switching frequency of its output. Calculate the speed- power product of the following gates at 2 MHz, 5 MHz, and 10 MHz: a. 4011B b. 74HCT04 c. 74HCU04 ANSWERS TO SECTION REVIEW PROBLEMS Section 11.1 Section 11.5 11.1 VOH 2.7 V min. (We cannot expect typical values for VOH.) IOH 0.4 mA (The negative sign indicates that the current is leaving the gate. See Figure 11.2.) 11.5 VNH Section 11.2 11.2 tpHL1 tpHL2 20 ns 22 ns 42 ns; tpLH2 22 ns Section 11.3 1.98 V, VNL 0.66 V Section 11.6 11.6 2.5 V. The interface buffer and load should have the same supply voltage so that the output voltage of the buffer and input voltage of the load are compatible. Section 11.7a 11.3 Source currents: IOH, IIL; sink currents: IOL, IIH 11.7 a. Provision of logic HIGH when output transistor is OFF b. Limitation of IOL when output transistor is ON Section 11.4 Section 11.7b 11.4 CMOS draws very little current when its outputs are not switching. Since the majority of current is drawn when the outputs switch, the more often the outputs switch, the more current is drawn from the supply. This is the same as saying that power dissipation increases with frequency. 11.8 Rext 592 . Minimum standard value: 680 Section 11.7c 11.9 When the output is HIGH, current ows to ground through a low-impedance path, causing IOH to exceed its rating. 564 C H A P T E R 1 1 Logic Gate Circuitry Section 11.7d 11.10 The diode allows the base of Q4 to be pulled LOW through G, but will not allow a HIGH at G to turn it on. This keeps both output transistors OFF in the high-impedance state and allows them to be in opposite states when the output is enabled. charge. If the oxide layer is damaged, it may no longer insulate the gate terminal from the MOSFET substrate, which causes the transistor to malfunction. Section 11.8b 11.11 Noninverting gates are actually double-inverting gates. They require an extra transistor stage to cancel the inversion introduced by NAND or NOR transistor logic. 11.13 It allows complementary operation with an n-channel MOSFET. Specically, a gate voltage of 0 V turns OFF an n-channel device having a grounded source. The same voltage turns ON the p-channel device whose source is tied to VCC. It does so by making the p-channel gatesource voltage more negative than the required threshold. Section 11.8a Section 11.9 11.12 The thin oxide layer in the gate region can be damaged by overvoltage, such as that caused by electrostatic dis- 11.14 13.36 pJ, 33.4 pJ, and 66.8 pJ. Section 11.7e CHAPTER 12 Interfacing Analog and Digital Circuits OUTLINE CHAPTER OBJECTIVES 12.1 Analog and Digital Signals 12.2 Digital-to-Analog Conversion 12.3 Analog-to-Digital Conversion 12.4 Data Acquisition Upon successful completion of this chapter, you will be able to: Dene the terms analog and digital and give examples of each. Explain the sampling of an analog signal and the effects of sampling frequency and quantization on the quality of the converted digital signal. Draw the block diagram of a generic digital-to-analog converter (DAC) and circuits of a weighted resistor DAC and an R-2R ladder DAC. Calculate analog output voltages of a DAC, given a reference voltage and a digital input code. Congure an MC1408 integrated circuit DAC for unipolar and bipolar output, and calculate output voltage from known component values, reference voltage, and digital inputs. Describe important performance specications of a digital-to-analog converter. Draw the circuit for a ash analog-to-digital converter (ADC) and briey explain its operation. Dene quantization error and describe its effect on the output of an ADC. Explain the basis of the successive approximation ADC, draw its block diagram, and briey describe its operation. Describe the operation of an integrator with constant input voltage. Draw the block diagram of a dual slope (integrating) ADC and briey explain its operation. Explain the necessity of a sample and hold circuit in an ADC and its operation. State the Nyquist sampling theorem and do simple calculations of maximum analog frequencies that can be accurately sampled by an ADC system. Describe the phenomenon of aliasing and explain how it arises and how it can be remedied. Interface an ADC0808 analog-to-digital converter to a CPLD-based state machine. Design a 4-channel data acquisition system, including an ADC0808 analogto-digital converter and a CPLD-based state machine. 565 566 C H A P T E R 1 2 Interfacing Analog and Digital Circuits E lectronic circuits and signals can be divided into two main categories: analog and digital. Analog signals can vary continuously throughout a dened range. Digital signals take on specic values only, each usually described by a binary number. Many phenomena in the world around us are analog in nature. Sound, light, heat, position, velocity, acceleration, time, weight, and volume are all analog quantities. Each of these can be represented by a voltage or current in an electronic circuit. This voltage or current is a copy, or analog, of the sound, velocity, or whatever. We can also represent these physical properties digitally, that is, as a series of numbers, each describing an aspect of the property, such as its magnitude at a particular time. To translate between the physical world and a digital circuit, we must be able to convert analog signals to digital and vice versa. We will begin by examining some of the factors involved in the conversion between analog and digital signals, including sampling rate, resolution, range, and quantization. We will then examine circuits for converting digital signals to analog, since these have a fairly standard form. Analog-to-digital conversion has no standard method. We will study several of the most popular: simultaneous (ash) conversion, successive approximation, and dual slope (integrating) conversion. 12.1 Analog and Digital Signals KEY TERMS Continuous Smoothly connected. An unbroken series of consecutive values with no instantaneous changes. Discrete Separated into distinct segments or pieces. A series of discontinuous values. Analog A way of representing some physical quantity, such as temperature or velocity, by a proportional continuous voltage or current. An analog voltage or current can have any value within a dened range. Digital A way of representing a physical quantity by a series of binary numbers. A digital representation can have only specic discrete values. Analog-to-digital converter A circuit that converts an analog signal at its input to a digital code. (Also called an A-to-D converter, A/D converter, or ADC.) Digital-to-analog converter A circuit that converts a digital code at its input to an analog voltage or current. (Also called a D-to-A converter, D/A converter, or DAC.) Electronic circuits are tools to measure and change our environment. Measurement instruments tell us about the physical properties of objects around us. They answer questions such as How hot is this water?, How fast is this car going?, and How many electrons are owing past this point per second? These data can correspond to voltages and currents in electronic instruments. If the internal voltage of an instrument is directly proportional to the quantity being measured, with no breaks in the proportional function, we say that it is an analog voltage. Like the property being measured, the voltage can vary continuously throughout a dened range. For example, sound waves are continuous movements in the air. We can plot these movements mathematically as a sum of sine waves of various frequencies. The patterns of magnetic domains on an audio tape are analogous to the sound waves that produce them and electromagnetically represent the same mathematical functions. When the tape is played, the playback head produces a voltage that is also proportional to the original sound waves. This analog audio voltage can be any value between the maximum and minimum voltages of the audio system amplier. 12.1 Analog and Digital Signals 567 If an instrument represents a measured quantity as a series of binary numbers, the representation is digital. Since the binary numbers in a circuit necessarily have a xed number of bits, the instrument can represent the measured quantities only as having specic discrete values. A compact disc stores a record of sound waves as a series of binary numbers. Each number represents the amplitude of the sound at a particular time. These numbers are decoded and translated into analog sound waves upon playback. The values of the stored numbers (the encoded sound information) are limited by the number of bits in each stored digital word. The main advantage of a digital representation is that it is not subject to the same distortions as an analog signal. Nonideal properties of analog circuits, such as stray inductance and capacitance, amplication limits, and unwanted phase shifts, all degrade an analog signal. Storage techniques, such as magnetic tape, can also introduce distortion due to the nonlinearity of the recording medium. Digital signals, on the other hand, do not depend on the shape of a waveform to preserve the encoded information. All that is required is to maintain the integrity of the logic HIGHs and LOWs of the digital signal. Digital information can be easily moved around in a circuit and stored in a latch or on some magnetic or optical medium. When the information is required in analog form, the analog quantity is reproduced as a new copy every time it is needed. Each copy is as good as any previous one. Distortions are not introduced between copy generations, as is the case with analog copying techniques, unless the constituent bits themselves are changed. Digital circuits give us a good way of measuring and evaluating the physical world, with many advantages over analog methods. However, most properties of the physical world are analog. How do we bridge the gap? We can make these translations with two classes of circuits. An analog-to-digital converter accepts an analog voltage or current at its input and produces a corresponding digital code. A digital-to-analog converter generates a unique analog voltage or current for every combination of bits at its inputs. Sampling an Analog Voltage KEY TERMS Sample An instantaneous measurement of an analog voltage, taken at regular intervals. Sampling frequency The number of samples taken per unit time of an analog signal. Quantization The number of bits used to represent an analog voltage as a digital number. Resolution The difference in analog voltage corresponding to two adjacent digital codes. Analog step size. Before we examine actual D/A and A/D converter circuits, we need to look at some of the theoretical issues behind the conversion process. We will look at the concept of sampling an analog signal and discover how the sampling frequency affects the accuracy of the digital representation. We will also examine quantization, or the number of bits in the digital representation of the analog sample, and its effect on the quality of a digital signal. Figure 12.1 shows a circuit that converts an analog signal (a sine pulse) to a series of 4-bit digital codes, then back to an analog output. The analog input and output voltages are shown on the two graphs. There are two main reasons why the output is not a very good copy of the input. First, the number of bits in the digital representation is too low. Second, the input signal is not 568 C H A P T E R 1 2 Interfacing Analog and Digital Circuits FIGURE 12.1 Analog Input and Output Signals sampled frequently enough. To help us understand the effect of each of these factors, let us examine the conversion process in more detail. The analog input signal varies between 0 and 8 volts. This is evenly divided into 16 ranges, each corresponding to a 4-bit digital code (0000 to 1111). We say that the signal is quantized into 4 bits. The resolution, or analog step size, for a 4-bit quantization is 8 V/16 steps 0.5 V/step. Table 12.1 shows the codes for each analog range. Table 12.1 4-bit Digital Codes for 0 to 8 V Analog Range Analog Voltage Digital Code 0.000.25 0.250.75 0.751.25 1.251.75 1.752.25 2.252.75 2.753.25 3.253.75 3.754.25 4.254.75 4.755.25 5.255.75 5.756.25 6.256.75 6.757.25 7.258.00 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 12.1 Analog and Digital Signals 569 The analog input is sampled and converted at the beginning of each time division on the graph. The 4-bit digital code does not change until the next conversion, 1 ms later. This is the same as saying that the system has a sampling frequency of 1 kHz ( f 1/T 1/(1 ms) 1 kHz). Table 12.2 shows the digital codes for samples taken from t 0 to t 18 ms. The analog voltages in Table 12.2 are calculated by the formula Vanalog 8 V sin (t (10/ms)) For example at t 2 ms, Vanalog 8 V sin (2 ms (10/ms)) 8 V sin (20) 2.736 V. The calculated analog values are compared to the voltage ranges in Table 12.1 and assigned the appropriate code. The value 2.736 V is between 2.25 V and 2.75 V and therefore is assigned the 4-bit value of 0101. Table 12.2 4-bit Codes for a Sampled Analog Signal Table 12.3 8-bit Codes for a Sampled Analog Signal Time (ms) Analog Amplitude (volts) Digital Code Time (ms) Analog Amplitude (volts) Digital Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0.000 1.389 2.736 4.000 5.142 6.128 6.928 7.518 7.878 8.000 7.878 7.518 6.928 6.128 5.142 4.000 2.736 1.389 0.000 0000 0011 0101 1000 1010 1100 1110 1111 1111 1111 1111 1111 1110 1100 1010 1000 0101 0011 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0.000 1.389 2.736 4.000 5.142 6.128 6.928 7.518 7.878 8.000 7.878 7.518 6.928 6.128 5.142 4.000 2.736 1.389 0.000 00000000 00101100 01011100 10000000 10100101 11000010 11011110 11110001 11111100 11111111 11111100 11110001 11011110 11000010 10100101 10000000 01011100 00101100 00000000 The digital-to-analog converter in Figure 12.1 continuously converts the digital codes to their analog equivalents. Each code produces an analog voltage whose value is the midpoint of the range corresponding to that code. For this particular analog waveform, the A/D converter introduces the greatest inaccuracy at the peak of the waveform, where the magnitude of the input voltage changes the least per unit time. There is not sufcient difference between the values of successive analog samples to map them into unique codes. As a result, the output waveform attens out at the top. This is the consequence of using a 4-bit quantization, which allows only 16 different analog ranges in the signal. By using more bits, we could divide the analog signal into a greater number of smaller ranges, allowing more accurate conversion of a signal having small changes in amplitude. For example, an 8-bit code would give us 256 steps (a resolution of 8 V/256 31.25 mV). This would yield the code assignments shown in Table 12.3. Note that for an 8-bit code, there is a unique value for every sampled voltage. Figure 12.2 shows how different levels of quantization affect the accuracy of a digital representation of an analog signal. The analog input is a sine wave, converted to digital 570 C H A P T E R 1 2 Interfacing Analog and Digital Circuits FIGURE 12.2 Effect of Quantization codes and back to analog, as in Figure 12.1. The graphs show the analog input and three analog outputs, each of which has been sampled 28 times per cycle, but with different quantizations. The corresponding digital codes range from a maximum negative value of n 0s to a maximum positive value of n 1s for an n-bit quantization (e.g., for a 4-bit quantization, maximum negative 0000, maximum positive 1111). The rst output signal has an innite number of bits in its quantization. Even the smallest analog change between samples has a unique code. This ideal case is not attainable, since a digital circuit always has a nite number of bits. We can see from the codes in Table 12.3 that an 8-bit quantization is sufcient to give unique codes for this waveform. An innite quantization implies that the resolution is small enough that each sampled voltage can be represented, not only by a unique code, but as its exact value rather than a point within a range. The 4-bit and 3-bit quantizations in the next two graphs show progressively worse representation of the original signal, especially at the peaks. The change in analog voltage is too small for each sample to have a unique code at these low quantizations. Figure 12.3 shows how the digital representation of a signal can be improved by increasing its sampling frequency. It shows an analog signal and three analog waveforms resulting from an analog-digital-analog conversion. All waveforms have innite quantization, but different numbers of samples in the analog-to-digital conversion. As the number of samples decreases, the output waveform becomes a poorer copy of the input. In general, the sampling frequency affects the horizontal resolution of the digitized waveform and the quantization affects the vertical resolution. 12.2 Digital-to-Analog Conversion 571 FIGURE 12.3 Effect of Sampling Frequency SECTION 12.1 REVIEW PROBLEM 12.1 An analog signal has a range of 0 to 24 mV. The range is divided into 32 equal steps for conversion to a series of digital codes. How many bits are in the resultant digital codes? What is the resolution of the A/D converter? 12.2 Digital-to-Analog Conversion KEY TERM Full scale The maximum analog reference voltage or current of a digital-toanalog converter. Figure 12.4 shows the block diagram of a generalized digital-to-analog converter. Each digital input switches a proportionally weighted current on or off, with the current for the MSB being the largest. The second MSB produces a current half as large. The current generated by the third MSB is one quarter of the MSB current, and so on. These currents all sum at the operational ampliers (op amps) inverting input. The total analog current for an n-bit circuit is given by: Ia bn 12n 1 b222 2 n b121 b020 Iref The bit values b0, b1, . . . bn can be only 0 or 1. The function of each bit is to include or exclude a term from the general expression. 572 C H A P T E R 1 2 Interfacing Analog and Digital Circuits FIGURE 12.4 Analysis of a Generalized Digital-to-Analog Converter The op amp acts as a current-to-voltage converter. The analysis, illustrated in Figure 12.4b, is the same as for an inverting op amp circuit with a constant input current. The input impedance of the op amp is the impedance between its inverting ( ) and noninverting ( ) terminals. This value is very large, on the order of 2 M . If this is large compared to other circuit resistances, we can neglect the op amp input current, Iin. This implies that the voltage drop across the input terminals is very small; the inverting and noninverting terminals are at approximately the same voltage. Since the noninverting input is grounded, we can say that the inverting input is virtually grounded. Current IF ows in the feedback loop, through resistor RF. Since Ia Iin IF 0 and Iin 0, then IF Ia. By Ohms law, the voltage across RF is given by VF Ia RF. The feedback resistor is connected to the output at one end and to virtual ground at the other. The op amp output voltage is measured with respect to ground. The two voltages are effectively in parallel. Thus, the output voltage is the same as the voltage across the feedback resistor, with a polarity opposite to VF, calculated above. Va VF Ia RF bn 12n 1 b2 22 b1 21 b0 20 2n Iref RF The range of analog output voltage is set by choosing the appropriate value of RF. EXAMPLE 12.1 Write the expression for analog current, Ia, of a 4-bit D/A converter. Calculate values of Ia for input codes b3b2b1b0 0000, 0001, 1000, 1010, and 1111, if Iref 1 mA. Solution The analog current of a 4-bit converter is: Ia b3 23 b2 22 b1 21 24 Iref b0 20 12.2 4b2 8b3 b3b2b1b0 0000, Ia b3b2b1b0 0001, Ia b3b2b1b0 1000, Ia b3b2b1b0 1010, Ia b3b2b1b0 1111, Ia Digital-to-Analog Conversion 2b1 b0 (1 mA) 16 0 0)(1 mA) 0 16 0 1)(1 mA) 1 mA 16 16 (0 0 (0 0 (8 0 0 0)(1 mA) 16 (8 0 2 0)(1 mA) 16 (8 4 2 1)(1 mA) 16 573 62.5 A 8 (1 mA) 16 10 (1 mA) 16 15 (1 mA) 16 0.5 mA 0.625 mA 0.9375 mA Example 12.1 suggests an easy way to calculate D/A analog current. Ia is a fraction of the reference current Iref. The denominator of the fraction is 2n for an n-bit converter. The numerator is the decimal equivalent of the binary input. For example, for input b3b2b1b0 0111, Ia (7/16)(Iref). Note that when b3b2b1b0 1111, the analog current is not the full value of Iref, but 15/16 of it. This is one least signicant bit less than full scale. This is true for any D/A converter, regardless of the number of bits. The maximum analog current for a 5-bit converter is 31/32 of full scale. In an 8-bit converter, Ia cannot exceed 255/256 of full scale. This is because the analog value 0 has its own code. An n-bit converter has 2n input codes, ranging from 0 to 2n 1. The difference between the full scale (FS) of a digital-to-analog converter and its maximum output is the resolution of the converter. Since the resolution is the smallest change in output, equivalent to a change in the least signicant bit, we can dene the maximum output as FS 1 LSB. (As an example, in the case of an 8-bit converter FS 1 LSB 255/256 Iref.) SECTION 12.2A REVIEW PROBLEM 12.2 Calculate the range of analog voltage of a 4-bit D/A converter having values of Iref 1 mA and RF 10 k . Repeat the calculation for an 8-bit D/A converter. Weighted Resistor D/A Converter Figure 12.5 shows the circuit of a 4-bit weighted resistor D/A converter. The heart of this circuit is a parallel network of binary-weighted resistors. The MSB has a resistor value of R. Successive branches have resistor values that double with each bit: 2R, 4R, and 8R. The branch currents decrease by halves with each descending bit value. FIGURE 12.5 Weighted Resistor D-to-A Converter 574 C H A P T E R 1 2 Interfacing Analog and Digital Circuits The bit inputs, b3, b2, b1, and b0, are either 0 V or Vref. When the corresponding bits are HIGH, the branch currents are: I3 I2 I1 I0 Vref /R Vref /2R Vref /4R Vref /8R The sum of branch currents gives us the analog current Ia. b3 Vref b2 Vref b1 Vref b0 Vref + + + 2R 4R 8R R b3 b2 b1 b0 Vref = + ++ 1 2 4 8 R Ia = We can calculate the analog voltage by Ohms law: V2 The choice of RF EXAMPLE 12.2 Ia RF b3 1 b3 1 b3 2 b2 2 b2 2 b2 4 Ia (R/2) b1 4 b1 4 b1 8 b0 Vref R 8 R2 b0 Vref 8 2 b0 Vref 16 R/2 makes the analog output a binary fraction of Vref. Calculate the analog voltage of a weighted resistor D/A converter when the binary inputs have the following values: b3b2b1b0 0000, 1000, 1111. Vref 5 V. Solution b3b2b1b0 Va 0000 0 2 0 4 1000 0 8 0 Vref 16 1 2