Logic & Computer Design Fundamentals 3e- Mano & Kime
672 Pages

Logic & Computer Design Fundamentals 3e- Mano & Kime

Course Number: 1234 2134, Spring 2010

College/University: Whatcom Community College

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H "'k",,, in WOoe<1;.,o ~,,, n .,,, """'" ou, 01, xii ; I'rdace O Cha pt e r 3 D IG ITAL C OMPlffERS AN]) 1 1 12 ' .J ,. ,.., , ,., J ~FOR).tA 3 t ION , , , , Digital Computc~ Informalion Repretentatton C omputer SmlClUre More o n the G cnerit C omputer N umberSystc"" Binary Numbers Octal a nd Hexadecitnlll Numbers Number Ranges Arithmetic O perations Con,"Ct~ion from lX<;imal 10 O ther Bases D ecima l Codes BCD Addition P arity lI it G ray Codes Alphanumeric Codes ASCII Ooaracter Code C hapter Summary Reference!l 3 8 n " " " '" " W " " " " " " """"= O Cha p lc r 2 29 C OMlltNATIOt<AL L oGIC C tll CUrrs 2 1 2 2 29 Binary Log ic and Oatc$ Bi nary Logic w gic Oa t"" Bo(Man Algebra Basic Identilie$ or fI.oolean Algebra A l g~bralc Manipulation 29 30 32 33 3S 37 o IIi C omplement of a Function S tandard Fnnns '4 ,., ,., ,., ' 6 ,.. 2- 10 D Chapter 3 " " M inlenns and Maxtcnns Sum o f P roducts Product of Sums Two-Level Circuil Optimization Cost Criteria Two-Variable M ap T hree_Variable M ap F our -Variable Map Map Manipulation E "e nt ial Prime Implicants Nonessential Prime Implicants Product-of-Sums Optimization D on 'I_Care Conditions Multiple-Level Circuit O ptimiza tion O lher G ale Type!; Excl us ive-OR O perator and Gates O dd Function High_Impedance O u tputs C hapter Summary References Problems " " ., " " " " " ' ."" " 0 Com e." 62 63 " " ,". n "' " "' 87 COMBINATIONAL LoGIC DESIGN Design Concepts and Automation D esign Hierarchy Top-Down Design C omputer-Aided Design Hardware Description Languages Logic Synthesis T he Design Space 3' G ate P ropeflies Levels of Integralion Circuil n chnologies Technology Parameters Positive a nd Negative Logic Design T rade _ Offs 33 Design Proce<!ure 34 Tec~ n OIOS)' Mapping Cell Specification 3 ' SO 87 "9 S '" '" " " % " " " ,m '" 003 "" '" 'W 'm " U bi-am ,., D Ch aple r 4 1\3 Map, MII T e ch niquell V eriflCat ioo M anual Logi< A nal).is S imulation P rogra mm ab le Im ple men tation T echn ol ogi es ReadOn ly M emory P rogrammable Logic Array Programm ab le A r ray l ogic D c ,-ices C hapter SummaI}' References l"roblem. m on '" ''" " 00 'm " m 141 C oMD INAT I ON!lL F liNCTIONS AI<D CIRCUITS ,~, ,~, 141 142 142 143 146 En~oding 152 E nrodcr b pa nsi"" .; C ombinatio nal CircuilS R udimentary L ogic Functions Value Fixing. T ran<ferring . nd In' -cnin, M ultiple-Bit Functions Enablin8 lXa.>ding D ecoder Ex pa nsion Decoder and Enab lin, Cornbinalion. Priority E ncoder " " 153 155 $electing M uUiplexe", Muluplexer Expansion A hcrnallvc Seteaion Implememalions C ombinational Function [mplemenlalion U .inl lk<: o<Iers 156 I S8 159 161 162 147 148 l SI 156 U sing M ult ip lexer:< 164 U . in g Read-On ly Me ,n orie, Using P rogrammable \...Qgk A rrays U sin. Ptogrammable Arra)' Logic De,-ices U llng L oo,,",p Tables H D I.. R ~present a tion for Combinational C ircuiu-V I1 D I.. H O I.. R eptl'Stnta tioo. r", C ombInational C ircuils-Verilog C ha pt er S ummary R eferences f"foblcm. 166 169 171 0 ." " 17S 1 76 ltw 1\10 191 '" 0 , 2 01 D Chapter 5 ARtTHMETtC FUNCJ10~S AND CIRCUITS h erative Combin"ional C ircuits 5-2 Bina!)' A dders Half A dder Full A dder Binary Ripple Carry A dder C arry Lookohe.d A ddcr , .; Binary Subtraction Complements Subtraction with Complemcnts Binary A ddcr- Subtractor!; Signed Bina!)' Number!; Signed BinaT)' A dd ition a nd Subtraction O vernow Binary Mu lt iplication O ther A rithmctic Functions C ontraction Incrementing Decrementing Multiplication by COnSI"nlS D i\'ision by Constants Z ero Fill and Extension H DL R epresentalions-V H DL Behavioral Description H DL R epre""nta1ions-Verilog Behavioral Description C hapter Summa!), References Problems ,, 201 '2" 02 2m 2"' '""'" 2W 'm " '4 '" ,., ,., 220 " ,'" ., " " '"' ,; 0 '" 221 ill 2M m no m 'm " '" m 233 2" m ''"" 2 41 D Chapter 6 SEOUE~TtAl 216 CtRCUtTS Sequential Circuit Definitions L atchc. S R and S I i L atchc. D Latch Flip-Flops M a,ler_Slave Flip_Flops Edge-Triggcre<:l Flip-Flop Standard Graphics S)'mbols eon"",, '" W 2M '" """ ' "" ''" " '" ''" ," "., " "" D irect I nputs F1 ip_ Fk'p T iming Seq uential Ci rcuit A nal)"i. I nput E qu ations State T ab le State Diagram ~ qu emi al C ircuit Timing Simulation Sequemial Circuit Design Design PTOCf'dure Finding S tate Di agram. a nd S tale T a ble!; S tate Assignment D e signing wit h 0 Flip-Flops Designing with Unus.ed States Verifieat;"n O th er Fli p-Flop T ypes JK and T Flip-Flops H DL Representation for Se<juential C ircuits-V HD L H DL R ep res.emation for Se<juential Circuito;--Ve,ilog Chapter Summary References PTobie IM D Chapte r 7 ''" ''' ''" " '" m m m ''"" '"" " 'm " m ,., 309 72 7 ) 7-4 7-S 76 " '" ,,, 3Q9 R (GtSTE RS A ND R EGtSTER T RANSfERS 7-1 R egisters a nd L oad E nable R egister with Parallel L oad Register T randers R egister T r an.fer O peration s A N ote f or V HDL a nd Verilog Us.e.,; Onl)' Mierooperations A rithmetic Microoperations Logic M icrooperatioll'l Shift Microoperation. M icrooperatiom o n a Sin gle Register Multip le- e' Based Transfers S Mt R egisters Ripple Count er Sync hronous B inary C ounters O ther C ounters R egister Cel! Design Multiplexer a nd Bu ... Based T ransfers for M ult ipJe R egisters T h ree-State B m CoGI.... 0 'm " m '" "" ''" " ''" " 'm " '" m ''"" 3D '" . .. Serial T ransfer a nd Microoperations Serial Addition 7 10 H DL R eprescntalion for Sh ift R egis tersand Countcrs - VHDL H DL Represe ntation for Shift Regis ters and Counters--Verilog C hap ter Summary R eferc nces Problems 71 1 7 12 o C hapter 351 353 35 4 3 56 356 363 8 S EOUE~C!NG A ND C omROl 363 81 82 3M T he Conlro l Un it Algor it hm ic S tate Machin .,. T he ASM Chart T iming Consi de rat io ns ASM Chart E,~ mp le. HinMY Mu lt iplier Hardwircd C ontrol Se'lucnce Registor and D ecodcr O ne Flip .Flop pe r StH tC H I) L Representation o f t he Hinn,), M\llhpl ier-V HD L H D L R epresentation o f Ihe Binary Multiplicr_V crilog Microprogrammed C o ntro l C hapter Su mmary References l 'roblcms ,., D Chap le r 9 M r,MORY B AS ICS Memory Definit iM S R ondomAcces. Memory W rit e and Read O p"r.tioM Timing Wa,'efo rm. l 'roreni es o f Memory S RAM Integra l ed Circu it s COinc id ent Selection A rrayofSRAM lCs D RAM les D RAM C dl D RAM Bit Slice % D RAM Typ"< SynChronous D RAM (S DRAM ) " " ,., " 0 '" ; 68 36' "" '" ''3"" " "' ''00 " ''" " ;n 399 ,., , i,i 363 Co o "." 339 3W "" '"' ." ." ." "" ''"" ''" '"" '" ,., " o C hapte r 10 D ouble D ata R ate S DRAM ( D DR S DRAM) RA~IBUS8 D RAM ( R DRA M) A rrays o f Dynamic RAM ICs C hapter Summary References Problems ''" " '" ''"" '" 429 ,., ' ., ,.2 CoMPUTER O l:.StGN BA stcs Introduction D atapaths T he A rithme!i dLogic U nit Arithmetic Ci rcui t Logic Circuit A rithmetidLogic Unit T he Shiner Barrel Shifter D atapath Repr=ntatia., T he C ontrol Word A Simple C omputer Architecture [nstructioo Set Architecture Storage Res<:m rtts Instructioo Format' Instructioo Specifications Single_Cycle Hardwirecl C ontrol Inst ruction D e<X>dcr Sample Instructions a nd Program Single_Cycle C ompute. Issues Mu ltiple-Cycle H ardwired C omrol Sequential Control Design 100JO C hapter Summary References Problems 429 430 "" '"" " ''" '"" " '"" ,., ,., ,., ,., ' '""" """ '" '" ". '" ."" ' ''" " '" '" .. .. , ... , o C h a pter 11 483 "" '"" " ''"" I NSfRlJcnON S ET A RCHfTl.'.CTURE t I_ I 11 _2 C omputer Architecture Cone<:pu Basic C omputer O perat;on Cycle Register Sct O pera nd Addressing Three _ Address In struction, '"' Co.", "" 0 " Two-Addr~s InstruNions O ne -Address Instructions Addn:ssing Architeclures Addressing Modes Implied Mode Immediate Mode Register a nd Register -I ndirect Modes D ircct Addressing Mode Indirect Addressing Mode Relati"e Addre",ing Mode Indexed Addressing Mode Summary o f A ddressing Modes InStfUc tion Set Architectures Data Tran,fer In structions St ac k Instructions Independe nt " e ... uS Memory- Mapped 1/0 Data Ma" ipulation Instructions A rithmetic Instructions Logica l and Bit M~nipu l ation Instructions Shi[t [nstructions Floating-Point Computations A r ithmetic O pe rations Biased E ~ pc>ncnt Standard O perand Format Program Comrol [nstfUNions Conditional B ranch [nstructions Procedure Call a nd Return [ n,tructions Program Interrupt Types o f In!errupts Processing E xtemal ln te rrupts Chapter Summary References Problems 11-3 11-7 11-8 11-9 11 - 10 D ehap t er 12 """ 'm m "' '''"" '''" " " '" '" "" ; 00 "" "" "" "" "" "" "'" 'm" m '" '"" 8 ''"" ''" " 5 27 R i se AND e l se C " NTRAL PR OCESS tNG U MTS 527 12-1 'm " m Pipelined D Jiapath Execution o f Pipeline M icr""perations Pipdined C ontrol Pipeline Programming a nd Performance T he Reduced Instructi on Set C omputer 12 _2 12-3 0 Coo, O"" m m Instruction Set Architecture Addressing Modes D at.path Organiza1ion O mlrol O rgani1.a1ion D ata Hazards C ontrol Hazards T he Complc~ In sl r"':lion Se1 Compu1er IS A Modifications D atapalh Modifications Control Unit Modifications Microprogrammed Comrol Microprograms for C omplu Instructions More on Design High-Performaoce C PU Coocepts Recent Architecturallnno~a1ions Digil al S ysums O Iaptcr Su mmary R eferences Problems 12-5 o C hapter 13 '" ''" " '" 'S"S3 ',., " '" ''" " '" "" "" ,n ''m" " m 579 >7, I SPlIT- O UTPUT ANO C OMMUl'ltCATtO:,< 131 132 135 C omputer 110 S"mplc Peripherals Keyboard H ard O i,k Graphic:< Display 1 T ransfer Ral es 10 110 rnte. faces 110 Bus and Interface Unit Example o f 1 Interface 10 Strobing Handshaking & ria l Communication Asynchronou1 Transmission Synchronous Transmission The Keyboard RC"i 1;tcd A P ad elBased Serial 110 B us ' """ ~lodcs o rTran srcr Example of ProgramControlled Tran,f~r [ nterrupt_ln itialed Transfcr I'r;orily Intcrrup1 C oo","" 0 "" "" '"" " ''" " '" ''"' ''"" " ''" " '" ''" " " "".", D aisrChain Priority P aralld Priority H ardware , ;] "m ," Dir~1 13 8 t J9 D MA C ontroll er D MA T ronsfer [/0 Processors C hapter S ummary R eferences Problems "" "" "" "" on o C hapte r " Meillury Acc.:.-ss 617 M E MORY S VSTr:MS ,., M emory Hierarc:hy L ocalitrof Rdercnc<= C ""he Memory C ache M appings Line Si~e Cache Loading Write M etlwds I ntegrat iOfl o f C oncepts Instruction and D ata C ""hcs MultipleU,,-el Caches Virtual M emory Page Tabl.,.. T rans l. lion L oohs ide Buffer V inual M emory a nd C ache C hapte r S ummary RefereTlCe 141 [ 43 "4 1 45 Problem ~ 0 617 "n ," "" ''"" "' '''m "' " m "" ' """ "" "" ,n "" 647 [ r<DEX A ;; 6B ,n C ooten" T he object of thi5 te~ t is to provide an understanding of the fundamenta l, o f logic a nd computer design for a wide audience o f readers. Many o f the fu ndamentals that arc p resented h ere h a"e not changed in decades. O n the O Ihu hand. the advances in underlying technology have had a m ajor dfe<:1 On the applicat ion o f the5<' fundamentals and the e mp hasis t o be placed on Ihem, The proceS'S o f design h as been automated by USing hardware description languag es and logic .ynthesis. a nd the quest for sp<:ed a nd low power has c hnged ( he f undamental. o f c omputer design. T he coment o f this third e d i(ioo continues (0 focus On f undamentals while a t the same time r cHuting the relative importance o f hasic concc:pts as the te<:hnology and t he design p roce. . evolve. A s an illustration. microprogrammin g. w hkh has declined in u5<' as a primary c o ntrol un it design m ethod. is t reated only as a c ontrol uni t design t echnique for implementing complex computer instruct inns. Also. o ""r time. the fundamental terminology i . e,'olving and. along with it. our perspect ive n f a wx-iated concc:pts. For example. in t his e ditton. 5<'<1 ions On N AND circuits and N OR circuits a ppe ar in the broader context n f technology m apping. The t e" c ontinues tn provide t be option t o instructors t o p rn"ide v "y basic co"erage of e ither V HDL o r V etil"- or omit h ardware descriptinn language ( HDL) coverage entirely, T he p erspe<1i,'e o f the introd uctory co~erage h ere i , the c orrespo nd ence o f the H D L description t o the actual hardware it represents. T hi. vit81 perspective. w hkh is c ritical in writing H DI.., fnr IOSk synthC'iis. can be lost in n ,ore detailed treatmen ts focusing On the language a nd fiuency in i. . u5<'. t n summary, thi s edition o f Logic a nd CompllleT De,y;gn F ""dammla/s features a strong e mphasi, o n fundamental. underlyin g c ontemporary IOSk design using h~ rdware description languages. synthesis. and ,'.rif,c8 tlon as wcll as changes in e mp hasis in the use n ffundamentals nf computer design. T he focus o n b ask concc:pts remains and manual e~.rci5e!l to enhance thorough understandi ng o f these concepts continue as a mainstay. In n rder In s u pport t he evolving p<:rsp<:c l i~e a nd t o d eal with growing structural problems. notably chapter length. this edition f eatures a m ~jor c h apter reOr ganizalinn, Chapters I Ihrough 6 o f the book lreat logic design. and Chapters 7 throu gh 9 (\ e.1 with digital systems design, Chapters 10 through 14 foc us directly o n c ompmer d e.ign. Thi. arrangement provides ""lid digital s)'!ltem design funda mental, ,,hile accomplishing a gradual. b nltnrn.up development nf fundamental5 fnr u5<' in top~own compu ter d esign in lat er chapters. Eleven of the 14 c hap ters o CO<1cain new material not pre5Cnc in t he second e dition . and . pproxim ace ly 5 0% o f the problems are m<.><lifi ed o r neW. There are <we r a dozen text supplemcnts avail- l~ t~~ I~~ 1[i~lli I ~I~~ I@I ~~I MI~ !lI j,J1J ",1: J, from prior e d ition s. Summariell o f tbe topics c overed in eacb chapter follow. Chapter I - Oi~t.1 C ompute. . and InformAtioll introduces computer systems and information representatio n. including a ne w $I.,<; li on o n G ray cod es. C hapter l -Con,hinarional Lo gk O re"i" deals wit h the basic lheory nnd concepts l or designing and optimizing gate circuits. A new section o n muiti[",cI logic o p timi'.alion appea .... [n addi ti on t o tbe basic literal coun t_ g ate inplll COIInt i . introduced as a more accurate cost cr it erion for use with multilevel logic circuits. Ch~pter 3------Co "'bination~1 Logic Design pr<w id es an ove!'>'iew o f the COntemporary logic design proce. . a nd deals with g ate c) ,aracteriSlics a nd delay, and technology is>;ues such as use of NAND. NO R. AOI a nd O AL a nd XO R a nd X NOR gate functions. The d eta il . o f steps o f t he design proce ss including proble m fonn ul ation. logic optimiza tion . technology mapping. a nd '-erification are co\-ered for combina liona l logic. As a pa rt o f technology mapping. this chapt er contains basic coverage o f ROM s. PLA s, a nd PA Ls. e o.-erage of Fi eld Program mable G a te A rra ys ( FPGAs). ,,'ilh the focus o n the parts typica ll y used in . t udent labs. is p ro"ided as a " 'ebsite supplement to permit updat ing as tb is technology cbanges d uring the ]ifelime of th;s e dition. C ha pter 4--ComlJinational Functions and Clrrn.ts covers t he buildIng blocks o f combinational dellign, Rem nants 01 MS[ logic ha>-e been removed with tbe focus changed t o I ) lundame nl al combinational fu nct ions a nd their implementalions a nd 2) techniqu es for uti liling and modifying these funct io ns and I~eir a ssocial.d implementation s- This focus provid es fundam cnU ls for a cle . ... . understanding o f structured logic design and for visuali,ing the logic re.uiting fmm H Ol syn thesis In a ddition to co>'cring d ttod in g. cneo<ling. code COIl\"ersion. selecting. a nd distributing. new functions s l>Ch lIS enabl in g and i nput _fi . ing are intr odured . Int roductory sections o n Verilog and V llOl a rc provided for tbc various t}'p<:s o f functions. C hapl er 5 - Arithmctk . ",,"<Iion. a nd C lrroil, d eal' with arithmetic lunc tion! and th eir implementations. Beyond number represe ntat ion. addition. s ubtracti on a nd mulliplication, function. and implementations a re int roduce<l for i ncu me nting. decrementing. fIlling. u tcnsioo and . hi fting. Verilog a nd V HDL descriptions a re p rovided for arithmetic functions. Chapter 6--Sc..qucnlial C ir . ...... i ntroduce. sequemial circuit anal )' 5;" and design, Laiche!, master-s la.-e fl ipOops. a nd e dge-lrigge r." nip-Oops a rc w ,'ered with a ll e mpbasis on the [ ) type. O tb er types o f flip-ll ops (S-R. J K. and -Il w hi cn are used less frequcnUy in m odem designs. are co"ered but given less em phasis wi lh in -dtpl h coverage moved t o website supplemen t. Verilog a nd V HDl descrip ti ons of Oip_flops and scq uential . i",u its a re provided. C ~aplcr 7- R eg istc . . alld Regi"er T "'n , fcrs ties toge th er d osely the imple. m entation o f regist . .. a nd tbeir a pplica t;on~ Shift register and c ounter design a rc b a se d o n combining registers with lunctions and implementations i ntroduced in C hapters 4 a nd 5 , O nly the ripple CO\lnter ;., presented a . a IOtally new conce pt. This a pprooch is in keepi ng with tbe reduction o f focus o n circu it s originating a s , .. 0 P r<fo MSJ parts. A new section focu se5 o n re gister cell design for regislers performing multiple o per alion s. Verilog a nd V H DL de""ripl ion. o f Ihe various regisler types a re i mroduced. Chapt .. , 8--Se que n";ng wnd Cuntrol co~ers c ontrol un ;1 design . A n a dd; tional feature a dd ed to the Al gorithm ic State Mac hin e ( ASM) represent .tion is a multiway branch thai is analogous t o the case from Veri log a nd V HDL. H ard_ ...a re c ontro l is emphasized. " 'ith reduced emphasis o n m icroprogrammed COIltrol. C h ap ter ~M c"lOry Basi c; c overs SRA M. D RAM. and b . .ic memory systems. A new section o n synchronous D RAMs treat. the b asia; o f t hese c urren t t ednologies. Veri log and V H DL meMOry m odels a re provided on Ihe website. C.... pt e' I O--Comp uter O os.lgn 8 * , 1 oovers regiSler files. function unit s. 01 dat apaths. and two sim pl e oomputers. A s ingle-qde o omputer a n d a new multiple-qdc oompute r arc designed in S(l me detail with ooth employing hardw;red c omro l. C hapt e, I I _ Instru ction Se t A r chitcC1u .... i ntroduces many facets o f in,truc_ tion s el a rc hi teclure. I t d eals with address c ount. a ddressing m ode . . a rchitecture . . a nd t he t ypes o f i n.truct;ons. Addrer;s;ng m ode. and o ther aspectS o f i nstruction. arc i llustrated wilh b ritt ""gme"IS o f i nstruction code. CIoapler U - RI SC a . .d C ISC Cen'",1 l'~nK U n it . introduces pipelined (!alapaths and oontrol. A Red"""d IlU truction ScI Computer (RISCj design using pi pe lining is gi,en. A new Comp lex Instruc, ion Sct C omputer ( C ISCj design is p resented. This design use, a microprogrammed oontrol unit in COIlj unc!ion with th e RI SC foundation to impl~nlCnl compl~x in'trUC1ion~ C hap' e . 13- lnpn, -O"tpu l MOd C nmm .. ni ",,,i,,n deals ",;th d at. t ran.fer b"t",een I he C PU, input_output interfaces a nd peripheral d c,kes. DiscuS$ions o f a keyooard. a C RT display. a nd a hard disk a . peri ph erals a rc i nduded. a n d a keyboard inte rfa"" i~ illustral~d . O lher topic:s ~o '"CTed range f rom scrial c om mu nica _ tion. includ ing the Universal Serial Bus ( USB) ' " a n i llumation.lo I/O processors. Chapl e. l~ __M e mory S ,."e ms has a particul3T focus o n memor~ hierarohies. The cenoepl o f locality of r efore""e i , introduced and illustrated by consideration o f the cachelmain memory and mai n m emorylhard disk rel'l\ionships. An o,crv;ew o f e ""he design pa ramelc t"$ i~ prO\ided. The I ",almenl o f memory management focu ..... o n paging and a t ra nslation lookaside buffer suppurling ,;nusl memory. In a d dition to Ihe text itself. there a re substantial s upport f ea.ures provided. descriptions o f wh ich fo ll ow. C o mpanion Web, il e (h ll p1Iwww.p",nhaJ l. romimano) COn len t i"cludes the following material: I ) (\>clv e r eading s uwlemen!> i nduding new material a nd m .terial d eleted from prior e ditions. 2 ) V HP L a nd Vcrilog SOurCe files for all u nmp les. 3 ) sol ulions for a oout one- th ird o f a ll text Cha pler and reading supp lement problems. 4) errata. 5) Powerl'o int- .lides for Chaplct"$ I t hrough 9. and 6) projee'io" origi nal ~ fo r c omplex f'gures and l ables from the lut D~ig n Tools packaged with most domestic a nd i nternalional printings o f t he t e" consi >! o f ( he Xilin x" ISE Student Edition $O flw. re graciously provided w ilhout cltarge by Xilinx. Inc. Download a cress to the d emo X E version of the M odel Si m- logic si mul ator from M odel Technology Inc orporated is availabl<: Pre r..,. D ,. t hrough Xilinx. These t ool. c an b e u sed t o e me r s chemati", a nd 51a te d iagrams. compile a nd , imulate V H l) L r ode . Verilog ~ode. o r sche ma tics, synthesize C PLD ~M rmn IIImlmml!l Dm m~ nmmm 11mIImlm~ Im~I;M;!~IIUl WJ~ I ~, I p urchase o f low-<:O$t e xperiment al bard ... are, these too,," p rovide e veryth ing n eede d for 5 tudent, to p e,fonn C PL D based Or F PG Abased e xperime m s. I nstructor's Man ual C<NI tent i nclude. important s uggestions for use o f t he boo ~ . i nformation for o btaining a ltem a ti"e C AO lools, and a n p roblem oolutions. Thi5 manual i . available from Prentice Iiali to i n.true ton at . ..a~mk institutions w ho a dopt the b oo k f or classroom IISC. B ecause o f ils b ro ad c o"erage o f b oth logic a nd c omputer design. t hi , boo~ c an seTVe :\evera! d ifferent o bjective. in s ophomore throu gh j unior leve l cou~s. C h apler.t I through I I. with ""Iected section. o mitted. p rovide an o verview o f h ardware for c ompute r science. c ompu ter e ngineering. e lectrical enginee ring o r e nginuring stu~nt. in g enua! in a single s cmler course. C hapter.t I through 8 give a bas ic imroduction t o logic design. which c an b e c ompleted in a single q uar t . . fo r e l""trkal a nd c omputer e nginee ring s tudems. C overage o f C hapte r.t I t hrough 10 in a s emesle r. with p erhaps K>ftIe s upplement ary m altrial, p rovides a s tronger. mOre C<NIle mporary logic design I realmem . n.e e nlire book. c overed in t ....., q u.rters. p rovides t he b asks o f logic a nd c omputer design for c om p uter e ngineering a nd s cieace ",udems. C o"erage o f t he e mire b ook with a ppropriate . upple m entary m aterial o r a la borato,y c ompone nt c an fill a twosemeSler s cquence in logic design a nd c omputer a rchitecture. Fi nally. due 1 0 its m oder alely paced t reat m ent o f a wide r ange o f topics. t he book is i deal for " ,If-uudy by ~ngin~er.t a nd c ompute r sciennst,Among t he many contributions 1 0 thi, book. uc~lIent ~ t ail~d comm~nt. a nd suggestions o n drafUl o f C hap ter.t I I hrough g were p rovided b y R ichard E. H askell. O akla nd Univer.tity; E ugene H enry. Un;vcr.tity o f N otre O a m e; S ung H u, San Franci$CO S late Univer.tity: a nd Walid I lubbi. New k~y I nstitute of'Jechno-logy. T h eir C<NItributions to text impr",..,ments a re g reatly appreciated. Faculty and stu~nts a t th~ Uni,er.tity o f WiSCQOsin also c ontributed t o t he teXl. A . uggestion from l'rof""'r J im Smith motivated t he direct ion t aken in C ISC design in C hapter 12. and P rofessor I...eQ n S hohel s uggested specific improvcmenUl based o n his use o f t he 2nd E dition. A special t hank s goes t o E ric Weglarz f or his i n-depth reviews o f new material for b oth c ontent a nd d arily.Alw tha n ~s t o E ric a nd to Jim l Ju for preparing oolutions t o n ew and modified p roblems for Ihe I nstructor'. M anual. O ur special a ppreciation goes o f t o all o f IhOiSC a l Prentice H a ll a nd elsew here for t heir efforts on this e d iti on . NOlable a re Tom R obbin. a nd A lice D work in for their guidance a nd s uppor t. Eric F rank for h i. c ontributions during the e a r ly s tages o f th;,; ~dition. a nd D aniel Sandin for hi ...,ry effici~nt a n d h e lpful ha!KlJjng o f t he p roduc tion o f this e dition. Finally. a " ery s pecialthank5 10 Val Kime for her p atience a nd u nderstanding t hroughoul the d e"elopmenl o f t he third editi on . M . MORRIS M ASO OiARU".S R. KI M!! ..., 0 1',"..,. - - LOGIC A ND C OMPUTER D ESIGN F UNDAMENTALS D IGITAL C OMPU T ERS A ND I NFORMATION ogoc design l un<lamemals a nd COIT1!l"1e, dMign l vndamell1als o ra t!l& topics 01 11>. t>ooI<. l ogic design <leals with lt1 e b asic OOOCIIplS and t ools u se<! 10 c lestgn d ig it al h a rdware consisti".. 0 1 . "'rcu~s. C ompute, d esign Ooals wit h the addiIJonal " """"I'ls a nd tDOls u sed t o d esign coml>U1ers a nd oI~ c omple x digital hardware. C ompulen ar>d digotal hardware in g e"",a l l ife r ekmed 10 digital ' ysloms. T hus, _ booIc is a bout u ndemanding a nd <!esigrlinV digital 11'51"""', D ue 10 its gene rality aoo OOIIlPI""iIy, t he OOI11p<JIBr prrNide. a n " ""'I " "hide l or ..... rnlng t he ooncepts 01, a nd t ools 10<, digital system " "sign. In a<ldibon. d ue to its widespread usa, I t!e " ""'PUler "self I s <Ie5e<ving o f stud)'. H ence, ! he foe .... .., 1hi11 boo!< Is o n c ompute", a nd their de.q,. L T he c omputer wi ll b e 001 on~ .. vehicle. b<JI 81$0 a motivator lor 8t..:!y. To this end, we U $O the exploded piclof;a l diag ram 01 a compuler 01 t he c lass c ommon/)' referred to as .. PC t ..... sooaI <::Omp\I1or) gill$tl o n t he ~e page. We uS<! ttlis gGOe<ic C<>m\l<Itaf to h iltlight t he signIfie.once of t he m at"rial ~rod . ,.., its fSll,ltJonship t o !he overeH system. A bIIlaler In t hol cI\aj)1er, we win (li$cuss !he m ajor ~. o f IIle geooric cornpuIer arid see !>Ow t hey relate 10 a bIOCI< diagram o ft"" usod to oescribe .. "',,';ow compute<. 1- 1 D IGITAL C OMPUTERS Today.digital computers ha"~ su<h a prominent a nd growing role in modern .ocicly thai we o rten say we a re in the ~i nform8 t io" 8ge." Computers 8re invol"ed in o ur b usines. transaction s. comrn uni cations. t n,"spona!ion. rnedical ! realrnenl. and COle n .inmenl. T hey rnon;tor our weathe r and environment. In the indus!.ial world. o, 4 0 CHAi'TEIi. 1 I OIGITAL C OMi'VTER5 A NO I NFORMATION Ihey a re heavily employed in design, manufaCl uring. diSlribulion. a nd sales. They have c onui hured 1 0 many sciemific disco,'eries and engineering d""c!opmenIS Ihal would have been unauainable O1herwisc,NoTably.lhe design o f a new p rocessor for a m odern c ompuler c ould nol b e d one " 'ilhoul Ihe use o f many compuleJ'$! T he mOSI slriking propeny o f Ihe digiTal c ompmer is ils genera~Ty. h can fo lIowa s equen"" o f inslructions. called a p rogram, thaI operalC$ o n given data . "llIe he user Can specify a nd change Ihe p rogram o r T d a la according 10 speci fi c needs. A s a result o f Ihi$ fiexibi1ily. general-purpose digilal compuleJ'$ can perform a variely o f informal ioo-processing lasks t baT r ange o ver a very wide Spe<:lrum o f a pplicalions. T he g eneral_purpose digilal compUler is Ihe best h o"" e umple o f a digi'''1 J)'Jlem, CharacTerislic o f a digital SysTem is iTS m anipulation of discreTe e lemenu o f informalioo. Any s ellhal is reSlricled 1 0 a finile n umber o f e lements contains discrele information. Examples o f discrele selS a re the 10 decimal digils, Ihe 26 k ll eJ'$ o f Ihe a lphabet. the 52 playing cards. a nd t he 64 squares o f a c hessboard. Earl)' digital compuleJ'$ were used m ostly fo r n um er ic compUlation s- In this case. Ihe discrele e lements u sed w ere the digiTS. From such a n a pplication. I he t erm digiml compm~' e merged. D iscrete e lements o f information a re r epresenled in a digital system by physical quan!ilie~ c a ll ed s;gnalJ. E Ie<;Trical , ignals , uch a s v ollag.,. a nd currenTS are mosT c ommon, Electronic devices called transiSTors p redominale in t he c ircuitry thaI ; mplemenu these signals. T he . ignals in mOST presenr.<lay e!e<;lTonic digilal sySTems u se j us l Iwo discrete value, a nd a re therefore s aid 10 b e b jtJary. We typically represent Ihe IWO discrele .'alue.> by range.> o f vo lt age values called H IGH a nd LOW. OutpuT m lt age ranges a nd input , 'oltage r a n ge s a re illus_ t raled in Figure 1- 1. T he HIG H OUlpUT voltage .'alue ranges beTween 4.0 a nd 5.5 volts., a nd Ihe LOW OUIPU! vollage " .lu e ranges betw ee n - 0.5 a nd 1.0 m it . T he high i npul r ange allows 3.0 10 5.5 m lts 10 b e r~gnized .... a H IGH. a nd Ihe low i npul r ange a llow. - 0,5 TO 2.0 vollS 1 0 b e recognized a s a LOW. The fact I hallhe inpur ranges a te longer Ihan Ihe o utput r anges allows t he circuils To funClion oorreclly in s pile of variations in Iheir behavior a nd u ndesirable " noise" v ollagc. Ihat m ay b e a dded 10 o r s ubtracted from t he OUTpUts. We give tbe OUTpUI a nd inpUT voltage ranges a n umber o f diffe rent name . . A mong Ihese are H IGH{H) and LOW{ L ), T RUE(T) a nd FALSE{F). a nd I a nd O. H ' G II ww lJ f i GU RE H An E nmp le of V<>1t . ge Rang. . for Binary Signar. t_t I o;gi . . l Compu ,... a s II i . clear thal the higher vollagc ranges a rc aSSOCi"led with H IGH or H, and lhe lower "ol1age range~ Wilh LOW o r L. We find. howcver. thal f orTRUE and I and FALSE and 0, lhere is a choice. T RUE and 1 can b e a$sociated with e ither the Itigher Or lower "ollage range a nd FA LSE and 0 with lite o lher range. Unless otlt erwise indica lcd_ we _ umt t hat T RUE a nd 1 3 associaled Wilh lhc highcr o f the voltage range .. H . and tltal FALS E a nd 0 are associlued Wilh tlte lower o f lhe "011 age ranges.. L. Why i . binary used? In c onlrasll0 t he sil ualion in Figure 11. consider a '1)'$' tern ..-ilh 10 values represenling lhe decimal digil" In . uc h a .)'Stem, t he voltages avaitab!~y. 0 to 5.0 WI1S--<OUld b e divid ed i mo 10 ranges, e!>Ch o f length 0.5 volt. A circuil would provide an OUl put ,'oltage wilhin each o f these 10 ranges. An input o f" circuit would need t o d etennine in which of tho 10 ranges a n applied ,oltagt lie . . If we " 'ish to allow for r>Oise o n the ,ollagts.. then oulput ~oItage might be permil!ed t o range over less lhan 0.25 "olt for a gi"en di git repr"""nlation, and boundaries between inputs could vary by only Ie . . t han 0.25 volt. This would require complex and costly elecllo~ic circuits and still could be disturbed by small "noise" voltages o r small variation,! in l he cirtuits occ-urring d uring t heir manufac ture Or use, A. a con5e<]uence. the use o f such mullivalued circu it . is very limited. Inslead, bi nary ciKuits arc used in which correct ci rcuit o peration Can be achicved wit h significant varialions in b olh the Iwo output voltages and the two input ranges. The resulting transislor circuit with a n o utput t hat is e ither H IGH o r LOW i$ simple. easy to d ts ign. a nd e xtremely reliahle. I nfo rm at ion R ep r esentation Since 0 a nd 1 are aswciated with the binary n umber system. they are the pre_ fe rred nameS for l he s ignal ranges. A binary dig; ~ i . called a />it, In formation is represented in digital computers by g roups of bit s. By us ing various coding tech niques. groups of bi ts can be m ade 10 r cpr"Senl not only binary n umben. b ut also o ther groups o f discrete symbols. Groups of bits. properly arranged. can e ven specify t o the c ompmer t he i n.tructions 10 be executed a nd the data to be proce w: d. Discrete q ua n,ities o f informalion either emerge from the n ature o f the d ata being processed o r may be purposdy q uantized from c ontinuous values. For c nmple. a payroll schedule i. inherenlly discrete d ala c ontaining employee names. social s.ecurily numbers. week ly salarie s. ineome taxes. and SO o n . A n e mp loyec's pa)'check is procew:d usi ng discrele d ata values . uch as Ictl CTll o f the a lphabet (for the employee's name), digits (for the salary). and s pedal symbols such as $. O n the o lher hand. an e nginur may measure the speed o f rotation of an a utomobile whee l. which varies conlinuously with time. but may record only specir", valueS at specific times in tabular forn \. T he enginee r is t hus quanti>:ing the cont inuous d ata . making c!>Ch n umber in the lable a discrete quantity of information. In a case , uch as this. if the m easurement can b e c on vened t o a n electronic signal. the quantization of the signal in both \lalue and time can be per forme<! automatically by an analog-t<KIigilal conversion device. 6 0 C HAPTER 1 I m (aTAL COM~ A ND I NFORMATION C omputer St ructure A block d iagram o f a d igital r ompul"';S s hown in Figure 12. T he m emo l)' Slores p rograms as wen as i npul. OUlpUI. a nd i nlermediate d ala. The d atapath f "'rform. a rithmetic and o ther d ataprocessing o perations a s sf"'cified by the program. The control unit s uf"''''ises 1 M How o f i nformation b etween the v ariou, unit&- A d ala p ath. when c ombined with t he control unil. forms a c omponent r eferred to as a u ntral processing ,mil. o r C P u. Th e program and data prepared by I h" user arc t ransferred into m emory by m eans of a n i npul devi"" such as keyb<>ard. A n o ul pul de,ice. such as a C R T ( calhode-ray l ube) monilor. d i'pl a )"s Ihe results o f t he compUlations and p resent'l Ihem 1 0 Ihc Use'. A digilal c ompuler c an accommodate m any d ifferent inpul and o utpul devices, such a s h ard d isks. floppy disk drives. C D - ROM drives. a nd scan ners. T hese dC"ices use SOme digilal logic. bllt o flen include analog e lectronic drclliL'l.optical sensors. C RTs o r LCD< (liquid crySlal displays). a nd e lectro m echanical componCnl&The c onlrol unil in Ihe C PU rClricv~ . I h. instructions. One by o ne. from Ihc . program s tored in l he memory. F or u ch instruClion. Ihe c onlrol unil manipulates lhe d alapMh 1 0 e~ecute I he o peration s pecified by l he instruction. B olh p rogram a nd d ata a re slored in memory. A digilal c ompu!cr is a p owerfuls)"tem. I I c an f "'rform a rilhmelic compulMions. m .nipula!e strings o f a lphabelic charaNer$. a nd b e p rogrammed to m ake decision. based o n i nternal and eXlernal condilions. M ore o n t he G eneric C omputer At Ihis p oint. "e will bricft)' diloCU SS Ihc generic rompUlcr a nd r elale i l' v arious p ans to lhe block diagram in Figure 1-2. A I t he lower letl o f t he d iagram al lhc b eginning o f Ihis c hapler is Ihe h eart o f t he compUlcr. a n i ntegra l ed d rcuil c allcd Ihe prox:~sso,. M odcm p rocessors such as this o ne a re q uite c omplex a nd consist o f millions o f l ransiston T he p rocessor contains four functional modulcs; lhe C Pu. t he FPU. the MMU. a nd the inlernal cache. M <""", y ~ I ~,~ " oi, tj D'''r- tII In~IIQ\i!~! o FIG URE I l Block Diagram o f. Di gita l Computer I We have a lready discussed the C Pu. T he F PU (floating-pain! unit) i . s ome what like the CP u. e xc<!pt that ilS d atapath a nd c ontrol unit a re specifica lly d esigned t o p erform lI oating.point ope,ation<- In essenCe. these o peration. p ro cess info,mation , epresented in t h. form of sciemi fi c nOlation (e.g .. 1.234 X HI' J. p ermiuing the generic c omputer t o h andle " ery large a nd " ery . mall numbeB. T he C PU a nd the FP U. in r elation to Figure 12. each contain a d M.path a nd a c omrol unit. The M MU is the m cmory managemem unit. The MMU plus the i memal c ache And the separate blocks n ear the b ouom o f the comput er labe led External Cache" and "RAM" ( random IlCc<!SS m emory) a re all p art o f the llli"mory in F igu,e 1-2. The twO c aches a re special k ind. o f memoT)' that allow the C PU and F P U t o get a t th. d ata t o be processed much f a.ter t han with RAM alone. RAM I 'l what is most c ommonly refe rred t o as memoT)'. As i t' main function. the M MU causes the memory that a ppears to be " "aibble to t he C PU to be much, much IIITge' t han the actu al s ize o f t he R AM. Th is is a ccompl ished by d ata transfe . . between the R AM and the h a,d disk . h"wn at the t "" o f the picture o f the g eneric c ompute, . So the h ard disk. wh ich we discuss later as an inpulfoutput dev;';". appears conceptually a s a part o f the memory and inputloutput The con nection p aths . ho wn betw~en t he processor. memory. ~nd e xternal c ack a re t he pathways between in tegr at ed circuit s. These a re ty pica ll y im pl e. m ~ntcd a s fi ne c opper c onductors On a p rinted c ireui. ooard. The c onnection paths below the bus i nterface are r eferred t o a . the processor bus. The connections a b",'e the bus interface a le r eferred to a~ the inpuUoutput ( lIO) bus. T he p 'Ottsso' b u. a nd the [10 b u. a uached t o the bus imerface carr)" d ata ha"ing di fferent numbers o f b it, an d have different ways o f c ontrolling the m o,'e ment o f d ata. T hey may also o pe.ate at different speed<- The b u, interface hardware h andl", t ""'" difference. s o t hat d ata can b e c ommun icated between the two bu . ... All o f Ihe remaining Struelu.", in the gene.ic c ompute. at<; COnsidcn:d p an o f [10 in Fi gure 1-2. In terms o f s heer physical vol ume. these . tructure. d ominate. In o rde. to e nte r informat i" n into th~ c omputer, a k eyboard i , p ",,,idcd. In o rder t o " iew o utput in the form o f te~t o r grap hi cs. a graphics a d.'pter card and C RT monitor a re provided. T he hard disk. discussed previously. is a n e lectromechanical magnetic storage devic<! . I t o r", l a.ge quantities o f information in the form o f magnetic nux o n spinni ng d i'ks c oated wit h magnetic materials. In o rder t o control the h a.d d i.k and t ran,fer i nform.tion to and from i t." disk C<)n trollcr is uscd. The kcyooard. graphics adapt~r card. and disk controller card are all a uached t o the I/O bus- Thi, allows lhese devices t o communicate t hrough the bus interfacc with the C PU alld o ther circuitry connected t o the pr~r bu . ... l'!.c generic coo n pu'er con,islS mainly o f a n interconnection o f digital modules. T o understand thc operation o f each modu le. it i . neceWlT)' to h~,"e a basic knowl edge o f digital . ystem, and their general behavior. G apters I through 6 of this b ook d eal wit h logic design o f digital circuit, in generaL G aptcrs 7 and 8 discuss the p ri . m ~ ry c omponents o f a digital . ystem. their o perati"". and their design. "The o pe rational characte ri .tic5 o f R AM a re expla in ed in C hapter 9. D atapath and control for simple computers at<; introduced in G aptcr t o. C hapters 11 through 14 present th e basic5 o f c omputer design . T)'pical instruction, emplO)'ed in computer instruction set 8 0 C HAI"TER I I D lGtTAl C OMPUTERS A ND I NFORMATION architectures are presented in C hapter I I. T he aTCh it eclure and design of C I' Us are examined in C hapter 12. Input a nd o utput devices and the v ar;"u, ways tnat a C PU can communiC.;lte " 'th them are discussed in C bapler 13. FmaUy. memory hierarchy concepts re!aled t o the e ach'" and MMU a re introduced in C hapter 14. To gui<k the r eade. Ihrough Ihis material a nd to k eep in mind t he fo.",(" as we carefully e xamine m any o f I he lree.. a ccompan)ing discussion a ppears in a b lu e box at the beginning o f e ach chapter t o lie the topics in the chapler t o the associated c omponenl' in I he generic c omputcr diagram at the , lart o f t hi' chapter. A t the c omplet;"n o f o ur journey. we will have covered moot of the various modul.,. of the c ompuler a nd will ha'e an understanding o f I hc fundamentah t hat underlie b oth its function and design. Earlier. we m entioned t hat a digital c omputer manipulates discrete c lements of information a nd t hat all information in the computer is r epresented in binary form. O perands used f or c a ku lations may be expressed i nlhe binary Dumber sys tern o r in t hc deeimal system by means o f a binary code. 11,e l euers of the alphabet are a lso c onvened into a binary code. The purpooe o f the remainder of Ihis c haptu i'l t o introduce the binary number system. binar) arithrncti~. and selected binary codes as a basis for f unller ' Iudy in Ihe succeeding chapters. In relation t o ' he generic compUlcr. this material is ,cry important and ~pans all of t he components except some in 1/0 l hat invol,e mechanical operations a nd analog (as COn l ra,t ed . .i th digital) electronics. 1 -2 The N UMBER S YSTEMS d~cimal n umber system is e mplo)ed in e vuyday a rithme tic t o r epre"""1 by strings o f digilS. D<:pending o n i l' p osition in t he string. each digit has a n associated ,alae o f a n i ntcgtr r aised 10 t he p ower o f 10. For e xamplc. t he d ecimal n umber n 4.S i . i nterpreted t o r epresem 7 hundreds p lus 2 t ens plus 4 a nits p lus 5 tenlhs.. The hundreds.. tens.. units, a nd t enths a re p owers o f 10 implicd by t he p<>'<ilion o f t he dig;t . . T he value o f the num~r is c omp ut ed a . follows: num~rs n 4.5 - 7 X 1 0' + 2 X 10' ~ 4 X ](1' + 5 X 1 0-' T he c oo,enl;"n is 10 w rile only the digilS and infer the COOTesponding powers n f 10 from t heir position . . In general. a decimal number , ,it h " digil. to ' he left o f the decimal point and m digils t o the right o f the decimal point is r epresemed by a s t rin g o f coefficient's: E ach codfocient A , is O ne of 10 digits (0. l . 2. 3. 4, 5. 6. 7. 8. 9 ). T he s ubscript value i gives the position of the coefficient and. hence. the we igh' 10' by which the coefficient must be multiplied The decimal number system is said t o b e o f ba<e o r 10. because . he coe(f1c ienlS are mulliphed by powers o f 10 a nd l he Sy>lem uses 10 distinci digit . . In rod,,, )_1 I N umb..- Sy....... g ener.I, a n umber in b a"", con lains' digil$, 0, 1 .2, ___ , ' - I, and is p ower series i n, wilh Ihe general form , ' ' ..A . _ IT0-' + A _ _ ), 0-' + . .. + AT ; A j + A _" -, + A _1' -) + . .. + A _ . .. " - ... , 0 9 e~pressed .s a + A _. .' -. When the number is expressed in ]">Q'!ilional n otation, only t he coefficienlS a nd the radi x point are ",yincn down; In g eneral , the - .- is called the ' /ldu p<Jin'_ A . _ I is r eferred t o as t he " 'Ofl .igmflra", {Iigi1 (msd), a nd A _ .. is referred t o as the 1 M" <icni/icanl digil (Isd) o f t "" n umber . Note lnat i f m = 0, the Isd is A ..., . . A o. To distinguish b etween numbe ... o f different b ases, it is customary 10 e ndose Ihe coefficients in p arentheses a nd place a subscripl a her the rig.ht p arenlhesi. t o in<l icate t he base o f t he nu mber. Ilowever, when the contexT makes the base obviou s, it is not necessary to use parenTheses The following illuslrates a base-5 number w ith" . . 3 a nd", . . 1 a nd ils conversion t o decimal: ( 312.4)!" 3 )(5'+] ) (5' + 2x5"+4 )(5 - ' . . 7 5+5+2+0.8 . . (82.8)'0 Note t hat for all Ihe numbers witho ut the base designated, the arithmelic is p er fOfmed with decimal numbers. N ote also Ihat the base-5 s)'S tem uses only five digits, and. therefore. the values of Ihe codficients in a n urn""r can b e only 0, I> 2. 3. a nd 4 ",he n e~presse d in t hat s)'S~em. A n alternaTh'e m ethod l or conv~rsion t o bas<: ] 0 that reduce< The n umber 01 operati-ons is b a.ed o n a lacto.-ed form o f the power serieo: ( .. .{{ A . _1 ' + A . _ ,), + A . - J) ' + ... + A , ), + A o + (A_, + (A _:+ (A _I+ . . + {A " ,'I+(A _ . . ~ , -I-A mr _1 )r -t _1 )T .. . ) r -I )r _j )r _l For ' he example above. (312-4 ), " ( 3 X 5 + 1) X 5 ) + 2 + 4 ) (5-' " 16)(5 +2+ 0_8 ~( 82_~ )1O ]n addition t o d ecimaL three n um""r s ystem, are used in c ompuler work: binary, octal, a nd he<adecimaL These are hase2. b""c8. a nd basc16 nu ml>ct s)"i tem s, respeCTively. B inary N umbers T he binary n umber syslem i. a ba..,2 syslem wilh 1"'0 digits: 0 and I . A binary number such as 11010_] 1 i< e xpressed wi lh a string of I ' s and O ~ a nd, p<.>$Sibly, a 10 0 C H.}.I'TER.' I DIGITAL COMPUTERS AND INFOR.MATION o T ARL E 11 I'o,, ~rs " , , , , , 0 ,. , , " " M ,~ of 1 ''''0 " " " " " " " " W ,. ,~ '" ,= ,.~ " ... g,l'i2 "'" 32,768 ,. " " " " " ~ " " " 65.536 131.072 262, 144 5 24288 1.048.576 2,O'n.lS2 4,194.J(j.l 8.388,<j bi nary point. T he d ""im. 1 c~u i v"lcnt o f a bi nary n um ber can be fou nd by u p"nding the n umber into a power , erics with a base o f 2. For exa mp le, (11010), _ I x 2' + lx2'+OX2 l + 1 X 2 ' -tOx 2" - (26),o As n oted e arlier. the d igih io " b inary n umber are called bit s- When a bit i~ e q ual to 0, it d oes nOt c ontribute t o the sum d uring the c<mversion. Th erefore, the c on version t o deci mal C 'n be obluincd b y add in g the numbers with power<; o f two cor responding t o the bits that a re e qua l tn I. Fnr e.~ m ple. ( 110101.11)2 32 - t 16 - t4 + I -t O.S + 0.25 - (53.75)\0 ' ll' e first 24 numbers obtained from 2 to the p ower o f n atC lisled in Table I !. In c omputer " 'o rk . 2'" i< r eferred 10 liS K ( kilo).2'" as M (mega). a nd 2-'" as G (giga) 1 1",\ 4 K _ 22 x 2' 0 ~ 2 " ~4,096 a nd 16M _ 2 ' x 220 . . 2Z4 . 16,777,216 T he c om'ersion o f a ' kci m 31 n umber t o binary can be easily achieved by a m ethod Ihat successively sublracts ",""CT! o f Iwo from the decimal nu mber. Th c onverl the decimat number N to binary. first rmd Ihe greatest n umber tha t is a p ower o f t wo (see Table j .l) " nJ t hat. suhtraClcd from N. p rod uces a posit;-c d if. ference. Lcl t h~ difference b e designated N,. Now find t he g reau>l numhcc th,1I is a p ower o f two and that. , ubtracted from N" pTOduce s a posili'"e difference N ,. C o nt in ue Ihi< pTOc<:dure u nt il t he difference is ,-ero. In this waY,the d ecimal number i . converted to its p owers. of. two componCnls. The e qu ivalent binary number i< o btained from (he coefficients o f a p ower scriL"< that fonns the Sum o f the component s. l 's a ppear in Ihe bi nary number in the positions for w hich terms appear in th ~ p ower " 'ries. and 0, a ppear in all o ther positions. This method is d emonstrated by t he cOI",e"ion o f decimal 625 to binary as fol lows: 6 25-512 - 113 _ N , 512 _ 2 ' 113 - 64 = 49 = N l 64 _ 2" 1_2 ' Numb S,.,. .n.. 49 - 32 . . 17 = ",) ]6 . . 2 ' 1 - 1 - 0""', II 32 _ 2' 17 - ]6-] - "', 0 ]="1!' (625), . .. 2 + 2" + 2' + 2 ' + r> '" (]OO]] ](XXI]h Octal and Hexadecimal Number. A S p .c,iouoly m entioned. all w mput et1 and digital o)'S tcms usc the b inary . epre senlat ion. The octal (ba>e /I) a nd hexadecimal (basc 16) syslems are u >eful for rept he properly Ihat their resent,ng binary q uanlitie. indirectly t>ecau,", they base. a re po"-c~ o f two. Since 21 .. 8 and 2" . . ]6. c ac h <>elal digit correspond$ 10 t hr ce b inary d'gilS and each he~ad e";ma] digit w rrespond$ t o four b inary digiu. T he m ore o ompacI representation o f b inary numbe~ in t il he r o c lal o r h cudec imal is m uch m ore COfI"enienl for p eople I han using bit ' Irings In bi nary l ha l a re I hree t o f our timell I S ion$- Thus.. m05t c ompUicr m anual, 11 )(: t ilhe r octa] or b exadccimal nUlnbe rs 10 Jpe<:i fy biliary quanhl;CS A g rou p of I ~ b tl S. f or e lllmplc. can b e r epresented in l be o ctal ' Y'lem with o nly fj'e d ili !s. A , roup o f 16 bi lS can be represented in h eudecimal wilh f our d,gits. T he ch.oice b etwecn an o ctal a nd a h exadecimal . cp . es.enlalion o f b inary n umbe . . is a .bit.ary. a llhough hexadecimal t end. 10 win o ut.lincc bi tt o ften a ppear in a g ro up o f . i ~e divisible by four. T he <>elal n umber . y.te m i , t he b ase /! ' y",c m wi th d igits O. 1 .2.3.4.5,6.7. An u a mplc o f a n octal numbc r I s 127.4. T o d etc .minc i t. equivalent decimal v~ l u c. we expand the number in a p ower series with a base o f 8: P""'''' { I27.4 ), " I X Rl + 2 x 8' + 7 X go + 4 X 8 -' = (87.5)'0 Nore that lbe digits 8 a nd 9 Clnnot appear in a n o ctal n umber. I ! is cw;tomary to " "" tbe fil"Sl r di g'l$ from th~ d,"",mal system. s tlrtin, W11h 0. 10 , epre""nt l he coefficJcnl$ ' n base..,. s ystem wben r is 1e5$ , han 1 O.1be l ellers o f t he a lphabet a re used t o l upplemenl t he d 'p ts when r is \ 0 o r more. 1 be h exa d mmal n umber S)'SIem . . a base-16 s)'Item wilh lbe til$! 10 digits borrowed l he decimal system a nd l be ]e l1 ef$ A. C. D. E. a n d F used for t be 'alue ~ 10. I I . I Z. 13. 14. and 15 . respec!i"~ly. A n e U01ple o r a h uadecimal n um ber;' n. rrom (B65F), . .. I I X 16) + 6 X I~ + 5 X 16' + 15 X 160 . . (46687 ) '0 T he firsl 16 n U01be rs in the decilllal. binary. <>etal. a nd hexadecimal nUlIlber $)'1. tC IIl ' a rc liSled in Table 12. Note th ntt hc ileq ucnce o f bina!)' numbers follows n prciCfibed p "ttcrn . Th e lea. t $iKnifica m bit . ltc rnatc , belween 0 a nd I. th e !joCwnd s ignificant bit a lternates belween t "'0 0 ', a nd Iwo 1"s. t he third significant hit a lte r n .leo b e t",..,n r our 0 , a n d (o ur I . . a nd the lIl 05t significant bit alternatel' betwee n e.ghl 0 , a nd c ighl I . . T he oo'l\"ersion from b inary 10 octal is u . ily a.romplish~d by p "rti ti oning lhe b inary n umbe r i nto Croups o f th.e.: b it. e ltC h. Marting from t he b inary poInl 12 0 C HAPTER 1 f D lGITAL C OMPlITERS A ND l NFOR.MATlON o TAlILE I : N ulll""n; . . iI~ O ifJc: ntll . ... s D eclllUll BiMr'y Octal H e . .de<:lmaI ( ba . .. 10) ( ba. . 2) (ba. . 8) ( ba_1fi) 00 0000 00 "' ~, " , , , , m 0000 0 0" ~ Oll l "' m 0101 0110 ~ "' moo M M ~ ru ,~ 00 M 00 '00' 1010 1011 " " " " " 00 1101 I ll O I II I " ru ~ ~ '" " " " " " " " , , A " c , , D and pr(lcd in g t<> !l,e leI! a nd to the righ1. The c orresponding octal digit is t hen a~signed to e ach group. The fo ll owing e xample i1lU$1ra1C!; t he p ,oced ure: (010 110 0 0 1 1 010 11. 111 100 000 I 10 ), . . ( 26 153.7406)8 T he corresponding octal digi t for each group o f tluee bits is obtained rrom !he firs t eight entr>cs in Table 1 2.Th make the lotal c ount o f b i!;" m ultiple ofth,ee.O~ can be 0i1 the lef! o f t he string o f bits to the lell o f t he binary point. M ore importantly. Os must b e added o n the right o f 1he string o f bil$ to the right o f 1he binary point to m"ke the number o f bilS a mul!iple o f three a nd obtain the correct octal resull. ",Ided C on'crsion ffOm b ina,y to he~adcci mal is s imilar. except that 1he binary numl>er i ~ d iviMd into gfOUI'" o f four d igits. T he previous binary n umber is c on verted t o hexadecimal as f01l0W!;: (0010 ] ]00 0110 1011. 1111 ( J(O) Ol IO) , . . ( 20i B.F06) ,. T he corresponding hexadecimal d igit l or e ach g roup of fo ur b its is o btained by ref erence t o Tab le ]2. Conversion from octal o r hexadecimal !O binary is don~ by r e.ersi ng the pro c edure just performed. Eac~ o ctal digit i , c on.erted !O a 3bi1 binary equivale"t and U lta O's ar<: d eleted . Similarly. each hexadecimal digil is c on.erted to its 4 bit binary e q ui valent. This is illustrated in ' he following . xomp les: ( 673.121. _ (3A6.C)" ~ O il. 001 010 _ (110111011.00lOlll _ (11101 00110. 11 ), 0 0 11 1010 0110. 1100 110 111 Number Ranges In d igital c omputers, t he range o f n umbers t hm c a n b e r epresenled is b a""d on lhe n umber o f b its available in t he h ardware ~tTUctu res t hat , tore a nd p rocess information. T he n umber o f b il' in t hese . tructures is m ost f requently a p ower o f two. s uch a s 8 , 16, 32, a nd 64 . Since t he numbers o f bi ls is fixed by the struclures, t he a ddition o f leading o r t ra iling z eros 1 0 r epre""nt numbers is necessary, a nd Ihe range o f nu mbers Ihal can be r epresent ed i . a lso fl~ed. F or e xample, for a c omputer proceiliing l6-bil unsigned integers, t he n umber 537 is r epresented a s 0000001000011001. T he r ange o f integers t hai c an b e h andled by tni s representation is from ( I t o 2 '6 - 1. I hal is, from ( I to 65,535. If t he same c omputer is p rocessing l6-bit unsigned fractions with t n. b inary p oint t o the left o f t he m ost significant d igit, t hen t he n umber 0 .375 i . re prese nt ed by 0.011((((0)))))))). T he r ange o f f rachons t ht can be r epresented is from ( I to ( 2' 0 - 1)12". o r fro m (1,(1 to 0~74 1 2. In l ater c hapters. we wil l d eal w ith fixed-bit r cpr.scm"lions a nd r ange. f or b ina ry sig ned n umbers a nd floating-point num ber . . In b oth o f t hese cases, . ome b its are used t o r epresent i nfor m ation o t her I h an s imple i nleger o r f rac ti on v alue . . 1 -3 A RITHMETIC O PERATIONS A rithmetic o perations with n umbers in ha"" r follow the same rules as for decimal n umbers. H owever. w hen a b ase o ther Ihan th~ familiar b ase 10 is used, One m uSI be careful to use o nly, allowable digits and perform .11 e omp LlI .tions with b ase, digil s, Examples o f t he addition o f two b iM')' n umbers a re a s lollows (nole Ih~ n ames o f t he o pera nds for a ddil i"n)' Carries: r om 101100 Augend: 01100 101 10 A ddend: +](XX) I + 10 111 11101 101 lO t Sum: The sum o f t wo b inary n umbers is c akulated following t he same rules as for d ed _ mal numbers.. e ~cepl I hat t ne , u rn digit in a ny position can be only I o r O. A I,o, a c arry in bin ary occurs if the Sum in a ny bil posilion is g realer I han l . ( A c arry in decimal occurs if t he s um in a ny digil position is g reater t han 9.) Any c arry o btain ed in a given posilion is a dded 1 0 t he bits in t he c olumn o ne significant position h igh". In I he first example. since all o f t he carries are 0, t he sum bits a re simply Ihe sum o f t he a ugend and addend bils, In t he s econd exa mple. (be s um o f the hil ~ i n Ihe second column from l hc right is 2, giving a Sum hil o f 0 a nd a c arry b il o f 1 (2 _ 2 -l- 0). T he c arry b it is a dded with t he I ' , in t he third posilion, giving a snm of 3. which p roduces a s um bit o f I a nd a c arry o f 1 ( 3 = 2 -l- I). 14 0 C HAI'TER t I D lGtTAL C OM I' UTEIlS A ND t NFORMATtON T he following are " ,"mplcs o f t he s ubtraction o f two binary n umbers: as with a ddition, n ott the names o f the operands: Borrows, r om 0 0llO Min uend: 10110 lO t to - 10010 - 1001 t 0 0'00 "'''' Subtrahend: Difference: 00110 \00 \ 1 - I I I IO X 1111 0 -lOO I I 01011 T he rules for s ubtraction a re t he same as in decimal. except Il1 ut a b orrow inlO a given column "<ld. 2 t o t he minuend bit. {A b orrow in t he d ecimal system a dds 10 t o the min uend digit.} In the first e xample s hown. no borrow~ o ccur . ..., t he d ilfer_ ence bits a re simply tho mi nuend b it. mi nu s t he s ut>1rahe nd bits. In the second example. in t he right p os itio". t he s u btrahend bit is I wi th the minuend bit O. SO it is necessary 10 b orrow from t he sccond poo;itio n ... ~ l1 own . This gi,'''-~ a d ifference b it in the first poo;ition o f 1 (2 + 0 - I I). In t he s econd poo;ition. t he b orrow i . s ubtracted. s o a b orrow is again n ecessary. Rec.1111hat. in Ihe c "ent t hat the s ubtra. hend is larger than the mi m,cnd, we . ubtract the minuend from the su btrahend ~nd give the r "wlt " mi nus sign. This is t he case in t he thicd e x~ m ple, in which tili' in terchange o f t he t wO o pemnds i . shm,"". T he fin.1 operation t o b e ill ustrated is b inary mull iplieotion, w hi t h is q uite simple. The mu lt iplier d igits ace nlw;ll"' I o r (J. T herefore. the partial p roduct' ace ~q "n l e i1her to t he m ultiplicand o r t o O. M ultiplication is iliustrMcd by t he fo ll ow_ ing e xample : Mu l tiplic~nd: Multiplier: 10 1 1 )( tol lOll "'" I UI 1 I >r<~l u et: II(JI I I A r ilhme t ic o perations with octa l. h exadecimal, o r a ny o ther b ase-, s},s t om will n orma ll y r equire t he f ormulation of t able. f rom which onC o blain, s ums and products o f t wo d igits in t hat b ase . A n e asier a lternat ive f or adding two n umbers in b asc, is to c onvert e ac h p a ir o f d igits in a c olumn 10 d ecimal. add th~ digils in d ecimal. and t hen c onvert t he r esult 10 tho c orresponding , um a nd c arry in t he b a.e -, s y.tem. Since addi tion is d one in decimal. we c an rely on o ur m emories f or o bta ining t he e ntries f rom t he famil iar d ecimal a ddition t able. T he , equence o f s tep' f or adding t he two hexadecimal n umbers 59F a nd E46 is . how n in E xample 1-1. t_J I Arithmcno Op<m;oru E XAMPLE 11 0 15 Hexadecimal Addition Perform the a ddition ( 59F),. + ( 46)", . Equivalent Decl"",t Clk:ullUon H ~deeim~1 1 Carry 7l 1 19 - 16 + 3 "I '" EH 13 E 5 - : , ~5 14 _ E - Carry 21 _ 16+.S The e q uivalent decimal calculation columns on Ihe right show (he m e nta l reaSOn in g thaI must be c arried o u t to produce cach digit o f the hexad ecimal sum. Instead o f adding F + 6 in hexadecimal. we add t he "'lu;va lent decimals. 15 + 6 = 21. We t hen c on,u t back t o h exadecimal by noting th ot 21 = 16 + 5. T hi' gi'es a , um digit o f 5 a nd a c arry o f I to t he next higher o rder column of digiti- The other two columns a re a dded in a similar fashion. T he m ultiplication o f two b ase, n um bers can b e accomplished by d o ing all t he arithmetic o pera tions in decimal and c omerting intermediate resu lt , one a t a time. Th;s is ill ustrated in the multiplication o f twO o ctal ~umbers ,how ~ ~ ex t in Exomple 1-2. E XAMPLE 12 Octal Multiplication Perform the multiplica t io n (762)3 x ( 45)., ~., '" " 4 672 3 710 4 3772 ~., ," 5 ><6+1 5 ><7+3 '" 4 x6 + I 4 ,, 7+3 - Declmat 10 _ 8+2 31-24+7 3 8=32+6 8 - 8+0 25 - 24+ I 31 _ 24+7 ~., -" -" - '" '" " .n T he c omputation, on Ihe right show the meni al calc ul ations for each pair of OCtal digits. The octat digits 0 t hTO ugh 7 have the ,arne vo lue as their c orre,ponding doci mal digits. T he multiplication of two octal digits plu, a carry. d erhed from t he calcu lalion on the previous line. i , d one in decimal, and the res ull is t htn r on'erred back t o OCl,!. The lefl d igit of the two-digit octal rcsull gives the carry t hat mustOe a dded to Ihe digit p roduct on the next li n e. T he blue digits from the oclal result, o llhe dec im al calculation, a re copied t o t he octal partial produc," on the left. For example. (5)< 2 ). - {12l.. T he left digi!. I. is the carry to be a dded 10 the p roduct (5)< 6) . and the blue least significant digit. 2. is the corre'ponding digit of the o ctal partial product. When t here is nO digit produC1lo whi ch the corry can be a dded. the carry is written direclly into the octal p anial p roduct. as in the case o f the 4 in 46. 16 0 C HAPTER I I D IGITAL C OMPUIE1.5 A N D I NFOR MATION C onvers ion f rom D eel ma l l o O t her B ase s T he COfIversion 01 a n umber in b ase r 10 d ecimal is d one by u pandinllhe n umber in a p o, e. s eries a nd adding a l1lhe lerm!. as s ho wn previously. We now 1're$Cn l a g~ner al p rocedure fo r t he re...::,.,.. o pe ralion o f o onverting a d ecimal nllmber 10 ~ n umber in 00"" r I hat is rd aled 10 Ihe a l( crnal ive u pan.ion 10 o;Iecinl ~ 1 in Scction 12. If t he n UOlber i ncludel " rodix point . il is n e<:essary 10 s epara le the number into a n int eger p an a "d a fraction I>Irl. s ince Ihe two pariS OlUS I be c o nverted dif ferently. The w nvers ion o f a dcciOlH I int eger 10 a n umber in ba se. i$ d o ne by dividing the n umher " nd all successive quol ie n15 by r a nd accu mu la ting I he r em ai nden. This prooxdure I i b ell expl ai ned by e~a m ple. E XAM P LE I ) C , ".ve~ o . or Oet; m . "nl ~ '" 10 0<1 111 C on .c r! d ccima115) 10 QCI.I: T he con...::rsi"" i . 10 b ale 8. F im . 153 is d ivided b y 8 10 l i.e a qUOlienl 0I1~ a nd r emainder o f I .u shO'lln in bl ue. T hcn 19 is d ivided by g 10 l ive:' qUOIiem o f 2 a nd a r emainder o f 3. ~lnally. 2 is d l,ided by 8 10 give a qUOlienl 01 0 a nd a r emaind er o f 2. The coefflcienls o f I he desired OC lal n umbe r a re o bl.i ned from t he remainders: 15318_19-+-1/8 19//1 - 2 -+-3.'8 218 - 0 -+-2/8 1 Le"", -3 R em"lOde' - I Significant digil -2 Mosl ligniticn nl dig', ( 153),o" (231 h NO le in E umple I ) I hll t he remaindeB a re r ud from laot 10 fiBI. as ind io cated by the a rrow, 10 o bt.in t he COfI\"Cned n umhcr.' I"be qlK)ti~nu a re dIvided by r u nlillhe result ;s O. We a lso can usc Ih rs p rocedure 10 c on'"C r! d ecimal i megen 10 b inary a s s ho ...n in Example 1-4. In Ihis a se. t he b ase o Ilhe t;QfIverted number is 2. a nd theTCf~ .al l th e divisions m\lSl b e d one by 2. E XAM PLE 1-4 Cn ~ . ~f).lo,o n r O et; m. 1. I"r '"' to Binary Con,ert decimal 41 to binary: 4112 _ 20 + 1/2 2 M - 10 1000 - S 5 f2 - 2-+-112 2n - , 1!2 - 0 -+- 1!2 (41 )'0 - (l0l001), R ~ma i nd cr _1 -0 -0 -, -, -0 Least significarll digil 1_3 I A fith",.ric Oper>tion' 0 17 O f course. the decimal n umber could be converted by the sum o f p owers o f two: (41)w 32 + 8 -I- 1 (101001)2 The conversion o f a decimal fraction t o base r i, accompli,hed by a m ethod s imilar to t hat used for integers. except t hat multiplication by r is used instead o f division. and integers a re accumulated instead o f remainders. Again, the method is b e,t explained by example, EXA~1 P LE 1,5 ConH'n;ion "r o.,..,lm~1 r....""Jons I " Bi.."ry C onvert decimal 0.6875 10 binary' R rst.0.005 is m u ltip~ed by 2 to give an in teger and a fraction, The new fraction is multiplied by 2 to give a new integer and a new fraction. This process is continued until the fraclional part equals 0 or until t here are enough digils t o gi'''' sufficienl accuracy. The coefficients o f Ihe binary n wnber are oblained f rom Ihe integers . . folioW!;: 0 .005 X 2 2 13750 0 3750 x 2 - U7500 0.7500 x 2 _ 1.5000 Integer = I Most "gOlfkant dtgtt -0 1 0.5000 x 2 = 1. 0000 (0.6875)\0 - (0, 1011), Least SlgOlficant d lgtt N ote in the foregoing example t hai Ihe inlegers a re r ead from firsl 10 1 .1, a , . indicated by t he arrow, 10 o btain Ihe c onvened number. In the example. a fini te n umber o f digits appears in Ihe convened number. The process o f mUltiplying fraction, by r d oe. n ot necessarily e nd with zero, s o we m ust d ecide how man}' digitS o f Ihe fraclion t o use from Ihe conversion, Also. r emember t nal Ihe mulliplication, are by n umber r. T herefore. 10 con"ert a decimal fraction to o ctal. We must multi_ ply the fractions by 8, as s ho wn in Example 1-6, E XAMPLE 1-6 C onwrsion o r o.,..,imal ."'cciOIl< to Octal C onvert decimal 0.5 j J to " t hree-digit octal fraction, 0 .5jJ){8 = 4 1().1 0. 1(\4 ){ 8 - 0,832 0.832 )( 8 = 1'1656 O.656){ 8 - ~248 Integer = 41 Most significant digit -0 00 -5 Least stgmfican1 d lgtt The Register to View Answero t hr ee . ignificant figures. is o btained from II1e i nteger digits- Nole t hai the last i nteger digit. 5, is used for rounding in base 8 o f the ,;erond -to-thc-Iasl digit. '" t o o btain (0.513)10 - (0,.t07k 18 a C HAI'TER 1 I l JIGITAL COMPUTEI>..S A ND IN FOItMATION T he ~onve~ion o f decimal n u mbers W h bolh integer a nd f raclional p aris is il d one by oonvCTt ing e ach p art s eparate ly a nd lhen combin in g lhe two answers. Using the results o f E xample I -J a nd E ,"mple 1-6, we o bta in (153_ 513} ,o - (231.407)" 1_4 D ECIMAL C ODES T he bin~ r y number sySle n' is the most n atural system for a com pUler, bUI p eople a re accustomed 10 Ih e decimal syslem , On~ way 10 r ewlve this d i{fercnce is t o convcr! decimal n umber,; to binary. perform all a rithmdic calculations in b inar y, a nd t hen c om'cr l Ihe bina ry results b ack 10 decimal. This m .lhod req uires thaI we store the decimal n umbers in the c ompu ler in a way thaI lhcy can b e c onverted 10 binary. Si nce the "om puter can accept on ly binary values, we must r epresent the decimal dig ilS by a c ode that contains I ' s and 0 ' .. It is also pos,ible t o p erlorm the arithme tic opcr"li..,ns directly wit h decimal numbers when they a re . to red in t he oompulcr in c oded lorm. A n II-bit binary rode is a g roup " f II bits that assume u p t o 2" d i. ti nci c ombi. ll al io", o f l ' s a nd O's, wit h each c ombi nation rcprese nl ing " "e e lement 01 t he sel b eing coded, A sct 01 fo UT c kmenls c a n be c oded with a 2 b it bina ry ><Ic, with e ach elem ent assigned o ne o f t he following bit comb inOl i,," S' 00, 0 1, 10, 11. A set o f 1\ e lemonts r equires a 3 bil code. a nd a SCI o f 16 elements req uires a 4bil c ode _Th e bi t c ombina tion, o f a n lI . bit c ode can be d etermined f rom th e count in bi nary from o to 2" - t. Each eleme nt m u,t b e a ssigned. u nique binary bit combin at ion, a nd nO IwO e lements Can h ave th e sa me " a lue: o t herwiw, the c ode assignm ent is . mhiguous, A binary cod e w;1I h ,ve w,,'" u na s.<; ig" cd bit combinations if Ihe nllm ber o f elements in I he set is not a p ower o f 2. The 10 ecim.1 digils fo rm s uch a set. A binary code Ihat di,tinguishes among 10 clements must co nt. in a ticall foUT hits, bUI six o ut 01 I he 16 possible combina ti ons wil l r emain u" assigned, N umerous dif lerent binary c odes Can be Obtained by a rrangiag four bits inlo 10 d ist in ct com bi . n. t io n . . Th e code most comnw nl y used for the decimal d igits i, the s traightlo ....'ard binary assign me nl li sted in Table 12 on page 12. T h is is ca ll ed binarY'''OII~,1 d eci " ,,,/ and is c o mmo nl y r derred t o as BCD, O l her decimal cOOes a rc possible. a few of whic h arc p resenled in o ,apter 3_ T.ble 13 gi>'es a 4 hit c ode {or eac h dec im al digit. A n umber with / I decimal digits will r equire 411 bits in BCD. ThUs, decimal 3 % is represent ed in !lCD wilh 12 bils as 0011 1 0010110 , ,;Ih e ach gro up o f four bits r epresent in g o ne decimal digit. A decimal nu mbe r ;n ! lCD is t he s ame as it s e qu ivalent binary number o n ly when t he n umber is belween 0 a nd 9, inclusive. A B CD nu mbe r greater t ha n 10 has a r epresentation d ifferenl from its equivalent binary number. eve n though both conlain l 's a nd O's. 1-4 I oro",.. o coo.. 0 19 T ABLE I J RinaryCotIetI D ed"",' (BCD) DecI"",1 S ymbol " , , , , , " 'CO D lgi! = ~, OM 0 0" moo 010 1 OliO O lll ,~ '00' More{wtr. (he binary c ombinalions 1010 l hrough 1111 a re n ot used a nd h ave n o m eaning in l he B CD o odt, Consider decimal 185 a nd i I' c orresponding value in B CD a nd binary: (185)10 - (00)1 1 00) 0101)1\CD = (10111001), T he B CD v alue has 12 bits, hut (he e qui"alenl b inary number needs o n ly 8 bil"- 11 i$ o hvious that a B CD n umber n eed, morc b it. lhan ilS e q uivalenl binary value. H owcvcr. lh ere is an a dvantage in I he use 01 decimal numbe~ b ecause c omp uler i nput and outpUl d ata are h andlcd by p eople w ho use t he decimal syslem, B CD number> arc dc<:im.1 number> and nOi b inary numbe .... cvcn though they a rc r ep r e"'nled in bils. The only d ifferen ce b etween a decimal a nd a B CD n umber is l h,t decimals a re w rinen wilh (he symbols 0, 1. 2. .... 9. a nd OCD numb<:rs use Ihe b inary c ooe, 0000.0001 . 001 0, .... 100 1. B CD A ddition C onsider t he addition of (wo decimal digits in BCD. togelher wilh a p os, ible c arry o f I from a previous I.", significant p air o f d igils. Since each digil d oc. not e xceed 9. Ihe sum cannot b e g realer Ihan 9 ... 9 ... 1 = 19. t he I b eing a carry. Suppose we add Ihe B CD digits a , i lt he y w ert b inary numbers. T he n the binary s um will p r<)o d uce a result in Ihe range from 0 10 19 , In binary. this will be from 0000 10 ]00 11, bUI in BCD, il s hould be from 0000 10 1 1001, t he firsl 1 b eing a c arry , nd I he nex( fOllr b it' being Ihe B CD digil s um. When t he binary sum is less than 1010 (wilhoul a c arry) , lhe c orresponding B CD digit is c orrect BUl w hen t he b inary sum i$ g rcaler (han or e qual 10 1010, lhc result i< a n invalid BC D d igit Th e addilion 01 b inary 6, (0110),. 10 Ih" su m c on"erts ;t lO t he correct d igil and also p rod uce. a dccimal carry as required, T he r eason is Ihat Ihe differcnce between a carry from Ihe mosl significant bil position of t he binary sum a nd a decimal carry i . 16 - 10 = 6. 20 0 C HArTER I I D IGtTAL C OMPUTERS A ND I NFORMATION Thus, Ihe decimal carry and t he correct B CD sum digil are forced by adding 6 in binary, Consider Ihe nexl Ihree-<ligil BC D add ilion example, I EXAM PLE I' Bcn A dd ition I II) , OCD carry moo "" '" moo +0100 + 489 Binary s wu A dd 6 B CD sum B CD resull '00' '"" +"'00 1101 +0110 + 100 1 ..n" + 0110 10011 '00 ' 10111 01 11 00 .. In each position, the t .... o BC D digils are a dded a< if Ihey were IWO binary number>. I f Ihe binary sum i , g realcr Ihan 1001. we add 0110 t o o blain I~e com'<;1 B CD digil sum a nd" carry. In I~e righl column . Ine binary su m is equal t o 17, T he p resence o f Ihe carry indicales Ihal Ihe sum is grealer Ihan 16 (certainly grealer Ihan 9). so a c orreclion is needod. T he addilion o f 0110 produces the correCl BCD digil , urn. 0111 (7). a nd a ~arry of 1. In Ihe nexi column. Ihe binar), sum is 1101 (13). a n invalid B CD digil. Addition of OlIO produces Ihe c orrect B CD di gil sum, 0011 ( 3). and a carry of I. In lne final column.lhe binary sum is equal 10 1001 ( 9) a nd is (ne c orrecl BCD di gil , P arity Bit To deleci error.; in d ala communication a nd processing, an add it ional bit is sometimo. addod 10 a binary c ode word t o define il$ parily. A p arity bil is Ihe extra bit included 1 0 make Ihe tOlal n wuber o f I ', in Ihe re,ulling code word e ither even o r odd. Consider Ihe fo ll owing Iwo cha racters a nd Iheir e,'e n and odd parily: Wilh Even ParRy 'MOO' 1010100 With Odd P .~ ty 0100:0:11 II(((JOOI 11010100 0 1010100 In each case. we use Ihe e xira bit in the leftmost posilion o f Ihe code 1 0 p roduce an e ven number of 1's in tnc cnaraCler for e ,'en parily o r an o dd nu mber o f I 's in I he c haracter for o dd parilY. In general. o ne parily o r the o ther is a dopled. wilh even parily being more commOn. Parity may I x use<! wilh binary numbe ... as woll a . with code . . including ASCH for characler . . a nd Ihe parily bit may b e placed in any fixed posilion in Ihe code. 1 -5/c...,.Codu a 21 T hc p a nty b it i . h elpful io d etectiog CrrOrs du ri og Ihc l r Bnsmission o f i nform ation from o ne location to a nother. A ssuming that even parilY is u ..,d. t he .impl~!t ca~ iii h andled a . follow,: A n eve n ( or o dd) p arity bit i . g enerated a t the !Ie ndi" , e nd for a ll7bit A SCH charoclers; t hc 8 bil c haraclcrs t ha t include parity b ils a re t r an smitted to th eir deSl ination. T he p arity o f u ch character is I hen c hecked a l t he r eceiving e nd; if t he pa rity o f t he r eceived c haracter is n o l (vCn ( odd), il meanS , hat a l leasl o oe bil has c hange d illi v alue during t he ' ransm ission. m ethod d etects t hree . o r a ny odd n umber o f e rrors in e ach c harae tu t ran.mitted. A n u en n umber o f e rron is u ndetected. O ther errOt"detectioo oodoe5. SOme o f which a re based On a dditional p ar ity bots, m ay b e n eeded t o t lke n re o f a n u en n umbe r o f e rrors. W hat is d o ne afteT a n e rror i , d etec t ed d epends On t he p artirular applicat ioo. O ne possibility i . t o r equest r etransminion u f rhe message o n I he assumplio n t hat Ihe e rror Waf r andum a nd will n ol OCCur agai n. T hu . if th e r ecdver d etects a p arity e rror. it $ends back a NAK ( neg. rive a d "ow ledge) conlrol Charac ler r onsilling o f Ihc e ven p arity e ight bilS, 10010101. f rom Table 1-5 On p age 25. I f n o e rror is d etected. t he r eceiver send. b ac k an A C K ( acknowledge) c ont ro l c haracter. OClOOOIIO. 1 be !le nding e nd ... ill r espond 10 a N AK b y t ransmitt ing t he mc:ssale I pin. u ntilthc c orrec t parity is r eceived. Jf. a fter a n umber 01 a ttempt !'. t he Il1Insmis sion is s till Ln errOt". I n indio;at ;Oft o f a m alfunction in Ihe Iransmission plIth is gIVen. 1"" 1 -5 0""". G RAY C ODES A ~ w e r ou nl u p u r d own u ,ing b inary c odes,lhe numhcT o f b ill Ih al c hange from o ne bi nary value 10 I he n ul vaTies. 'l"il is illuS lra lcd by t he bi nary r ode f ur t he u clal digits Oft t he I dt in Thble 1-4. As ...e c ount f rom 0 00 u p t o I I I I nd ~ roll OVe T ~ 10 000. the n umbe r o f bils Ih.1 c hanlC b el . .cen the b inary " ah. es rBnges from I to 3 . O TABLE 1-4 G ....y Code ." - Binary '''00 " " ''" " '" '" , , , , , , , , Chang. . , - '" .,~ ." '''"" " '''00 "" .. Chi_ 22 0 C HArTER I ( DIGITAL C OMPUTERS A ND I NFORMIITION F or m any a pp lications. multi ple bit c hanges a s t he c ircuit c ount, is n ol a p rob lem . T here a re a pplications. h owever . in which a c hange o f m ore t han o ne bit wh en c o unt ing up o r d own c an cause s erious p roblems. O ne s uch p ro blem is illustrat ed by a n o plical s hafl a ngle e ncoder s hown in Figure 1-3(a). T he e ncoder is a d isk a llached 1 0 a r otati ng s haft for m easurement o f t he r otational p osition o f t he s hafl. T he d isk c ontains a reas t hat a re d ear f or b inary 1 a nd o paque l or b ia ary O. A a i llumination s ource is p laced o n o ne side o f th e disk . a nd o p tic al . ensors, o ne f or e ach o f th e bits t o b e e ncoded. a rc p laced on the o ther s ide o f t he disk. W hen a d ear r egion li es b etween t he source and a s ensor , t he . ensor r esponses t o t he lig ht w ith a b inary I o utput. W hen a n o pa que r egion l iu b etween t he s ource a nd t he s enwr. t he s e nsor r esponds t o t he d ark w ith a b inary O. T he r otating shaft. h owe,w . c an be in a ny a ngular posilion, F or e xam ple. suppose that t he shalt a nd disk are positioned s o t hat the s enso ... lie right at the boun dary b elween O J! ""<.I 100, I n this case. s enso ... in p ositions B,. BJ a nd Bo have t he light partially blocked . In such a si tuation , it is u ndear w hether t he t hree s enso ... will see light o r d a rk, As a c onsequence, each s ensor may p roduce e ither a l ora O. ThUs. Ihe r,,"ulling e ncoded binary n umber for a va lue between 3 a nd 4 may b e ( 0), 001. 010, OJ 1. 100, IOJ. 110. o r 111 . E ither O! I o r 100 will be s atisfaetory in this case. b ut t he o ther six vatu,," are clearl)' e r roneous ' T he s olution t o t hi s p roblem b ecomes a pparent by n oting t hat in t hose c ases in which only a single bit c hanges when going from o ne , 'alue 10 th e next o r p revious ,'alue. t hi' p roblem c allnot o ccur, For e xa mp le, i f the sensors lie o n t he b oundary be tween 2 a nd 3. t he r esulting co<le is e ither OIl} Or 0 11. e it her o f wh kh i , s atisfactory, I f we c ha nge t he e ncod ing o f t he v alues 0 t hrough 7 such t hat o nly o ne bit value c hanges a s we c ount up o r d own ( including r ollover f rom 7 t o 0 ). t hen t he e ncoding will be s atisfactory for all p ositions. A co<le h a"ing t he p roperty t hat o nly o ne bit at a t ime c hanges b etween c odes d uring c ounting is a a 'ay code, ' ln ere a rc m ultiple G ray c odes for a ny s ct o f n c onsecutive integc ... , wit h" c ,'en, o t 'l ClJHE 13 Optical Shalt Angle Eocooe r 1_6 I AJprumunloric 0 xI<. 0 23 A specific G ray e ode l or the octal digil . . c .lled a b i""ry reflected Gr"y code. a ppears o n t he right in Table )4, N ote t hat the counting o rder l or binary codes is now I))}, 001 . 011. 010. 110. 111. 101 . 100. and I))}. If we want binary c odes for processing. then Yo'e can build a digital circuit or use ""ftware thaI converts Ihese c odes 10 binary before t hey arc uscd in f urther processing o f the information. Figure 1-3(b) shows the oplical s haft angle e ncoder using the Gray c ode from Table i 4. N Ne Ihat any I wo segments o n the disk a djacent \ 0 e ach o ther h a"e only o ne region that is cl ea r for o ne a nd o paque for Ihe o ther. The Gray code is n amed for Frank G ray who patenled i t' use for shaft encoders in 1953. Th e oplical s haft e ncoder illustrates o ne use of the Gray code concept. T here a re m any o ther s imilar use, in which a physical variable. such as position o r .'oUage, has a c ontinuous r ange o f ,'alues t hat is c onvened t o a digital r epresentalion _ A q uile different use 01 G ray c ode, a ppea" in l ow.power C MOS ( Complementary Metal O xide Sem iconduCIOr) logic eircuits thaI c ount u p o r down. In CMOS, power is consumed only when a bit changes. For the example c odes given in Table 1-4 wilh continuous counting ( eilher up o r d own), t here arc 14 bit c hanges for binary counling for every eight bit changes for Gray code r ount ing. Th u. . Ihe p ower c onsumed a t the co unlcr oUlputs for t he G ray code c ounter is only 5 7% o f lhal consumed a t t he binary c ounter o utputs. A G ray c oJe for a counting sequence o f " binary c ode words ( n must be e ,'en) can be constructed by replacing e ach of lhe first rtI2 n umbers in the s equence wit h a c ode word consisling 01 0 followed by Ihc c "en parity for each bit o f Iho binary code word and the b it t o its left. For e xample. l or t he biM!)' c ode word 0100. Ihe Gray c ode word is O. parity(O.I}. parily(l.Oj, parity(O,O) = 0110. N nt. take the sequen~e o f n umbers formed and COP)' it in r e"C" e o rder wilh Ihe leftmosl 0 r eplaced by a I. T hi' new seqoe nce provide<> Ihe G ray code words for the second 1112 o f the o riginal" c ode word& For e~amp l e. for BCD codes. Ihe first fiv e Gray code words are OOOO.I))} I. 0011. 0010, and OliO. Reversing l he o rder o f t hese coJ"", and replacing Ihe leftmosl 0 with a I. we o blain I 110. 1010. l Oll. 1001, a nd 11))} for the lasl fi"e G ray code",For Ihe speci"1 cases in which t he o riginal bi na ry c odes a re 0 Ihrough 2" - 1. e ach G ray c oJe word may be formed d irectly from the oor~spondlng binary c ode word by copying ils leftmost bil and Ihen replacing each 01 the rem aining bils wilh t he e vtn parity or Ihe bil 01 the n umber and the bit 10 il s lefl. 1- 6 A LPHANUMERIC C ODES Many applications of digital c omputers r equire Ihe handling o f d ata consisling n ol only o f numbe . .. bUI a lso o f leners. For instance. an insurance company wilh t housands o f policyholders uses a c omputer 10 process i ts files. To r epresent the names and o t h er p ertinent informatio n, it is n CCCSS3!)' to formulaIC a binary code l or the le ners o f the a lphabel . In addition. Ihe s ame bina!)' code musl represenl n umeral. and special c har.cters such as S. Any alphanumeric c haracter..:t l or English is a s el o f c lemenls Ihat includes Ih e 10 decimal digil s, the 26 l eners o f t he a lphabet, and s everal ( more than Ihre e) ' pecia l charactcrs. If only c apilal l eners a re 24 0 C HAPTER I I D IGITAL C OMPUTEI<.S A ND l NFORMATION included, we need a binary c ode o f a t le.1St s i:< bils. a nd i f both uppercase letters a nd lowercase letters are included. we need a binary code o f at leaS! beVen bit s. Binary codes play an important role in d igital computers. T he codes musl be in binMY because c ompulers can handle o n ly I's and 0'1. Note that binary encoding merely changes Ihe symbol., not I he meaning o f the elements 01 informalion being encoded . ASCII C haracter Code T he s Wnd;l, d binary c ode f or Ihe a lphanumeric c haracte . . is called ASCH ( American Slandard C odc for tnformation loterchange). I t uses seven bits 1 0 code 128 characters. as shown in Table 15. T he s even bits of the c ode " ' C desig. nated by 8 1 Ihrough 8 ,. with H? being Ihe moot significant bit. NOle Ihal Ihe m oSt significant I hree bits o f Ihe c ode d et er mine t he c o lumn of the table a nd Ihe lellSt s ignificanl four b il' the row of t h e table. The le{{er A . for example. is r epresented in A SCII as 1000001 ( column 100. row 0001). The ASCII c ode c on t .ins 94 c haracters th ai c an b e prinl ed and 34 nonprinting c haracters used for various control functi,,"s ' me pr in ting c haracters consisl o f Ihe 26 uppercase lette rs.. the 26 lowercase le{{er s.. the 10 numerals. a nd 32 special p rintable e h",aC lers such a s %.@> and$. T he 34 control characlers a re d esignaled in the ASCI I table with .,bbrevialed n ames They a rc listed a g.in b elow the table with their full functional names T he conlrol characters are used for routing d ala and arranging t he p rinted !e~t into a prescribed for","t. There a rc lhree types of control characters: formal effecto rs, information separators, a nd Conllllunication r o nlrol characters. Format effeclors a re c haratters t hat con!rol the layout o f printing. They include t he fam ili . . type _ writer controls such as backspace (!lS). horizontal tabulation ( H T), a nd carriage r el urn ( CR). Information separators are used 1 0 s eparate the d ata inlO <li"is;on sfor e xample. p ar.grap hs an,1 pages. They include characlers such as record " " para_ l or (RS) a nd file s eparator (FS). T he c ommunicalion conlrol c haracters are u. .d d uring Ihe transmiS$ion of t e.l from One IOCJOtion to the o t her. Examples o f com_ munication control characlers arc STX (slart of l ext) . nd ETX (end of lexl) , which are used to frame a lext message transmiHed via c ommunicalion w ires ASCII is a 7-bit code, but mosl compulers manipulate an S-bil q uan!ily as a single unit ca ll ed a byte. Therefore>ASCII characters mosl often are stored o ne p er byte. wilh the mosl significant bit ""I to O. T he extra bit is somelimes used for specific purpn<es. d epending On the application . For e xample, s ome p rinlers reoogniJ.e a n a ddilionall28 8-bil characters. with Ihe most significant bit set to I . These ch arRCUrs e nable the printer to produce a dd itional symbols. such as Ihose from the G ree k alphabel or characters with accent marks as used in languages o lher Ihan English. ~ , UNIC(lOE This supplement o n Unicode, a 16.bit slandard code for , epresent;ng the s ymbol' and ideographs for the world's language s. is available on t he Companion Websi1e (htlp~lwww.pren h all.com/mano) for Ihe le xt. t_7 I Ch.>", . . Soonnoory 2S 0 0 T ABLE 1_ S A merkKn S ta ndard C ode f or I nformKtion I n. eKhonge ( ASCII) - B,B, B,B. s,.B.B , 00' N UL L DC> m 0000 OC, 00 roN "on ''' 00'" o ",00 ' 00 = = DO< 0101 011 0 "0 '" . 0, . ee om ,~ SYN ~ CAN " NT ' 00' 1010 un '," " " " 'D ~ 1011 " 00 11 0 1 1110 1111 ' 00 e ", " "' " CCHIIsoi C ,,**, '*rI: N UL L roN on ET X ' 00 "0 ' C< 'R 'n ,rr " ~ " " " e, ro 1-' ,n '" , , ", , ,, , U ) [ < w m M > N 0 = DO< 'IT. " SYN CAN '''" " SC e, " " "' "'" w O C, Dd relum T ' ," , , N D LE Ca rri. ~ C V Stan o f " ".ding S .an o ltex. E nd o f'e" E nd o f t r.m.m i>sion E nq"iry A d_ le dge Oell Oack,pa<o H o,i.on l t ab U ne feed Venical 'at> Shih o ut Shih in '" ' " 0 ,, ,,, " , D , ,, , e, w ,,,, , , ;, , , , " ,, N ULL Fo<mf~ '00 O EL 0 O EL D .,a link . ...." " DcvK:<: c ontrol 1 D"'-K:<: con.roI. 2 DeVK:<: con.roI. J Device con.roI. 4 i" ep 'ive ""kDOW!ed!< SynchroooLl$ idle E nd o f " ansm' ,, "'" block Canoel E nd o f medium S U",""'"'e """~ File . ., po'''''' Oroup . .,.,. , . .' " K Ofd " ' pon, O! U nil s epo,","" 1).,... C HAPT ER S UMMARY In Ihis c hapter_we h.~e i nlroduced digilal ' ySlem, a nd digilal computer.; a nd h .'-e s hQ""I1 w hy ~ ""h s )'Slems u '" s ignals h aving o nly IWQ values. We h .,'e brieHy i nl,Q _ d uced comr>u,.r Slruclure wi,h a block d iagram a n d discussion Qf ' he n a'ur e of Ihe 26 0 C HAPTER I I D IGITA L CO M P1JfE~ A N D I NFORMATION b loch N umber system concepl s. i nduding base (radix) a nd radix [>Oint. w ere pre sent ed. Bc~a u se o f t heir corres[>Ondence to two-valued sig nals. bina ry numben; were discussed in detail , Octal (base 8 ) ond hcxadecimol ( base 16) were also e mphasized, s ince they a re useful a s short nand notation for binilTy. Ari\hmclic o per.tion$ in b "",. o ther t ha n base 10 a nd t he conversion o f numbers from o ne base 10 a nother were c overed , Becausc of the predo minance " f deci ma l in normal use. B in ar y Coded Decim.1 ( BCD) was t reated. T he parity bit was presented as a t echnique for e rror d e tection. a nd t be G ray c ode. whieh is c r itical to selected a p pli_ cations. was d ~fmed. Finally. t ~ e rcpR'SC n1 ation o f information in Ihe form o f c har_ acters in stead o f nu mbers by mCanS of t he ASCI I code for t he E nglish alphabet waS pTese nt ed , In subseque nt o hal'tcr" we will t reat the representation of signed numbers ,Ill" fi o"ting-jXlim numbers. We will also int roduce additional codes for t he d~cim~ 1 digits. A ltho ugh these topics fit we ll with the topics in t his c hapter. Ihey a re difficult to moti,'ate without as.ociati ng t hem wit h lhe h~,, ' w",e u sed to impleme nt the o pemtion, they d eno te. ThUs. we d elay t heir presentation u ntil we exam ine lhe " ,sociated h ardware. R EFERE N CES I. G RAY. F. P "lse Code Com",,,,,iUltio,, U S . Pale J1 t 2 632 (l5~. Mareh 17.1953. 2. M""o. M . M C amp." Ellgineering: l io"I"'ore D~'igll, E nglewood Oiffs. NJ : P rentice Hall. 19M. 3. M ANO. M . M. Digital Design . 3rd ed. E nglewood Cliffs. NJ : P rentice Hall . 4. S. 6. 7. 8. '"" M, M . C omp",er S ptm, A rch iteel",e. 3rd cd, Englewood C liffs. N J: Prentice Ha ll . 1993 , PA nEIlSON . D . A .. A "I) He""F.>Sv.). L. CO"'I',uer Orgoni: ario" " ",/ D c,ig": The H,m/"'nre/So/t ....nre Imerlace. 2 nd c d San Mateo. C A: M orga n Kaufman n. 1';98. T ""'-F.NRAUM. A . S. S trllCl",ed C O"'I,,,,a O'Koniza,ioti. 4th e d . U pper S addle Ri"cr, NJ, Prenlice ~ I all. 1 m. W llllll. R. Ho'" Comp"'N~ W ",k. Emeryville. C A : ZiffD.wis Press. 1993. W lll J ".~S. M , R.II l Iistory oICO"'pW;"K 7h:liII"/ogy. Englewood Cliffs. NJ : Prentice -H all,I985 , M ANO. P ROBLEM S , a ~ T he p lu'. ( +) indic.1tcs a mOre a dvanced p roblem a nd t he asterisk ( *) i ndicates" solu1ion" ava .lable o n t be Comp" ~ ion Website fOT the tex t. I - I. ' Lisl the binary. octal. a nd hexadecim al n ~ mhers fTOm 16 t o 31. 1 -2. W hat is t he exact nu mber o f bits in a memory Ihat contains ( b) 3S4M bits: (c) 8 G bits? (~) 4$K bit,; 1 -3. What is t he decimal equi,'al~ nt o f t hc o htai ned with (~) 12 hilli and ( h) 24 h its? l arg~s t I....to Convert t he following hinary n umbers t o decimal : 1001101. 100ooiLlO l. a nd 10101 11 0.1001. binary integer that can be 1_5. C o nvert l Iw fo ll "wing decimal numh<:r. to h i""ry: 125. 6 \0. 200 3. a nd 18914 , 1-6 . Each o f the following (,vc n umbers has a different hase: (111 00111);,. (22120),. (3113),. (4 110k a nd (.343)". Which o f Ihc fi"e num bers have Ihc same value in decimal? 1 -7. Convcrt Ih c following numbers from the given base 10 Ihe o ther t hree bases li st ed in Ihc table: ~., Decimal H e._I.....1 , , , 369.3125 , , , 101 11 101.\0' , , 3 ,26.5 , , , F 3C7.A 1-8. COIIven the fol lo wing decimal n umbers 10 the indicaled b ase, using Ihe mel h od, o f Examples 1 3 on p age 16 and 1-6 On p age 17: I ") 7562 .4 5 10 OClal ( h) 1 9J8.25Jlo h uadecimal I e) 1 1517510 binary. 1_9. Perform the fol lo"iog oon.'ersion by using bas<: 2 in ste ad o f base 10 as . he intermediate hase for Ih c conversion : ( _) (673.6). ' " hexadecimal ( h) ( E1C8),.lo tXla l ( e) (310.2). ' " 00:1"1 1 -10. Perform Ihe following binary multiplicati on .: 1_) 1101 X 1001 I h ) 0101 X 101 1 (e) 100101 x 0 110110 I -II . +Divi.ion is c omposed o f multiplieations a o d s ubtractions. Perform the binary divi~inn 1011110 + 10 1 1 0 o blain a q uotient a nd remaimlcr. 1-12. T here is considerable e v id ence t o suggest that b ase 20 has historically b een used for number Sj'$lems in a n umber o f c ulture s. C l Wrile Ihe digils for a b ase20 <)'Stcnl. using a n extension o f tlle sam~ digit a represeolalion seheme e mp loyed for h eudccimal. ( b) C onvert ( 2003)," 10 b ase 20. (~) C om'erl (BCH.G)zo to decimal, 1- 13. In e ach o f Ihe following case . . d elermine the r a di~ ( a) ( BEE) , - (2699) ,. (h) (365), - (1<14),. r; 1 -14. T he follo""ing c alcnlation was performed by a p articular breed o f unusually in ldligent c hi cken , I f Ihe r adix, u sed h y the ehi~kcn corrCSfJO ndS 10 ils l o. ai n umber of toes. ho'" ",any loes docs . he chicken have on e ach fOO l? 3n+ (24),) x (21), ~ (1501), I -I So * Rcp rese nt Ihe decim al n umbers 69-1 a nd 835 in B CD. and theo ' how Ihc sleps necessary 10 f ono Iheir Sum. 28 0 CHAYT~ I I D IGITAL C OMPllTERS A N D I NFORMATION 1- 16. . P'md lhe binary reprelol:nlatioos for each o f the follo"-in& B CD numbers: t_ j 0100 1000 0110 0111 ( bl 00 11 0111 1000.0111 0101 1_17. List t be j b il binary n um ber e quivalent' for 16 lhrough 31 ""jth a parily bil a dded in t he r i"' tmosl position giving o dd p arity t o I he overall 6-blt n umben. Repeal fo r e~n panty, 1_ 18. B y using Ihe procedure g h'cn in ~c l io n 15. fi nd Ihe Gray c ode f or Ihe hexade<:imal digits. 1- 19. .. W hat is the p e"'cntagc o f power c o nsumed for c o ntinuous CO llnting ( either up o r d own b ut n Ot OO lh) at the output. o f a binary G ray r od e c ounter compared 10 a binary cou nter ", a function o f Ihe numt>cr o f b its, f l. in the two counters? a n A SC II code must be complemented t o c hang. the A SCll le uN repre$<l:nted from uppe~ t o " ""'en:'''''' and vi! v...... ? 1_20. What bit po6ili<>n in 1- 21 . Write your full name I n ASCI1. " ,ing a n S-bil c ode t_) . . ith lhe I dt mQ(;t hit a h."ys 0 a nd ( b l wilh the leftmosl bil selected t o p roduce even panty. Include a .pacc bet . ., "n no~ and a p eriod a fter t h" middle in it ial. I-n . Decode t he follo . .';n, ASCI1 c ode : 1001010 1101 11 1 1101000 1101110 01()UX) 1000 100 1101111 1100101, 1_23. ' Show the bit configuration t hat r.prc&<!nlS the decimal number 36S in ( a) binary. ( b) BCD. t~) A SCI I, 1_24 . A c omputer represents informAtion in g roup" o f 32 bit" H ow !tI A dif fe re nt ny integers can be represente,1 in , a ) bina.y, ( b) B CD, a nd " 'iog 32 bilS? (~ ) lI bi. A SC II , all C OMBINATIONAL L OGIC C IRCUITS n IhOs c hapte r, . ... w ;ll l earn a bout galeS, t he m ost primm"" logic e lem"" IS L>S<Id in <ligna! systems. In addlllOn, we "';11 l earn the m atMma tOcall&Chriques u sed In <!e!;jgning dA:UilS from _ g al(l$ and learn h ow to cI9sign C (l6t-ef\eclive cifCUils. These techniques, which ..... h ndamen\a l to ! he cIesign ( II almost . 1 digital c irw'ts, a re b aMd o n Booi&an aIge!><a. O ne D specI 01 d esign ia to avoid un~ry cirwilry a nd " "cess cost, 8. g oal aocomplisl>ed b y a techniqLJe c ahd opIimi1:atJOn . Kama."!)'I maps provide a ~aphic&1 meltJod 10< enhar(:ing undel'$tanding ( It optimization and $OIving $rtIaI1 o m ization problems lor "two-leYor logic circuits. More g enera l optimi2a1ion r nelhods\or e ilWits with m ont m an t wo - . . a re introdu<:ed. T ypes 01 l ogic g atos d>aractoristic ot COI11&fT1l(lra'Y i ntegrnted cifcuiI impIemoolation am dlSCHSSe(!, ExcIusiYu OR a nd ExcluSive t KlfI9"tes a re i n1foduced, along with I a ssociated a lgebraic techniQ ........ I n t erms 01 too <liagrnm a t the t><>gioo<ng o f C hap!a, t . " """"1'\5 trom this " ""'pie< a pply to m ost o j t he g ene<ic c ompy tar. Exceptions a re c ircuits t hat ara large/\l """"O<Y. Sucfl as c a"'- and RAM, 8000 analog ekK:t rooic c irouits in t oo moni1or a nd h ard <IisI< controIIef. N evenheI8ss, with its use t hroughout the design o f m os! 01 the c omput&r, 'oO'hal . ... slll<!)t in ! his c haplet I s l undamental t o a n iI>-<Iep!h " """rstanding 01 COII'IJlUIers a nd digital s)'Stems and h ow t hey are 0 0sigrIed. 2 -1 BINARY L oGIC A ND G ATES Digital ci",uilS a rc hardware c omponents t hat m anipulate binary infonnatioD. T he circuit. a re i mplemented using {raos;.toTll a nd i meroonneaion. in complex semiconductor devices called im~gra/ed cire"i/.<. E ach basic circuit i . r~ferred to a$ a l ogic 81~. For . implicity in d e,ign, we m odd th e transistor_ based electronic o" 30 0 C HAPTER 2 f C OMB I NATIONAL L OGIC C IRCUITS d rcuils as logic gote>. Titus. the designer need not b e c oncerned with Ihe i nlema l e lectronics 01 the individ ual gates. b ul on ly with tl1 cir ex1emal logic properties. Each gate p erform. a specific logical operation . The o ut puts o f g atcs aTe ap pl ied to the inputs 01 o ther gales 10 fO Tm a digital circuil. In o rder 10 describe Ihe o peralional p roperlies o f d igitat circuits. il i . necessary t o i nlrod uce a mathcmatic~t n otation that specifies t he operation o f e ach gate a nd t hat can b e used t o analyze and design circ uil>- T hi s binary logic ' Y' tem is one o f. class o f m~t h cmat ; cal systems referred to ge nerally as fjQo/ean a/g.br~._ T he n ame is in h onor o f the Englhh mathemat ic;"n G eorge Boole. who in 1854 puh. lished " book introducing the m athematiea l thcory o f logic. T he "p,."citic Boolean a lgebra we wi ll <Iudy is uscJ 10 describe the in lcrconnection of d igital g ate. a nd to design log i ~ circuit. thIOugh the manipu lalion o f 1:h",tean cxprcssio TI s. We first i ntroduee t he c oncepi o f bina ry logic a nJ s how its relationship t o digita l gates a nJ binary signals. We t hen present Ihe propcrti~""j o f the Bootean algebra. together wilh Olher concepts ,md methods useful in designing logic circuits. Binary L ogic Bin ary togic deats wilh b inary variables. which take on two discrele ,".tue .. and wi th the o perations o f mathem.tica l togic app li ed t o these variables. T he two values the variabtes take may be called by different names, as me ll tioned in Sc<:tio n 1 1. b ut for o ur purpose. it i . C(H\ vcnic TIt 10 Ih ink in terms o f binary " a lues and assign I o r 0 to e ach variable. In the first p art o f this boo k. v ariable. a re des ig nated by tellers o f the alp habet, , uch as A . H. C. X . Y. and Z. Later this notation will be expanJed 10 include . tri TI g. o f leners, numbers, and speciat charaelers. Assoo:ia!eJ with the binary variables a re three Im sie tog icat o peralion. ca ll ed AND. O R. and N OT 1. A N D. This operation is rcprcsenlC<J by a d ot o r by the ab5ence o f an operatOT . For " ,am ple. Z . . X - Y o r Z . . X Y is r ead " Z b equal t o X A N!) Y "The logical o peration A ND i . i nt"preled 10 m ean that Z . . 1 if and only if X . . I a nd Y . . 1; otherwise Z . . O. ( R emember t hat X, Y. n J Z a rc binary ,'ari abIes a nJ can be equal 10 o n ly 1 Or 0.) 2. O R. This operalion is r epresenled by a ptus symbol. For e xample. Z . . X ... Y i . r cad " Z is equal 10 X OR V: mea ni ng t hat Z . . I if X . . I o r if Y _ 1,0r if b oth X " 1 and Y - l. Z . . 0 i fanJ on tyif X . . 0 and y . . O. 3. N OT 1 hi, o perat ion is represented by a bar o ,'er Ihe v .riab te. For example, Z oo X is rcad " Z is eqoat 10 N OT X.~ m eaning t hat Z is what X i . no!. In o lher words. if X " I . t hen Z . . 0; bUI i f X . . O. then Z . . 1, T he N OT operation i . a lso r dcrred 10 as the CQmpl~",e", o peration. since it c h.nges a I 1 00 a nJaOtol. B inary logic resemblcs binary a rithmet ic. a nJ the o pera lions A ND and O R h","e simi larities to mu ltiplication a nd a dJilion. respecti"ely. This is why the symbols used for A ND a nJ O R a re the same as t hose "sed for mut(iptkatio n a nJ addition. H owever. bi nary logic . houlJ n OI b e c onfused with binary arithmetic. O ne s hould realize thai a TI a rithmetic variable designates a number Ihal may consisl of 2- 1 I IIinory LoP< ...d G ot.. 0 J1 many digils, ",hereas a logic variable i . a l",a}'. e ilh er a I o r a 0 , T he follo"'ing e q u alions defi ne t he logica l O R o pera tion, 0 -1-0 - 0 0 +1 - 1 1 +0_1 1+ I - 1 These rese mb le binary " ddilion. "oCC pl for rhe lasl o pera tion. In binary logic. we il a"e I -+- I _ 1 ( read " one O R o ne is e<juallo o ne"). b UI in binary a rilhm clk. we have 1 -+- I - 10 ( read " one plu~ one;~ e qua l 10 IWO"). To a,-oid ambiguity. rhe ~ymbol " i~ w melim", ust:d for Ihe O R o pera l ion i nstead o f Ihe + symbol. B ut a . long as arilhmelic a n d logic operOlioTls are nOi mix ed. each can use Ihe + s ymbol wilh ilS O"'n independent meaning. The nexi equa li on. define Ihe logical A ND o peralion: 0 -0 _ 0 o I - 0 1 -0 - 0 ' ''is ope ral ion i~ idenlic all O bina ry m ultiplicalion. provided thai we use only a sin. gle bi\. A lterna live symbols 10 1M . for A ND and + for O R. a re s)'m OOI,; " a nd". respeolivel y. Ih al represent conju ncli,'c and di~juncli,'e o pe rations in proposil,onal calcul us. ,'Or e ac h combination of lhe values o f binary v ariabk. s uch as X and Y. l here is a value o f Z ~fI<'cified by I he definilion of Ihe logical o pera lion. The d e tin i lion. may be l i.ted in c ompa cl form in a t ruth l able. A I nllh lobl~ for ~n o per"l;on is a l able o f o ombinations o f the binary variables Jho",ing t he r elalionship I>c lween Ihe values I hall he variables lake o n and Ihe v"lucs o f lh e resuit o f Ih e o pera lion. T he t ruth l ables for the operations AND. O R. a nd N OT a re sho wn in Table 2-1. T he . abies li sl all p(:.ssible oombinalions of value~ for two liariabl"'land the resulls o f t he o peralio n, They clearly de m on~trale t he d elinition o f Ihe thr ee o pera li ons- o T ABLE 2-- 1 T nnh T _ t>t"" ror I be TIoI'H Bll>it l.<>ginol O """'li. .... , ' "' Z_ , "" , "" , x y '" , "" " "" Z_ x. y '" "" ,, ~ J2 0 C II"l'TIlll/ C OMBINATlON"L L OGIC C IRCUITS ... Logic s a le$ are cle.::tronic circuits thnt operate 0 0 One o r mOre in pu t sig"nls to produce an outpu t s igoal. El ectr ica l j;g"nl. such as voltages o r cu rrents exist through out B di gi ta l ~yste m in e ilher o f IWO recogni~ab l e value .. VoUage-opcraied circu its r npood to t wo , ., paralc voltage Tloges t hat I'f:pr"",nl II binary v lriable equal to logic I o r logic O. n illUSlrllled in f igure I -I. The input termlllais o r logic galO$ a cttpt binary s ignak within the a llowabk r ange and r espond I t the o utput t enn inak . ."ith binary lignals lbal fall " '"lIhin. specified range. n.e i ntermediate I'f:gions bct-...n t he allowed ... "8"1 in t he figure are ~ d only d uring c ba nges from 1 10 o o r f TQlt1 0 to I. Th "'" changes are called 'rtI/U;IWIu. and the ;ntermediate rcgiQn$ a re called the I Tami,ioll T~g;O/U. l lte g rap hi C! sym bols uS" d to designate t he three tyl""i o f gat Los - A ND . O R . a nd N OT_ are s hown in Fi gure 2- I( a). TI,e gates are e lectronic ci rcuits that produce the e qu ivalent. of logic-) and logic-O o utput sig"al $ in accordallce with t heir resllCC live truth tables if the e q uivalent. o f Iogic-I and Iogic -O i nput signals arc applied. T he two inpU I signa]s X a nd Y t o lhe A ND a nd Oil. gatO$ take o n o ne o f four possible rombi .... tions:OO. 01. 10. o r 11. 1 besc input s ignak are iohown as timing d iaga.m in Fig"l'f: 2 -I(b). t ogether with ,he limi ng diagrams for the rom::_ ,ponding o u tput s ignal for ea.c: h Iype o f p ie. n.e horizont al axis o f a tinrUlg d wg,am f cpres.en" (ime. a nd the " crt"'al u is sl>o " ""$ a sicnal as it changes belwe<:n the two possible voltage levels. " "e low level . epresents logic 0 and t he hi gh level rcpreS"nL& logic I. The A ND ga te responds wi ' h a logic- l o u tput sigoa l when b olh input sign als a rc logic ] l "e Oil. ga te reSIIO "ds with a logic.] outl) "t signal if either ~=O-Z - X.Y : : ::::[)-- z - X 0 __ + Y . --{>o-- z-x NOT"".,... in . ..... " 1'0'0_ (0) 0 "\>1>"'''-''' x l 0 o I t l l~-"'--;=' ==-N = ' _'~ x+yW l J of ("1'0'0) X y ( OR) ( NOT) X o 1 F1GUKt: l _l Di B,t.] L op: Ga< . . z_z l:=[)---- p - "IIC (O )Th'-""'P'" " N[) ~'O 'p.: , II " f I _on A 1gdn 0 33 O _ A+B+C+D+E+P . ( b)S . . ;"pu'OR~'o o n G UII.E2 -2 G ., . . wilh More Ih.n Tw<> InpulS input signal is logic I . T he N OT gale is more c ommonly referred 10 as a n Inverrer. T he reaSOn for litis name is app3rem from the response in I he liming diagram. The OUlpUllogic s ignal;s a n inverted ,'ersion o f i nputlogk signal X A N D a nd Oil. gales may bave more Iban Iwo input s. A n A N D g ale wi lh Ihree i npul, and an O R gale wilh , i . i nput. aTe , hown in Figure 2-2, The IhTeeinput A N D gale respond, wilh a logic-J OUlput if a lllbree inputs are logic I. T he o utput is logic 0 if any i npul is logic 0 The si~-input O R g~te responds witb a log ic I if a ny input is logic 1: its OUlput becomes a logic 0 only w hen all in puts are logic O. 2 -2 B OOLEAN A LGEBRA T he B oolun a lgebra we presenl is an a lgebra dealing witb b inary v ariables a nd logic opeTations. T he variable$ are d esignated by IeUe", o f the a lphabet. a nd the t hree b asic logic o perations a re A N D. O R. and N OT ( complementation ). A Booleall a p,usloll is a n alge braic expression form ed by using b inary v ariable., t he c onstants 0 and I . t he logic o pera tion symbol., and p arentheses. A Boolean function c an b e d escribed by a B oo lean eq ual ion c onsisting o f a binar)' v ariable identifying the fu nction followed by a n e qua l sign a nd a R oolean expression. O pt ionally. t he function i demifier is fo ll owed by parentheses e ndos in g a list o f the funNion variables " 'para ted by commaS- A , i"gie-ompI" 8QOlean [u"ction is a m apping from e ach o f t he possible c ombinalions o f values 0 a nd I o n the function v ariables 10 value 0 o r L A n",itipl~-o"tput 8QOI~Qn [Ullction is a mapping from e ach o f t he possible c om bi nations o f values 0 a nd 1 o n the function vari able< t o c omb ia alions o f 0 a nd I o n tbe funclion OutPUIS. C onsider a n e xample Boolean eq uation represcnling funClion F F {X.Y.Zj - X-tYZ T he two parIS o f Ihe '" pression. X and Y Z, a re c alll termS o f the expression f or F T he function F is e q ual t o 1 i f term X is equal 10 1 o r if Y Z t enn is equal to 1 (i.e" both Y a nd Z a re e9ual to I ) . O therw ise, F is equal 10 O. T he c omplement o pera. t;on dictates that if Y ~ 1. t hen Y must e q u al O. T herefore, we can say t hat F I if X _ I. o r if Y _ 0 a nd Z _ L A Boolea" e quation e xpresses l he logical relalion sbip between binary variables. I t is evaluated by d etermining Ihe b inary " alue o f the " "pression for all possible c ombinalions o f values for I he variables. A l.looIean fuoction can be r epresenled by a t ruth table. A t mth tQI>I~ for a functiot> is a list o f all combinations o f I 's a nd O's that can be assigned to the binary variables and a list tbat .Ilovo. . Ihe va lu e o f Ihe tur><:tion for each binary combinalion. E 34 0 C HA I'rnR 2 I C OMBINATIO N AL L OGIC C IRCUITS ~ Trolh T.blo ABLE 22 T f .... , h ""0<1;00 F _ X ,, + yz """ "" , "," " "" " , " " , T he trulh lab les for the logic operation. given in Table 2- 1 a re special cases o f t ruth lables for fu nCl ions. T he number o f TOW< in a Irulh lable is 2". w here" i . Ihe numbe r o f ' .riab les in the fun Cl ion . The binary combina lions for Ihe l rulh lable are Ih e n bil bi nary numbers Ihal correspond t o counling in de<; imal from 0 Ihrough 2" - I. T abk 22 , hows Ihe truth lable for the funcl ion F - X + yz. T here a rc eigh l possi_ ble binar)' combinat io ns Ih~t ass ign bits to the Ihree variables X. Y. and Z. T he column labeled F contains e il her 0 o r I for each of Ihese C<)mbin~l i ons. The t~ble , how" Ihal the funCl ion is ~qu"1 t o 1 if X = I and if Y - 0 and Z - I . Olherwise. Ihc funclion is equal to O. A n ~Igcbraic expression for a Boolean f unclion can b e I ransfonned inlo a c ir cu it d iagram composed o f logic gales Ihat implement, the function . The logic c irc ui t d iagram for fu nclion F is shown in f igure 2-3. A n i nverter o n input Y g enerat es Ihe com"'plemenl. Y . A n A ND gate o perales on Y and Z .and an O R g ale combin es X and Y Z. In logic circu it d iagrams. Ihe variables o f Ihe function F are l aken as Ihe in puts o f the circuit. and the binary , 'ariable F is laken as Ihe out pul o f the circuit. ff t he cireuil has a single OUlput . F i, a single output funct ioo. If the circuil has mu lt iple oUlputs. function F is a multiple oUlput fu n Clion wit h mu lt iple e quations r equired 1 0 r epresent its o u t put<- Circ uil gales a re inlercooneclcd by ,,'ire~ Ihal c arry log,ic ' igno l<- Logic circuits o f this Iype a rc called c ombinational logic circuits. since t he variables are "combined" by the logical o peration s. This i , in cont rast to Ihc sequential logic 1 0 he treaTed in C hapler 6 . in wh ich variables are stored o ver time as well as b e ing combined . o n CURE1_J Logic C ircuit Diagram lor F = X + YZ l-Z I BooI . ... Alj<rl>n 0 3S T here is o nly o ne way l hal a B oolean function Can be r epresented in a t ruth lable. However. when t he function is in a lgebraic e qua ti on form. it c an b e e xpressed in a v ariety o f wa}'s. The particular e xpression u..,d t o r epre"..nt the funclion dictatcs t he in lCrCOnneelioo o f g ale. in t he logic c ireuil diagr am . By m anipulating a Boolean e xpressioo according t o B oolean a lgebraic rules. it is o ften JIOSSible t o o blain a simpler e xpression for the . . me funclion. T hi. s impler u p'"". sion rcd...:es b oth t he n umber o f gale'S in t he circuil a n d Ille numbers o f in pu ts t o t he gales. T o see how this is d one. it is necessary first t o s tudy Ihe basic r ule. o f Boo lean algebra. B asic Identities o f B oolean A lgebra l ab]e 2-3 lists Ihe most b a.ic i denlities o f B ookan algebra. T he flOlation i . s imp lified bJI o mitting the s}'mbol for A ND " "henever d oing $ 0 d oe. nOI lead 10 " "nfu sio,'- The first ~ine i(lcntilies show t he r elationship between a single '-ariable X . its c omple ment X , a nd t he binary " "nstanl> 0 a nd 1. T he nexl five i denlil ies. 10 t hrough 14, have c ounterparts in o rd inary a lgcbra _T he I a" thr~ e. 15 t hrough 17, d o n ol apply in o rdinary a lgebr . b ut ar~ u. . ful in m anipulating Boolean expression~ The basic r ule. listed in t he table have bccn a rrange d inlO 1"" 0 " "Iumn. I hal d emonstrate t he p roperly o f d uality o f B oolean algebra. l l>e d ual o f a n a lgebraic u pr"",io" i . o btained by int~rchanging O R a nd A ND O ptration. a nd replacing I 's bJI O's a nd 0'$ by I~ An e qualion in o ne column o f l he table can be o b lained from l he c orre.pon ding e quation in t he o ther c olumn bJI t aking t he d u al o f tM: e xp"""_ s ion' o n b olh si des o f t he e quals sign . F or e xample, relation 2 is the dual o f r dation I beC.1USC t he O R has been r eplaced by an A N D a nd t he 0 by 1. It is i mportant to n ote that most o f t he l ime the d ual o f an e xpression i. not equal to Ihe original e~p 'cl$ion. SO Ibat a n e~prel$ion usually c annot be r eplaced b y its d ua l. T he n ine i dentities i n"olving a single v ariable c an b e e a.;ly verif,ed b)' s ub s tiluting each o f the 1"-0 possible values for X. F or e .ample. to s how t hat X + 0 . . X . let X . . 0 t o o btain 0 + 0 . . 0 , a nd t hen let X . . I t o o btain I + 0 . . 1. Both o T ARLEl J 8 ",,,, Idenl;,i . . o r 8 00 lu n AI1l"bno , , , , " .. " ". X +O _ x X+I _ I X +X _ X X +X _ 1 , , , , x- I _ X X O _ 0 X -X _ X x -x _0 x-x X+Y _ "X X +( Y+Z) - (X+Yl+Z X ( Y+2 )- XY+XZ X + Y _ X_Y " " ". " x y _ YX Commutative X (YZ) _ ( XYlZ X + YZ _ (X+Y)(X+Z) A"""" i"" Di",;OOli,.. X ' Y _ X IY DeMorg. n'. 36 0 CHAI'TER. 2 I COMBINAT IONAL L oGIC C IRCUITS e quation, ar~ true according t o the defin it ion o f th~ O R logic operation. A ny e xpression can b e s ubstituted for t he v ariable X in all the B oolean ~quatjons lis ted in t he table. ThUs, by ident ity 3 and with X . . A B + C. w e o bla in A B+C +l _ ] N ote lh"t idc"(ity 9 s tates t hat double c ompbUl'ntation restore, tbe variable t o i ts original value. Thus. if X _ O. t hen X m I and X .. 0 . . X . Iden(iti"" 10 and 11. the commutati,c laws, s(ate (h "t t he o rder in which the variables a re " 'rine" will n ot ~ffect the result when using the O R and A ND o pera tions Identilie, 12 a nd 13, t he aW)Ciativc laws, . t"te that the resu lt o f applying a n o peration over three vari"bleo i , independent of t he o r der t hat i , l a ken. and t herefo re. the p ",e ntheses can be r emoved altogether a . foUows, X +( Y +Z) " ( X+Y)+Z - X+Y+Z X (YZ) . . ( XY)Z" X YZ These two laws " nd t he first distributive law, ide ntity 14, a re we ll known from o rdi_ nary algebra, SO t hey should not impose any difficulty. T he second di$tributive law, given by i dentity 15, is the dual o f the o rd in ary distributive law a nd d oe. n ot hold in ordinary algebra. A s illustrated previously. each variable in a n idemity can be r eplaced by a B oolean expression, and the iden tity slill holds, Thus, con.id~r the expression (A + H) (A + C D) , L ening X _A. Y _ n, a nd Z . . CD. a nd applying the II-Ccond distributi,'e law. we Obtain (A + B)(A+CD) " A +OCD The las( twO idemities in T able 2 3, ar~ r eferred 1 0 a . D eMorgan. theorem . This is a very important theorem and is used 1 0 o bta in the complement o f a n expression and o f the corresponding function. D e Morgan's theorem can be i llu't rated by meanS o f t ruth tables that assign all (he possible binary values t o X a nd Y. Tab le 24 snoW1 (wO t rulh l ables that verify t he first p ari o f D eMorgan. I heo"m . In A. we evaluate X + Y for a ll po<.ible values o f X a nd Y. Th is is d one by first e ,'aluati ng X + Y a nd then ta king i t. c omp lement. tn Il. we evaluate X a nd Y a nd (hen AND t hem together. 11,e resu ll i$ (he Same 0 T ARtE 24 Truth Table, to V, rlr, D dl0'i"n '" Thooren, ,, ' " "" " , "," " "," " 0 0 , , , , i Y " ,,,, ", " " """ 0 0 0 0 0 l _l I 1io<>I<. .. A.,.,.. 0 37 for tM four binary oombinatiom o r X . nd Y, "'hoch verifieo t M identity o r t he e q uation. Note tile o rder in wh ich the opera ti ons Me performed when evalun ti ng . n e . pression. In p art I ) o f t he table, th e complement o\"er a single variable is evalu ated first . followed by the A ND o peratio n. JUSt ~s in ordinary . Igcbra wilh multip li ca t io n a nd addition. In part A. the OH. o pera t ion i . ev al ualed fitS t. lllen. nOling lha! t M oomplement o ,..,r an expression ' IOC h X + Y ill consi<k red as . pifying l 'OT ( X + Y) . ....., e va lu ale 1M expression " I thin the p arenlM se5 and take t be complemenl o f 1M r au l!. It is customary t oexd ude t he p arenlheses ...ben com plr: m entin, a n expression. since a b ar over the enti,.., n pression joins n togelher. Th ",,(X + Y ) is expressed as X + Y ,,hen designating the complement o f X + Y. DeM o.g a n. IhcOTe m can be e xten ded 10 three Or more variables. l lte Kcn eral D cMorganS llM:or em c aD b e nprc5&C:d U X, + X, + ... + .1.'. _ X ,X, .. X. X , X , ... X , - X I + X, + . .. X . O b.erve t h.1 Ille logic "I"'nllion changes fr om O R to A ND o r from A NO 10 O R . In addiTion . the complemenl is rtmovW from I he e nlire expression and platt<! in slead ove r e "" h variable. For e xample. A + B +C + D - ABeD Al gebraic M anipula t ion B oo lea n "l gehra is" usc fu l lool for . im pHfy ing di gital circuils. Con side r. for exa m p le.l he Doolean funolion r epresented by F - XYZ+XYZ + XZ The implementalion o f Ihis equation ...'lh los'" &" Ies is sho....n in A gu", 2-4(a). Inp ul v;!Iria lll es X and Z . rc complemenled with invenel$ ' o o btain X and Z. The Ihree t er"" in t he e xpreMion are implemented ,,ith Ihree A.,"\IO p tes. T he O R p te fonn ~ the logical O R o f l he ' Cr"m$. Now consider a simp hf ocati on o f . he expreision for F by a pp lying oon,e of tIM: id enti.ies liMed in Ta ble 23: , - XYZ i XYZ+XZ - XY(Z +Z')+ XZ by idenlity 14 XYI + X Z XY + XZ b \ id enTi ty 7 by i lknl;'y 2 n.c u pression io r educed t o only tWO terms a nd c an b e implemented ,,;th l !"'es" ,II"",,, in f igure 2-4(b). I t is obvious th~1 lhe circuiT in ( b) ia s imple, t han the o ne in (a). yet. b oth i mplemem ,he Ioamc funclion. It is possibLe 10 uSC a tru,h table t o ver ify th at the Iwo impiemcn la1l0M arc equivalent. l h is i . Iho ... n in T able 25. A s e Xpr~5S4'd in Fig ure 2-4(a ). Ihe fu nction ill e<]UaITO I if X . . 0, Y _ I. and Z - I;if X - O.l' - l.and Z - O:o r if X and Z are oolh I .lltis p roduce. lhe 38 0 C HAI'TEII. 2 ! C OMDINATIONA L l OG IC C IRCUITS (. j F - XYZ+XVZ"+XZ (b) F _ XV "- XZ o FIG U RE 2 4 Im pl emenla ti on 01 B ook.n Fuoclion .,i,b Gate. o T ABLE 2 5 T ruth Tabl ~ f or Boole~n F unc'ion l our I's for F in p art ( a) o f Ihe table. As expres.<ed in Figure 2-4(b). the fu nction is to I if X = 0 and Y ~ 1 o r if X - I and Z - 1. T his produces the s ame four I's in part (b) o f t he table. Si nce both e~prcssio n, produce the s ame t ruth table. ' hey a re e quivalent. T herefore. the t wo cireu i! , have the same o u tput for all (lOSSi. b le binary c ombinations o f the th ree inp ut variable,- Each circuit implemems the s ame function, bU! the one wit h fewer ga te< is preferable becau&<.' it requires fewer components. W hen a Boolean e quation is im plemented with logic gates. e ach term r equires" g ate, and e ac h variable wit hin the term d esignates a n input to t he g a te. We define a / ileml a , a single variable within a t erm t hat m ayor may n ot b e complemented. T he e~pre"ion f or th e function in Figure 2-4(a) has lh ree terms a nd e ight literals: t he one in Fig ure 24( b) h as two t erms and four lit erals. B y ~q ua l l _l I ! look. .. AIg<bn 0 39 r educing Inc n umber o f terms. t ne n u mber o f li terals. o r b otn in a B oolean expression. it is o fte n possible 10 o h lain a s implN cireuit. l.loo1e an algebra is applied 10 r educe an e xpression l or the p urpose o f o htaining a sim pler circuil. For highly oomple~ functions. finding Ihe best u pression b ased o n c ounts o f l erm, a nd lit erals IS ,ery diff.cult. e ven by Ihe usc o f c omputer programs. C er tain methods. h o .... ever. for r educing expres>ions a re often included in c omputer t ools for .ynlhesizing logic cirCU;Is. T hese m e l h od, can o blain good. if nol t he b e". SO lulions.. T h c o nl y m anua l m ethod for lhe general case is a c uta nd-t ry p roce d ure e mp lo)"ing the basic re lations a nd o t her m anipulations t hat I>ccom e familiar wilh ""c. T he following n amp les u se i dent il ies Irom Table 2-3 t o i llu,trate a few o f Ihe possibilities, I . X +XY - X(I+Y) - X 2.. X Y +XV - X (+Y) - X J . X +X Y - (X+X)( X + Y ) - X+Y N ote that the intermediale step X - X 1 h as b een omilted when X i , factored out + Y - I is useful for elim ;n aling red,:!"danl lerms. as is d one wilh Ihe l erm X Y in Ihis same e qualion. The relalion Y + Y - 1 i , useful for oolllbin ing Iwo lerms. a s is d o ne in e qu alion 2. T he Iwo being combined must b e idenlical excepl for o ne variable. and Ihal variable mu", b e c omplemenled in o ne l erm and nol c omplemented in the othe . E quation 3 is sim_ plified by m UnS o f the scoond di,lribuli,c law (ide ntily 15 in Tablc 2 3). T he fol lowing a re Ihree more e "" mpl e. o f simplify ing Boolean expression" i n e qual;on 1. The relalion,hip I ",nn. 4. X (X+Y) - X+X Y - X 5. ( X+ Y)(X+Y) - X + YV - X 6. X (X + Y) - XX + XY - XY ~ NOle Ih al the i nlermediale <lop< X X . . X . . X I h ave been omilled during Ihe m;onipulati on o f e qualion 4. The c~press i on in e quation 5 is simplifi ed by me.!n, o f Ihe occond d imibuti' e law. H ere again. we o mil Ihe intermediale 51ep< Y Y . . 0 a ndX+ O_X . E qualion,4 Ihrough 6 a re the duals o f <!<jual;on, I Ihrough 3 . Rem ember Ihal the dual 01 an expression is o btain e<l by changing A ND 10 O R a n d O R t o A ND Ihroughoul (a nd l s 10 0 , and 0 , to l s i f Ihey appca< in Ihe expression) . T he ,j""llIy I'riMdl'l~ o f B oolean algeb . . S1ales Ihat a Bool ean equalion remains valid if .... " t ake Ihe dual o f the expressions o n oolh . ides o f I he e qual' sign. l "hcrefore. e quation, 4. 5. a nd 6 can be oblaine<l by laking Ihe dual o f e quation, I . 2. a nd J . respecti.ely. A long wilh Ihe resuUs just gi 'cn in Cl luation, I Ihrough 6. Ihc fo ll owing C Ol! II",,,,,,,,, is u<cful when simplifying Boolean expression" ."ns", X y+xz + Y Z - XY + XZ T he t heorem . bo..... thai the third lerm. Y Z. is r edundant and can be eliminated. N ote Ihat Y and Z a re aloSO<iale<l wilh X a nd X in Ihe f,l"St 1"0 lerms and a ppear 40 0 C HAPTER 2 / C OMBINATIONAL L OGIC C IRCUITS 10gelher in lhe lerm Ihat is eliminated. T he proof of the consensus theorem is obtained b}' tirst ANDing Y Z with ( X -+ X ) _ 1 a nd procecds as follows: X Y+XZ+YZ X Y+XZ+YZ(X+X) - X Y+XZ+XYZ+XYZ - XY + XYZ+XZ+XYZ X Y(I+Z)-+XZ(i+Y) - X Y-+XZ T he dual of l he consensus t heorem is ( X -+ n (\' -+ Z )(Y -+ Z ) - (X -t Y )(X -t Z ) T he following example s ho .... how the consensus theorem can be applied in manipulating a B oolean expression : ( A-tB)(A-+C) - AA+AC+AB-t8C AC-+AB+BC A C -+ AB N01 e that A A _ 0 and 0 -t f lC = A C . The r edundant term e liminated in the lasl s tep by the consensus theorem i5 B C C omplement 01 a F unction T he complement representation for a function F. F , is o btained from an inter_ change of l 's t o 0 '$ and 0 ', 10 l 's f or the values o f F i n the l r uth table. Thc complement o f a funclion can be derived algebraically by applying D eMorg.n, t heorem. T he genera li zed form of t hi. t heorem sl .te, l hat t he c omplement o f an expression is o btained by imerchanging AND and O R o perations and complementi~g each variable and c onstam, as , hown in Example 2 t. E XAMPLE 2-1 C omplementing t"undions Find the complemenl of each of the functions r epresented by the e quation. F , _ X YZ -t X VZ a nd Fl - X (VZ -t Y Z) . Appl}'ing DcMorgan 's theorem as many times as necessary. we o btain the complem~nts as fol lows' F, - -- X YZ -t XYZ = ( XYZ)' ( XYZ) ( X + Y - tZ ) (X -t Y -t Z ) X (YZ -t Y Z) = X -+'eZec+,ycZ~) " 2 -J I S,,,,,J:ttd f utm, 0 41 X -t (l'z , Y Z) ~ X -t ( Y-tZj(Y -t Z) A s impler method for deriving 1he c omplement o f a fu nction i , t o t a ke the d ual of the function e q u .tion a nd oom pl ement each literal. This me1hod fo Uow! from 1he generalization of DeMorgan's theorem, Remember l hat the dual o f an expression is o btained by interchanging AN D a nd O R o perations a nd \ ', a nd O's. To avoid c onfusion in haod li ng c omplex functions, a dding p arentheses a round t erms before ta~ i ng the dual is helpful, as illustrated in the next example_ EXAM PUC 2-2 Comf"le"",nt;ng Fun<l;on< by Usin~ Duals Fi nd the complements of the functions in Example 2 1 by t aking the duals of t heir equation! and c o mplementing each literal. We begin with F, _ X YZ -t X YZ - ( XYZ) -t ( XYZ) The d u al o f F, i , Complementing each lit eral, we ha>' e ( X -t Y -tZ)( X -t Y -t Z ) - '" Now, F, = X (YZ -t YZ) _ X Y Z) - t(YZ T he d u al o f F, i . X -t(Y -t Z)(Y-tZ) C omplementing e"ch lileral yields X -t (Y -t Z j(Y-tZ) _ 2 -3 F" S TANDARD F ORMS A B oolean func1ion expressed algebra ic a ll y can be wriHen in a variety of u'a}'S. T here are, howe,'er . specific way. of writing algebraic e qua tions t hat are considered to be s tandard forms. Th e standard form. facilitate the simplification procedures for Boolean expre'-S;ons and frequen tly r esuh in m ore desirable logic circui1s. The standard forms contain prodl<ct terms and " "" ' em .... A n example of a p .od uct term is X YZ. Th i, i, a logical product consisting o f an AND o peration a mong three literals. A n example o f a su m term i< X + Y + Z . This is a logical . um consisting o f a n O R o peration among the litera ls. h muSt be realized t hat the 42 0 C HAPTER 2 f C OMIliNATIONAL L OGIC C IRCUITS words " product" and '.um~ d o n ot imply arithmetic o perat ions in Boolean algebra: instead. thc}, sJ'<'cify l he logicat o peration. A N O a nd O R . rC'J'<'ctivcly. M lnlerms a nd M axterms II has becn sho,,'n lhal a l rulh table dcl in c", B oolo.n function. An a lgebraic expression r epresenting the function i . d erived from t hc tablc b)' finding thc logical , u rn o f ~II p roduct t erm. for which the function .,"ume", the binary v .lue I . A p roduct term in which all thc variables appear eMcliy once, either cornplcmcnt~d o r uncomplemented, is called a m imam, l is characteristic p roperty is t hat it r epresents exactly o nc c ombination o f the bi",!ry v.riablcs in a truth table. h h .! the value I l or that c ombination a nd 0 for a ll o t hers. T here a re 2" J istincl mintcnll~ for " variables- The four minterm! l or th e two ,'miables X and Y are X l '. X y, x l', and X Y T he eight mintcrms for the lhrce , '.r iables X, y, a nd Z a re l i'leJ in ' I"b lc 2-6. T he b inary numbc~ from ( ((I to 111 a re listed u nder the variables. For each binary c ombination. there i , a related minterm . Each minterm i, a p rod uct term " f e,;<ctly t hree li terals.. A li teral i , c omplemented variable if the corresponding bit o f t he rclated b inary c ombination is 0 a nJ is an uncomplcmentcd v ari.blc i f it is 1. A symbol " '; f or each minterm is also shown in thc tab lc. where the sUMcript j d enotes lhe decimal c 'lu iv;<lcnl o f the bin'lT)' combination for wh ich the m intcrm has the val ue l . This list o f mintcrms for any given n , 'ariables can t>e formed in " similar m .nner f rom" li sl o f t he binary numt>e,.. from 0 through 2" - I. In addi tion. t he t ruth table for each minlerm is g i"cn in !he righl half " f the lable. -rncsc truth tobles cl ca rly show t h.t e ach minterm is I for the c orresponding binary combination a nd 0 for all o ther comb i n alion~ S ud ] truth l able. will t>c h dpfu llol c r in using minlcrmS to form B oolc.n expressions. A ,urn t erm lh nl conl~i n s a ll l he variableS in c omplemenled o r nncomple_ menled form is called a ",axlem" Again, it is possible t o formulatc 2" m "'term s with II variables. 11," eigh t m a,lerms for thr ee varillblcs arC li sted in T;\blc 2 -) , E;\ch maxterm is a logical ' urn of the thr ee variables. wi th each variablc t>cing complcmented if t he corresponding bit o f the binar)' numlJcr is I a nd uneomplemcnted o T A8LE 26 Mint" nn ' fur T h", e Va ri. hl e, ,, , """ " """ " , "" " 0 .- Product x i'z Hz X YZ X YZ X Y2 xi'z X YZ X YZ Symbol ~ m, ~ m, m, '0. " m-, ~ m, m, , ~ m, """ " """"" """," "" """"" " """ """ " 0 """ 0 0 ~ " " " ~ " " " " "" "" " " 0 0 ~ 0 " " " " " 0 2_3 I S .t><Iord Fo<n" . o ,- T ABLEl-7 ~t.'lenm f.... T Il..., \ " ariab!a , , , , ,, , ,", 0 ," ," " " -,~ X->-Y->-Z X->-Y +Z X +y +Z X->-Y->-Z X +Y + Z X + Y +Z X ->- Y->-Z X+Y->-Z M, M., ., ., .. . .. .. .. ., , ,,, , , ,, ", M , M, M . M J 0 M , M , M, ,, ,, ", i fil is O .l'he ,)1nbol f or a m nle rm is M I' ... h cr ei d enotes Ihe decimal equiva lent o f Ihe binary combiruuion ( Of ... h.eh t he maXterm has t he value O. In t he right half o f t he table. t he l rulb table f or e ac h m utenn" &i'-cn. N otc thaI the vahoc o f t he m U' t erm is 0 ( Of t he coIT.-sponding combination a nd I for all o ther c ombinations. I t is now d eu . .,he.e the l enni ~ minterm ~ a nd ~ mutenn " c ome from :. mint er m is a ( unction. 11(>1 e qual t o O. b aving lhe m,ninmm n umber o f l ". in its t ruth l able ; a onaxterm i . a f unclion. n ot e qua l to L. having the m a.imum o f l 's in il$ t ruth table. Note (rorn Table 2--6 a nd TobIe 27 I hat R m inle"n a nd m a.term " 'ilh th c SlI me . ub.cript " r c lhe c ompleme"t . o f clICh oIlier; lh ul is. M ) r-or example. J _ 3. we !lave m). m XYZ J- f". - X + Y+% _ AI , A Doo lean functiOfl c~n b e , ep rese nted a lgebraica ll y f)m ~ s i"cn t ruth t able by f onning t he logical s um o f all lh e minlenDS l hal p roduce 8 I in l he function. I'h" , ,-,pression . . c alled. s um o f m llllrm", C onsider t he Hoole"" funclion F in Tloblc 2 -8(& 1 k f unction . . C<]ual t o I for e ach o f the follo ...in g binary c omb in a' ). t ions o f t he " ariables X . Y. a nd Z ; <XXl. 010.101 and lll. I ~ c ombinations ....,.rc . pond to minlerms O. 2. 5. and 1. Ily e xamining Table 2-8 and lhe ' rulh t ables for l hese m inl"nns i n Table 2-6. it is e vide nllh . l t he function F an b e cx prc"""d BL gebraically a . t he I ogical,um o f t he Sialed mi lllerms: F . . X YZ + X YZ + XYZ ' ;-XYZ . . mo+ m, ';- m, + m , T hi. c an b e f urther a bbrcvia( ed b y list in g o nly th e d ecimal . UMe.iplS o f t he m interms: F (X. )',%) . . ~",(O.2.5.7) T he . y mbol ~ " ,nd< for t he I os"'al.um (ll<:><>k,n O R) o flhe m in' erm.. TIM' ""on b<!n fo llowing it r ep""",nt t hc mmIC.on. o f lhe f uncti"". T he l en ers in p arenl he. s es 1011o ...;ng F lorm a lIS! o f the variables in the o Jcr taken ... hen I he m lnle, m. a re COfI~encd ' 0 p rod"'" tenllS. 44 0 C H A PTER 1 1 C O MBI NATI ON AL LOGIC C I R CUITS o T A8LE 2-8 8 00lean "1 ~' u n ct i un ' ,,, , , "" "", " ", "" I I 0 I o fTh..,., " .riabl", ,, 0 "" , ", " , '" ,,, , "", """ , ",, " I I I " " " 0 0 I 0 Now c onsider the comple ment o f a Hoole an fU ll c\i<>n The b inary v~ l "e, o f ];' in Table 2-S(a) are obtained by changing 1's 10 0 ', a nd 0 ', to I 's in t he values o f F. Taki ng t he logical Sum o f mint CTms o f 7:, we o b13in or, in a bbreviated form, f \ X. I ',Z) '"' 1 :",(1,3,4. 6) N ote that Ihe m interm n umbers for F a re t he ones missing from the lisl o f t he m in t erm numbers o f F We nOw t ake the c ."npl<ment o f];' to obt~i n f '; - (X+Y+Z)(X + Y + Z)(X + Y+Z)( X +Y + Z) This sh oW'! t he procedure for expressing a Boole,'" f un ction as a prod"cr o f m ax ' ams, T he a bbreviated form for this produ Cl is F (X Y ,Z) _ n M (1.3,4,6) where symbol fJ d enotes t he logical product (Boolea n A N D ) of the maxterms " hose n umbers aTe li sted in pa renlh~ses. NOle l h,t t he decimal numbers incl ud ed in l h. p roduct o f m axterms will always b e t he some as th~ mi nt um lis t o f t he c omp lemented function, such as (1 . 3, 4 .6) in lhe foregoing exa mple. M axter m, are seldom used direclly when d ea li ng wit h B ool~an fu nction s. a s we e a n always replace them wilh the mimerm lis t o f F, T he following i$ a \ U mmaTY o f t he most i mportant properties o f mi nt er ms: 1. T here a re 2" minterms for " Boolean variables. These min tenns Ca n b e c "alu at~d from [he binary numbers from 0 t o 2" - I. 2. A ny B oolean f unClion can b e e xpressed a s a log ic al sum o f mi m cr m s. 2_3 I S. ."d"d Form. a 45 J . T he c omplement of a function c onta ins those m interms n ot included in t he o r iginal function. 4. A function that i ndu d e, a ll t he 2 ' m interms is e q ual to logic 1. A l unction that is n ot in the sumof_mi nte rm s form can b e c on"cried to t ha t form by meaos o f" truth t able. since t he truth table always specifie.; t he m interms o f t he funClion . Consider. for example. t he Boolean function E - Y+XZ T he expression is n ot in su mof.minterms form. be<;a use each lerm d oes n ot c ontain all th ree variab le.; X . Y; a nd Z. T he t ruth table for this funclion is listed in Table 2-S(b). f rom t he table. we o btain the minterms 01 t he fu nction: E (X. Y ,Z) - ~ m(O,1.2.4.5) The m interm. for t he comp lement of E a rc given b)' E (X. Y .Z) - 1m(3.6.7) N ote that the total n umber o f minterms in E a nd I f is e qua l to eight. si nee the function has three variables. a nd three v ariables pr{)duce a t otal of eig.h t minl crm . . Wil h four variables. there will be a tota l of 16 minterms. a nd for t wo variables, t here wHi be 4 m interm s. A n e xample o f a funetion thaI i ndude s a ll t he minterms is G (X. Y) - 1,"(0. 1.2.3) _ 1 Since G is a funchon o f Iwo variables a nd c ont ains all l our minterms. it is a lways e q u al to logic I . S um o f P roducts T he .,mof mi nterms form is " s tanda rd algebraic c ~ prcssion t hat is o b tained dire<:tly f rom a truth table. T he e~press i on s o o btained contains the maximum II umt>er o f l iteral. in e ach term a nd usually has more producI terlT1$ t han necessa ry. T his is b ecause. by definition. each minterm must include all the variables o f t he functio n. c omplemem ed o r u ncomplemented . Once t he s um o f m inICnn. is o btained f rom t he truth table. Ihe ne~1 s tep is 10 t ry 10 si mplify the expression t o s ee w hether it is possible t o re duce the n umber o f p roduct terms a nd t he n umber o f literals in t he lerm s. '[lIe resuh is a simplified expression in . u"'-oj-produciS > form. This is an alternative . ta ndard lorm 01 e xpression t hat c oma in, product l erms with o ne. IWO . o r any numi>er o f literals. A n e xamp le o f" I loolcan funclion expressed a s a 'U rn o f p roducts is F - Y +XY Z+XY 111e exp ression has three pr{)duct terms. ille first with o ne li tera \. t he s econd wit h t hree literals. a nd t he thi rd with two literals. T he logic diagram l or a sum-<>f-produCls Corm consists o f a g roup o f A ND g a te. fo llowed by a single O R gat~. as s hown in Figure 2_5. Each pr{)duct t erm 46 a C HAJ'TEJl l f C O.\I I11NA1'IONAL L OGIC C IRCUITS , -----, a I'I GU II. E2-5 S"m.u"''''odllC1. lm plcme ntat"", re<juires a n AN"D gale. exccpl for l~nn wilh a s ingle literal. The logical ' un . is f ormed "'ilh a n O R g ale l hat h at .in&le l ilera" a nd l he OU l plll$ o Ilhe A ND g ales as inputs. I I is assumed . hat l he inpul variables are d irtt.ly a,-ailable in t heir c ompkmenl~d a nd uncompl~rm:nted forms. ~ ,n'ffi~ ... a re nOl i ncluded i n the d iavam. 1l>e A ND gale& ( ollowed " " l he O R &ale f onn a c imlll OOI1fig urluioo referred to a s a ",,">./n"('1 impk"'tll/~.i"" ( IT " ""_lfi"tl e ircui. [ f a n e.xpreMion is I lOl on lum-of-prodUC\$-form .;1 can be OOI1"~ 'I ~d to l he s la nd ard l onn by m eans o f Ihe d isui bulio'c law. . C0ll5id~r l he cxpreMion f" _ A B +C(D -+-E ) T hi. IS n ol in . um-of.products fQrm. because I he IeI'm D -+- E is parI Q( a prodUCl. bUI i , nO! a . ingle literal, Th e e.prcl\Sion can be c onverled t o. s um o f p r od uclS by applying Ihe a ppropriate d istributive law a , follow.: f" _ A I) -+-C(V + ) _ A B + CD + CE T he fU nc1 ion f ' ; . implerm:ntcd in a n on.landard f onn in Figure 2 -6(a). T hi. re<juire. ' wo A ND g ales a nd t wo O R gales. nw"" a .., Ih..,e le,"('I . o f g alin, in t he circuit. f" i . implcrm:nted in IUon..of_prodUC\$ form in Fi ,ure 2-6(b). ThIS c ircuil requires l hrce A ND p ies a nd a n OR g ale a nd uses (l.u leod. o f gating. T h e d j$lo11 a s t o ,. .. h ether t o u~ two-le,..,1 o r m ultiple-""..,I ( th ree le"el, 0<' m ore) implerm:nlation is c omplex. A mong l he issues ; nvoh-ed are the n umber o f p Ia n umber of g ale i npul S. a nd t he a nwun t o f " " lay bel,,-cen l he t ime t he i nput values are ~l a nd Ihe lime lhot r esuhin, OU1JlUI v alues appear_ Two _lev e1,mplementatioos are the n alural form for c erlain implementation l~hnologie . . as we ... ill s ee in C haple.4. P roduct o f S ums A nolher . tandard form of e xpressing Boolea n f u nclion. algcbraically it the 1",,,1 "c. o f"'-"", Th ill form is o blained hy f mming a logic.1 p roduci o f s um lerm~ E ach logical sum term m ay have an y nu mb<:r o f dtSt,nCl l iteral. . A n e xample o f. fune lion e xpr .......d in p rod uct-of-Jums form ill F _ X (Y + Z)(X + y +z) Thil; exp<ession l uis s um t ennl o f on ... t"-o. a nd .h.-ee hlerals. T h e fum ternn p er_ form a n O R o peralion.and t he product i . a n A ND o peralion. , ~~ ( .)AO+C(D+E) o , J 0 J c , J , (~)A a+CD +CE F IGURE: U ; T hr \...e,cI and T".,.lcvellmplomentotioo The gate s!ructure o f t he prod uct_ol_su ms expression consiSis o f 3 g roup of O R ga tes f w t he Sum ler "" ( c pt for a .ingJe ]it e'al term), fo ll owed by a n AN O gale. This is . how n in Figure 2-7 l or the preceding function F A s with the , u rn o f product s. t his standard t ype o f expression resulls in " two-level g ating s tructure. 2 -4 T wo-LEVEL C IRCUIT O PTIMIZATION T h e c omplex; l y o f t be digilal logic g a1C$ I hat i mp lem en t a B<Xl]e,m f unction is d irectly related to the algebra ic expression from whi ch the function is im pl ementoo. A lthough the trut h table representation o f a function is u nique, when e xpressed algebraically, the fUlI Cli,," .ppcaTS in m any d ifferent forms. B ool"," expressions may b e ~i mpl ific d by algebnoic manipulation", d iscussed in Section 2-2. However. t his proc~ d ure o f sim plification is awkward b<:cause it lack. 'pecific rules t o predict eac h succceding step in the m .n ip u Wi ve procc.,; a n d it is difficult t o d etermine wh ether the s im pleS! expression has b<:en aehi~v~d, By contrast. the m~p m et ho<I provid"'l a , traight fo tward p , OC(:d urc for o ptimiring B oule,n functio ns o f up to four v ", i"b l"", Ma p!; for iive aDd.ilI variables ca n b<: drawn as well. b ut a re m "'e cu mb<:rso me t o use. Th~ m ap is also known a , t he K a"""' l<iJ " 'af!. Or K map. T he map is a d iagr.m m ade up o f S<j u'Tes. wit h each sq uare representing one minter ", o f the iu nc tion , Since any B oolean function can I", e xpresscd as ~ su m o f mi ntcrm>. it follow, t hat a H'>olcan function is r ccogni'''d graphically in t he m ap by those squ" res whose m intcrm s are includ ed in t he function. In fact, the m ap p rcscnts a , 'isu al d iagram of a ll1 )OSSib ie way' a function may be e xpressed in a st andard form , By roxognizing ",,,iO ll S pattern>. t he user can deri>'e a lternative algebraic ;. ~oo t 'lGlIKE 27 Pr<>duc1-ofS ums Imp lemen,., iQn 48 0 C HAI'TEIl21 C OMlltNATrONiI.l. LOGtC Ct~CUtTS n pressions l or the same function, from which the simplest can b e sele<:\e<J, The o plimized expressions produced b)' the map a re always in sum-ofproducts o r p rod uet-ofsums form. Thus. maps handle optimization l or I wole"el implementations, bUI d o n ol a wly directly to po&Sib1e simpler implementalions for the g eneral case "'ith three o r more level . . Initially. this section covers sum -of-prod""" o plimization and. later, applies i lto p erforming p roduc\ofsums op l imi~"tion, C ost C riteria In th e prior section. c ounling literals and t erms was ment ioned"", a " 'ay o f measuring I he simplicity o f a logic circuit. We introduce two COIiI c rileria 10 formalize this concept. T he first criterion is literal COSI. the number o f lilerat appearance> in a Bool. e an e 'pre<sion c orresponding exactly to the logic diagram. For example. for the circuits in Figure 2-6. the corresponding Boolean e xpre"ion, a re F = AR + C(IJ + E) and F - A8 + CIJ+CE T here a re five literal a ppearance> in I he first e quations and six literal a ppearanceS in t he s econd equ~lion. s o the fi rst e quatio n is the simpiesl in t erms o f tileral cost. Literal c ost h as Ihe a dvantage Ihat il is v uy simple t o e valuate by counting liter.1 appearances. I t does not. however. represent circui t c ompln ;t y accurately in all caws. eVen for Ihe c ompariso n o f d iffue nl implerneMations o f the s ame logic function . The following Boolean e qu ation . . b oth for function G, illustrate this situation; G - ABCD + ABCD a nd G - (A+B){B+C){C+D)(D+A) T he i mplement"tions repre..,nte<l by t he.., e qu ations both h a"e a titcTat COIit o f eight. But . the first equation h as two t erms a nd the second equation has four ternlS. This suggests thai the first equation h as a l ower cost t han the second equation. To c apture the difference il lu<lrated . "'c deflDe ga/~ i nput ~O$I as the IIum\>e r o f inputs t o the g ate. in the i mplementalion c orresponding exacl ly t o the given equation o r e<tuations. l " is c os. can b e d Clumined easity from the logic diagram by simply counting the total n umber o f inputs t o t he g ates in the logic diagram. For 5um-of' produCI$ o r producl-<lf-sums equations. i\ can b e found from the e quation by finding the sum o f ( 1) all li teral a ppearances. ( 2) the numDer o f t erm, excluding terms thai c on,;st only o f a single litera l. and, o ptionall y. ( 3) t he n umber o f distinct c omplemented single literals. In (1). all g ate inputs from outside the circuit a re represented. In (2), all g ate inputs wit h in the cjrc:uil. excepl for t hose In in,'erters are represenled and in (3), im'erters needed 10 c omplement the input variables are c ounted in the e vent that complemented input variabtes a re n ot provided, For the two preceding e<tuation .. e~d"d ing the count h om (3), (h e respeeti,'e gate i nput c ounts are 8 + 2 . . 10 a nd 8 + 4 " 12. 2_4 I Two-ln'<1 Circuit O p<muz";o,, 0 49 Including lhe count from (3), that o f input inverte~ the respective counts are 14 and 16. So Ihe first equation for G ha$ a lower gate input cost even thoug.h the lit_ eral costs are equal , G ate input cost is currently a gO<Xl measure for contemporary logic implementation. since it is p roportional to the n umber of transistors and wire. used in implementing a log ic circuit. Representation o f g ate inputs become, particularly important in m easuring e mt for circuits with more than two level .. Typically, as the number o f levels increases, literal cost r epresents a smaller proportion of t he actual circuit e m t since more a nd m ore gates have n o inputs from oUlside t he circu it itself. L ater, in Figure 2-29, we introduce complex gate types for which evaluation of I he gate input e mt from an e quation is in"alid, since Ihe c orrespondence b etll'een t he AND, O R and N OT o perations in the equation a nd the gates in t he circuit can n o lo ng er be e stablished, In such case .. as well as for e qua tion forms more complex t han , um _o f.products a nd p roduct_ of.sums, t he gate inpul count m u't b e determin ed directly from the implementation. Regardle ", of the cost c riteria used, we s ee later Ihat the ,implest e xpre",ion is nm nece",ari ly unique. I t is &ometime. possible t o find two o r m ore expressions t hat satisfy t he cost criterion applied , In that ca>e, e it her solution i , sati,factory from tbe e mt standpoint . Two-Variable Map T here a re four minterms for a Boolean function with Iwo variables. Hence, the two-vari.ble m ap consi~us of four squares. o ne for each minterm, as s hown in Figure 2-8(a). T he m ap is redrawn in Figure 2-&(b) to show Ihe relationsh ip between the squares and I h. two variables X and Y. T he 0 and I mar~ed on I he left side and the top of the m ap designate t he values of the variable .. The variable X a ppears complemented in row 0 and uncomplemented in row 1. Similarly, Y a ppears complemented in colu mn 0 a nd uncomplernonted in column 1. N ote that Ih e four combinations o f t hese binary v alue, correspond to the truth t a ble rows """",,iated witb I he four minterm s. A function of two variables can be represented in a m ap by marking the squares t hat correspond to the mintenns of the function. As an example. the func_ tion X Y is shown in Figure 2-9(a ), Since X Y is equal to mi merm m j, a I is placed ~ 0 ~o, " EE I "~ c ;r;] t@:g ~ ,.j o F IGURE 2_8 "IWo-V., i.ble Map 1 ,,, I (oj XY o 'f.-O l o LE] t~ ( b)X " Y H GURE 2-9 R epresen ta tion o f F unctions in the Map so 0 C HAI'TUI. 2 I C OMlUNAll0NAL L OGIC C [RCUITS i nside [ he "'Iuare Ihat b elonp [ 0 mJ_ f igure 2-9(b) . hows tbe nt.3p f or t he logical sum o f t h rtt m;nterms: - - m , + ml + m ) - X Y +XY+XY = X + Y The o p limilcd expreloSion X + Y is detennine<l from t he tWO-S<luare a rea for the variab le X in the se.:ond row and the IWo-S<JUare a rea for Y in the SCC()nd c o lu mn, Together. these two a reas enc lose the three "'Iuar"" beJong;nllto X Or Y. Th is simp li fi cation can be j u' ti ned by a l llcbr~ic manipulat io n' X Y+Xy+ X Y _ X Y+X(Y+Y) - (X + X)( Y +X) - X + y 11><: exact procedure for c wnbining square!! in tbe map will be clarlfted In the e um pl"" thai follow. Three-Variable Map ll>ere a re eight m interms for t h",e bina!'}' vari~bIe:s. l l>ercfore.. Ihru_vari.able map o f eighl squares. lIS s lto"-n in f ig ure 2 - 10. T he m ap d r:oWJl in par1 ( b) is marked wil h !l;nary numbers for each row a nd e ""h column t oshow t he bina!'}' val_ ue. o f the minle nn s. NOie Ihat lhe numbers along Ihe coIum n ~ d o not fol low the binary coun t " 'q ue"",c, T he e hUKler ill>c: of Ihe listed sequence is Ih .t only o ne bi t changes in value from o ne adjacent colu mn 10 Ihe neX I. wh ic h c orre.po"ds to the G ray r ode in trod uced In C hapter \ , A m int erm " 'IuJre can be localed in the map in t wo ways. First. we e~n memorile t ~ e n um ber< l i' ted in FIgure 2- IO{a) f(>f each m ln le rm location. or we can refer to the bina!)' numbers a lon, Ihe rows and colum n. in Figure 2-IO(b). f o r e ump \e. the square aSSIgne d ( 0 III . co rre.pond~ \ 0 row 1 and column 0 1. When t he# two n wubers a re c ombi""d . they gi"e the b inary n umber 101. " 'bose decimal cqu;~alent"~. _ A not .... r , ,'ay o f looking al square XYZ i . t o consider it 10 be In Ihe ro . . m arked X and I.... CQlumn beionsong 10 Y Z ( column 0 1). NOie Ihal Ihere ale four squart:< "' h<:re each variable is e qual ( 0 I and four " here each I, e q ual t o O. """,iM. ffl , - , "' " '" 00 ~ ., m , m, m, m m, , ~ olxY'l X YZ , X YZ XYZ X YZ , ', ' " , ,., '" C " l CU KE Z-IO l br=Van.bIe Map XY:": T he v ariable appoor>; u ncomplemented in Ihc fo ur s quare, w here il is e qual 10 1 a nd c omplemented in t he fo ur squares wl1er e it is e qual 10 O. For convenience. we wrile Ihe variable n ame a long Ihe four s quares w here il i . u ncomplemented. A fler o ne t>ccomc. familiar with maps, Ihe use o f Ihe , .riable n ames alone i , , ufficienllo lat>c l Ihe m ap regions. T o Ihi , e nd. it i , important 1 0 n ote Ihe lOCal io n of Ihese lat>c l. 10 o btain a ll m interm, on Ihe map. In t he two-variable map. Ihe funclion X Y d emonSlraled I hal a function o r a l em, for a funclion can c on,;.t o f a , i ngle . quare o f t he map. B U1 to achie,e simpli. ficalion. we need 10 c onsider mult ip le s quares corresponding t o producI lerms. To u ndersl"nd h ow combining s quare implifies B oolean funclions.. we mUSI recognize Ihe b .,ic p roporly possessed by ~ J.ia cent s quare, A ny two adjacem squares placed horizonta ll y or vertica ll y (bul not d iagonally) 10 form a r ""tangle correspond to mint erm' t hai d iffer in o n ly a s ingle variable. T he single variable a ppea rs un comp lemenled in o ne s quare a nd complemenled in Ihe o ther. For e~" mpl e. " ' 5 a nd ... , lie in two a djacent square .. Variable Y is c omplemented in a nd u ncom_ p lemented in wl1ile I he Olher t wo variables malch in both 5<!" . .e . . The logical Sum o f t wo . uch adjacent m interms can t>c s imp li fied into a single producI lerm o f Iwo variables: m, m,. " 'l + "'7 - XYZ -+ X YZ - X Z(y-+ Y) - XZ H ere t he Iw{) ,,! u" res differ in Ihe variable Y. which can t>c removed when Ihe log. ieal s um ( OR) o f the two minlerms is formed . T h us. On a 3variable map. a ny IwO m inter nt s i" adjacent squares thai arc O Red t ogether produce a producI lerm of two v ariable .. T his is s ho"n in E xamp le 23. t :XAMI'U: 2J Simplifying _ Bool nn . 'unction U sing_ M ap Simplify the Boo lea n function F (X. Y ,Z) - ~m(2.3.4.5) i-Irsl. a I is m arked in e ach mi nt erm [hal represents the function. T hi' is . hown in Figurc 2 11. w here t he s quares for minlerms 010. OJ 1. JOO. a ttd IO J a re m arked wil h J.~ r"Or c onven ience. a ll o f the r~n\ainin g sq uares for which t he funCl ion 11 ,,, value 0 arc left bl"nk r alhcr t han entcring Ihe 0 .. T he next slep is 10 e xplore col lect io n, o f s quares on I he m ap represe nting product l erms t o t>c c onsidered for Ihe si mpli fi ed e xpression. We c,,1 such o bjects reciallgie. ince thcir s hape i , Ihat of a 1 rectangle ( induding. o f course. a square). Reclangles t haI c orrespond t o p roduct Icrms a re reSlricted. however. 10 contain numt>cr> o f s qu" re. thaI are powers o f 2. s ud", 1 .2.4.8. . .. . So o ur goal i, t o find Ihe fewesl , uch rectangles Ihat include all of Ihe minlerms mark ed wilh Is This will give the fewest producl lerms. In Ihe map in Ihe figure. Iwo rectangles enclose all four s quares c ontaining 1.. T he u pper righl rectangle represents t he p rod uct lerm X Y. T his is d elermi ne d by ohserving Ihat Ihe r eclangle is in row O. c orrespo nd ing t o X. a nd Ihe laSI t wo col umns. cOrresponding t o Y. S i milarly.t ~ c lowcr left rectangle r epresent' Ihe producI term X Y. ( The s econd row r epresent' X a nd Ihe t wo lefl col um ns represenl Y .) Sin ce these 52 0 C HA I'rnR 1 1 COM IlINAnONA~ l OGIC C I R.CUITS o FI GU R E1 1l . Map fOf F... mp . . 2.3: f'(X, Y .Z) _ . Im(2.3.U) - xy .. x l' lwo rectangles include .11 o f I he I ', in I he map. lhe logical . um o f Ihc corlUpOOding I "'" product l enn. gives lhe optimized uprcss;on for P. F_ XY+XY In $Orne casn. I "" $<jua r", in l he m ap a re adjaceOi and form. rc<:langlc o f Mze 1-..0. e "en Ihough Ihcy d o nOi louch cach Olhe,_ For u ample, in H lurc 2-10. ,...., is adjacenl 1 0 m l a nd m is adi ~nl 10"" I:>ccause lhe mi nlerms differ by One , varia b". T hi. can b e readily ,'crined algebnlically: m o+ntj t n, + t n6 " XYZ +XYZ - XZ(y + Y) - xl' XYZ+ XY Z - XZ(Y + Y ) - xl' T he rectangle. correlponding 1 0 these two product tenni\, xi? a nd x l'. are s hown t he map i n ~jgure 2-12(a ) . ll a~d o n (he localion o f I h_ reel.ngles. w e m u. t mod ify the dcfinilion o f IKijllCCnt s quar", 1 0 include Ihis a nd o ther. s imil.r cues. We d o $ 0 by c onsiderin, I he map I I being dra".., on a cylinlkr, a t tbov.'n in ~ lgurc 2 .12(b). , ,-bere l he r i,ln a nd Ie!! e dges touch e acb ot hcr 1 0 c orrectly establish m imenn adj~ncies a nd form the r eel.ngh In the map" in F i,ure 2. 12, " e ha,'c simply used n umbers n ther Ihan t o reprcscm Ihc mintenns. 6 0th o f thc5c n otalions .... ill b e used freely. 00 m. (, . (" a n GUME l - U T b"", " "noble M.p: flo, . nd on C)'Iinde1 t o SIIow Adjao:n, Sq,.arco 2_4 I , , , ,""" , , [" , , , 00 " 'JWo..lev<l Circuit Oprimizotioo 0 53 , Z OO\OJ , , " ', ," " , ,, , ,OJ ( oj o n GURt: 2 -iJ Prod""t Term, U.inK Four Min tenn. A four-square recJangie represen!:! " p roduct t enn t hat is tbe logical sum o f four mintenns. For tbe thr~e - ,'ariable case. such a p rod uct t erm ;s only o ne li tera l. As an e. ample. t he log~al , um o f the four adjacent m;nterms O. 2 .4. and 6 reduc"" to a ' ingle lite r.ltenn Z : " ' o+ ",, + m. + m o - XYZ+XYZ+XYZ +XYZ -- - -- XZ(Y + y)+XZ(Y + y) - XZ+XZ=Z(X+X)=Z T he rec t a~e for t m. product torm i~ shown in Figure 2-13(a) . Note that the prod uct t enn Z uses the fact that the left and right e dge, of the mop Ole a djacent in o rder t o form the recta ogle. Two o t her e .ample. o f r ectangle, c orre'ponding t o product t erm. derived from four m intenn. a re , hown in Fi gure 2-13(b). In general. a , m ore squares are combined. we o btain a product te rm with fewer literals. T hree -variable maps exhib it the following characteristics' O ne s quare represents a m intenn of t hree literals. A rectangle o f t wo squares represent' a p roduct term o f \ "0 literals. A rectangle o f four squares represents a product t erm o f one literal. A rectangle o f eight squar"" encompasses the e mire m ap and produces a fuoction t h.t is always e qual t o logic 1. These characterist ics are illustrated in Example 24 . ~:XAM Pl..E 2 4 Simplif)ing Th",,~- Variahle Function, . .i th M ap. Simplify the following two Boolean functioru;: F,( X,Y ,Z ) - 1m(3.4.6.7) F l(X. Y. Z ) - 1",(0.2.4.5.6) '$ The m ap for Ft s hown in R gure 2.14(a). There a re four s quare, mark ed with 1's. one f or each minterm of the function. Two adjacent sq uares are combined 54 0 C HAPTER Z I C OM IlIN AT10NAL L OG IC C l""CU 1TS , , ( .) F ,(X. Y. Z ) ~ l :m(J . 4. 6 .?) ~ Y7.~X 7. o ( b) F,(X. Y Z ) a l:m(O, 2 .4 . 5. 6) _ 7. ~ XV F lGUKE1 _14 Maps for E,,;.mple 2-4 in Ihe Ihird column 10 give a two-liter.llerm Y Z . T he r emaining t wo sq u .rcs with 1's are also a djacent by the cylinder-based definition and are shown in th e diagram with t heir values enclosed in half rectangle .. Wh en com bi ned. these two s qoarcl gi,'c the tw,,literal t e rm X Z . ' !l'e oplirni?.cd function t hus b ecomes F, YZ+XZ Th e map fo r Fl is shown in Figure 214(b) , Fi r$k wc i mmtdiately c< ,mbine t ht four a djacent squarc$ in thc first a nd last columns based on what we l earned from Figure 213. to give lho , i ngle literal term Z, Th e rema ining s in gle s qu.re r epre senting minter m 5 is c ombincd wit h an a djacem square that a lready i , being us<-'<l once. This is not only permissible. b ut desirable. $i n <;e tht t ", ,, adjacent square.; gi,'c t hc tw<c!iteral tcrm xl'. whilc the singlc square represents the lhreeliteral mi n t erm X YZ , The o ptimized function is F, _ Z + X Y O n occasion there aTC a llernat i,c ways o f c omb ining s quares t o p roduce e q ua lly optimized expressions. A n example of th i' is demonstrated in the m .p o f Fig ure 2 15. Min{errns 1 a nd 3 a re combincd to give {he term X Z. a nd mi merms 4 a nd 6 produce I he torm XZ, However. t here a re two "'3YS t h.t {he s quare o f min t erm 5 can be c o mbined "'ilh another a djacent <quare 10 produce a t hird twOlitcral lerm . C ombining it wi th minterm 4 gives the term X V; c ombining i{ i nstead with mi n{ erm I give~ the term Y Z. Each of t he two pos,ible o ptimiled expressio ns lis{ed in Figure 2- 15 has t hree terms o f two li terals each. s o l here a re lwO possible optimized SO lutions fOT this function . If a funclion is n ot expressed as a sum of mimerms. we can use the m ap {O o b tain {he m inlerms o f Ihe function and then simp li fy {he functio n. I t is necessary, h owewr. {o h ave {he algebraic expres,ion in sum-of-produc{s form, from which each p roduct term i , p loned in t he map. The mimerms o f the function a re {hen reud direc!l}' from the map. A , a n " 'Ample. cons id er t he Boolean function " ' .DIEiEJ[] XlmwcEl [ , } ; 00 o 01 11 10 FI G UR E l-i S F'\X. Y, Z) ~ 1 .,.,(l.3.4,5,6) - -- o n GU KE 21 6 F'\X. Y , Z) M 1 "'(1.2. 3,5,7) - Z + Xy - XZ + XZ + Xy - XZ+ XZ+YZ T hree p roduct t er m. in the expre,;s;on h",-c ,wo literals arid a re r epresented in a l hree-variable map by ' '''0 sq uares each . " \e two <quares c orresponding t o t he lin;11crm, XZ. a re fo und in F igure 216 from the c oincidence o f X (first fowl a nd Z ( two mi ddle c olumns), t o give , 's in !.quaTe! 001 a nd 01 L N ote I ha, w hen m ar ~ _ ing I ', in the s qua res. it is possible {Q f ind" 1 a lready placed I hc.e ( rom " p reced ing leT"' _T his h appens wilh the " ""ood term. X Y. which I's in s quares 0 11 a nd 010: but s quare O il i . CO m mOn wilh Ihe fi rsl (erm, XZ. SO on ly o ne 1 is m arked in i(. C o ntin ui ng in t his fashion. we find that Ihc fu nClio n h as five min terms, as irl dicated by Ihe 1\,'" 1', in t he figure. The m interm, a re r ead directly from the m ap t o be 1. 2. 3 .5. a nd 7. ' l1 ,e f unc tion a s originally givcn has fo ur p roduct tern,s. I t c an b e o pti. mized on the m "p to only lwO simp le t erms as h". F _ Z + XY g i"ing" , ignilicanl r eduction in the c ost o f imple mentatio n. F our -Variable Map T here a re 16 m inteTm, for four binary var iables.. and t herefore. a fo ",,'ariable m ap consists o f 16 " I uares. a s s hown in Figure 2- 17. 'l1,e m inlerm a ssignment in e ach " I " an, i, ind ic.led in p art ( a) o f the diagram , T he m ap is , e d rawn in (b) 10 ' how t he relalionsh ip o f t he four v ariable <- T he r o". . a nd c olumns a re n umbere d SO that only n ne bit o f t he binary n umber c hange. in ,'a lue betwee n any t wo a djacent columns o r rows, gua ranteeing the , ame p roperty for a djacent "IMre<- T he row and col umn number c orrespond, t o a two hit G ray code. a s i ntroduced in O tap ter I T he minte rms c orresponding t o e ach sq u are c an b e o btained b )' com bi ning the row n umber wilh t he col umn n umber . For e xample. w hen c ombined. the nu mbers in the Ih ird row ( II) a nd the s econd colum n ( 0 1) give t he binary nu mber 110 1. the bi n aT}' e qu ivalenl o f 13. 'IlIu,,- the sq uare in I he third row a nd second oolumn rep re", nlS minterm t n, ) , I n a ddition. e a ch v ariable is m ar ked o n the m ap to s how Ihe eight " I uarcs in wh ich it a p pears uncomplcmc ~t td . T he o t h . . e ight squares.. in "'"hieh no label i . indicated . oorresponJ t o I he v ariable bei ng c ompicmen led . T hu . W a ppears oomp lemenled in the first t wo r o". . a nd uncomplemented in the seoonJ t wo rOws. 56 0 C HAI'rER 2 I COMBINAllONA~ L OGIC C IRCUITS ., ., m, ., ., m, ., w ~ -" ., m" -" - " ~ -" - " w '!-z 00 00 "' " '" "' " '" , ") ( .) o FIGURE 2017 rour_Vari.ble M .p T he method used t o simplify four-variable functions is sinlnar to that used t o si mp lify three-variable funct ion!. Adjacent squares a re defined 1 0 b e s quare, n ext to each o t h er_ as for two- and three-variable maps. To show adjacencies De IWeen square!. the map of Fig ure 2-18(a) is drawn as a t oru, in Fi gure 2- 18( b), with Ihe top a nd b onom e dges, as we ll as the right and left e dgtt louching each other to show adjacent squares, For example_"'<J a nd " '2 a re two adjacent squares, as a re " '0 and m,. The combinations of s quarei t hat can b e chosen d uri ng t he o p timizalion process in t be four-variable m ap are as follows: O n e square A rectangle A rectangle A re.:taogle A recta ogle represents a m imerm o f four li terals, of 2 squares r epresents a p rod uct term of I hree literals. o f 4 squares r epresents a p roduct term of IWO lilerals. of II squares repre""nt. a p roduct l eno of o ne lilera l. of 16 s quare, produces a function that is alway. equal t o lo gic 1. , ;Z' w'x 00 "' " ', " 00" " , ,, "' ) w "" " " " , " '" '" , (. ) o , (0) f lG URE 2- 13 Four-V.riable Map: Fl., . nd o n. TOnI' to Show Adjacencies 2-I / T.....L nd Circui< O "om'lIoo" 0 57 N o o ther c ombination o f sq~aru c an be u ~. A n i merestinl p roduct l erm o f Iwo lil erals X 2 , i$ . how n in F i, ure 2_18. I n ( b ). wh en t he m ap i5 viewed a5 a t orus. the adjacencies o f the s quaru Ihal represe nl I hi. p rodu ct tcrm a rc d uro b ut in ( 8) these square5 are on t he f our COrnen o f t he map a nd app<=ar qui le r emoved fr om e ach Ol her. T hi' p roduct l erm i5 i mportan t to recall. since it i . o ften missed.lL al so " ' rYe' a . a r eminder 1ha1 I he left e dge a nd I he r ight e d ,e o f t be m ap a r e a djam . a . a re I he t o p e d,e a nd t he o ollom e dge. Th u ... in l ene raJ. reclang1e ~ on a m ap cross t he le ft a nd r i,ht e dges. t o p a nd b ollo m e d,es. or b olb. 1b.e neJCt examples s how tbe p rocedure for simplifying f ou.varia bl e B oolun f unction . . E XAMPLE l oS Simplif)ing a 4-\".riabl~ . u""tlon " jth a M ap Simplify the B oolnn f unction F( IV. X , Y . Z ) ~ 1 ", (0.1.2.4. S. 6. 8. 9. 12. 13. 14) l bc nUnlerms o f t he funetioo a re marked wilh \ ., in I be m ap of Fi ,ure 219. E ight s quares in l he lWO left columns are(JOltlbined 10 fo rm a r ectangle for l he OM li le ral l erm. Y.The r emaining t hree I 's c annot be _ IIbined 10 give a simpli6ed le rm ; r aIM. , l he y mU51 be (JOItlbine d I I!! t ....... o r rOU' square rectangle . . " "", l op t wo 1'$ o n Ihe ri&ht a re combined with the top IWO I 'J 00 t he left t o cive the term w Z . N ote again lhat it is p ermissible t o U$C Ihe $arne "'luare m or e t han once. We a re n ow left with a sq uare m arked wilh a I in t he thi rd TOw a nd fo~rl h co l~ mn ( min t erm 1110). Insl ead o f l oking tbis s quar e a lone. which will give a term o f four lilerals. we c ombine il wilh " 'IUlre. a lrud)' u$<Cd to form a " "'Iangle o f f our S<juarn in the I"''''' middle rO "" and the t wo end columns. giving t he telID x l' .Th e o pti mized e xpr essi on is I he lopc.ol $U rn o f t he three lel1l"ll: , w'I:- "' " '" ,, , , , , ~ , ,, , ~ , , , 00 00 o F IGURE 2 19 Map for E xomple 2S : F _ Y + if::! + x l' 58 0 C HAPTER 2 f C OMB INATIONAL L OG IC C IRCU IT S co A~r c ", " ', ' " OOcb ,, "' " 10 li t II I II , ,,- o n GuKE 2 1D Map for h 'mple 2,,(; : F - E XAMPLE 2-6 80 + BC +ACD Si"'plif)';nK 8 4-Vari~b'" t"nnclion . . i tb. M ap Simplif)' the Boolc"n function F " A BC+BCD " 'ABC + ABCD T hi. function has four variables: A , B, C, a nd D. I t is e xpressed in s u .... o f.product' form with thTec terms o f thTct Ji teT.ls each a nd One term o f four li1era ls.. T he area in the map covered by the function is shown in Fi&.u!.e~.2{J. E ach te rm o f t hree lit e ra l< is r epresented in the m .p by two $<juan's.. A 8 C is r epresented by $<j uarcs 0000 a nd 1)001. BCD by s quare. 0010 a nd 1010, and A B C by s quares 11))} a nd 1001. '11,c !Or m with fo ur l itua ls is m interm 0110, T h e runc~o-,,- i5 simp li fied On (he m ap by tak in g the l 's in {he four comers., {o give {he term B D , 11' is p roducl term i$ in {he ~me map l ocalion~ as Xl' in FI gure 2, 18. T he two I '!..il! t~c lOp rOw aTe combined wit h the two l 's in the b onom row to gi,'c {he term BC. T he rcmaining h i"-.squaTe 0110, is combined wilh ilS adjacent square, 0010, to give the term ACD. Th e oplimi7.ed function is lhus F .. B D+BC+ACD 2 -5 M Ap M ANIPULATION ""'hen oombining s quare, in a map, il is n eces",ry {o e nsure {hal all {he minterms o f {he fU ction ure included, A( t~e l ame time. it is necessary to minimize t~e n umber l1 o f l crms in the o ptimized function by a mi ding a ny redund.n{ terms whose min , terms are a lre.dy includ ed in o ther lorm~ In this = tion , we c onsider a p rocedure that assis{s in t he recognition o f useful pUl1cr n ~ il1 l he m ap, O ther {opics {o be 0 00, e r.d a re t he optimization of p roducts o f sums and thc optimization o f inoompletely specified func tion~ Ea $entl al Prime Impllc an ts T he p rocedure for CQmb ining " I u" res in a " ,ap m "y ~ m ade more s ystem.t'" i f we int roduce Ill e t erm. " implicant: " prime implicant," and "~ntial p .ime im plka nt ," A p rod uct term i , an i",plie,,,,, o f ,1 fun Cl ion if t he f unction h a, the value I f o. a ll m interm. o f t he product l erm, Clearly, all rectangle. o n a m ap m ade u p o f s quares CQntaining I ', CQrr~spond to implicant .. If t he r emoval o f a ny l iteral from an im plicant P r esult. in a p roduct l erm that is nOi an implicant o f tbe function , t hen P is a pri~ implloJm, O n. map f ot a n n ,,'aliable fUnc lion, the...,1 o f p rime implicant. c orre.pond. t o t he ...,t o f a ll rectangles m ade u p o f 2'" s q uaU'! __ containing I's (m ' " 0, l . _ n ). with e ""h rectangle containing as m any squares . . " "",ible. [f a m inlerm o f a fU<>clion is included in on ly o n e p rime implicant, Ih al prime implicant i5 said t o be ~sU"'ial . Thu . . if a squnre w ntain. ng a 1 is in on ly One . ecl angle reprecn\in8 a prime imp li cant, Ihen that prime im plica nt i , eo",nti.1. [ " Figure 2.15 on page 55. the te rm. X Z ar 'J X Z a .e e w,,,t ial prime implicanl" a nd t he l erms Xl' and YZ a .e nones5entia' prime implica;;t.. T he prime i mrhoanH o f a function .... /1 i>e obt.inL-d from a m ap o f the function as all possible maximum CQllectlon. o f 2"' "'1ua.eo CQntainin, n ( m - 0, I . .. . n ) t hat c on.,i tute rectangles. This m eanSlhal a single I o n. map rCpIl'scnl$ a p rime implicant if il is n ot ad;"","ntt/) a "y o the. I 's, T wo a djacent 1'1 form a . ectan gIe repr esenti", a p rin,e implicant, provided thai they a re n ot within I rectangle o f four o r more " Iuares CQntaining ] '. . Four l 's form a rectangle represc:J\ling a prime implica nt if t hey arC n ol wilhin re<: langle o f eight o r m o.e '"'luares comaining I '.. a nd s o o n. Each cSo$C ntia l p ri me implicant con lnin$ a t least one "'1u are Ih~t is n ot eonlain e(1 in any o lh er prime implicant. Th e SY$tem alic p rocedure for finding Ihe o ptimized expression f rom the map re 'l uires that we fir!t delermine .11 prime implicam . . Then, t he 0Il. im i7.ed expr",,oion ill o btained f.om the logical . um o f all I he ~ntial prime implicants. p lu. o the r prime impiicanl$ ncc<kd t o include remaining minternt'! n ot indUd<:d in the essential prime implicant .. l bi, p rocedu.e , ,',ll b e d arilied b )' examples. EXAM P LE Z7 Sim pli fia u ion U . in l PrilM lmplkM nlS C o n, ici er ' he mnp o f Fi gure 2 21. T here arc Ihree way. t h.t we cnn CQmbine fou r '"'lua rc. inlO . eclangle. . The pr od uct terms o btained from these combin Mio " , a re the prime implicnnlS o f Ihe functioo , A/), I ii) a nd AB. T he l eml, A /) a nd 8 0 a re essem ial p rime implicant . . bUI A 8 is nOI essent ial. Th is is b ecause minle. n1S I a nd 3 c an b e incllKled only in Ihe l erm A O,.ltd mlnle . ." " 12 and 14 can b e included only in ' he l eon 8 0 . B u t min term< 4 , 5. 6, I nd 7 a re each includc:d in lWO p rime implicants.QDC Q ( ...hleh is A A . .. the le on A8 II n ot a n e ssential prime impitcanl. [n fact. o nce the e _nt ial plime implkanu I re d IoIcn.lhe lrurd Icon i , not I Ided because all the m,nterm. a re already inCl1Kled in the essenlial prime ,mplicant . . The OIltim~cd e xpr . ... ion for Ihe function o f Figure 2-21 i . F =AD + /JD 60 0 CHAI'"TR 2 I C OMBINATIONAL L OGtC C IRCUITS ;R: " C 00 00 "' " W , "' ," '" o D FIGU RE l U Prime Implicant' for E. . mple 27: l iD , B D, and A B Simplifi<ation Via Es..,lItial ~,td NOII . .... nllal P rime I mplko"l> A s econd e xample is , hown in Figure 2-22. Th e function p lotted in p an (a) h as seven m intenn . . I f we t ry t o combine square., we will find that t here a re six prime implican ts. In o rder (0 o btain a minimum number o f terms for Ihe function. we must first d eterm ine Ihe p rime impUcants t hat a re essentiaL A , shown in p an (b) of t.!!<:... figure, the function ha, fo ur " ,sentia. prime implicant . . T he p roduct term A BC D is essemial because it i.!,. lhe onl~:..rrime img!icant that includes minterm O. Similarly, (he product .ermS B CD, A BC. and A BC a re essential prime impli. c ants because t hey are the only prime implicants (hat incl ude m imerms 5. 12, and 10, respoctively. Minterm 15 is in cl uded in l wo nonessential p rime imp li cant . . The o ptimized expression for (he function consists o f Ihe logical Sum o f Ihe four essen t;al prime implicanls and one prime imp li cant Ihat includes m; nl erm 15, E XAM P ll! 241 F ~ A BCD +BCD +ABC+ABC + [ A~D A BD c ru A';;( 00 C W , "' " , , "' , , , ," ,, 00 00 D (a) PI"" i". ,he m;n"",,,, o 01 11 10 00 , "' w L ..J,= D (b) Men,iol prime impticon" FI GU R E l oll Simplilkation wi th Pr ime lmplio.n" in Example 28 o 61 T he identification o f es.stntiaJ prime imp/ironlS in 1M m ap p .ovid" a n a ddi ti on al t ool ""hich shoW$ t he lerll1 tha t muSt ab5o!utely a ppear in e ,'ery $lI m..,' produ<:t. expression l or a fun<:lion a nd p ,O'<idei Bparl;.1 nruclure for a mOre ' ys' tema tic met hod for choosing patt erns o f 5Q uarelL Nonessential Prime Impllcants l kyond using all e ssential pri me i mplicanu. 1M folio..ing r ule c an b e _ppljc,d 10 include t he remain ing m inle""" o f t he f unction in nQf>C5Se nlial prime i mplicanu: S ekdioll Rule: Minimize t he C\'VerLap among JJrime implicanu as mIlCh as p ol- sible. In par1ic,llar. in Ill<! final solution, make W~ Ihal c adi prime implkllnl ~lectcd includts A lellS ' " "" minlerm DOl included in a ny Qlhe, p rime implicant $elected. t I n mOSt cases. t his .e.\l11S in a simpl ifi ed, a ah ou gi1 nOt necus arily minimum cost, $unl-<)f.produClS u pression. T he II $<: o f ' h I! $Clection rule is i IIu'trated in t he next exa mple. E XAM I' U: 1 ' Simp l;!)";a, _ . "un<1'o11 Ullin~ l he So:lecli"n R ule Find a s implified sum-of prodoCI$ form for FlA. B.C. 13.15). m - :!:m (0. 1. 2 . 4 , S. 10, ! l. The map for Fils give n in ~i8U"" 223, .... ich all p rime implicants J hov,,, . j i C i , t he o nly e ssenti.l p rime implicant. U ,i n8 the preceding selection rule. we can choo.se t he re ma;ni n8 p rime implicanrs f or t he lum.Qf.prodoclS f<>Tm in t he o rder indicated by the n umbe .... Note how th e prime im plican lS I a rid 2 a re s.c~cted in o rder t o i nd .. de " ,intc.m. wit bo m o>'c. loppin&. p .ime i ",p li cant 3 (ABO) a nd prime implicant BCD b oth i ndude the o ne r emaini n8 m inturn 0010. nd prime implican t 3 is . ." 't ily " "leeted 1 0 include the minterm and c omplete the sum-of products expression: f{A. B.C.D) - AC + ABO + A8C+A8 D D F IGURE 2 2J M . p for n .ln'ptc 2-9 62 D C HAPTER 2 I C OMBINATIONAL L OGIC C IRCUITS roduct-ol .sums Optimization The optimized Boolean functions derived from the m ap" in a ll o f the previous e .ample. werc expressed in sum_ _prod uCIS form. With o n ly minor modification. of the product_o{_sums form can be o blained, Thc p rocedure for oblaining an optimized expression in product-o{-sum, {orm {olio"" from toc basic properties of Boolean {u nct ions. The t ., ptaced in the squares of the map represent the mi nt erm. o f the function. T he m interm, not incl ud ed in the {u nction belong 10 the complement o f the (u nct ion, Prom this, we sec t h.l the complement of a function is r epresented in I he map by t he squares nM m arked by l 's- If we mark Ihe e mp ty s quares " ith O's and combine Ihcm into va li d rectangles. we o btain an o plimiled expression o f the complement o f Ihe function We tben take the complement o{ F t o obtain t he function F as a product of sums. This is d one by tak ing thc duol a nd c omplementing e ach literal. as described in Example 2-2 o n page 41. EXAM PL E 2-](1 Simplif)'ing a Product_of_Sum$ F o"" Simplify the following Boolean function in product_o{_sum, form; F (A. B. C. D ) - :im(O, 1,2,5, 8,9, 10) The \ ', m arked in the map of Figure 2-24 r cpresent the m interms of t he funclion, The squares marked with 0 ', represent the minterms not includ ed in F and t here_ fore denote the c omplement o f F Combining the "'Iuare, marked ..... it h O-s.. .....e o btain the 0plimized complemented fu nct ion F - AB+CD+BD Taking the dual and complementing each lit er"1 g ive, tne c omplement o f F Th i' i , F in p roduct-of-,ums form: D I 'IGUR 2 _24 Map lor Example 2-10: f - (A + B )( C + D )(B + D ) T he pre~;0U5 tltllmple shoW5 the procedure l o r obIaining the produCl.-;>f$u m. o pt;m;uu ion wh e n th e funClion is origina lly expressed a I a Sum Of mi nterms. The p rocedure i, alK> va lid when the funCllon i, originally expressed as a p rod""t of maxterro l5 o r a product o f Sum S. Rem embe: r th at the maxterrn nu mbe:rs a re t he same as the " ,interm numbe:1"l of the complemen ted function. SO 0 ', are entered in the map for the nla~tcrnl' o r for t he complenlcnt o f the function. To e nt cr a lun e-tion e ~ presoed ' " a p rod"" t 01 sums into the map. we take the compienlent o f the function a nd . from it. find tbe squares t o b e m arked ..-ith 0... f ur e umplc. the lunction F - (A + R + C)( B +D) c an be: p loned in the map by fil"lt o bta ining its c omplement. a nd tben markin, 0 ', in the squares representing the minterm s o f F. The remaining sq uare< are marked with I'.. Th en. comb in ln,the I 's gives the opli m i~ed u pres.ion in sum-of_producl5 form. C omblnina the 0 ', a nd t ben oomplemcn lO na , w.". the opIimiud expression in p roduct-ofsums form_ Thus.. fot any fUnclioo pIoned on l he map. " 'e can tlcrive the o plimized fU""lion in e ilber o ne o f the 1"'0 standard 'm = Dont-Care C onditions The mint crms o f a Boolean function specify a ll c omb,nat ion. o f varinble value. fo r whicb the fU nclion i . e qua l to 1. T he function is . ..umed t o be: ~ualto 0 fot lhe rest o f t he m lnterm .. Th~ a ..... mpl ion. however. is not al", a)... valid. s in t here a re a ppliouions in ",'hich lhe f """ ll oo is not 5p"l1ied f or c erta,n ,'ariable " al"" combinations. T here a re t,,o cases in which this o caITS. In t he f inl ca",. Ihe inpul combinalions never O<Ctlf.As a n e xamp".lhe four-bI t bonary code for lhe d m mal digil$ h. .. six combinalions Ihal a rc rtOl used and nOl e xpected 10 occur. In lhe second < :Me. l he i"pul combinati on s a rc . ~ pected to occur. but " ,e d o nOl c Ue " 'hI t he o utputs a re in re!pon se to these combination .. In both c ase" the OUlp"ts are said to btl u nspecitled for the in put c o mbina lion .. Function, Ihat h .ve un i pcr ifie<:J o utputs for some inpul c o nlbinations a rc ca ll ed j,,~oml'letely < no/fit'/ / 'lIIcrIOl". In p mOSt applicatIons.. we simply d o nOt ca re ",hat "allle i . a. . umcd by Ihe function for the unspecified minterms. For tbis reason. it is . u$lonlary t o call l h. unlp...: ifi cd minte rm< o f a funclion d on',.""" lYmditkm$. T he.., COfldilions ean ~ uoed on a m ap t o p ro'ide further simplilicalioo o f Ihe funclOon. I t should be leah ~ed Ibal a donl <.r. minterm cannol ~ m arked with a 1 o n lhe map. because thaI would rcqui", thaI the function Ilwa)... be: a I for such a minlerm. Lik e"' ise. pUllIng a 0 in the " "u",e r "'lu;"", the functioo 10 be: O. To distingui,h (he d on't<ore condition from 1 ', and IrS. a n)( i . used. ThUs. an X tnside a sqllar~ in Ih e mop indicale. Ihat we d o nOI Cltr. ",helh er the val ue o f 0 o r I i$ a. . igned 10 11 ,e (U II Cti011 for the part ic ular O1i 111 er nl. 64 0 C HAI'TEP-ll C OMBINATIONAL L OGIC C IP-CUrrs minter"", may be used. When simplifying function F, using Ihe I ', we can choose 10 include Ihose don'H:are m~lerm, Ihal gi"e lhe simplesl prime imp lican lS for F W hen simplifying function F using the 0 '., we can choose t o include those d on't care minterms t hat give the ' implest p rime implicant, for F, irrespe<:live of Ihose i nduded in the prinle i mplicant' for F. In both cases.. whelh er o r not the d on 't c are min terms are indu ded in the terms in I he final e xpre,,;on ;" irrelevant. T he ha nd li ng o f dOn'l c are cond il io n, i, illustrated in Ihe nexl example, E XAMPLE l-11 S implilkation . .-illt D on't C are Conditions To clarify the procedure for handling Ihe don' t-",,,e condition., consider t he fol lowing incompletely $re<' ified funclion F Ihat has Ihree don't-care mint erm, d: F (A,B,C,D) - :m(1.3,7, 11 , 15) d (A,B,C, D) 1 m(O,2,5) T he min terms o f F a re t he variable combinations thaI ma~e Ihe funclion e qua l to 1. T he mime rm, of d a re Ihe d on't -care minterms. The m ap o ptimizalion i , , how n in Fig ure 2-25, T he mintenns o f F are " ,",ked by I '.. those o f d are m arked by X'So a nd t he remaining ' quare, a re filled wi th O's. 1 0 get the simplified funclion in sumof-product' form, we m u,t include all five 1 ', in the map. but we m ayor may not i ndude any o f Ihe X'., M pend ing on Whal yields the , imple't expression for Ihe function, The term C D i nclude, Ihe four mimerms in lhe third column, The remaining mi nlerm in s quare ( )))l can be c omhined wi th s quare 00 11 t o give a three-l ileralterm , However, by including one or two a djacem X's, " 'e can combine fo ur s quare, inlO a rectangle to give a two-literal term, In p art (a) o f Ihe figure, don't-care minterm, 0 and 2 are included Wilh lhe 1's. which r .,ultl; in t he 'impli 6ed function F _ C D +AB m '?: 00 ' ' "00 , ", " '" ,, 00 ,," ,, "' " "' " ," ,"" " "" "" " " , " "" " " , " '" " " '" " " ( o)f - CO+AIl (b )F - CO+AD " A~ '," , ", " ', 00 o n GURE l -l5 E .amp le with Dont,Core Condition, In p an ( b), d on't """re mintenn lion oow is ~ " includtd with thc I '. . a nd the $implificd func- f - CD +AO Th e IWO e~prcssions r epresent t,,'o functions that orc al gebraica lt y unequal. Both include thc specifioo mintcrms of t hc origin al i nwmplctcly specified function, b ut cach includes diffcrcnt don't-<:arc mint tnnL A I far as t he incom pl cte ly specified function is ~nwd, b oth expressions a re actt~a ble l1te ooly differcnce is in tbe value Qf F fex the un~pecified minterms. I t is also JXlUiblc IQ o olain I n optiml2ed product-"Of-su lm C lpr$i<)O fex the fU netiQn o f Fi gu re 215. In tbis case. the way t o combine the O's i . to include d on'l' c are m imerm, 0 a nd 2 witb the 0 '. giving the o l'timi~ed c omplemented function Th king tbe r omplemcnt o f 101m: F &,vt$ t he o p limi'A:d u pression tn product-ofsums 11lc f ore.oin, c umpl c s hows thaI lhe don'l-care m imenn. in I ht m ap arc inilially considered lIS representing both 0 ~nd I . T hc 0 or 1 value e.'cnlually assigned depends o n Ihe optimi""tion process. Due 10 Ihi . rTOee sL the optimized runcrion will h ove" 0 o r I value for each minter", o f the originnl function, incl ud in g those Ibat were initially d o n 'l cafeL ThuL although ' he OUlputs in the in itiat specification may c on' ain X'. . ,Ite o utputs in a p anicu lar implementation Qf the spe.cification a re only O's a nd l's, 2 -6 M ULTIPLE-LEiVEL C IRCUlT O I >TlMlZATIO N A lthough we have found I ha' Iw o-Leyel circuil op,imization can reduce t he c os, of c ombinalional ' ogk circuits, there a rc o fIon addilional cost ..... i np _vollable b y uS in, ci rcui ts with more t ha n two level .. Such circuits a re r eferred t o as mulli ple_le.'e l circu i! L T he", savin gs a rc iIIu ~tmted by Ihe implementHtioll o f Ihe function G . . A BC + ASD + + ACF+ADF Figure 2 -26(.) &,"Q tl>e t",'O-level implementation o f G ""hicb h at B&ltcinput cost o f 17, N o . . suppo6c tha, . .-e _pply tl>e distrib\lli.'e l aw o f Boolean a lgebn IQ G 10 g. ..e G - AR(C+D)-f E + A(C+D)F This e quation &i.'e. the multiple-level implcmema!ion of G in FiS,,,e 226(b) which has a gale in pul cost o f 13, a n improvement o f 4 gale input . . In FlgUf c2.26( b), 66 0 C HAPTER 2 I C OMBINATIONAL L OGIC ClRCUI~ G '" "j 'OJ o F IGURE 2 26 M ullil'lc.U:vcl Circuit Example C ; D i , implemented twice. Instead. one implementation o f this subfunction ean h e s hored t o give Ihe CiTCUil in Figure 226(c) with a g ate in put cost o f 11. an improvement o f 2. T his c ommon usc o f ( C + D ) s uggests thai G ean " " w rinc" a 'S G " (AB+Af)(C + D)+e ThiS increases t~e cOOt to 12. BUI by factoring oUl A from A B + A F. we o btain G " A (B+f)(C + O) + e Flgur~ 226{d) g i,'cs the multilevel implcmenlation o f G using t hi s equat ion wh i c~ has a g ale inpUI coot o f only nine. is slightly more l han one half o f the origina l cos\. Thi. r eduction was achic,-~d by a s equence o f applic a tio n ~ o f algebraic iden. tilies at e ach SlOp o bsen-ing l he effect on lhe gale inpu t cost, Just as ,,ith the usc o f B oolean algebra 10 o bla in $ i mplifi~d twolevel circuit s. the p rocedure u~cd h ere is not p art icularly systematic. F ur lhcr. an algorithmic p r"""dure c orrespond in g 10 the usc o f Kama u gh maps for twole.'el circuit optimi zation lhat gi"es a n o pti mum circu il cosl d oes nol exist d ue to t he b roader range o f possible action, and the n~ rnb<:r o f SOl ut ions pos, ibk $ 0 multiple level o ptimization is b a",d on l he u"" o f a set o f l ransformations t hat are applied in c onju nction with cost evalualion t o find a good. b ut not neeessarily o pt im um s olution . In th o r ema in der o f t hi, section, we r onsider such t ransformations and illustra te their a pp li cation in r educing circuit cost . T he t ransformations. to 00 illustrated by Ihe n exl e xample. a re defined a s f ollow" 1, Factoring is finding a faclored form from e ither a sum -of-producls expression o r p roduct _of_sums e xpression for a function . D~coml'osirion is t he expre . . ion o f a function as a s et o f new funClion s. ) , Ex/rac/ion is tho expre. . io n o f multiple functions as a set o f new function s. 4, S "bs/irwion o f a function C i nto a function F is express in g F a s a function o f C a nd s ome o r all o f Ihe original variables of F 5. EliminMion is t he inverse of subst itUlion in which function C in a n expres_ sion for function F i , replaced by t he expression for G. Elim in ation is a lso called jlallening Or c o/lapring. 2, f :XAMPLE 2-12 Muhilevel Optimizatiou Transformations T he following f unct ions "'ill 00 used in i llumat ing t he transformation!: G =A C E +A C F + A D E + A D F + / JCD E F 11= A / JCD + A C E +A C F + BC E + BC F The forst t ransformation to 00 ill ustrated is factoring by us in g function G. Initially. we will 1001: a t algebroic jaclOring. which avoids axiom, that are unique to Boolean algebra, such as t hose im,otv in g t he c omp lement and i dempotence. Faclors can 00 f ound not o n ly for t he e nt ire expression for G. but a lso for its suooxpr"",ion s. For e xamp lc. since t he first fo ur t erms o f G all c ontain .' ar iable A . it can 00 factored o ut of thcse terms giving: In t hi' case. n ote t nal A a nd C E + C F + D E . . D F a rc factors. a nd B CD E F is not im'olvcd in the factori'!S operation . By factoring o u t C a nd D. C E + C F + D E . . D F ca n 00 wrinen as C ( E + F) + D ( E + F) whic~ Ix! r ewritten as ( C + D )(E .. FJ. Placing t hi' e~pre.si(>n in G givcs: C =A(C .. O ){E+FJ + BC D E F T he t erm B CD E F c ould Ix! factored i nlo product terms. b ut such factoring wi ll nOt red uce Ihe gate in pul count a nd s o i , not c ons id ered . The gate in put count for the o riginal . um -ol-products expression for G i , 26 a nd for the factored form of G is t8 . for a saving o f 8 g ate inputs. D ue 10 t he fa ctoring, there a re more gate. in , "ries from inputs to o utp ut s. a maximum of four level, i~stead o f Ihree levels including input i nverters This may result in an increase in t he d e lay through the circuit after technology mapping has oocn appti~d . 68 0 C HAPTDt 2 I C O,\IBIN ATIONAL L OGIC C IRCUITS !ft.e second Iranstormal!On t o be illuSiral ed i . decomposition which "IiOWll o pe ration. beyond algebraic {aeloring. T he {aelDred (orm o{ G can be wrillen as a decomposilion as folloWll: G =A(C +D)X, + BX , EF X , = CD X , .. E + F O nce XI " nd X , have been d e6ned.lhey can b e complement ed. a nd Ihe complemenlS can replace C+ D a nd E F. respeclively. in G. A n illuslralion o f Ihe substilution Iransformation i . G =A X , X, +8 X, X , .. C D X , _ E+F X, T he g ale inpul count l or Ihis decomposition i . 14. for a , "ving o f 12 g ate inputs from Ihe original sum-<>f_produclS expression for G, a nd o f 4 gale in puls from Ihe factored form of G. [n o rder 10 illustrate U l raction. ""e M ed 10 perform decomposilion on f I and exlracl c ommon subexpressions in G a nd H. FaclOring out B from H, we have H = B (A C D + A E + A .. C + C F ) D etermining addiliona[ facIo ," in H, we c an wr ile H = B (A (C D ) .. ( A + q (E + F )) Faclors X " X ,. a nd X , can now b e eXlracled t o o blain X, _ C D X , _ E+F X , =A + C and faclors X , and X , can b e shared between G a nd I I. Performing . ubstitution, we can wrile G and H a . G _ AX,X, + BX,X, H xB(AX, + X,X,) A logic diagram is giv en for Ihe original s um of.products in Figure 2-27(a) a nd for Ihe extract ed lorm in Figure 2-27(b). The gate input cost f or the original G a nd 1/ without shared terms. e ~ cepl for in pul invef\ers, is 48. For decomposed G and I I withoUI shared lerms between G and f l, it is 31. With shar ed t erm s. il i . 25 , cutting the gate input cosl in h alf. Thi. example il luslrate. the value o f Ibe transformations in reducing inpUl count cos!. In general. due 10 Ihe " ide range o f a hema l;"e solu ti ons and the complexily in , , delem,jning (he d j.,;..,... t o use in decomposition a nd .Xlroclion. obtaining truly optimum SOlution. in t ern" o f gate input count is usually not fea<ib le, SO only good soluti ons a re sought. The key (0 successful t ransformatioru; is t he d ctcnn inalion o f the 70 0 C HAPTER 2 I C OMIl INATIONAL L OGIC C IRCU ITS Ix, uscJ Jactors 10 1n J eeo mposldon or eXlracl;on and choice of the transformation sequence to apply. These dc>ci,ions are complex and beyond lhc s copt o f our study here. but are rcgula,ly incorporated inlo logic synlhcs is tools. O ur discu,;,jon thu, far has d eah only wil h muhilevel optimization in terms of reducing g ate inpul count. In a large p roportion o f designs. the le ngth o f lhe lon ge. t path o r p aths throu gh the circu it is often constrained due 10 the path delay. the length o f time it ta~ ~s for a change in a signal to p ropagate down a p ath through lhc gates. In such cases. t he number o f gates in series ma y need t o be reduced. Such a red uct ion using the final transformation. elimination. i, ill ustrated in the fo ll owing example. E XAMPLE 2-13 E umple <;fT",nsr<;nnati<;" fo. Delay Reduction In the circuit in Figure 2-27(b). lhe p aths f rom C. D . E. F and A to H "I I p a" t hrough four 2-input gate . Assuming th at all multi .input gates c ontr ibute the Mme delay 10 t he p ath. a d el"y g reater th an t hat c ontrib ut ed by an inverter. these a re t he longest delay p aths in t he c ircuit. D ue t o a specification On maxi_ mum pa th delay for the circuit. these p aths must be s hortened t o a t most t hree multi .input g ates o r t heir c quivaknt in m ultiinput gates a nd i n,wter delays. T hi. p ath , horlcning , hould b e d one with a minimum increa,~ in gat~ i nput c o unt. T he elimInation transform which replaces intermediate ,'ariabtes. X h with the expres.ions on their right hand sides o r removes o t her factoring such as thm of variable B is the m""hanism for r~ducing t he number o f gates in series. To d eter_ mine wh ich factor o r combination of factors shou ld b e eliminated, we need t o look a t the effect on gate input count. T he increase in gate in put count {or the combin a tions o f e li minmions thm red uce 1he problem p ath lengths by at least o ne gale are of i ntere,t, Ther~ a re only three such combinations: e li mination o f the faclOrin g of B. elimination of intermcdime variable, X" X l. a nd X ,. and elimination o f the factor B a nd the three intennediate variables X ,. X ,. a nd X l' The respective gate input count increase, {o r these action, a re O. 12. and 12. resp"C1i"ely, Clearly. the removal o f lhe factor B is the best choice since the gme input count does not increase. This also d emonstrates t hat. d ue to the additional decomposition o{ H. the g ate i nput ro:o;t gain o f 3 that occurred by factoring out B 31 the beginning has disappeared. Th~ logic diagram resulting f rom elimination o{ the (actor B is given in Figure 2-27(c). While t he neces",!), delay reduction was o btained by " sing elimination to reduce the n u mber of gates along the palhs in Example 213. in general. such a g ate reduction may not reduce delay. o r may e ven increase it due to d ifferences in the dela)' characteristics of lhc gales t o be discu!Cd f unher in G ap ter 3. 2 -7 O THER G ATE T YPES Since Boolean functions are c xpre=d in terms o f AND. O R. a nd NOT operations. it i , a ' traightforward procedure 10 implement a Boolean fu nction with AND. O R. and N OT gales. We fi nd . however. that the possibility o f consid~ring gates wi th o ther logic operation, is o f considerable practical interest. Factors t o be t a ke n i mo consideration when constructing other t ypes o f g ates arc the feasib il it}, a nd eoon o my of implementing the g ate with electronic c omponent'" the ability of the gate t o implement Boolean functions alone o r in oo njunction wit h o ther gates. and the oo n\'enience of represent ing gate functions thal are Irequemly used. In this section. we introduce these o ther g ate types which ar~ used t hroughout the rest o f the text. Specific t e chn iques l or inoofporating t hese g ate types in circuits are gi"en ] fl section 3-5. The graphics "YTllbob and truth tabtes o f six logic gate types are shown in Figure 228. ",-;th six additiooal gate types gi,'en in Figure 2-29. 'The gates in Figure 2-28 are referred to as primili"~ gates. and those in Figure 2-29 are referred to as <'omple.. gat es. A lthough t he ga te s in Figure 2-28 are s hown with just two binary i nput variable . X a nd y, a nd o ne o utput b inary v ariable. F. ""ith t he e xception of t he inv erter a nd t he buffer. a ll may have more th an two inputs. T he distinctively s haped s ymbol. shown. as well as r ectangular symbols not shown. arc specifi ed in detail in the I nstitute 01 Electrical a nd E lectronics E ngineers' ( tEE E) Sum , /a,d G'aphic SymboL, / 0' Logic Func{io"s ( IEE E S tanda rd 91-1984). The AND. O R. a nd N OT g ate, were defined previously. T he N OT c ircuit i nyerts t he logic sense o f a b inary signal t o p roduce the complement o peration, Recall th at t his circuit i . typica ll y called an ;,,,,en,, r ather t han a N OT g ate. The sma ll circtc a t thc o utput of the g raphic symbol of an i n"erter i , formally called a nega_ lion indica/or and d esignate. the logical complement, We informally r oler 10 t he n egation indicat or as a " bubble." The triangle symbol b)' itself d esignates a buffer circ ui t, A b l/ffe, p roduces t he logical function Z ~ X , , ince tbe b inary value of t he o utput is e qual to l he bioary value o f the input. This circui t i . used p rimarily to a mp li fy a n electrical signal to permit more g ates t o b e a tlached t o the o utp ul o r t o d ecrease the ti me it l akes f or s ignal. t o p ropagale t hrough the circ uit The J state b uffer is unique in t hat outputs of 3-state buffers can be con nected together provided that only one of the s isnat, on their E in puts is I a t any given ti me. This type o f buffer and its basic use are discussed in detail later in Ihis section. The N AND gale represems the complement of the A ND o peration. and the N OR gate r epresent. the c omplement o f the O R o peration . Their respective names are abbreviations of N OT-AND and N OT-OR. rc \peCliv~ l y_ T he graphics symbols for the NAND g ate and NOR gate oo nsist 01 an A ND symbol and an O R symboL respectively, wi th a b ubble o n the output. d enoting the complement o peration. !n c omemporary integrated circuit t echnology, N AND and N OR g ates are the natura l prim it ive gale function. for the simplest a nd fastest electronic circuits. 11 we considcr the inverter as a d egenerate version 01 N AND and N OR g ates wit h just one input. NAND gate. a t"ne or N OR g ate. alone can implemem any Boolean fu nclion, ThUs, l hese gate types arc much more wiMly used than A ND and O R gates in actual logic circ ui ts, As a oo nsequence. actual circuit imptementations a r. o ften d one in terms of l1>osc gate types. 72 0 C HAI'TER 1 / C OMBINATIONAL L OGIC C IRCUITS o ... pf,;';" Srm Ooi . N .m< AI!;<b<.;c , hap" "D D iot;r."j" < quo'''''' T,.'" ,,~ , H , , ) -, f - XY "" " "' " " "" , H 0' :=D-- f f _X. Y "", " , "" " 1'101' ( ;,,"',,) R ulf ) S, ,, . Bulf., N AND N OR , -{>O- , F_ X ' -t>-' F_X f",fi", , f",fi. ,. " "' , "" " " : =ifF H iZ HiZ ", " , , ?- ' : =Do F F _ X:V F_ I I.GUkE 228 Primitive Digit. l Logic Gote< x :;:y "" "" ' " ", ", "' " "" " CO "" 2_7 I O ,her G are1fp<. 0 73 O",phic>S),mOOb A ll"bnic eq uatIOn , , "" , "' , "" , ", " , "' , H E mu,ive-OR ( XOR) ~ =D- F F ~ X Y+XY f udII"ve-NOR ( XNOR) ~=D-F F _ XY +XV ANOO~I)<VE~T I ; 0- , w - 5:$V . " w (AOI) - Xe y , F ~ W X+ YZ ~ O R ANO INVERT ( OA I) F ~ ( W + X)(Y Z ) AI<DOR ( AO) O RAlm ( OA) F - (W+ X XY+Z) o F I GU RE: 229 Comple .. Digital Los"' Gotes A g ate Iype Ihat alone Can b e used t o imp le ment all Boolea n functions i5 a universal 8a/~. To s how the N AND gate is a u niversal gate. we need o nly s how t hat the logical o perations o f A ND. O lt . a nd N OT can M obta j n~d wit h NAN D gates only. This is d o ne in Fig ure 230. T he complement operation is ob t 8in~d from a o ne input NAND gate oorr~spo nd s t o a N OT gate. In fact, the o ne input N ANO is a n in valid . y mbol a nd is replaced by the N OT sy mbol . as shown in the figure. T he A ND o peration req uires a NAN D gate followed by a N OT gat~. Th~ N OT in'~rts th~ outp ~t o f t h~ N AND giving an A ND O p' ration as call~d '4 0 C HAI'TER 2 1 C OMbiNAT IONAL LOGIC C IRCum A~D : = :C:::)- --{[)o---- o XV - XV F I GU R El.)O L.op:al Operal..,.., ... " h NAND G ., . . Ihe resull _1lt.e O R o peration is a chlt\'cd using a NAND gale wilh 1'IOTs on each i nP'll When I kMorgan' , Ihe(>fem 1:1 applied as shown in Fi gure 2':lO, Ihe in ~e ... s iom ( a""" l a nd a n O R fu,ltIion rt'Sutlt. -n.e exe)",iveO R (XOR) galC s ho.... n in Figure 229 is . imilar 10 lhe O R gale, bUI e~dud." ( has Ihe value 0 for) Ihe oombinalion .... ilh b olh X and Y equallo I. The graphiC'! symbol for Ille XOI{ ga le i. simi lar 1 0 Ihal for Ihe O R gale, CX'"'PI for Ihe a ddilional cu ,wd line On Ille inp UI s. The u cl",i'eOR has Ih e special sym bol @ 10 designate il s operalion, Th~ cxcl u\i,-e- NOR is the complement o f the exdusi,'e-OR, as indicalcd by Ih ~ b ubble al Ihe o u tpul of iIS g raphi'" symbol. T he A NOOR .1NVEIfl' ( AOI) gale forms the complement o f a sum nf prooucts. T he are many different AND OR INVERT gales depending on the num b er o f A ND gatCS a nd the numbers of input. t o each A ND and d irw ly t o lhe O R &ale. For e umple . ufl'PO$C th . . t he (uncl1 on implemented by an AO I is F - XY + Z T hi. AOI is referred t o l IS. 2- 1 AOI sin<:e il consiSIS o f a 2.inpul A ND . nd I tOp.>1 d"~l y 1 0 Ihe O R g al e. If Ihe funelion i mplc_nled is F - TUV"' II'X + YZ I hen t he A OI is c all ed a 322 AOI. The O RAl'.'D-11'IVERT (OA I) is I he d ual of t he AO] a nd i mplcn,cn" t he c omplement of a pTOdUC I.of-. um. form, The A ND O R ( AO) a nd O R-AND ( OA) I rc ,"eroion, of the AOI a nd O AI ",i!hnu! !he complement_ In general . complex ga l~ i ~re u ~ d 1 0 reduce Ihe circuit c omplexi !)' needed for implementing specific Uool en n function. in ocdcr t o reduce inlegraled c ircuit COi5t. In addilion, they reduce II,e time required for s ignal. 1 0 p ropagate t hrough" circuit. & CMOS CIIICUlT'S Th i. s upplemenl, ,,-hleh d iscu...,. t he I mplementation o f b o th " ICI "",Ih CM O S lechnology. i vailable o n Ihe C om p anion Web5ite f or I he I n! . ~ [lfimitive a nd rompk~ 2 -8 E xCLUSIVE- OR O PERATOR A ND G ATES In addition t o the e~c l us i .. e OR gu te shown in Figure 2 29 . there is an exclusive O R o perator wit h its own algebraic identities, The exclusive OR ( XOR) , d enoted b ye, i s. 10gic.1 o peralion t hat performs the functi on X Efl Y=XV + XY I t is equal t o 1 if exactly o ne input ,.,.riable is equal to L Th e exci usive NOR.. also known as the .q,,;v~len"", is the complement of the e xclusive -OR and is expressed by the funct ion X $ Y - XY + X Y I t is equal to I if both X a nd Y are equal t o 1 o r if both are e qua l t o 0 , The two funClions can be shown to be t he c omplement of e ach o thcr , either by meanS o f a truth tahlc or, as fo ll oW$, by algebraic manipulation: X $ Y - XY + XY - (X + y )( X + V ) _ X Y + XV The follOl"ing identities apply to the excl usive O R o peration: X $O = X X$ ! = X X $X= 0 X $ X= ! X $ V - X$Y X $ Y - X$ Y A ny o f these idcn tilies Can be wTirocd by using a trulh table or by replac ing the e o peration by it s e q ui valent Boolean expression . I t can a lso be shown that lhc exclusi,'e OR o peration is both comm Ul ative and associati"e; that is. A Efl B - B Efl A (A $ B) $ C = A $( B $ C) = A $ B $ C This means t hat the t wo inputs to an exclusi,'e OR gate can be inte rc hanged wit h o ut affecting t he o peralion , It also means {hat we can evaluale a t hree-variable e xclusive -OR o perat ion in any order. a nd for l hi' reason. exciusive -ORs with three OT more variables can be e ' pTesscd witho ut parentheses. A t wo-input e xclu sive -OR funclion may be constructed with c om'ent ional g ates Two NOT g a t es . t wo A ND gates. a nd an O R g ate are used, T he a "ociativ ity o f the e xclusi"e -O R o peralor suggests the possibilit y o f excl usive-OR gat es with m ore than two i nputs T he exciusive OR c oncept for m ore than two var i abies. howevcT. i. replaced by t he o dd function to be d i.cu.sed next , Thu . t here is n o symbol for exclusive-OR for more t h n two inputs By duality, the exclusive-NO R is r eplaced by the e,'en fu nc tion and has n o symbol for m Ore t han lwo inpUls. 76 0 C HAPTER 2 I C OMBINATIO:-lAL L OGIC C I R CU ITS O dd F unction T he e xdusi,'e-OR o peration " 'ith three o r more variables can be conven ed i1110 l UI ordinary Boolean function by " 'placing the Ql symbol with its equivalent Boolean expression. In partiClllar. the three-variable ca se c aJI b e converted t o a B oolean expression as follows: X !ll Y$Z - (XV+XYjZ+(XY r XV'j Z - XYZ+XYZ+X Y Z+XYZ l be Boolean expression dearly indicates that the threevariable u d",,;veO R i . equal t o 1 i f only one variable i , e qual 1 0 1 o r if all t hree ""riables are equal 1 0 L H ence. where8$ in Ihe two-variable funclion o nly one variable need be equal to 1. wilh t hree o r more variables a n o dd n umber o f variables mU>t b e equal t o I . A s a consequence. the multipl e" 'ariable u clusive-O R o peration i . defined a, Ihe o dd " 'nc/ion, In fact, s trictly speak ing , this is Ihe c orrect name for the El o peration with Ihree o r m ore variables; the name "udusivcOR~ is applicab le 1 0 the case with only Iwo variables. T he definition o f tbe o dd function can b e clarified by plolling l be function on a map. Figure 2-31(3) $ho"'' 1l he m ap for the t hrec-,'ariable o dd function. The four mimerm, of Ihe function differ from u cb o ther in at least two l iteral, a nd hence cannOt b e adjacent o n the map. T hese m illienn, are . aid t o be distance lwo from each o tber. The odd funct ion is identified from the four minterms wh()5e b inary val_ ues have an o dd n umber of 1 '" T he four-variable case is shown in H gure 2-31(b), T he ~ight minterms mar~ed wilh I's in the m ap constitute Ihe o dd function . Note the c huacleristic p anem o f the distance between the \ 's ill the map. I t should be mentioned I hatthe minlerms not mar~ed with 1', in the map have an even number o f 1's a nd c on'litute the complement of the o dd functiOfl, called the e .'m fWV::lion. T he o dd function ; , i mplemented by m UnS o f two-input u clusi"e-OR gates, as , m ;}:oo 00 ", " ', ' " , , "' , ,, ", , '" , ( b)A$B$C$ D o F IGURE 2-3 1 . \laps for Mult iple- Variable Odd Fuoct ion, 2 _9 f H i gh-lmp<d.m o ..'pu" 0 77 ) -- c (0) P - X (j)\'(j)l o (b) C _ X (j) Y (j;> Z (j;> P F lGURE:.32 Mul<iple. lnput O dd Fu",,;OIU s hown in Figure 232, T he even function i , o btained by replacing the outp ut gale with an exclusive.NOR gate. 2 -9 H IGH-IMPEDANCE O UTPUTS Thus far, we have considered gates that h a\'e o n ly o utput values logic 0 a nd logic I. In this section, we introduce two importanl structures. tbree-state buffers and transmission gOles, that provide a third o u tput \'alue r eferred to as (he high;mfNd a na .tat~ and d enoted by Hj Z Or just plain Z o r z, T he H i-Z value behaves as a n o pen circuit, which means that, looking back into (he cir~ui(, we find thai t he out put a ppears to b e d isconn e<;tcd , High impedance outputs may a ppear o n any gate. but h ere we restrict consideration t o t wo gate structures with single data inputs. G ates with Hi Z output val ues can have 1heir OU1PU1S connected together, p rovided t hat no two gates drive the line a! the same time t o o pposite 0 and 1 values, In c ootrast, gat es with o n ly logic 0 "Dd logic 1 OUlPU!S c annot h a"e t heir oU!pU!s connected loge!her, Thru- Sla'~ B uffen T he 3-state buffer W", i ntroduced earlier a . o ne o f the primiti,'e gates. As the name implies, a three_state log ic output exhibits three dis tioct states. Two o f the "states" are the logic 1 and logic 0 of con"enliODallogic, The third "Slate" is the H iZ value, thai , for t hree-state logic, i. referred to as t he l IiZ sla/~, T he graphic symbol and truth table l or a 3-sta1e bufler arc gi.'en in Figure 2 -33, The symbol in Figure 2-33(a) is d istinguished from t he , ymbol for a n onna l buffer by the enable input. EN. e ntering the bottom of the buffer symbol. From the trulh lable in Figure 2-33(b), if E N - 1, O UTi. e qual t o IN, b eha\'ing like a n om,al buffer, B ut for E N - 0, the output value is h igh impedance ( lliZ), regardl~s o f t he value o f IN. T hree-state b uffer o utputs can b e connected together t o f onn a muhip l e~ed o utput lin e, Figure 2-34(a} sbows two 3 'tate buffers wi th t heir outpUtIl connected t o lorm o utpm line O L. We a ,e interested in lhe oU!put of t his structure in t enns o f the four i nputs E NL ENO, I NI. a nd lNO. The oU!put behavior is given by t he truth table in Figure 2-34(b), For E NI aDd ENO equal 10 0, both b ull., oU!puts are Hi -Z, SiDce b oth a ppear a , o pen circuits, O L is al<o an o pen circuit, repre~nt ed by a l li _Z value. For E N! _ 0 and ENO _ I . the o utput o f the lOp b ufler is INO 78 0 C H APTER l I C O.'lIJINATlONAL L OGIC c n'.CUITS o X I liZ ( .) J..ot;< . ym bol o f IGURE 2 jJ Thrce . . ote Bu ffer " ' -- (5) r--- -~---- ----- E N! _--,-~ vr ( .) J..ot;< D iog.., '"' '"" I N I IN. , "' """ (S)O(~)l , ", , ,,," , , " , , , , " " , , ,, , , , , ,,, ~ " H i Z ( b)T"' L llObl< h o FlGURF. 2 M Thr " l.tc BuflerS r'Ol"ming a Multiplexed Line O L a nd the o utp ut of bottom buffer is H iZ. Since the ,aluc o f I hD c ombined wi th an O p'n circ uit i$ iuu //'.'0. 0 1. has value I I\D. giving th~ s econd a nd third rOwS o f the (ru(h table. A c orresponding. bur opposite. case occurs l or E N! - 1 a nd ENO - O. s o 01. h as value IN1. giving t he fOurlh and fiflh rows o f (he truth l able. For E NI a nd ENQ b olh 1. Ihe situation i . more complicated. I f I N! _ INO. t hen their m utual ,aluc a pp'arS at O L. Bul if I NI "" INO. then their v alues connic. a t t he o utpur. T he COIlfticl r esuhs in an electrical c urrenl ftowing from lhe buffer ourpur Ihal is 31 1 inlO t he buff~r o ut put thai is at O. T his c urrenl is often !arg~ c nn ug! ' t o 2-9 ( High_lmre4mc<> O u'P"" 0 79 c ause healing a nd m ay even deSlroy Ihe circ uil. as symbolized b)' the " smoke" ioons in t he t ruth table. a ear ly, such a s it ualion m ust ~ a voided , The d esigner must e nsure t hai ENO a nd E N l ne,'er e qual I at the same lime. In t he general case. f or" 3-'tale b uffers a nached 10 a bus li ne. E N Can e qual I for o n ly o ne o f Ihe b uffers a nd must be 0 for t he r e,t. O ne way 10 e nsure this is t o Use a d ecoder t o g enerale Ihe E N signals. For the two-buffer case, t he d ecoder is just an i nverter with select i nput S. as s hown in d oned lines in Figure 2-34(a), I t is imeresting t o exa mine the t ru th table wit h the i nverter in place, I I con siSIS o f Ihe shaded area o f Ihe table in Fi gure 2-34(b). C learly. t he YIllne o n S selects b et"'een inputs INO a nd I N I. Further. Ihe cireuit o utput O L is n ever in the H i-Z state. T rans",;",;on GDfeJ I n integrated circuit logic. t here i , a C MOS t ransi stor circuit logic that is i mportant enough 10 b e s epara tely r epresented at the gate leveL This circuil. called a t r""s",;"io,, gale ( TG). is o ne form 01 a n c lecITonic sw it ch for connecti ng and disconnecting two points in a circuit. Figure 2-35(a) sho"'~ t he IEE~ s ymbol for t he Iransmissiun gate. I t h as f our external connections o r p orts. C a nd C are the control inputs a nd X a nd Y are t he signals 10 be c onnected o r discon nected by Ihe TG. In Figu Te ~-35(b) a nd (c). t he switch model l or t he u a nsmission go te appear>, I f C - I and C - O. X a nd Y are c onnected as r epresented in t he m odel by a ""cl osed'- switch and signals can pass from X to Y o r from Y t o X. If C = 0 a nd C = I . X a nd Y are d isconnected as represented in t he model by a n " open" switch a nd signals c annot pass b e tween X a nd Y. tn normal u se. the c ont rol inputs a re connected by an invertor " ' s hown in Figure 2-35( d ). s o t hat C and C are t he complements o f each o t her. To i\tustTalc the use o f a transmission gate. an exclusive-OR gate constructed from two transmission gates a nd t "", im'crters is shown in Figure 2-36(a) , Input C con_ trols the paths through t he transmission gates, a nd input A provides t he output for F. If input C is equ al t o I . a path e xi'tsthrough t ran,mission gate T OI connecting F t o A. a nd no path exi'ts Ihrough T GO. [f input C is equal to O. a path exiSls through TGO connecting F to A . a nd no path exi,ts througb T O 1. ThUs. the output F is oonnectcd t o A . T his results in t he exclusive-OR t ruth lable. as indicated in FIgure 2-36(b) , , , , -, " C _ lanJC _ O '-$-' ,., c ' 'l , ro X _______- :::- y C _ O.nJC _ 1 ,,' c (0' o ! 'IGURE 2_J5 Tran,mruion Ga'e (TG) 80 0 CHAPTER. 1 ' CO MIIINA110NAL LOG IC CIRCUITS , 2 -10 '" ' CA N opo.h P .,h P .,h ~opo.hl N opo,h P .,h , " r.. , ,.) o .". H N OPl.h 0 b ( 0) fII GUJlIi: 1-36 nan",,"""" Gat. ~,..;"" O R C HAPTER S UMMARY l lIc p rimili". lock o pc:r"ions A ND. O R . and NOT define Ihro. p rimil;'. logic c omponents called gates. from which digilaJ .yolems are implemenlcd. A Boolean algebra defined i n l erm! o f lhese opera.ions provide t ool for manipulating Boolc~n funetions in designing d i,itallogic eiKuits. Mint erm and , "u.erm Sta n d ard form, correspond directly t ruth tables f or funetion .. n ,cse st.n<lord forms c~ n b e m anipulated into , uOl of.product a nd producl. o(-I UIi IS forms., which correspond to two lcvel , ate circuits. TWo eost mcasures t o be " 'inimi,cd in optimi"ing a circuit are the n umber o f i nput literals 1 0 t he circuit and the tOlal number o f inputs to the gatCS in the circuit. K _m aps with tWO 1 0 f our va riables a rc an effective . lternalive t o a lgebra,e manipulation in o ptimiring small circuits. The$e maps can be used 10 optimize sum-of-producl$ forms, p rodutt -of_. um. for m . . a nd incompletely ipecified functions with d on'H:a re c ondit ions. n ansfornu f or optimizing multiple 1e,,,1 circuil$ " ',lb t bree o r m ore l eveh o f gating a r. illu.1rated. The primitive opc:ntions A ND Bnd O R afe DOl d irlly i mplemenled by p rimiti'" logic clements in the mOSt p opular logic family. Thus, NAND a nd N OR primitiv.,. ' " well as r omplcx , .tell t h., im plement lbese fami li es arc introdoced. A m ore complex primitive. the u clusive-OR. 11$ ,,'ell 8 $ ito CQIIlplemcnt. the excl usive-NOli. . arC presented alOft, with their mathematical p . opc:.ties. .0 R EFERENCES t . BooLE. G. A n Im'u/igarion o f/he Laws ofThoughr. New Yo rk : [)ovcr. ISS4. 2. K A RNAUGH, M . ~A Map Method for Synlhesis o fCombinal ional J.o&k Circull5.~ n"""""Uons o f A lEE, CommunictJrion " nd El'To"i(l. 12.l'r1 I (Nov. 1953). 59399. 3. D'EnlEYER, n L Losic 1RJ.8'" o f Digum Sy~r.mu; 3rd ed. 8Qston: Allyn Bacon. 1988. 4. M.... No, M. M. Do"giml DMign, 3 rd c d U pper S addle R iver, NJ: Prenlice H all. 2002. S. ROTH. C H . F",,,jamenlOl. o f L ogic Design. 41h c d . Sl. Paul: We~1. 1~2. Ii. H ... YES. ). ]> ' ''''od" c/ion 10 Digital Logic Design. R eading, M A : A ddi",n We sley. 1993. 7. W ... ~ERLY. J . F. Digiml Design: Principles a nd PmC/las, 3 rd e d . U pper S addle River, NJ: P rentice Hal), 2000. 8. G!lJS~I. D. D. P'inciples o f m giml Design, U pper S addle R i'er. NJ: P rentice H~II. 1~7. 9. / E EE SWI/da ,d G'''I!hiC Symbols / 0' Log;c Fimelion.<. ( l nclud Cll I EEE S td 910 -1991 S upplement a nd I EEE SId 91 _19&4.) New Y ork:The Inst itute o f Ele.:!ric.,t and E lectronics Enginee~ 1991. P ROBLEMS d'.!;;.. The plus (;.) i n dic~tcs" mor e advanced problem and the asterisk (0) ind icales a ~ solution 2 - 1. is a vailable o n Ihe C ompanion We\>sil e l or Ihe l ex!. D<:mon,trate by m ea"" o f Irulh t abl", Ihe validilYo f l he following ide 1lt ilies: t a) D eMorgan', theorem r or t hree variables: X YZ - X + y ;. Z t b) T he "'-'Cond d i'lribmi"e law: X + Y Z - (X;' Y )(X + Z ) -----(e) X Y;' Y Z ; 'XZ - XY+ Y Z + XZ 2 -2 . ' Prove Ihe idenlity o f each <or the '<ol)<owing atgebraic man iputation: Aoote~n e quation s, usmg (M) XY+XY+XY _ X;.y (b) AH+RC +AII + HC _ 1 ( e) Y + X2+ XY _ X+Y+Z - -- - --- (d) XY + YZ + XZ + XY ~YZ - XY + XZ+YZ 2 -3. +Prove Ihe identilY o f each o f t he followi ng Boolean e quation s. using algebraic manipulalion: -- ta) A B + BCD + A B C + CD - B + C D ( b) W Y + I VYZ + W XZ + W Xy . . W Y+ W XZ + XYZ +XYZ (e) A C +AB + B C+ D _ ( A + B + C + D)(A + H + c+ 'OJ 2---4. + Given Ihat A B _ 0 a nd A + I l _ I . use atgebraic m .nipu l.tio n t o p rove t hm (A + C)(A + il)(1l + C) - /JC 2 -3. +A s pecific B oolean a lgebra wilh j u,t IWO element< 0 and I has been us-ed in thi s chapler, O ther B ool ea n atgebras can b e d efined wilh m ore I han two e lements by using c lemenls t haI c orrespond t o binary 'Iring"- These a lgebras r<orm the mat he malicat foundation ror bitwise logical o peralions 82 0 C HAPTI;R I I C OMUINATIONA L L (x; I C C I R CUIT'!! Ibal ....e ....ill ~Iu d y in C haple r 1. S uppose Ibat Ih~ S lnni' a~ e ach. nibble (h.alf o f. b yle) Qf {Qur bits. T hen Ihere a re 2", ' " 16. elemenl5 in I h. l itebra. w bere a n e l._nl I j , Ihe 4-bit nibble in bi nary rorrcspoo;1ing IQ I in decimal. S"...,d ()fI bilwise applicaliQn Qf l b. I....o -elemenl S oolun algebra, define n cb Q ( Ihe follo"'iog for Ihe new algebra S () t hat the B oolean ide nt ities b old: (a) Th e O R o pcrationA I /J for a ny Iwo elem ent. A and 8 (b) Th e AN D o peration A B for a ny two clemenlSA a nd H ( t) T he e lement Ihat acts as the 0 ( If I h. a lgeb. . (d) The e leme nt Ihal acts lIS the I f"!.,.liK algebra ( e) f ur any element A, lhe e lement A , 2-4. Simplify I he fQllo-Aing S oolun npreosi<>ru; 10 cxprCS5lons t ontaining a minimum number o Ili lerals: ( a) A C + ABC + HC (b) (A + B)(A + Ii) A OC+AC B C+B(AD + CD) ( e) (B + C + B C,(BC + AB + A C) I T) (d) 2--7. Reduce I h. fo ll owing Hoolean e xpr.", ;ons t o Ihe indicated number o f lit e rals' ( .) x l' + X YZ + X Y t o three literals ( b) X + y (Z + X +Z) 1011010 )ilera ', ( e ) W X(Z+l'Z)+X(W+WYZ) 10 one li teral d) < ( AB + A B)(CD + CD) T Ac t o four lilerals 2 -8. U .ing D eMorpn'J IheOfem. up",.lhe function F - ABC+8C + AB (. ) " ilh only O R a nd c omplemenl " "" ralions. (b) " ilh ()fIly A NO and complement operalions. 2--9. Fi nd the complement of Ihe following e xp't$$io ns: (a) AB+AB Ib) (V W + X )Y+Z ( e) W X(l'Z + Y Z) + W X(l' + Z )(Y + Z) ( d) ( A + B + C)(A" + C )(A + 8 q 2-- 10. O blain lhe t rulh lable of t he following functions, and in sum.of. minlerrn1.nd prodUC1-of. rnaxlerms fOJm: ( .) ( XY + Z )(Y + X Z ) ( b) ( A + 0 )(8 + C ) I T) \ VXY + II'XZ+WXZ + YZ ~x p re ss each function 2-1.1. For I he Boolean functions E a nd F. a s gi ven in Ihe foUow in g \ r uth table : ,,, 0 0 0 0 0 0 0 ," , 0 0 0 , " , , , , " 0 0 0 , 0 , " 0 , " , (a) List lhe minterms and m axtenns o f e ach fun ~tio n . ( b) l is t the m interms o f E a nd F. (c) List the m imcrm, 01 E + F and E F . ( d) E xpress E a nd F in s um-ol-mimerms a lgebraic form . (e) Simpl ify E a nd F to e xpressions wilh a minim um o f lilerals 2-12. ' Convert t he following expressions i nto s u mo l product. a n d product-<>fsums form.: (M) ( A 8 - t 0 (8 - t C D) ( b) X - t XI X - t Y)( Y + Z) ( c) ( A - t B e - t C D)(B + E F) 2 -13. D raw t he logic d iagram l or the following B oolean e xpressions The diagram sho ul d c orrespond exaclly to t he e qua tion. A ssume t hat the c ompleme nts of the inputs a re not a vailable, ( a) W X Y + W Z+YZ I b) A (BD - t 8 0) - t D IBC + BO Ie) W Y(X+Z)+XZ(W + Y)+WX(Y + Z) 2 -14. O ptimize t he following B oo lean funct io ns by means of a t hree _variable ma p: ( a) F(X. Y ,Z) - :l:m(1.3.6,7) ( b) F (X, Y ,Z) - :l:m(3.5.6,7) (e) F(A ,8,C) - :l:m(O.1 .2.4, 6) ( d) F (A,B ,C) m :l:",(O.3. 4.5,7) 2 -15. ' Opt imize t he following Boolean expressions usi ng a m ap ' l a) X Z+YZ+XYZ (h~ A8 -t BC-tABC (e) A B+AC -t BC -t ABC 84 0 C H AI'1CIl 2 I C OMIJINA TIONAL LOG IC C IRCU ITS 2- 16. O pl imize lhe: f oil_on, B ookan f unclion. by meallS o f .. four- ~afiable m ap : (lI) F (A,B,C D ) . . : ::",(2,3,8.9,10,12,13,1 4) ( b) F (IV,X, Y ,Z) . . : ::",(0.2.$,6,& 10,13,14.15) ( e) F( A,B .CO) ... :::m(0.2.3. 7,11.10.12.13) 2-- 17, Opl i miz~ ( a) F( II'. Ihe following Bonltan (unclions. using a map: x . y. Z ) . . :::", (0.2,$.8.9. 11.12. 13) ( b ) F (A,B.C. 0 ) . . :::111 0. 4.6.7.9.12.13.1 4, 15) 2--18. Find Ihe minterms o ( Ih e (0110 "" in8 e xpression, by fl 1"51 pIOIl;n, each expre . . ion on a map: I ll) X Y + XZ + XYZ Ib) X Z - WXY + W XY+W}'Z+ W YZ Ie) B D+ABO + A8C 2 - 1.9. ' Find all t he p rime implicanlS f or l he following fIook:an (Unci ions. a nd d elermine , ,'hich a re elSCn lial: (.) F( W, X, y . Z ) . . :::111(0. 2 .S, 7 .8. 10. 12,13. 14. 15) ( b ) F(A . 8 . C. D ) . . ::;", (0.2.3.5.7.11. 10. 11. 14. ( 5) ( e) F(A. 8 . C, O J . . ::;"'( 1 .3.4. S. 9, 10. 11. 12. 13. 14. 15) z....IO. O ptimize t he follow;n, l.Ionl ca n funel;ons by fin ding a ll prime i mplica,m and e ssential p rime implicAnl' nnd applying the s election rul e: ( a) F (W.X, Y .Z) . . : ::",(0.1. 4.5.7.11.9. 12.14.15) ( b) F (A. 8 .C,D) . . : :;",(1.5.6.7.11.12,13.15) ( e) F ( W, X. Y. Z ) . . : :;",(0.2.3.4.$.1.8. 10. I I. 1Z,13. 1S) 2--2 1. O ptimize lhe: (oIlovo" n, B oolean (unci ions in prodUCl --o f,sums fQITII: ( a ) F (W.X. 1-'.Z) . . :::", (0.2 . 3,4.8.10. I I. IS) ( bl F (A. B . C , D ) . . l IM(0.2.4. 5 .& 10. 11. ] 2. n , 14) 2--22 O p limize the f ollowin, expressionl in ( I) i u m-of- producu a nd ( 2) p roductof-$ums f orm" (~) ( b) ( e) A C+ l iD -+-ACD -+-AlleD (A + B + O)(A -+-B + C)(A + 8 + 0)(8 + C +O) (A + B + D)(A -+- D)(I! + IJ -+-D)(A + B + C + D) 2 -23. Optimize Ihe followin& fun<:liom i nto (1) . um-of_product. a n d (2) p roduct. o f..,ml ( orm., ( .) F (A,B,C.D) _ ::;111(2.3.$.7.8.10.12.13) ( b) F (W,X, Y .Z) . . I IM (2. 10. 13) P rob)., . ... 0 85 2 - 14 , O ptimize t he foUowing Bool~~n funClions F t ogelher wilh t he d on ' I-care conditions a: (a) F lAB, C ,D) _ ~m(O,3,5, 7, I I, 13), a (A,B,C,D) - :"1(4,6,14,15) ( h) F lW,X, Y ,Z) - 1",(0,6,8,13,14), d(W, X, Y ,Z) - 1m(2,4, 7 ,10, 12) (e) F lA, 8, C ) - 1m(0, 1 ,2,4,5), a (A , 8, C) = : ,.,(3,6,7) 2 -2 5, ' Optimize t he follow;ng Bool~an functions F t ogether with t he d oo'l-care c ond itions d, Find all prim~ i mplicam, and e .semi.1 pr i m~ implicants. a nd ~pply t he selection rule. ( a) F (A, 8 ,C) = ! m(3,5,6), d (A , 8, C ) - 1,.,(0,7) ( h ) F (W,X, Y ,Z) - ::::,.,(0,2,4,5,8,14, 15), a (W,X, y, Z ) - :m(7 , 10, 13) ( e) F (A,8,C,D) - 1m(4,6,7,8,12,15), a (A , 8,C,D) = ! ,.,(2,3,5, 10,IU4) 2 -26. Opt i miz~ t he following B oolean funclions F t ogether with the don ' Hare c onditions d in ( I) s um-of products a nd ( 2) p roduct -of-sums form: ( a ) F (A,8,C,D) ~ l iM(1.3, 4,6,9. I I), a (A,8,C,D) _ ::::,.,(0, 2,5,10,12,14) ( b) F(W ,X, y , Z ) ~ 1 m(3,4,9, 15) , d (W,X, Y ,Z) ~ :m(O,2,5, 10, 12,1 4) 2 -27. Use d omposilion 10 find mi nimum gate input c ounl, multiple-level implementations for Ihe f unctions using A ND a nd O R gate. a nd inverters. + A BC + A BO + A B D ( a ) F (A,B,C,D) _ A 8 C ( h) F (W,X , Y, Z ) - WY + X Y + W XZ + W XZ 2 -23. Use e xtraction t o find a s hared, minimum g ale input count, m ul liplele.oel implementat ion for I he p air o f fu nctions given using A ND a nd O R g ales and inverters. ( . ) F (A, 8 , C , D ) - 1m(O, 5, I I. )4, 15). , I(A, B , C , D ) - ::::",(10) ( b) G (A, B, C , D ) = ! ,.,(2, 7, I 0, 11. 14), , i(A, B, C , D ) - :",(15) 2-29, Use e limination (o Hanen each o f t he function s ets given i nto a two-level su m o f_products form. + B G + A 1 /, G (c'D) = C D + C D, ( a) F IA , B,G.II) _ A BG I /(B,C,O) - B+CD ( b) T(U, V, y, Z ) _ Y ZU + Y ZV, U (W,X) = W + X , V (W,X,Yl _ W Y + X 2 -30, . Prove t hm lhe dual o f t he exclusive OR is a lso its c omplement. 2 -3 1. I mplement t he following B oolean function with exclusive-OR a nd A ND g ate . . using a minimum n umber o f g ale inputs: F (A,B,C , D) _ A BCD + AD + AD 86 0 C HAPTER Z I C O MBIN ATIONAL L OGIC C IRCUITS Z-J2. t a) Impleme nt funclion H = X Y+XZ using Iwo Ihree-stale buffers and an (b) ConsiruCI an e~d u,h' e - OR gale by interconnecling IWO Ihree ... t ate buffers a nd Iwo inverters. 2 -JJ. ( . ) C onnect Ihe OUIP UI S of three 3-slale buffers IOgelher, a nd add add il ional logic 10 implement Ihe funclion F =ABC .. A BD .. A BD A "ume Ihat C D , a nd i5 a re data inputs to Ihe buffers and A and B p as' Ihrou gh logic Ihal generales Ihe e na ble inpUIs. (h ) Is your d e,ign in p art (a) free of Ihree_oJ ale OU l pUI conllict,? I f nOI, change Ihe design if necessary 10 be free of such conflict s. Z-~. U ", only Iransmission gales and inverters 10 im pl ement t he function in problem 2-32, 2_35, D epending o n the design a nd the overall logic fami ly b eing used, it is usua ll y not a good idea 10 l ea,'c the output o f " Ihrce -slale or transmission gate circ uit in t he high impedance (Hi-Z) stat"(a) For t he transmission gate circuit designed in problem 2-33. give all i nput combinations f or which the output F is Ihe h igh -impedance " ate. ( bl Mod ify t he enable logic driving the enable inputs s o t hat t he o utput is e ither a 0 o r a I (instead o f Hi_Z)_ C OMBINAT IONAL L OGIC D E SIGN I n this chaj>1er, we ...a m aOOUl t ho 00';11" 01 comt>natK>oai ci rcuits. We In!re'''.lC a t he use 01 8 ~ierarchy a oo lOp-down 00s>grt. bottl 01 w!1ict1 a re essent ", 1t o t"'" de$>gn 01 digita l c ircuits. Further, r ompuIe r- alOed d es'll" .,; b riefly dffiCUsood. i",," uding hardwa re CleSCr iplion "r>gLl8.QeS ( HOLs) aoo logic Syn t heSIS, t wo COI>OOpts with Cf...cial ,<>Ie s in . "" " Hie", nt design o f mode<n, oompIex d rru it s. C oncepts ",tatoo to tt>e ur"l(l(trlying t echnology for digital c l rcu~ i mplemematioo a re c o"".. in t he d esign space $(!C\ion. Tl>e p 'OI"' rl ies o f logic g ales, iocl ud<ng inI"9ffiIioo ,,,,1 I<wo l s, logic l ami';". , ar>J parM'Iel<m. for logic t echnologies, a te I>'"sanled. Fan- in , fan0"", aoo propagatioo d e lay for gal .... a re d efined , arid ! he p ositive and nega~ve logic t >e_ d imensions of !he ~g<1 spac", COI'\CeI>Is M e introdt.>ced. Finally, ' ,adeoOlf. such a s 0051 a nd p erlorma r.c e. a relouche(j '-'PO<' A ~g n p rocedure with ~"" m ajor staps is p resented. The Ii "" t hree steps, a,,, specification, Iorm"",!,,,", a nd o ptimizatioo illustra!ed b y ,,<ampl"'" Fixe(! Impiement atiM tochnoiogies a re intrOOlJCoo, a oo ,. .e lmo'ogy mappong for t hese '~es. the ne xt s tep o f t he d esign procedure, is oot;ned aod ill ustratoo. T he final s tep of the deolgn procedure. ve riticatioo, i6 iIIl.OSIra too b y a n e xample us in g t>o1h a m anual method a nd logic simulaboo. T he chaptar COfIC ludes with a n intrOduCtion to p rogrammable implementation technologies . T he various concepts", ,ros chapte r a re pervasive " ' t he oas;gn 01 t he 1I<'"", ic computer in the diagram al 1 M beginning 01 Chapter 1. Concep,s l rom ,ro s c hapte' a pply a cross a~ of the dOgita l components o f the generic compute, including memories. 3-1 D ESIGN C ONCEPTS A ND A UTOMATION In C hapt er 1. we learned a bout binary numbers and bina,y c odes t hat r epresent d iscrete q uantit ies o f i nformation. [n C hapler 2, we i ntroduced t h e v arious logic o 87 I!""'!:) I"UOI,.Ulqwo:). jO ",.,:W'Q ~>O11l 1-i3 1 tllO I,l 0 ",,",II<> W - I!""'!' l' UO<""iGWO".) "OO"! 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' A , fu _ _ Ilu o dd , l u",,'oon "" J IhX,L ~".' V "o , ~ / V C- ", " V - " (b) O n u ;, . . ; n!"",,,,,,1l 3.'nptJt _ I"oc'"," 1>10<. . ~ " " '" (e) .H npu' " "" [u ""'''''' e;",u;, . . ;n" r roft nocted excl " ", . . OR bi<>< " I) > A; ~ l>- (d) E><I .... " ,OR block . .. n'efOOltnectO<l 1'IANo. o f lGURE 3-Z Example of Des ign Hierar<hy ond Reu",ble fl lock. appear. This means that if a 9 in pUi odd function circuit was designed directly in terms of NAN D gates, the .chemotic fOT the circuit would consist o f 32 imercon necled N AND gate symbols.. in c ontra" t o j ust 10 , ymbols used 10 d~ribc ' he cir cuit implementation as " hierarchy in Figure 3-2. Thus. a hi ~rarchy g ives" simplified representation o f a co mp lex circuit. Second . tbe hierarcby en ds a t a set ofleav", in Figure 33. In this c ase.lhe leave, consist o f N AND g ale .. Sin ce the NAND g ates are electronic circuit . . a nd we arc i nteresled h ere only in designing t he logic. the N AN D g ales a re c ommonly called p rimi1ivr blocks. T hese ore rudimentary bloc~s, such as gate .. thai have a symbol. b ut nO logic schemalic.Primitive bloc~s a re a r udimentary I}pc of pre ,I~fi,,~d b loch In general. more complex ~t rUC(UTeS t hai likewise ha,e ,ymbol .. ' -I 1 I )aIp> C or.upt. ODd / w,_ 0 91 o D -NMW ,., o I 'lG VR I! ~J D,~."", '" i teprncn,jn, , ''' H ierardly f or F ill'''' 3-2 b u. n o logic: sc h ema ..,., a re a M pre<!efin.ed b lod... Inslead o f sdw:malics, . heir func.ion can be defined b y a p rogram o r d escrip' ion . ba. can " ,rve as a model. For example. in Ihe hiefarehy d ep icTed ill Figure 3.3. Ibe exciusiveO R g alu could have been c on.idered as predefined block .. In . uch a case. Ihe diagram describin g . he exclusive-O R blocb in Figure 3-2(d) would no. be necc1S"'y. T he hi . .archieal represen.a.ions in f igure 33 would . hcn e nd wi.h t he u clusive-O R b loch. In any hier Archy. Ih e " le.ves" consis. o f predefined block .. l OfIl " 0 ( whIch may be primi'ives. A . hird '~ ry importan. properly . ha esullS from hierarchical d e$i", 1$ t he reusc o f b lock. as il l"nrated in FiJl,urcs 3-J.(.) . nd (h). 10 parT (0), .here . ,. . four copies o f lhe ) .inpu . oddfunCTion b lock a nd .. igll' copies o f t he u dusive-O R block. In p a . . ( h) . h ere i:'I only one ropy o f the 3-inpu. o dd function block a nd o ne copy of Ihe cxclu.i....,_OR block. This " 'prCKn" Ihe f...,ttha M desig~r lIa. 10 de.iS!' only o ne ) . inpul odd-fu nclion blocl! and One exciusiveOR block a nd can use Ih e", blockS four limes a nd eigh.'im~$, r"'pecli,ely. in ' he 9 i npul o dd.function circuit. In general. suppose Ihat a ' various Ie"els o f the hierarch y. Ihe blocks u ",d a ", carefuUy defined in loch a m anner ,hat many o f ' hem a re iden'ical. 1'Or IhC$C r epea.ed blocks. Odly o ne d esign" nccess.ory. This design can " " used everyv;here the block is r cqu;ud. T he a ppearance of I block "'i'hin a de$ign i . u Ued a n i n$/Dnu o f Ihe block a nd ilS use is called an i lUlllrllimion . T he blod::: is ~lUtlbk in lhe " "nR Iha. il c an be: used in multiple [IIaces in . h e circuit desiJl,n I nd. possibly. in lhe design o f o ther circuilJl as ..'CU. Thia concept v ea . ly re<!ucn Ihe design effort " ' qu ire<! for c:omplu ciJTIJilJl. Note ,hal . in Ihe implemenlation o f Ihe ciTcuil. "'pa_ rale hardWllre h as 10 be provided for each InSU.nce o f ' he block as repre~n.ed in Figure 3-3(a). T he feu~. as r epresented in Figu", 33(b). is confined 10 ' he sch~mat i "" not ' 0 ' he aClu ~ 1 hardware impl.mentalion. 92 0 C HAI'TER 3 I C OMIlINATIONAL L OG!C D ESIGN A ller oompleling a discussion o f Ihe design p,-oc~ss. in C hapters 4 a nd 5. we focus o n predefined. reusable blocks that lypically lie a t t he lower level. o f logic d esign hierarchies. TheSt are b loch l hat provide basic funclions used in digital d esign . They allow designers 10 d o much of the design proce<s above Ihe primiti"e block leve l. W~ rcf~r 10 these particular block. as ! unc/;onalblocks, T hu . . a functional block is a p redefined collection of i nterconnecled ga t e~ Many o f Ihese fU nclional b loch h a"e been avoiloble f or d ecades as medium-scale integrated (MSI) circuilS that w ere imeroonneCled t o lorm larger circuits o r sy.;tem~ Sim il ar blocks are nOw in o omputeraided design tool libraries used for designing larger integrated circu i t~ These funclional blocks provide a catalog o f e lementary digital components that a re widely used in t he design a nd implementation o f i ntegrated circuits l or computers and d igital 'ystem~ Top-Dow n Desi gn Ideally. the design proccs:s is performed lOp dOR 'n. This means that the circuit fUnclion is spt:Cified typically by lext o r a hardwarc description language (HDL). plus COn straints on = t, perfollllance, and reliability, A t high le\"els of the design. Ihe circnit is then repeatedly di,ided imo block:! a . ne<:essary u ntillhe block. arc .mail enough ! O perform logic design. rw manual logic design. tilt: blocks may need to be furtber di'ided. In aUlOmalcd synthesis, the H DL <Jescription is c onvened 10 logic automatically, Then. for boIh manual design and a utomated symhesis, the logic is optimized and then mapped to the available primitive dement~ In fact, reality departs significamly f ronllhis ideal view, parlicularly a t the higher le"els o f t he design. In o rder to obtain reusabi~ty and 10 make maximum use of predcfined modules, it is oftcn necessary to perform portions of tbe design b mlom "P, In addilion. a panicular circuit design obtai~cd during the design proce. . may viobte o ne of the oonstl1lints in the initial src<'ification. In this case. it is newssary t o backtrack upward through tt>e hier_ archy until a level is reached a t which the violation can be eliminated, A p onion 01 the design is then revised a t that lc,'cl and the re" isions are carried back d o"nward through the hierarchy. In this text, since reader familiarity " ith logic and c omputer design is p roba_ bly limited. we need to build a ready set 01 functional block, t o p tovide d irection in lopdown design . Likewise. a sense of how to break up a circuit into blocks that can s e,,'e to guide the top-<iown approach also must be mastered. So tbe focus in much o f the text will be On bol1om-up r ather tha~ topdown design, To begin building the basis for top-down design. in C bapters 4 a nd 5. we focus o ur efforts o n the design o f frequcntl)' used functional block~ In C hapters 1 a nd lO. we illustrate how larger eircuil~ and $ystem~ a re b roken down into blocks and how these block. a te implemented with funClional b loch Fina ll y, beginning with Chapter 11. we apply these ideas to look at design fTOm mOre o f a topdown perspective. C ompute r- Aided Des i gn Designing oomplex 'y.;tems 000 intcgrated circuit' would not be feasible without the use o f comp",er-aide{j desig" ( CAD) took Schemmic m pwre tools support the dra"ing ) _1 I l k,;gn C onp" ,,,J Au,,,,,,,,;,,,, 0 ~3 o f b lodli a nd interconnections at a llle,'.I, " f t he hierarchy, At t he level o f primitives a nd fu nc tional blocks, libraries o f graphics symbols a rc prm'ided. Schematic caplUre tools SIlpportt~e construction o f a ~ i erarchy by p cnniuing the generation o f , ymbols for ~i<.'Tan;hical blocks and the replicalion o f symbol, fOJ reuse. T he p rinlitive block, and t he f unctional block . ymbols from libraries h "e a ssociated m odd. t hat allow t he b ehavior a nd t~c timing o f t he hierar c ~ical h loch a nd the e m ire cireuil to h e verified , T his verification is p erformed by a pp lying inputs to Ihe blocks o r circ ui t a nd using a logic sim"lmor to d etermine t he o utput :!. We will he illustrating logic s imulation in a n umber o f e xamp les T he p rimitive block, f rom libraries c an also h a,'. a ssociated d ata. suc ~ a s physical a rea i nformation a nd d elay p arameten. l hat c3n b e used by l ogic s ymhesiurs t o o ptim ize designs b e in g gen erated a ut oma tically from h ardware d escr ip_ t ion b nguage specifications. H ardware D escription L anguages T hu . far. We h ave m en tioned h ardware d escription la nguages only casually. In m odern design. h owe"er. s uch languages hR,'e bceome crucial t o Ihe design pr<>cess. Inilially, we justily such languages by d escribing t hcir u ses We will t hen briefty d i scus~ V OHL a nd Verilog~ , t he most p opular o f t hese language s B~gin ni ng in C hapter 4. we imroduc<: bo lh o f t hese l anguages in d eta il. a lthough, in any given course. w e c xpecltha t o nly o ne o f t hem wi ll be c o"ered, H ardware d cscrip,ion languages rescmble p rogra mming languages. but a re specifica ll y o riented to d escribing h ardware s , ructureS a m i behavior. 'l1,ey differ m arked ly f ,om t ypica l p rogram ming l anguages in that they ' "presen, e~,cnsi"e p arallel o perat ion w herea. m ost p rogram ming langu.ges r epresent s erial o peration. A n o bv ious u SC for a h ardware d escription language is t o p rovide an alterna _ tive to s chemati"" When a l anguage is used in , bi, fashion, it is r eferred t o a . a sl",c"'T~1 tk""T;I";,,/1 in which t he language d escribes a n i nterconnection o f com _ po nents. S uch a s trucl ur;,1 d e=- iption, referred to as a n~IIi.>'" c an b e used as i nput to logic sim ulation j ust a s a s chematic is " ",d . For , hi , a pplication. models for e ach o f t he p rim itiv" hloc k, a re r equired. If a n H DL is u sed. then these models c an alo;o b e w rille" in t he H DL p rovid ing a m Me u niform, p ortable r epresen tation l or si mulation inp ut. T he p ower o f a n H DL b ecomes more a pparen t. h owever, w hen it is used t o r epre,enl m ore than just sch ematic i nformat ion . II Can r epresent B oolean e q uations. t rul h t"bles, and complex o peratio ns such a s arit hmet ic. ThUs. in t op _ down design . a , 'ery high-level descriptio n o f a n e ntire s y,lem c an bc p recisely s pec ifi ed using an H DL A s a p art o f t he d e,ign process. this ~igh - le"cI d escrip, ion c an then h e refined and p artit ioned into 10"'cr_Ievel descriptions Ultima tely. a final d escription in l enns o f p rimiti"e c ompone n t, a nd f unctional b loch c an h e o btained a s t he r e, ,,1t o f t he d esign procc<s. NOle t hat a ll o f t hese d escript ion, c a n b e s imulated , Since t hey r eprescnt t he . "me . y.tem in t ern" o f f unction. but not neces<arily ti ming, t hey s ho uld r espond by giving t he s ame log ic val ues f or I he s ame a pplied i nputs T h is vi tal simulation p roperty s u pports d e,ign verif,eation a nd is o ne o f t he p rincipal r eMon, for the uSC o f H DLs. 94 0 C HAPTER 3 f C OMB!NAT!ONAL L oG!C D ES!GN A final maj or reason for the growth of t he use o f H DLs is logic synthesi . . A n H DL description o f a , )'stcm c an b e written at an intermediate l e"el referred t o as " register t ransfer language ( RTL) level, A logic synthesis 1001 with an accompanying library of c omponent. can convert such a description into an interconncclion o f primitive components that implements the circuit. This r epl.ce ment o f t he manual logic de,ign p roce" m ake. the design of c omplex logic much more efficient. Currently. lher~ are lwo HDLs, Y HDL and Yerilog. that a re widely_used . , tandard hardware design languages T he language s tandards are defined. a ppro'cd. a nd published by the Institute o f Electrical and Eloclronies Engin~ers ( IEEE). A ll implemcntalions o f Ihe"" languages must obey t heir respecti,'e standard. This standardization gives HDI..< anOl her advantage over schematics. HD I..< are portable across c omputer-aided design tools wherea~ schematic capture tools are lypically unique t o a p 'rlicular v endor. In addition 10 t he s tandard languagcs," num1:>cr of m ajor companies have their o"'n internal languages. often dC\'eloped long b efore the s tandard languages and incorporaling f emme. unique to lheir p articular prodUCIs. Y H DL ' tand, for VHSIC Hardware Description Language. Y HDL was developed u nder c ontract for the U. S. D epartment of Defense as a p ari o f the V~ry_ H igh _ Spee<l Integrated Circuits (V HSIC) p rogram and sul)sequent ly b ecame a n I EEE s tandard language. Yer;loge was developed by a company, Gateway De$ign Automation. which w a. bougll1 by C adence- Design Systems. Inc, For a while, Verilog was a p roprietary language. but eventually 1:>ccamc an I EEE s tandard language, In this t~x t . we p resent b rief i ntroductions to both V HDL and Verilog. T hese p ortions o f the leX! are oplional and permit your i n"ructor to CN'er One of the two l anguage, o r neither. R egardle" o f the H DL, there is a Iypical p rocedure used in e mp loying an H DL description as simulation input_These procedure steps a re a nalysis, elaboration, a nd initializalion, followed finally by the simulation_ Analysis and e laboration are typically p erformed by compiler similar t o those for programming languages. A nolJ5;' che.c"s the description for violations of the synta . a nd s emantic rules for the H DL a nd p roduces an i ntennediate r epresentation o f I he de,ign, E laboralion I raversei the design hierarchy represented by the d e",ription; in this process, the design h ierarch)' is ftaUened t o an interconnection o f m odules tha t are dc",ri1:>cd only by t heir behaviors. The e nd result of t he a nalysis a nd e laboration p erformed by the c ompiler is a simulation model of the original H DL description, This model is Ihen passed t o the simulator for execution, f niliafil.olim' selS all o f the ,ariahle. in t he simulation m odd to specified o r default values. Sim"Iarion e xecutes the simulation model in either batch o r i nteractive mode wilh inpuls spe<:ified by t he user. Becau"" of t he abilily t o deocribe fairly complex hardware efficiently in an H DL a special H DL struclure called a lesrbench may 1:>c used. The testbcnch is a description that includes the design to b e testcd. typically referred 10 a , the device under Ie", (DUT). The t e.tbench describes a collecl;on of hardware and software functions that apply input. t o the D UT a nd anal)'"" the o u tputs for correctness. This approach bypasses the need t o provide separate input' t o the simulator and to J _t I D<":gn Con<<p< oo A u,.,.".oon Cl 95 analyze, often manually. the simulator o utpu ts. C on,truction o f a lestbench pro"ides a u niform verification m~chanis m t hat can be used at multiple levels in the top-down design process f or verification o f c orrect function o f the design, Logic Synthesis As indicat~d ~art i er, t he avai lability of logic synthesi, too!, is o ne of the driving forces behind the g ro,,;ng u.., of HDLs. Logic synthesis n ansform, an RTL description o f a circu it in a n H DL into an optimized nellist r tprese T1 ting storage e lement' and combinational logic. Subsequently, t his neilist may be t ran,formed by using physical design t ool, into an actual integrated circuil layout. This la}'out ..,rves as the basis for in tegrated circuit manufacture. The logic , yn t he,i, tool takes c are o f a large portion o f the details of a design and allows exploration o f t he cosilperformance trade-<>ffs e ""nt ial to advanced designs. Figure 3 4 gives a simple high-level flow o f the Sleps involved in logic . ynthesis. The user p rovide. an H DL d e",ription o f t~e ~ i tCu i t to be designed as " 'ell as " arious oonstrainl$ o r bounds o n the design. Electrical o onma ints include allow.ble gate fanouts and output loading restrictions. A rea and s peed constraints direct t he optimization step;! of the synthesis. A rea eonstraints typica ll y gi"e Ihe maximum permissible area t hat a circuit is allowed t o occupy ,,;thin the integrated circuit. Atternatively. a general directi,'e may be given which specific> t~at a rea i$ to be minimized. Speed constraints a re typically maximum allowable value. for propagation M lay on various p ath. in t he circuit. AUern3li"cty, a general direeti,'e may be given 10 maJ<im ize speed. A rea and speed both translatc into the <:<)1;t of a circuit. A I tDL O <""ipl;oo o f O ",.h E lecorooi<, SpeOO. . od A". COOS". ;"" Th<h ooioJY L ib..,y n .".l.t"", Interml,ole Rep"' . . nt'Oion j I 'rwp,inta..t;oo _ C Ip<;m,"'"", _ Tc< ' "",""y ~'l'P'n l I N elli!! Cl n G U R E l - 4 High-Levet ~10 . .' / ", l og'" SyntOes;, 1 00\ 96 0 C HAPTER] f C OMIIINATIONAL L OGIC DESJGN fast circuit will typically have larger area and thus cost m ore to man ufacture. A cir_ cuit that need not o perate fasl can be optimized for aTea, and. relatively speaking, costs less t o manufacture. 10 some sophisticated ,ynthesis tools, po"'er c onsumption can also be used as a constraint. Additional information used by a synthesis 1001 is a technology library Ihal d e.cribe, t he logic elements a"ailable for use in Ihe nenist a . well a , t heir delay a nd loading p ropertie s, T he l aner information is essential in meeting constraints and performing optimization. T he f im majoT s tep in the s ynlhe,is process in Figure 3- 4 i , translation o f t he H DL descriplion into a n i ntcrmediale form. The information in Ihi. representation may b e a n inieTconnection of generic gat es a nd storage clements, not taken from a l ibnry o f primi!i,'e bloc~s, called a l echn%gy library, It may also be in a n a lternate form Ihal represent. clusten; o f logic and the interconnections between the clusters, T he ""cond m ajor . tep in the synthesis proce ss is optimization , A preoptimi 1.ation . tep may be u. .d t o simpliry the i ntermediate form, For e xample, logic t hat is identical in t he intermediat e form rna)' be shared. N c,t is the optimization in which the intermediate form is pcocessed t o a nempt to meet the constraim pec;. hCd. Typica ll y. twole,'el and multiple -l eve l optimizo tion are p erformed. O ptimization is followed by technology mapping which r eplace, A ND gates, O R gates, and in"erten; with gates from the technology library. In o rder t o evalume area and ' peed p arameters ass.ociated Wi1h these gates, additional information from the technology library i . used. In sophisticated synthesis tools, furth er o pt imi7.ation may be app li ed d uring technology mapping in ordec t o improve the likelihood of meeting the c onstraint' o n lhe design . Optimization can b e a " cry complex, time consuming process for large circu it ,,- Many optimization passes may be necessary 10 achie,'e the desired r e,ulls Dc to d emonstrate t hat constraints are difficu lt , if nOt impossible, to meet. The designer may need t o mooify t he c onstraints o r the H DL in o rder t o achieve a satisfactory design, Mooification of the H DL m ay include manual design o f SOme portions of 1he logic in o rder to achie"e t he design goal,,The o u tput of the oplimization/leehnulogy mapping processes is typically a nellist c orre'ponding t o a schematic diagram made u p o f stomge elements, galCS, a nd o ther combinational logic functioMI bloch This output s erve, as input t o physical de.ign too l, thal ph)'sicall)' place the logic e lements and route the inter connections between t hem t o p roouce t he la)'out of the circuit for manufacture, In the case of programmable p an, such as field_programmable g ate arroyo a , dis cussed in SectIon J~ . an analog t o the physical design tool, proouces the bi nary information used t o p wgram the log ic within the part"3-2 T HE D ESIGN S PACE For a gi ven design, there is t)'pically a target implementation technology t hat specifies the primitive clements available and the p roperties o f those elements, In a dd ition. there is a set of c onstraints 1hat applie. t o the design . This section deals wi th the potential primitive gate functions and p wpertie. and brieny di!>C\lsscS design conslraints a nd the t radeoffs that must be considered while aUempting to meet the constraint ,,- Gate P roperties Digit.1 c ircuit' are constructed with imegrated circuits. A n integrotcd cIrcu it ( abbreviated IC) is a silicon ilCm iconduetor crysta l. informally ca lle..:! n chip. con taining the electronic r omponen ts for the digital s ate. and s toraae c lcm""t . . The var iouo componentS are imerronnectcd on the chip. T he chip is m ounted in a c eramic o r plastic container. and connections are welded from the chip t o t he e xternal pill1to form the integrated cirroit. 'The number o f p ins m .y range f. om 14 o n 3 .maJl IC package 10 several hundred on Large packago=. Each IC has a numeric designation p rinted o n the surface 01 the package for idenllf\callon. Each vendor publi,hes t btasheets o r a calalog that contains the descnplion and all the Oe<:es!<3ry infornlDllon a bout t he Ie. t hat it manufactures. Typically, t hi, i nlonna tion is available On v endor "'eb!; i t~ l evels o f I ntegration As Ihc technology o f IC. has improved, lhe number o f g ates Jlf"i!Cnl in a lingle sil. icon chip b as increased considerably. C uslomary r elerence t o a pad:a&e as being cilher a $mall. , medium. , large . O f very la. .c ale i ntegnlled device is U$/!d 10 d ,f fCttntiale bel""ecn chip" " ith jusl a few internal gales a nd Ih06C " "Ih tbousand!; t o t em 01 m i llion~ o f p t .... Small.Jcalc I"'~nllcd (SS I) devices contain sevc r-al i ndependent primiti,'. gates in a single p achge. The inputs a nd OUtput! of the gates a re connected directly t o the p in. in the package. T he n umbe' o f gates is usually le515 t han 10 and is limited by the !Iumber o f pins . "a il blc Oil the Ie M~diu"" $("'" jrr1~grtlled (MS1) d c.ices h a.e a pproximately 10 to leMl , ate. in a single package. Th ey u .ually p<:rform specific elementary digilal fUI\C1;ons, . uch a . the addilion o r four bits. !>1ST digilal f unction. a re similar 10 the functional blocks ~ribcd in Chaplel'$ 4 a nd C hapter S , u.rgr~Qlr ilttrgrtJltd ( LS I) d e,'ices t on tain b el,.. ... n 100 a nd a lew lhou . . nd g ates in a single package. 'They include d i,ilal . ystems s uch as $mall p """"""rs, small memories. and pfOlJ1lmmable modules. V uy /Qrg~'$"I" jltugrtJl~d (VLS I) de_ices contain several thousand t o t en. o f million. of gates in a s ingle package. E~ampll'1l are complex microprOCC5I5()' and digital signal proce5l5ing c hips Because o f their . mall transistor dImensions. high density. and c omp.,ati,el) low cost. VLSJ device. have revolutioni/,ed d i,na l s)'s tem and comput er design. VLSI I""" nolng)' gives dI.'1Iigners Ihe c apabilit y to <TcalC complcx 'lrUC1ur~ t hat p reviou!ly were not CCOflomicaT t o manufacture. CircUlI Tec:hnologies Digilal integrated ciTCUil$ a re d a"ified nOi onl)' by t heir function. b ut a ko by their specific implementation te<:hnolOCY. Each technology has its own ba .ic d ec I ronk device and circuit structures Upoll which m ore complex d i,it.1 circuits a nd functions are developed. T he ' pee ific e lectronic dc,'iccs used in Ihe co nstruct ion of the b as ic circ uits provide t he name for thc technology. Currently. itieon based 98 0 CHAPTER J o I COMJ1INATlONAL LOGIC DESIGN FIG URE J...S Implemen," tion 0 1. 7 . inpu, NAND Gate u.in~ NAND G at'" with 4 ( )f Fn.'or Inpu" C ompl"mentary M etal O xide s"miexmd uctor ( CMOS) technology dominates d ue 10 it . high circuit d ens ity, high performance. and low p ow"r c onsumption. A lternati"e technologies ha~ed On Gallium A rsenide ( GaA,) and Silicon G ermanium (SiGe) a re u sed selectively for very high speed c ircuits. T echnology P arameters For each specific implementation technology. t here are details t hat differ in their electronic circuit design a n d circuit param.te~ T he most important parameters used to c haracterize an implementation tcchnology follow' Fan in specific. Ihe number o f inputs ~v"il"t>le On a g"le, Fan-{)II/ specific,; t he n umber 01 s tandard loads driven by a gate output. M a,d m ",n f a" ' f)w for a n " ulput ,pecifles the fan -<> ut Ihat Ihe oulpUI can drive with OuI impairing gate performance. Standard loads may b e d efined in a variety o f w" )IS d epending upon the lechnology. Noise margin is the max im um external noise yoltage superimposed on a n ormal inpUI value Ihat will nOI c ause an undesirable change in the circuit o utput , C ost for a g ate speciflC'l a m easure o f its contrib ution t o Ihe c "Sl o f Ihe inl e gralcd circuil oontaining it. Pr"ptllitl/ion deltly i. the ti me r equired for a change in value o f a signal t o p rop agate from input to output. Th e operati ng speed o f a circuit is inYcl'$e ly relauxl to the longest propagation delays through the gates of the circuit, Po wer (iissipaliof1 is the power drawn from the power , upply a nd c onsumed by the gate. T he p ower c onsumed is dissipated a~ heal. s o the power dissipalion must be considered in relation to the o pera ting t emperat ure a nd cooling r<quirements of the ch ip, A lthough all o f thC'le p arameters a re i mportant to , h. d e'igner. further d eta ils o n on ly s elected parameters a rc provided next. F. ... IN f ur high-speed technologies. fan -in, t he n umber o f inputs to a gate, i . o ften restr i ct~d o n g ale primitives to no more Ihan four Or fiv e. This is p rimarily d ue to electronic c onsiderations reiated t o gate speed. T o build g ates with larger fan .in. i nterconnuted g ates wilh lower fan in a re u. .d d uring technolog)' mapping. A mapping f or a 7 -inpul NAND g ate illustrated in Figure 3-5 i , m ade up o f two 4input NANOs a nd an inverter, PROP.G.TION DELAY T he d elennination o f p ropagation delay is ill ustrated in Figure 36. Thr ee p ropagation delay p arameters are defined. The high -IO-Iow J_2 I n .. O e.ip S r- 0 " mVOlIT I O~ I o t '"\ , , , \ 99 ,- / f l GU R E}.6 I'rovag at ion o. l. ~ for I n In''crler p ropagation li"' t I ""L is Ih c d ela~ measured from Ihe r eference "oll a se On t he input IN t o Ihe r dc",nce oltage o n Ihc o utput O llT. with I he oUlput o lt age going f .om H 10 L n.e reference voltage we a re using is the 5 0% potnl , h alf...', y bet " 'u n lbe minimum a n d tbe maximum values o f the voltage liignJl1: OIber . er e",,,,,,, ml1ages may b e " ",d. d ependinll On l be logic family. l be l ow-w-high p rop. agalion lime '1'U1 ' s Ihc <klay IIICMured from Ihc . d"",n"" oltage o n the inpul m lt age IN 10 tbe " ,feren voita&" o n IIIe OUtpul voltage o m. with l be OUlput voltage Coing fro m L 10 H . We define the prOpiJ$arim, t lday I....... the m aximum o f t he.., two d e la ys. T he rcaw n we have chO$Cn Ihe m""imum value is , hat we will be mosl c o " cerned wil h finding the lonaest Ume for a s ignal 10 p ropBgatc from input. t o o ut put L O lherwise. the delinil ion! given fo r I... may be incon,iSlcm. depen ding o n Ihe use o f (he d a la. M 'nufacl ure B usually specify the maximum a n d typical va lues for both I.,OL , nd '1'1.11 01 for ' ... f Of t hei. proc:luCI $. TWo d iffe reD . models. IrJru;poo-l delay and ; ""n i,1 d e lay. ar~ e rnployed in model;ng g atel d uri"8 . i muialion. For ' '''''sport d"My. IIIe change in an OU'pUI in ..... po''''e 10 Ihe c han", o f a n inpUl OttUrs afler a speci fied propag" uon <klay. I Mf>,ia/ tI~l"y os $&milar . 0 lnompon delay. e~pt Ihal i f l he inpul changes caU$C IIIe OUIPUI 10 c hange IWicc , n alt inlerv:lI 1e5S Ihan Ihe ' rj,um ' imr. Ihen Ih e l im o f the Iwo " "Ipul c hange. <Joe. not occur. 1lIe rejeclion lime is a specified ,'alue n o l arger tha n the propagalion delay and il o hen equal to Ihe propagalion del"y. A n A ND gate modeled w ilh b olh a " """POrt delay " nd an ine rtial d e lay ii ill ustrated in FI gure )7, To he lp v i,nalize t he oklay l>eh~v i or. we have a l", give n Ihe A NO o u tpul " 'it h n o dcl~y, A c olored b ar on Ihis w' lV e(urm iho,,~ 2 n s p ropagalion delay lime afler e ach in put c hange a nd. s maller b lad b ar sho ..... 8 rejection lime o f i ns. l be OUl put modeied with Ihe InoftS90rt t klay is i denl ocal . 0 thai for n o delay. excepl thaI i. i hifled 10 II><: righl by 2 n. . For l he inertial d e lay. tile "' ' "fonn is li t e ...~ Sh'fted. T o d efine lhe waveform for l he <k1a)e<J " "'PU', we will call each change in a ,,"ovdorm a n ~,/p. To d e le nninc ,,'hether a p a.ticular edge appea", in , he [ D " "'put. it must be: d elermined ... h elhe. a second edge OCC urs in the N O o utpul before the end o f the . ejecli..,n l ime f w Ihe edge in q uell ion. a ~d whe lh er Ihe c dge w ill result in " c hange ill the [ 0 o utput. SinC<l e dge b OCC urs before lhe e nd <If l!o e reject ion ti me for e dge a i" Ihe N O o utp ul, edge a dOC$ nul 1 00 0 C HAI'TER 3 I C O M IlINATlONAl L OGIC D E5 IGN u U ru I F I 'o[}ela)_ _ _- -' ( ND ) T,.n'!'Of1 I U I - ,Ft .. ,FEJ5iOO , n nJ Dcb ' (TD)_ _____~~---,'----' ' l nen . . l 0 <1. )' (JD)'-::=~==~~_:_--~=~==;=~='-"c;;:: ~- I I I I I 0 2' 6 # 10 I 11 14 I 1 6T,mc(ou) o n GUR37 Example, o f Bch . ,ior ofTron'J>Ort and Ino rti .1 D elay. a ppear in (he 10 outp ut. Since ~dg~ b does not change the state 01 10. it is ignored. Sin ce edge d occurs at the rejeclion ti me a lter e dge c in (he NO OUlpUt. e dge c does a ppea r. E dge e . however. occ urs wit ~i n t ~ e r ej~et;on time alt er e dge d, so edge d d oes not appear. Since e dge e appeared a nd edge d di d not a ppear. e dge e d oe, n Ot cause a change. FAN -our O ne a pproach to measuring lan-out is the use o f a n~"d~rd 1000d. Each input o n a driven gate provides a load On the Output of Ihe driving gate which is m easured in standard load Unils. For example. the input t o a specific i n,'er ler can h "'c load e q u al to 1.0 standard load . If a gate d ri"es si x such i merlers. t hen the fan-oUi is e<juallo 6.0 s tandard loads. In addition. t hc output o f a g ale h as a maxi mum load that it can drive c a ll ed ils m a,imu m fa noul. T he d etermi nation of the m a.i mum fanout is a function o f t he particular logic lamily. O ur d iscu",ion will b e rcstrictcd to CMOS. curre nt ly t he mOSt popular log ic fa mily. For C MOS gates.. the loading o f a gat~ o u tput by th~ integrated ci rcuil wiring and the in puts o f o ther gates is modeled a . a capacitance. This ca pacitive loading b as n o eff",,! o n the logic levels as loading often does for o t her fa mili~s. In stead. t he load on the OU1put o f a gate deter mines t he t ime required for I he out put o f t he gate to change from L 10 H a nd Irom H t o L , I I the load on the outp ut is increased. then th i< t ime. called the lrans;t;"" I ;m~. incr~ases. Thu,," t he maximum fan-<l ut for a gate i, Ihe number o f s tandard loads of capaci tance thaI Can b e dri,'en with t he tran< it ion ti me no greater t han its maxim um a ll owable value. For example. a gale with a max im um fano ut o f 8 s tandard loads cou ld dri>'e up t o 8 in "er tel> that present 1.0 standard load o n e ach o n t heir inpu ts. Becau se it rc presents capacitance d r iven. t he actual fan out o f t~e gate, in terms o f s tandard loa d" also affects the p ropagation delays of the gate. Th us. a 32 ( The De,;gn S!'""e 0 101 simple expression for propagation delay can b e given by a formula or l able t hat consider!; a ftxed delay plus a delay p er s landard load limes the n umber of s tan d ard loads driven, as shown in Ibe next example. E XAMPLE 3-1 C .lculalian o fGote Delay Based o n t"anOut A 4i~pUl N AND g ate o u tput is a ttached 1 0 the i nput' o f the fo ll owing g ates wit h the given n umber o f s tandard loads repre~nting t heir inputs: 4 inpul N OR g ate 0 .80 sta~dard load 3 input N AND gale - 1.00 s tandard load, and i nverter - 1.00 s tandard load, The formu la f or the d elay of the 4. input NAND gate is 1"" _ 0.07 + 0.021 x S L ns where S L is t he sum o f the standard loads driven by I he gate. Ignoring t he wiring delay. t he delay projected fO! the NAND gate as loaded i , 1 = 0.07 + 0.02 1 x (0.80 + 1 .00 + 1.00) = 0,129 ns In modern higb ,peed circuits, the portion of the gate delay d ue to wiring capaci . tance is often significant. While ignoring such delay is unwise. it is difficult t o evaluate since it d epe nd, o n the layout of the w ire, in the integrated d rcu it . Nevertheless. since we d o not h .,e this information o r a m ethod t o o btain a good estimate of it , we ignore this delay component h ere Ooth fan _ and fan -oUl must b e dealt with in the technology mapping s tep of in the design process. Gales with fa n- ins larger than those avaitable f or technology mapping can b e implemented with mul\iple gat es. G ates with fan-<l ut' t hat e ither exceed Iheir maximum allowable fan -out or h a"e too hig h a delay need t o be replaced with multiple g ates Or have buffers added a t their o ut puts. C osr For integrated circuits, the cost of a primiti,'e gate is usually based on Ihe area occupied by the layout cell for the circu it . The layout cell area is p roportional 10 t he size of the transistors and the wiring in the g ate la}'o u l. Ignoring the wiring a rca. the area o f t he gate is p roponionallO (he number o f transistoTS in Ihe gale. which in 1urn i , usuatty proportional t o t he gale input cou nt tf t he a ctual a rea o f (he layoul is k nown , t hen" normalized value o f this arca provides a m Ore accurate eS1ima tion of cost Ihan gate input count. P ositive a nd N egative L ogic E xcluding transition . . t he binary .ignals at the inputs and o utputs o f any g ale have one of twO val ues: H o r L. O ne value r epre..,nts logic I a nd the other logic O. T here are two different "ssig.oments of s ignalle,'el. to logic values. as s ho,,'n in Figure 3-8, Choosing the high le"el H 10 r epresent logic I defines a posi(i"~ /ogic s~tcm Choos in g t he low level l . 10 r epresent logic 1 d efines" 1U!8t11i"e-/ogic '~ t cm , The terms "positive" and 'negative ~ a re somewhat misleadin&> since both signals may be posit;,'e voltages or both may b e negative voltages. I t is not the ac tual signal values 1 02 0 C HAPTER J f C OMBI N ATIONAL L OGIC I )E.SIGN v oh", " '" Siln. 1 'al"" v Sifn1 . . I"" .. . 1"" " " , ( . ) Fl><iti.elofi< , , ( Il) N, ,,, 'iv e . 0 FIG URE 3-8 S'gnal AS$ignment and Logic ~Ia ri ty Ihal d demt ine Ihe Iype o f logic. but , .I h er t he assignment o f logic values t o t he relo f t he two signal ranges. I ntegrated circuit d ata sheets define digilal gat~s in t~mtS o f both logic " alues and signal va lues H and L I f H and L a re used, it is up to lhe user 10 d ecide on a po!;itive o r n egative logic assignment. C onsider. for e .ample. the t ruth t able in Figure 3-9(a). T h is t able is given in a d a ta bool: for t he C MOS gate s hown in Figure 3-9(b). The table speci fi es t he physical beh ""or o f t he gate when H i , 5 " olts a nd L is 0 .. oilSThe tru th table o f Figure J -9(c) assumes posili,'e logic. " ,th I assigned to H and 0 assigned to L T he table is the s ame as t he t ruth table for the A ND o peration , T he graphics s ymbol for a poosilive-logic A ND gate i , shown in FIgure 3_ d ). 9( Ofiv~ ampli,ud~s ,, ,, , , " " "" ,, "" " ," , , , , , " (a) r ",, " ",~Ie . . i th I l.n<l L , " , " X=----z Y Got. (b) G ot. ' I"ck J ;"S' . ", ~=D-z ( c)1ho,h . . h k I"" !'O'h,.... 1oJi< ( JJ I't><i \;v<-\ot;c ANO " ,,, , " ~=D---z ,, , "" " " ( e)Tm'htabl< I"" . .. " < ;v e,,,", o FIG URE (I) Neg.at;v< . 1opc OR; l '''. J- ~ I kmon"'. t ion 01 i'o>iti,'e a nd Negative Logie J_2111>< D<,;gn Sp'co 0 1 03 Now consider the negative logic a ss ignment for the s ame physical gate, with 1 a>signed t o L and 0 assigned to 1-1. T he result is t he t ruth table of Figure 3-9(e) , This t ab le r epresents the O R o pera tion with the table rows re'-crsed , T he graph ic symbol for the negative-logic O R gate is shown in Figure 39(f). The small triangles on the inputs a nd o utput are polar;ty indicalO'''. T he p resence o f a p olarity indicator o n an input o r o utput signifies t hat negative logic is a ,"u mcd for the COrre sponding signal , ThUs, the s ame ph)"lical g ate can o perate as e it her a positi,'e .]ogic A N D gate o r as a negative logic O R g ate. Th e c on"eNion f rom positive logic t o neg ati,'e logic a nd vice versa is an o peralion t hat changes l 's t o O's and O's to I 's al both (he i nput' a nd the output o f a gate. Since t his interchange of l ' s a nd O's is a part o f t a king the d ua L the conversion o perat ion p roduces the dua l of the gate function. Th u. . the change o f a ll g ate inputs and o utputs from one polarity to the o ther r esults in la kin g t he dual o f the f unction, wit h a ll A N D operation, ( or graphics symbols) c on"erted to O R o pera t ions ( or graph ics symbols) a nd vice versa. In a dd ition. one must not forget t o incl ude the p olar it y indicator in the gmphics symbols when negative logic is assumed. a nd o ne must also recognile that the polarity definitions for circuit inputs and c ireuil OUtpul8 h" 'e b een changed . In th is b ook we d o n ot use ncgative logic. b ut assume t hat all g ate, o pe rate wilh a positive-logic assi gn ment. Design Trade-Offs Previously, it has I:>ccn 8hown t hat there is a relations hi p belween the actu al fan _ out of a gate a nd its propagation d e lay. Higher fan-out increases the propagation delay. For e~a m ple, a circu it has a gate G having a fan, oul equ.1 10 16 .00 s tandard load . . T he delay through th i, gate, including Ihe delay c omponent based on the standard loads d ri,'en, is 0.406 n . . To reduce this d e lay. a b uffer is added to the o utput of g ate G a nd t he 16,00 , tandard l oad. s re connect ed t o the buffcr o utpu t. Th e o utpul o f g ale G now drives just the buffer. T he delay f or this combination o f the gate a n d the buffer in s eries i< only 0.323 n s, giving a delay reduction o f ov Cr 20% , G ate G alone h a. a cost o f 2.0 while gate G p lu< the buffer h .,'c a cost o f 3.0, Thes-c two circuits illustrate a cost/performance trade off. the most common o f the u adeoffs with which a designer must deal. While t hi' example u se, two simple circuit. . c osllperformance trade-offs can be m ade at much hi gher levels in a syste m design, These trade-off' rna}' inn ucnce function al specifications for t he sySlems and Ihe implementation approach us-cd for s }'.km function . . C o nt inuing with (he simp le e xam pl e, the designer has two choices If gate G a l'mc is fast e no ugh . il should be s-clccted because o f its lower cost. O n t he o ther h and, if it is nOt fast enough, then g ate G plus the buffcr s hould be selecled. In o rder to make tn is tradeoff. we n eed t o have o ne o r more const raint. o n the design o f the circui!. Suppose that t he constraint is Ihat the maximum in put-t o-output delay 'pol""" = 0.35 n s Sin ce g ate G alone d oe, not m eet this constra in t. Ihe b uffcr must be a dded. A lternalivdy. suppose t haI the c onstraint is that the ma~j mum nu mber o f area units for the circuit i , 2.5. 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IU!"". - uo, a 'll .10 ' lill "' l SUO" ~41 SH~W 104 1 punoJ "<l l.nlU uj!.~p NI~U "';;JOI'"J'lI1l'S "W~41 N~!S"'Ia ::J[~llYNO\~VNIIWIO::J I f 1 IlldYH::J 0 t OI 31 1 t1< .ign l'ro<<dUf'< 0 1 05 ~xpres<ions in a standard form for e ach o utput, The next s tep is mu lt iple lovel optimization wi th terms shared between multiple outputs. In more sophisticated syn. thesis 1001s. optimization and technology m apping may be in terspersed t o improve the li ke li hood of meeting constraints. I t may b e necessary t o r epeat optimization and tec hn ology mapping mult iple times 10 m eet the specified constT3ints. T he remainder o f this chapt~, ill u st'"t~s the design procedure by u sing t hree examples. In the rest o f t his "'CIion, we p erform the fi rst three steps of design. specification, formulation. a nd optimization, We t hen cons id er implementation technologies and t he final two steps in s eparate " ,et ions. Th e first two example specifications are for a d ass of circuits called code con verlers. which translate information from one binary <X><k 1 0 M other. T he inputs to the ci rcuit are the bit c ombinations specified by the fi rst code.. a nd the outputs geue rate the corres po nd ing bit combination of the second code. Th e combinational circuit performs the tT3nsfonnation from o ne c ode to the o the,. The firs t code converter example convetlS the BCD <X><k to the excess-3 code for the decimal digits. The o ther r o n" crts the B CD c ode to the seven signals required to dri"e a " ,ven."'gmen t light-emini ng diode (LED ) display. The third o .a mple is t he design o f a 4bit equal ity COmpa ralOr that represents a circuit h a,ing a large n umber of inputs. I E XAMPLE 3-2 o D es ign o f a 8 C D----f(>-Eu. .... 3 C ode Con"erter TABLE .l- 1 T ruth Table f or C ode C o n .'erter Exompk! Oeet"",t Digit o , , , , , , , ; tnput ,' ", , ,, ,, 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 , 0 Oulj>ut ~ -~ ,,, , , , , ,, "" ,, ,, ,, W 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEC IFICATION: T he " "ass -3 cod for a decimal digit is the binary combination c orresponding 10 the deci mal digit pl us 3. For example, the excess-3 code for decimal digit 5 is the binary c omb in ation for 5 . . 3 = 8 . which is 1000. T he e xcess) c ode ~ as d e,irable p<Op"rties wit h respect t o implement ing decimal subtraction , Each B CD d igit is four bits with the bi ts. from m ost significant to least sig nificant, labeled A . B. C. D . E ach excess-3 digit is four bits. wit h tbe bits. from most signifi cant t o least significant. labeled W. X. Y. Z , 106 0 C HAPTER 3 I C OMBINAT IONAL L OGIC D ESIGN = C 00 00 "1 ",' 11111 '" , "' , , , , " " " ,,, '" o W _ A+IlC~BD c c A'R "' " ', "' " '" " , , , , , , "' , , , , " "' , , , , " ," , [" , ,, ,, , '" '" o Z"o '?: '" 00 00 00 , 00 Y _ CD~CD o t lGURE.l-1Il Maps lor BCD--,(}-Exce. .. 3 C ode Con>'erle, F(lRMU .....1lOtl: T he exccss.) code word is easily obtained from a BCD code word by a dding binary 0011 ( 3) t o it , T he resulting truth table r ela\ing the in put a nd OU1PU\ variables is shown in Table 3 \. NOle \ hal \hc l our B CD inpm vari ables may h a,'e 16 b it c omb in ations. b ut only 10 are li sted in tbo \ruth lablc. T he six c ombination. 1010 th,ou gh 1111 are n m lisled under \he input s, since \hcse c ombinations have n o m eaning in \he B CD code, aod we can assume I h.t Ihc)' will never occur. Hence. for the se input com bi natio ns. it d oe, nOt m aner what binary values wc assign \0 \he excess3 o utp u lS. and therefore. we can \real them as don teare c ondilion . . QPTlN \Zo\1lOtl: Since \his is four-variable funNio n. we use \he K ma p~ in Figure 310 for the io;\ial optimiza\;on of \he four output function . . T he maps a re p loned to o b tain simplified sum o!produc\s B oolean e xpression, for lhe o u tputs, E ach of the four maps represents o ne of \he o utput, o f Ih e circuit as a function o f the four inpms, T he J"s in Ihe maps are o btained direc\ly from the trut h table o ul p m columns. For c~"mple. the column u nder oUlpm W has I ', for m in\enns 5. 6. 7. 8, and 9. Therefore. the map for W muM have l"s in the squares cotTesponding to t hese mimenn s, The six don"toCaTe minterms, 10 t hrough 15. are each marked w;\h a n X in all the maps. T he optimized functions are listed in sum-of-products f onn under the m ap for each o utput ,-ariabl" T he two-level A ND-OR logic diagram for t he circuit can be o btained directly from the Boolean expressions derive<:! from the maps. We apply multiple-level optimization as a second optimization s tep t o d ctennine if Ihe gate input count. which is currently 26 (including in,-erlers). can be reduced. In this optimization. we consider sharing s ubexpression, between the four outp ut expressions. The following m~niput"tion illustrate. o ptimization with multiple _o utput circuits implemented wilh three levels o f gates; T j-C+D W - A+BC+BD " A+BTj x . l ic + IJI) + n co m nr, + BCD Y _CD + CO 2-D T he manipulation allows the g ate producing C + D 10 be s hared by t he logic for w and X. and reduc<:d the g ate input count h om 26 to 22 . This o ptimi,cd res ult is vicwe<:! as being a dequate and g ive. the logic diagram in Figure 3-11. E XAMPLE 3 -J Design o ra DCl>-to-Seven_Sq:;ment Decoder Dig ital readouts found in many consumer electronic products such as alarm d ock. often use Light Emining OiodCl; ( LEOs) Each digit of the readout S ,""C'FICATION; , w , I- v , , v ll- , I D v o H G U RE .l- 11 Logic D i.gram 01 BCD-fo----Exss-3 C od. C on'tr1cr , , 1 08 a C HIII'TER J I C OMBINATIONAL L OGIC D ESIGN aU23LfS6789 , 0-0< " ( b) " UP""lo " """""'" l ot <tior4y a FIGUREJ.1l s.~nS.tm<nl o..pIay is formed from " "" " L ED scgmeniS, ElICh K gmenl can I x UJuminalW by a digjlal UCJ)..to-4C'~n . . .,g" . . nt decoOc:r is a c ombinational c ircUli t hai a ca:pU a decimal digit in B CD a nd gencratcllh~ a ppropriale outputs for the !.Cgmcnt. o f the display for Ihat d imal digit. 1110 seven outpUiS o f Ihe decoder (n, />,~, d.~, t, g ) select Ihe corresponding segmcnll in the di'play. as shown in Figure 3-12(8). The n umeric d e,ignalion' c ho=n t o repre!.Cnl the decimal digitI a rc s ho wn ill F igure 3-I2(b). l lte BCD - I o---se"ell~gmem d ecoder h u four in pu l!, A . H. C. lId D ro r Ihe BCD digil a nd K~en oulpUIS,,, t hrough g, for c onlrol hllg l he !.Cgmell"" sigl,aJ. A FCIIIWlIUI T1IQH: 1 lte llUlh table o f t he combin.oliooal circuil ; . ~SIe4 ill Table 3 -2 O n lhe ~ o f I ~gurc l-12(b). e ach B CD digil illuminates the p roper SCl""'nL5 for I Ix decimal display. For n a mple. B CD 0011 oorresp 0II<15 \ 0 decimal 3 . " hich is displayed a. !.Cgmcn . . ~.I>, c. d . a nd g, T he Uuth lable " ",umes Ihat a logic I " gn al illuminates the SClime nt and a logic 0 signal tmllS the !.Cgment off. Some sc"en-o.cgment displays o peral. in revelS" fashion a nd a re il luminated by a logic 0 signn l. For Ihe.., displa ys. the " 'ven o urpu . . must De complemented. The six binary c ombinalions tOtO Ihrouglt 1111 have nO meanin8;p BCD. In , he previo . .. example. we ass;gned these cornbinali . .... 10 d oo't-are conditions. I f ,,"'e d o 11M: s ame h~re.lhe design ,,"iU a T A8l.E J. l Trull> Tobie for BC I ~-sep.m , ~ , , , , , , , , , BCD Inpu. ,, ,,, ,,, ,, ,,, ,,, , , ,, ,,, ,, A ll " 'ber in"",~ s .....-Soogme nl D eoodtr , , , ,,,,,,, ,,", , ,, , , , ,, , , , , ,,,,, , ,,, , ,, , , ,,, , , ,, , ,, most li ke ly p roduce some a rbitrary and m eaningless displayi; for (he unused combi nation . . As long a , these combina(ions d o n O( occur. we can use t hat a pproad to reduce the complexity o f (he com w(er. A s afer choice. tum ing off all the segments when a n yo ne of (he unused input combinations occu rs. a"oids any spurio us displays if any o f the com bin ations occurs. but increa"", the conve rt er comp lexity. T his choice can be ac.;omplished by assigIling 311 O's to minterms 10 through 15, Op nlollZ,o,TION: Th e information from the t rut h table can be t ransferred into seven K_maps from w h ;~h the in itial optim iZc<l o utput functions can b e d erived , The plot_ (ing o f the seven fu nctions in map form is lell a . a n e ~ercise, O n e possible way of si mplifying t he seven f unct ions resuhs in the following Boolean func(ions: a - AC+ABD +B CD+ABC b oo A B+ACO + ACV +A BC AB + AD + BCO + AB C d .. ACD + Aiic + i i CD + Aii c + ABCD e _ ACD + l i CD t .. ABC + ACD + ABD+A/IC g- ACD + ABC+AlJc+ AH c Independent implementation o f th~'Se seven functions r equire. 27 A ND g ates and 7 O R ga(e .. lIowever. by s hari 1lg t he six produc( te'm s CO m mO n 10 (he d iffertnl o utpu l e ,prc ss ions. the n umber o f A ND gat"" can be reduced to 14 along with a s ubstantial sa"i ngs in gate input c ount . For exam pl e. t he t e,m B CD occUrs in a.c. d , a nd ~. T he <)u tput o f Ihe A N]) g ate th .t implemen tS thi s p rod UC term goes t d irectly to the inputs o f the O R gates in a ll four function . . For th i' func(io n, we s top o pt imization with (he two level circuil and share d AN ]) gOles. r eali, in g th aI il mi ght be possible to red uce the g ale inp ut c ount even f urther by a pp lying muhiple level o p timization. The BCD-Io-seve,, -segmenl d c-co<le, is called a d ecode, by m ",1 m .nufac _ l uras o r integrated circui(S bc~a use it decodes a binary code fo r " d ecimal digi!. Howe,'er, it is a ctua ll y a code converter that converts a fo urb it decimal code ( 0. seven_!>i, c ode. The w o,d ""decode,"' is usually r.:sen'cd for another t)'PC o f circuil, presented in the next c hapter. In gen era l, t he lot.1 n u mber o f g ates c .n b e r educed in a multiple_OUl put combinational circuil by using c ommon lerms of Ih e OUlp ut f un ction . . T he maps o f the o utpu l functions may help find t he commO l\ terms by finding ide nt ical implican(s fr om two Or mOre maps. Some o f the COmmOn terms may n ot b e p rime implicants o f Ihe ind ividual function . . T he d esig"er " ,ust be inventive a nd c om bin. s quares in the m aps in such a way as to creale c ommon term . This ~a n b e d one m ore f o, ma lly by using a p ,oced llre for s im p li fyin g m u lt iple'OUlput functi ons. T he p rime i mplicant. a re defined nol only for each individual f unction, hut 110 C HAVTHl I I C OM III N ATIONAL L OGIC D ESIGN 0 ~II "'ese ! mplt~ nto a l"" for p ossible c ombinations o f t he o ul put functions. p J me a re f ormed by u sing t he A NO O p"rator On eVNY p ossible n onempty subS<'1 o f I he OUiput funelions a nd finding Ihe p rime i mplicanls o f e ach o f Ihe resulls. Using Ihis e nli re s et o f p rime i mplica nt s. a format s election process c a n be u $&lto find the o ptimum t wo-le"el mulliple OUiput c ircuit. Such a p rocedure is impl cmented in " arious forms in logic si mplification . .,ftwarc wilhin logic . y nlh esi. t ools a nd is Ihe m ethod u sed to o blain t he e quations in E xa mple 33 , I E XAMPLE: J .4 O e.illn u r . 4-bil Equalil )' C umparalur SPE CIFICATION: T he i nput s 10 t he circuil consisl o f l wo 'cetors; A(3:O) a nd B (3:O). V eclor A eon5ists o f f our bils. A (3). A(2). A (J). a nd A(O) ..... ilh A (3) as Ihe most sigllificant bil. Vector B h s a similar d escription ",jlh B rcpl"""d by A ,The OOlput uf the circuil is a s ingle bil v~riable E, O ut put E is e qual to I if A and I:l a rc e q u.,l a nd equal to 0 if A a nd B a..., un equa l. FOftItULATION: Since Ihis circuit has e ight inputs. use o f a trUlh table for f onn u_ l alion is i mpractical. I n o , der for A a nd D 10 be e q ual. I he bil values i n e ach o f Ihe r espec tive positions. 3 d uwn t o O. o f A a nd I:l muSt be e q ual. If all o f Ihe bit p osiliuns fu, A a nd B c ont ain eq ual " alue. in e very posilion. t hen E _ I: o therwise. E ~ o. O mIOlZATION: For ! his c ircuil. we use i ntuition t o immcdia!cly d evelop a mul ti ple level e ireuil using hierarchy. Since c omparison o f a bil fro m A a nd t he c orresponding bit from B muS\ b e d one in e ach o f I he bi t positions. .... e c an dc<:omposc Ihe p roblem i nlo f our [ hil c omp a rison cireuil$ a nd a n a dditional d r_ e uil t hat c ombines t he four c omparison ci, cY;! OUlpU," t o o btain E. F or bil p osition i. ..., d efine t h. circy il o utput E, 10 b e 0 i f A , a nd 8 , h ave t he SlI me values a nd E, _ I if A , a nd 8 , have d ifferent v.lues. T his c ircuit c an be d escribed by t he e quation E, _ A i 8, +A i Bi which has t he circuil diagram s hown in I ~gu re 313(a). By using hierarchy a nd reuse. we c an emplo)' fOOf c opies o f Ihi$ eircuil. one for CB<' h o f Ihe four bits o f A a nd H. O utput E ~ 1 o nly if all o f t he , v .lues a re O. T his c an b e d escribed hy t he e quanun E _ ,, + ,+E, + , a nd has I he d iagram given in Figure 3-13(b). Both of the circuit' giYCn a rc o ptiilium two level circuits. rne ,we rail circuit c an be described hicr;' rchically by t he d iagram in f igure 3- I3(c). 3 -4 T ECHN OLOGY M APPING T here ; lTe t hree p rimary .... ay. uf d c.igniog VLSI circuits. In filII cII"om design. an e nl ire design o f Ihe chip. d o . .n t o I he s ma li eSI d etail o f Ihe l ayoul. is p erformed , 3_4 I TedltlOlogy Mopping 0 I II " ~, ' " E, ,.j ME ~ -lMX 1'.0 ME E "j o F I GURE 3 - 13 Hie rarchical Diagram f or. 4-bit Equalily c omparator Since this proce ss is very e~pens i ve, c ustom design can be justified only for d ense, fa st ICs thaI a re likel y 10 b e w id in sizable q uant it ies. A closely r elated t echnique i sswndard c dl d wgn, in which large p an s o f the design ha"e b een p erformed a head of time or, possibly, used in previous designs. The p redesigned parts a te c onnecied t o form the Ie design. Thi s i ntermediatecost m ethodology gives lower density a nd l ower performance than rul) custom design. The third a pproach t o VLSI design is the use o f a gMe areay. A gate array u se, a r ectangular p attern o f g ates fabricated in s.ilicon . T hi' p attern is r cpeated t housands of t imes, s o t hat the ent ire chip c ontain' identical gates. D epending o n the technology used, p anern a rrays of 11))) 10 mill ions o f g ates can b e f abricated within a s ing le I e. T he application o f a gate a rray r equires that the design specify how the g ates arc interconnected and how the i nterconnections a re r outed. Many s teps o f the fabrication process a re c ommon a nd i ndependent o f Ihe 6nal logic functio n. T hese s teps a rc e conomical, since they can be used for numerous different design . . In o rder t o customize the gate array to the partic ul ar design, additional fabrication step~ a re required t o i merconne ct the gates. D ue t o t he c ommonality o f fa brication s teps a nd ability to sliare the results o f these s teps with m a ny d ifferent design'>. this i , the lowest cost melhod among Ihe fixed implemenlat ion tec hnologies For s ta ndard c e ll a nd gate arra}, 1echnologies, circuits a re c onstr ucted by i nterconnecting cell . . The collection o f cells avai lable for a given implementa tion t echnology is called a cell l ihary. In o rder t o design in t erms o{ a c e ll 1 12 a CHAPTE<.. l I C OMBINATIONAL l OGIC IJES1GN library, it is necessar)' to characterize e ach of t he c e ll s (i .e . p r ovide a d eta !leJ specification o f the cells for use by t he d esignerl . A l ibrary o f characterize<i cells provides a foundation f or t he technology m apping o f ci rcuits. Coupled with the library is a technology m apping procedure. [n this sectio n. W cons;der e technology m apping p rocedures f or cell libraries c o nsisting o f ( I) single gate types such as N AND gates. a nd ( 2) mul tiple g ate Iypes. Technology mapping may focus on a n umber o f the dimensions o f t he design space. particularly On cost a nd p erforma nce , For simplici t y. o ur p rocedures focus o nl y on o ptimizing cost. F urther. these procedures a re r udimenlary versions o f technology mapping algorithms used in o ompuler-aidcd design lools and are suitable for manual applicati on t o only the simpleSI o f circuilS Nevertheless. t hey give u s some insight into how a design using A ND gales. O R gales. and i nverle", can be t ransformed i mo cost-effeClive designs us ing cell types s upporl ed b)' available i mplementation technologies Cell S pecific ation Specificalions fo r cells used in s tandard cell and gale a rray designs ty pically have many compOnents. Typical c omponent. i ndud" 1M: following: I . A scbematic o r logic diagram for the function o f the cell. 2. A specification o f the a rea the c dl occupies. often normalized to the a rea of a small cell such as that o f a mi n im um a rea i n"erter. 3. T he input loading. in standard load s. t hat each in pul of a cell presenls t o t he output driving it. 4. Delays from each inpul o f a cell 10 each OUlPUI o f a cell (if a palh f.-om the inpul to OUlPUI u ists). including the effect o f Ihe numb<'r o f Siandard loads driven by Ihe o utput. S. O ne Or m ore 1em j>l ates for the cell for use in performing technology mapping. 6. O ne or more H DL models for the cel l. If the lools used provide a uto mated la)'out. then the following addilional components a re also incl uded in the specificalion; 7, A n integrated circui t layout for the cell. 8. A fioorplan layout s howing t he l ocalions o f the inputs. o utputs and p ower a nd g round c onnections for the cell for use d uring the cell inicrconncetion process. T he firsl five compOnents listed arc included in a simple lechnology library of c ells," the nexl subsec ti on. Some o f these c omponents are d iscussed in mOre detai!. L ibrarie s T he cells for a particular design technology a rc organized ;nlO o ne o r m ore libra,ies. A /obm,)' i , a co ll eclion o f cell specifications. A circuil that initially consislS o f 3_'1 I To<hnniogy M.pping 0 I II A ND. O R a nd N OT g ale, is OOnve r led by Icchnology m apping 1 0 o ne I hal uses only cells from Ihe a pplicable libraries. A very , mallicchnology l ibrary i , d escribed in Table 3- 3. T hi' l ibrary contains p rimiti'. inverting g ates wilh f an.ins up 10 f our a nd a single A O I circuit. T he firsl c olumn o f Ihe table contains a descriplive n amc for Ihe cell and Ihe second column c ontains Ihe cell schematic. T he third column c ontains Ihe a rca o f Ihe cell n ormalized t o the area o f a m inimum inlierter. A rea c an be used a s a very simple m casure o f Ihe COSI o f t he ceiL T he next column gives Ihe typical load Iha! a cell i nput places o n t he g ale driving it. The load values a rc n ormalilcd 10 a q uantity called a s iandard lood whi<h in Ihis case is the c apacilance presented 1 0 the driving circuit by t he inpul o f an in"erter. rn t he case o f Ihe cells given. the input l oads a re aimOSI all Ihe same, T he fifth column g iv", a simple lin e . .. e quation for calculating Ihe typi<al input-to-output delay for Ihe cell. T he variable S L is Ihe . u m o f all o f Ihe standard loads p resenled by the inputs o f cells d ri"cn by the cell output. It may also contain an e .t imale. in Sia ndard loads. o f Ihe capacilance o f t he wiring connecling Ihc c e ll OUlput 1 0 Ihe i nputs o f o ther cells. This e qualion illustrates the n ot iOn Ihat cell d ela)" c on,i" o f s ome ~~ed delay. pl us a delay Ihal is d ependent u pon Ihe c apacilance loading o f Ihe cell as represe nted by SL. Cell delay c;llculation is i llustraled in E xample 3-5. E XAMPLE 3-5 CMk" lati"n o f C e ll Oe l ~y T h is e xample i llustrates Ih~ effect " f l oading o n cell delay, A 2 NAND o utpul drili~$ Ih~ following c ell" a n i n'encr. a 4 NAND. a nd" 4 NOR n ,e , um o f I he s tandard l oads in [hi s c ase is S L _ 1.00 + 0,95 + 0.1>0 ~ 2.75 With this " aluc. the delay o f t he 2 NAND d ri"ing t he cells specified is Ip ' " 0 .05 + 0 ,014)( 2.75 m 0.0I!9 n$ T h e fInal column o f Ihe lable gives templates for the c dl funCli<1U t hat use o nly basic fu nctionS as c omponent s. In I hi. case. t he b asic f unction. a rc a 2 in put N AND g ale a nd a n in\'c ner. Use o f t hese b ask fUnClion t emplales p rovides a way o f r~preSl:nting e ach cell funClion in a " standard" form. A s illu<traled by l he 4 i nput N AND a nd K OR cells. the h asic function l emplate for a cell is not n cce",or ily unique. II s hou ld be nOled Ihal these diagrams r epre se nl only a n~IJist. n ol a ctuallocalion. o rientati"n. o r i nterconneci la)'out. F or e xamp le. consider the tern p l ~l<: f or the 3 NAND. I f t he left N AND a nd the foll<>wing i n,'erler were c onnecled 1 0 t he t op i nput o f Ihe righl NAND. i nslead o f t o its ool1om in puk Ihe l empl.le w ould b e u nchanged. T he value o f t hese l~mpl"le S will b eeome a pparent in Ihe nexi section o n mapping t echniq ues. Mapping Techniques I n Ihi' subsection. we c onsidcr t he m apping process for fixed c eillechnologies. A c om'cnicnl way 1 0 i mplement a B oolean f unction with N AND g .les is 1 0 o blain t he oplimized B oolean funClion in l erm, o f t he B oolean o perators A ND. O R. a nd 11 4 0 CHAI'TI'R I I C O MU'NATIONAl u:x:.; IC DES IGN a T i\.BU 3-3 E umplc C eU Ubo. ,. ro r Tcdo.oIogr Mappin, .- I.,. -"'" 0001"-, '".,., ,- 1'0'._ S <k-.o, ;, ' 0' N . ... oII . . d In . . " . . { - '00 '00 M il" SL lNAl'iO : 0- W '00 (1.01." i\.L l SAl'iO D- ,~ ' 00 . NA ND 0- ~ '" ( lUll. S l 2."0 11 D W ' 00 + )1'010 11 D- ~ '" . 0.011" SL ~, A . .. , "-<. .. ~ T. ... o. -j)o- = : D:D-{>oD- ~ 0.0.1 " SL = ~ ~i>D- ~ o. n.ol !" SL '" p.... ' -J>. "~ - yo -<> <NOR 2-.1AO' 0- B>- = '" + 0.011 " SL ) 0, -<>?"' V "' 2.1.'1 '" om 0.019 " $ L got>- .V 3_4 I Te<hnology Mopping 0 t iS N OT a nd then m ap t he function to N AND logic, The c onversion o f an a lgebraic expression from A ND. O R. a nd N OT to N AND can t>e d one by a si mple procedure t hat chan g'" A ND-OR logic d iagrams to N AND logic diagrams. T h e same c onyersion a pplies for N OR gates. G i"cn an o plimized circ uit t hai cons ists o f A ND gates. O R gales. aod inverters. t he following p rocedure p roduces a circuit using e ither N AND ( or N OR) g ates with u nrestricted g ate fan -in: L R eplace each A ND a nd O R gate with the N AND ( NOR) g ate a nd i nverter e quivalent c ircuit, shown in Figure 3- 14 (a) a nd ( b) , 2. C a ncel all i nverter pairs. 3. Without changing the logic function. (a) ~pus h - aU inverters lying t>etween (i) eit her a ci rcuit input o r a driving N AN D (NOR ) gate o utput a nd (ii) the - - (0) M.pp;t\ to " ANn I " " (b) Mopping ' " NOR 3" '" - -po-[)o- - -- (d) C'r>e<lli O in "",, , ! 'Om o F IGURE 314 M awing " f A ND G ates. O R Gate, and In"erters t o N AND ga tes. N OR gares.and Inverte r< 1 16 0 CHAPTER} I COMIUNATIONAL LOGtC DEStGN d riven N AND(N O R) g ale inp uts to,,'ard the driven N AND(NOR) g ate input s. C ancel pairs o f i n,'cr ters in s erie, w henever poMible during th is ' tep, (b) Replace inverters in parallel with a single in verter t hat d rive, all o f t he o utput, o f the p arallel inverters. ( c) R epeat ( a) a nd (b) u ntil t here is at most o ne in"crter b etween t he circuit input o r d riving N AND(NOR) g ate o utput a nd the a nached N AND(NOR) gate inputs. In Figure 3 - ]4 (c). t he rule for pushing a n i nverter through a " dot" is given , T he in verter on the i npUllinc 10 t he d ot is r eplaced "'itli inverter,; o n e ach o f t he o utput lines fTom the d ot . T he c ancellation o f p a in; o f i m'e rters in Figure 3- ]4( d ) is based o n t he B oolean . Igcbr"k identity X=X T he next e xample illustrates this p roced ure for N AND gales. E XAMPLE 3-4 Implemen tatio n . . ilh N AND G ales I mplement the following o p timized f unction wilh N AN D gates, F - AB -+- (AB)C -+- (AB)D -+- E The AND, O R , inverter i mplementation is given in Figure 3-15(a), In Figure 3- 15 (b). ' Iep 1 o f t he p rocedure has b een applied replacing each A ND g ale a nd O R gate wilh its equivalent circuil u ,ing N AND g ates a nd i nverters from Figure 3 14(a). l abe ls a ppear on d ots a nd in vene . . 10 a "ist in the explanation. In ' lep 2. t he , " , c ," , ,., , ~ , ----- 3 .---~ , _ ______ J ,., I4 ' , , -~--' ,,) o '" n G UR3t S Solut iOflt o E~. mple ) 6 , , Pl-c , , , J_4 I Ted",ology M,,'pin~ a 1 17 i n"erler pairs (1) 2) and (3. 4), cancel. giv ing dirccl connections betw""n the correspond in g N AND g ate. in Figure 3- 1S{d). As shown in Figure 3-15(c). inverter 5 i . pushed through X and cancels " ith inverters 6 a nd 7. respectively. T hi. giv es d irect connections between the corresponding NAND gat es in Figure 3-1S{d). N o further steps can b e applied ,ince invertcrs 8 and 9 cannot b e paired with o ther inverters. and nmS! r emain in the final m appl circuit in Figure 3-15(d). The next example illustrate, this p rocedure for N OR gates. _ l eXi\MPt[ 3-7 1mplenlcntalion " ilh N OR G .le. Im plement Ihe same optimized B ooie.n function used in Example 3-7 with N OR gates: F _ A 8 + (AB)C + (AB)D + E T he AND. O R. in,'ertcr implementalion is gjvcn in Figure 3-16(a). In Figure 3 16(b). step I of Ihe proced ur e has been applied rcplacingeach AND g"le and O R g ale with its equivalent circu it using NOR g~tc. and inverters from Figure 3 14(b), Labels appear on d ot. and inverters t o assist in the expl"n"li"n. In s tep 2. inverler I can be pushed through dot X 10 c"ncel wilh inverlers 2 and 3. respectively_ The pair " f i nverte" m, t he D inpul line caDcel as well. T he s ingle i mwtcrs on input linesA. B, and C and outpul1ine F must rcmain.giving the final mapped circuitlh~1 appear'$ in ~igure 3-16{c). In e .ample 3_6. the gate input C<:>&t <>f , be m apped circuil is 12. a nd. in E xample 3-7. Ihe gat~ i npul cost i, 14. so the NAND im plemenlalion is less costly, A lso. the N AND implemenlalion in volves a maxim um o f t hrec gales in . .,r ies while t he N OR implementa ti on h a,,, m ~x imu m o f fiv~ g ates in series. D ue 10 the longer s erie. o f g atcs in Ihe NOK circuit. t he maximum delay from . n i npul change 10 a corr~sponding o utput ch;onge is likely t o be longer. In the pr~C(;ding p rocedure a nd e xample" the mapping t "'8el consisl~d o f a single gate type, e ither N AND gal<: s <>r NOR gales. T he following p rocedure han_ d le. mu ltiple gat<: Iypes' L R eplace each A ND a nd O K gat~ Wi1 h an optimum e q uivalent circuit consist_ ing only o fl -in put NAND gate. and inverlers. 2. In eacb line in Ihe circuit al1ached 10 a circuit input. a NAND gal~ input. a NAND gate out put. o r a circ "i l OUlput in which no inverter appears. inserl a serial pair o f in,crlers. ) , Perform a replacemenl of conncclions of NAND ga!"" and inverters by Ihe a,'ai lable library cells such t h"t Ihe gate input cost which re,uits within fanout free sub.:ircuits is oplimized. A fan -OI,I free s "bcirc"it is a circ uit in w hich each g ale oU'P'" drive. a 'ingle gate inpul , (This s tep is not c overed herc in detail due t o its complex it y. bu t is p rMidcd o n the course website with an example. The lemplaleS shown in lhe risht co lu mn o f Table ) _ are used t o 3 malch connecti"ns " f N AND gales and i n,'er1e" t o a ,'a il able library cell .. ) t t8 0 C HAPTER J I C OMBINATIONAL L OGIC D ESIGN c , " (., (e) o F IGURE 3- 16 S<:>lu tion to Example 37 4. ( a) Wilhoul c ha ngin g the logic function. ~ push" all inverters, lying b etwun (i) a circuil input o r a driving gate oUlput a nd (ii) t he d ri"en g ate input s.. t oward the d riven g ate i nputs C an cel pairs o f inverters in series w henever possible d uring this step. (b) Replace i nverters in p ara llel with a single i n"ener l h.1 d riws all o f the o utp ut , of t he p arallel i nverten. (e) Repeal (a) and ( b) u ntil t here is a t mosl one i nverter between the circuit i nput o r driving g ate o ut put a nd t he a ttached driven gate inputs.. This p rocedure i . o ne o f t be f oundations for lechnology m apping in c ommercial synthesis lools.. T he i ntermediate replacement o f l he initial circui t g ate, with only 2 input N AND g ate, . nd i nverters breaks the circuil u p i nto small piec in o rder 10 p rovide the maxim um fl exibility in mapping cells t o achieve an opti. mized result. Example 38 shows an i mplementation a pproach using a small cell l ibrary, 3 _4 I t :XAMPLE 3-8 Implementation "'ith ~ T&hnology M'rping 1 19 0 Small Cell Library [ mplement the same optimized Boo[ean function u sed in Examp[es 36 and 37 F - AB + (AB)C +(AB )D + E wilh a o elilibrary containing a 2-inp ot N AND gate, 3inpot N AND g ate, a 2 -input NOR gate, and a n inv ener. T he A ND. O R. i nv~rter implementation ; . given in Figure 3-17 (a) , In f igure 317(1)). steps 1 and 2 o f the procedure h aye been app li ed . Each A ND gate and each O R gale has been replaced wi th ilS equivalent circuit made up of 2-input NAND ga1es a nd in,'erters. Pairs of inverters have been a dded to the internal li ne, without inverters. D u e to lack o f space, t he pairs o f in"erters o n I he inpub a nd o ut puts a re not shown. App[ication o f I lep 3 resuits in t he mapping to t he cells from the oe llli hrary shown in Figure 3-17(c), The hl ue outlines e nelow connections o f N AND gates a nd inverters, each of which is to be replaced by an avai[able cell using the templates in Tab[e 3-3, In t his case, all o fl he a .. ailable ce ll s h ave been lISte d a t [east once, Applicalion o f s tep 4 cancels o u t three of t he inverters, giving the fi n al m apped circuit in Figure 3--17(d), The " ,[ulio n fOT E , am p[e 3-8 has a gate input cost of 1 2.compared to costs o f 12 and 14 for E xample, 3-6 and 37, re'pecli,'ely, A lt hough the C06 t in E umples 36 and 3-8 are ide ntical. it should be noted 1hal the cell libraries d iffer. In partkular, Example 3-6 benefits from the use of a 4-input NAND gate that is unavailable in Example 3-8. Without this ce ll , 1he solution wou ld cost t u'o addition al g ale inputs. Th us, the use of a m Ne d iverse ce ll libra!)' h as p ro,;dcd a COSt b enefit. , " , , " , / tf< > , ,., , " , " " > " , " " ,,' o " IGURE 3-- 17 Solution t o b ''''ple 3--8 , ( 0) 1 20 0 C HAPTER 3 I C OMElIN!lTION!lL l OGIC DESIGN T h p rov id e cont in uity wit h examples in e arlier >ections o f this c hapter, t he following example shows the mapping o f the B CD - to-Excess -} C ode C onvener for an e xpand ed cell library_ E XAMPLE 3-11 Te<:hnology M appin, r o. B CD-Io-Eucss-} C ode C o".. . r tu T he fi~"1 r esult o f the technology mapping for the B CD-to-Excess-3 C ode e on ,' crier is given in Figure 3- 18. T he orig in al A ND. O R, i nverter logic d iagram appeaTli in Figure 3- 11. a nd t he cen library used i , gi" en in Table 3-3. T he o ptim ization has r esulted in t he Use o f the follo,,'ing ce ll s from I hat library: in wrtccs_ 2input NANDs. a 2 -input N OR. a nd a 2-2 A OI. T he g ate in put cost o f t he m apped circuit in E xamp le 39 is 21 . wi th a g ale input C():\; l o f for lhe o r iginal A N D. O R, N OT circuit. The o p ti mization procedure. aside from locally mi nimizing inverters. ,,'orks s epara tely on t he various p arts o f t he circ uit. T hese p "rts a re separated by g ate fan-oUis in t he o r iginal A ND-OR circuit. T he selection o f these p oints ill t he oplim iw t io ll Can d fetl l he o pl im .lily o f t he tinal resull . In the ca se o f t his circuit, a d ifferent o r iginal circuit may yield a b ener o pti mi "atioll_ 111 genero!. t hi s problem o f s cp",,,le o ptim ization and m"ppi ng is hondled by using combined o ptim ization steps a nd m apping s teps in c ommercia l logic optim i ~ation t ools. n < ~ ADVANCEO TE CHNOLOOY U ....... N(l Tnis s upplement On t echnology m apping, detailed e xamples ill ustrating t he m app in g pr()Ced ure for ge<ICral e e ll l ibr.ries, i, available On the Comp;<nion Website for the text. ~ including , ~ w ~ " c '1 I P, ~ t>-' , o F IGUKE 3- lg Te<ohnology Mappi ng E nmple' B CD- to--e, ,,, . . -3 C ode Con vetter 3_S 3 -5 I \!u;fKotioo, a 12 1 V ERIFICATION In this seet;on. m anual logic anal)si. a nd c omputer s imul ation -based logic analy sis a re c o nsidered. b oth with the gool o f v~rific a t;on o f circuit f unction (Le .. d etermination o f w hether o r n ot a g iven circuit i mplement. its speeified function). If t he circuit d oe. n()l m cel its spc:cifieation, t hen il is i ncorrect. A s a conSC<Juence. verification plays a vital role in p reventing incorrect circuit d esigns from being manufactured a nd used. Logic anal}'sis a lso can b e u ",d f or o ther p urposes. including r edesign o f a circuit a nd d etermina tion of the f un clion o f a circuit. I n o rder 10 verify a c ombinalional circuil. it is e ssent ial t ha I Ihe specifica_ tion b e u nambiguous a nd corrC<'t . A s a conS<:'1ucnce. specifications such as t ruth tables. B oolean e quations. a nd H DL c ode a re mOSI u ",ful. Initially. ..c c umin. m anual "crilicalion by c ontinuing " ;Ih l he design e xample. " 'c i ntroduced in Ihis c hapler. M anual L ogic A nalysis Manual logic a n alysis consisls o f finding Boolean equations for tbe c ircuil o utputs or, addilional1y. finding Ihe t ruth table fQT t he circuit . The a pproach taken here emphasizes finding Ihe equal ions and then using lhose e qual ions 10 find Ihe Irmh lable. In finding Ihe e qualion for a circuil. il i . o ften convenienl to break up the cir_ cuit into subcircuil$ b y defoning i ntermedi3te v ariables.1 . . lecled poiOlS in t he circuit. P oint. Iypically selected a re tbose a t which a gale output d ri"es two o r m ore g3 te inputs. Such points 3rt: o ften referred to as i an -O"I p o;m. F"n -out p oint. from a single i nvener o n an inpul Iypically would not be selected . T he delerminalion o f logic equalions for a circuil is illuSltaled using l he U CD-t o-E"oess-3 C<Xk Con vener circuit designed in previous "'Clions. E XA;\IPLt: ~IO M.nu~1 V~ritk~tion o r RCD-to-t;.~3 C ode Con"~"er Pigure 3_ 19 s how. (8) Ihe original lruth lable specificalion. (b) lite final circuit implemcnlat ion. a nd (c) an i ncomplete trulh l able t o be c ompleted from Ihe implementation . "d Ihen c ompared 10 Ihe original truth lable. T he I rmh t able val _ u e. a re t o b e d etc nni ned from Boo tean equations for W. X , Y. a nd Z d erived from I he cireuil. The point T l is . .! ecled a , a n i mermediale variable I n simplify Ihe analysis: TI . . C ..- D .. C ..- D IV . . A (TI8) . . A ..- /J Tl - X " ( B'TlHB'C'D) " B Y _ CD..-CD _ CD+CD Z~ D -n + BC'D 1 22 C HAPTER l I C O MBIN ATIO NAL L OGIC DESIGN 0 Inpu' :Pot 0 u'1"'. OCO E.xc< . . 3 ,, ," " ", """, , C0 ,, , "" , _w H , ", " , ", , ", ", c, "" " " " " "1 , """ """ "" "", " "", " , " , ttr>.J ~ r~ ,.) o F I GU RE J - l9 Verilicali",,; B CD-to-.-bce,,3 C ode Convcn t r Subsliluting {he e~p r ess i on for T ! i~ t he equahon~ for W ~nd X , we h a"e W ", A + B(C+ D ) .. A + IJ C+ H 0 X .. Ii ( C + D)+IJCD . . 7 iC+HI)+RCD E ach 01 {he product lerms in {he four OUlpul ~ q u a{ions ~"n be m apped 10 ] 's in lh~ lrulh lable in Figure 319 (e), T he mappings o f the 1 ', for A. Ii C. BD. CD. a n d D a re shown. A fter the remaining p roduct terms a r ~ m .pped 10 1'$, {h e b l.n k entries a re fillcd wi,h O' $, T hc new lrulh table in t hi' case wi ll match the original o ne, verifying thai {he circuit is corrcc{ ,~ . LooK: ANALYStS ~ '(1 ,i, supp lem.n{, in duding additional logic anal ys is techniques a nd examples. is availJble on the Companion Webs ite for Ihe {exL Simulation A " alternative t o m anual verifica'ion is the use o f com puter si mul ation for verifica tion. Using a c omput er permits truth {able verification t o b e d o ne f or a s ignificant ly la rger n umb", o f variables a nd g.reatly reduces the tedious analys is effort required, Since sim ulation uses applied va lu e .. if pos< ible, it is de~i r able for thorough v~r i r, . cation t o a pply all ]X>'>S ib l~ i nput c ombinations. The next exa mple illustr ate, {he u se o f Xilinx ISE4.2i F PGA developm~n{ {OOt$ and X E [ I Modelsim simu lator t o verify {h e B CD- to-Excess-3 C ode C o nvener usi ng.1I possible i nput combination, from the Ifuth {ab le. }.oS I V.ri/ico<ion E XAMPLE)'lI Simulation-base<! Verification o f BCl>-to-E~.,..,...3 0 12.1 C ode C(ln~el1er f igu re 3-19 s hows ( a) the o riginallruth t able specification. a nd ( b) I he final cir_ cuit imple mentation o f the BC D-t o- Excess 3 Code C onvener. Th e circuit i mpleme ntation has b een e ntered i nto Xilinx ISE 4.2i as the schemalic shown in f igure 320. Since there are no A Ol s available in the symbol library. t he A OI has b een m odeled with available symbols. In addition t o e mer ing Ih e "" hematic, the inpUl combinatioM gi"en in f igure 3 19(a) have also b ee n e ntered as a waveform. These input w avdorm s a re given in the I NPUTS sect ion o f the s imulation out put shown in Figure 3 -21. T he s imulation o f Ih e input waveform s a p plied t o the eir cuit p roduce. the o utpul " 'avdorms given in the O UTPU T secl;on. Examining e ac h inpUl r o mbination a nd the c orres ponding out pu t c ombin at ion r epresented by the wav eform s. we ca n manually verify w hether the o UlPUI S malch the original t ruth table. Beginning with (A.H.C.D) ~ (0.0.0,0) in th ~ inpUl waveform. we find thaI the r orresponding QUIPUI wa .. d orm re presents / W,X. Y .Z} _ (0,0.1. 1). C on ti nuing. for (A.B,C.D) ~ (0.0,0.1). th e values for the OUIPUI waveforms a re ( W.X,Y ,Z) _ (0,1.0.0). In b olh cases. Ihe values a re c orrect. This process o f c hecking I he waveform values against the specifIC stion ca n b e w nl inu cd fo r th e r emaini ng e ight i npul c ombin.tio", t o r omp lele the verification . , I SV N M<D2 N ANDl "- " , " , v I~' V , N ANU2 v I NV '" NA!<Dl - SANDJ , ------------,, , , AND:! Lr- , , , , , , ~1 , , , , ' AI<D:! A OI: '------------o INV NO It ~ < , ~lG U Rf: ). 2(I Scllcmo'N: fo< SimnJ.,ion o f B CD-,o-u.,.,...3 rode: Con""fi<r 1 24 0 C HAYfER) f C QMl:IINATIQNAL L OG IC D ESIGN O [JT P!J['S , w , , , o " ,. tOO " ' F IGURE3-:1 Example 3 10: Simul. . ion R "ults---8CD-to-E,ce . .3 Code C on'''rler .a ~ VfRtR<:ATlOH This supplcmcnt. c ontaining a dd it ional verification techniques a nd examples, is aoailable o n the Companion WeMite for the t" ~t. AOV . ... (:EO 3 -6 P ROGRAMMABLE I MPLEMENTATION T ECHNOLOGiES Thus far, we have introdured implementa.ion tc<;hnologies that are fi xed in the se n se that thcy arc fabricated as integrated circuits o r by connecting together integrated circuits. In contrast. programmable logic devices (PLDs) a re fabricated with structures that implement logic fUlICtions and structures t hat are used t o c o nt rol connections or to store infonnation specifying the actual logic function, implomented. These latter structures require programming. a hardware proced~re t hat determines which function$ aT~ implemented. The next three ,ubsections d eal with three types o f simple programmable logic devices (PLDs) : t he r ead.only memory ( RO M), the programmable logic array ( PLA). and the programmable aTTay logic (PAL'" ) de,'ire. In a Companion Website supplemenl, t he more c omple, fieid-pTOgra mmable gate array ( FPGA) i , discussed and illustrated . Before treating PLDs. we deal with the , upport ing programming technologies. In PLDs. programming technologies are applied to ( I) est"blish or break imerconneclion" (2) build lookup tables. and (3) c ontrol transis tor swi tching. W~ will relate the te<:hnologies to lhese three applic:otions. The o ld e't of programming technologie<; for controlling connections i, the use o f /""<'$. Each o f the programmable point. in the PLD consists of a connection fonncd by a fuse. When a vo lt age considerably h igher t han the n orm al pow-er sup_ ply "oUage is app~ed "croM t he fuse. the high c urrent breaks the c onnection by "blowing o ut" the fu St: . T he two connection states. C LOSED a nd OPEN. arc repre.. n ted by a n imact a nd blown fuse. respecth'cly, A second programm ing tcchn Olog)' for controlling connection, is m ask p. o grammiNg. which is d one by the semicond uctor manufacturer d uring the last steps o f t he chip fabrication proce,;s, C onnections ore made o r not mode in the metal lay ers ser~ing as c ond uctors in t he chip. D epending o n t he d esired fu nction for the chip. t he . truc lU re o f these la}'ers is d etermined by the fabrication proceM. T he procedure is costly because m asb for g eneraling . he layers and custom fabrication aTe r equired fOT e ach customer. FoT t hi. reason. m a.k programming is economical onl)' if a large quantity o f the same P LD configuration is o rdered. A th ird programming technology for controlling connections is the u '" o f anlifi"~ . A s Ihe name suggeSIs. the ant ifu ", is ju st t he o pposite of a fuse. In c ontrast t o a f use. an a nlifu", r on, isl, o f a small a rea in which 1"'0 ronduC1Ors aTe ",paral~d by a material having a high resi'lance. T he a ntifuse a cl, as a n O PEN p alh before pTogramming. By applying a '"flUage s omewhat higher Ihan Ih e normal po""er supply voltage across Ihe IWO conductors. the malerial ""para ling Ih~ IWO c ond""tors is melted o r o lherwise changed 10 a low r esi' tance. T he low-resistance material r ond uCIs,causing" w nn ection (i .e .. a C LOSED palh ) t o b e formed. All three o f t he p receding connection technologies a re p "rmanen!. T he d evice. c annot b e r eprogrammed. be<:ause irre"ersiblc physical changes ha"e occurred as a resuU o f ""-vi.,., programming. ThUs. if the programming is incorrecI OT n eeds t o b e changed. the d e,ice mu.1 b e discarded. T he final p rogramming lechnology . hal can b e applied for r olltrolling c on nections i$ a single. bit Slorage d eme nt driving the galC o f an MOS "ch~n n el tran sistor at t he programming poinl. I f t he stored bit , 'a lu e is a 1. Ihen Ihe uansiS!or i , l ur ned ON, a n d Ihe connection belween ilS SOUrCe and drain forms a C L O SED p ath. For Ihe . lored bit value e<]uallO O. l he l ransi'lo< is O F F. and Ihe conne<:tion belWeen its source and drain i< an O PEN p ath. S i""" storage element conlent ~an b e c hanged c1ectron;"a ll y. Ihe device can b e easily repTogrammed. BUI in o rder 10 slOre values. Ihe p ower supply must be available, T h us.. the ' torage e lement lechno logy i . volalile; tilal is.. Ihe programmed logic i , IOSI in the .b:scnce o f Ihe poweT s upply vohage. The secood application o f programming Ie<:hnologies i . building lookup labl . .. In add ilion 10 w nlroll ing connections.. storage eiements a re ideal for b u ild ing th~ tables. 10 Ihi. ca~. t he input combinalion for the Iruth l atM i . us.ed 10 ",k-cI a slorage e lemem c ontaining the c orresponding OU1PUI value l or l he Iruth table a nd provide il as Ihe logic function output . The hardware consisls o f ( I) Ihe stoTage elemenls. (2) Ihe h ardware t o progTam values inlo Ihe SIOT'ge elemenls.. a nd (3) the logic Ihat " ,lecI' lhe slorage e lemem c oDlenl.lo be applied 10 Ihe logic function o utput Beca~ . torage e lements a re being s dected hy Ihe i nput ,alues. Ihe s10rage elements w mbined with lhe hardwaTe ;n (3) Tesemble a memory in " hleh slored d ala values a re ",Ie<:led 10 a ppear o n the memory o utpul by using a n a ddress applied t o Ihe inpuls. Thus. Ibe logic ~a n be implement ed simply by storing t he lrulh 1able in l he memory -h en.,., Ihe term look"p t abk T he Ih ird applicalion o f programming technologies is conlrol o f transiSlor Swilching. The " "",I popular Ie<:hnology is N ",d on . toring c harge o n a Hoo1ing g ale. T he l aller is localed below the regular gate wilhin an MOS lran.islor and is complelely isolated by an ;nsulaling dielectric. SlOred negative charge On l he Hoo t ing gate makes Ihe transiSlor impossible 10 l um ON. T he abscn.,., o f ' tored negaliYe ch arge makes it p<l.ible for Ihe transistor 10 lurn O N if a I II G I ~ i . a pp li ed t o il< regular gate_Sin.,., il is possible t o add o r r emo,'e l hc s tored charge. lhese technologies can permit erasure arK! reprogramming. 1 26 0 C HAPTER}! C OMHINIITIONIIL L OGtC DEStGN I I I ID ( .) COmenl;,. .. t ,ymOOi o n G UREJ22 C O<lventioo.t . nd A rray Logic S ymbols for O R G .te Two tech nologies u si ng controt of tra ns is to r switching a re called ec(JSub/t: a nd electrically emsabl~, Programming app li es com bi nations o f ,'oltagc hig h er than normal power supply ,'oltagcs to the transi.tor. E rasure uses exposure to a , tro"g ultraviolet light source for a specified a mouot o f ti m e, O nce this type o f chip has ~eo e rased. it eM ~ reprogrammed. A n electrically erasable device C, m ~ e rascd by a process somewhat s imi lar t o t he program mi ng process. using voltages higher than the normal power supply value. Since transiitor control prevents o r allo"",, a counection to ~ es tablis hed between the source an d the drain. it is really a form <>f connection control. gi\'ing a choice between (1) a lway. O PEN Or (2) O PEN or C LOSED. depe nd ing on an applied HI G H o r L OW rcope<:ti,cly. On the regular transi.tor gate. A t hird technology based 1m oontrol o f transistor switching is flash technology. whiCh is very widely used in flash memories. Flash tec hn ology i . a form <>f ele ctricall~'erasable technology t hat has a v .riely o f e rase options includ ing the e rase of stored c h.rge from individ ual Hooting gat es. all o f ' he "o~li ng gates. Or spe<: ific subsets of Ho ating gales. A typical P LD may have hundreds to mil lions <>f gMes. Some. b ut not a ll . p rogrammable log ic technologies have high fan-in gates. !n o rder to show Ihe in lernal logic diagram for such technologies in a (xmci se form. it i. necessary to e mp loy a special 8 "te symbology a pplicable to array logic. Fig ur e 322 shows t he conventional a nd a rray log ic I}'mools fo r a mu ltiple input O R gate. Instead o f hav ing mUltip le input lin es to the gate. we d raw a si ngle li ne to tho 8 " te. The input lines a re drawn perpendkular to this li ne and a re selectively c onnected t o t he gate, If a n . is present al th e intersection o f two lin es, t here is a c o nn ection . If an x is nOt p resent. then there is no c o nn e<;t ion . In a similar fashion. we can draw the array logic for ~ n A ND gate. Since this was first d one for a fu:;cbased tec hn ology. t he g raphi'" r epresentation. when m.rl:<d with the selected connection s. is referred t o as a j"u map. We will us.. the . a me graphics represe ntation a nd terminology e "en when the p rogramming tuh nology is not fuses This type o f g raphi'" r eprcsctlla. tion for the inputs of gates will be used su l=q uently in drawing logic diagrarm. We next consider three distinct programmable device structures. We wi ll describe each of the s tructures and indicate which of the t "" hn ologies is tJ'llica ll y used in its impleme nta tion. These t ype' o f I 'LDs differ in the placement o f pr<>o g rammable conn e<;tions in th~ A ND OR array. Figure 3-23 shows t he locations o f t h ~ connection! for the three types. Programmable read o nly memory ( PROM) as well as Has h memory has a fi.<ed A ND a rray constructed as a d ecoder and program mable connections for the outp ut O R gates. T he PROM implemenl:! Bo<> lean function, in su m- of.min terms form. Th e programmable a rray logic ( PAL~ device h as a p rogrammable connection A ND a rray and a fixed O R array. T he A ND gates are p rogramm.d 10 provide the p roduct terms for the Bo<>lea n functions. which are 3 -6 I Prng . ." "nabl< Impl< . ....... t ion U chnoloc;" e," rr.~"mm'bk AND " <>y Inp "" O R ' !T' Y 1 27 C- L' ' ' c'c"_;;'_,':_:._:'"-"Jr-----1L,--_O_'"___-"J~ ~ OulfK''' ' ' ::',, , Inp ' " ( b) " "'Inmm.oble . n oy I<>P< (PAL) 1o""" Pr"""""".bIe Cort<>l;oo, (_,) 0 I"rosnommahl< C, . . n<rt . ... I",.,s,am mabk ,,",-~ C,m"",'""" M ;D.n.y o <1<..,., O -~ -R . noy - Ou'""" FI GURE 3-23 Config.rat;on o fTluee PLDs Basi< logieally s ummed i n e ach O R gate. T h e m ost Hexible o f t he t hr ee t ype. o f P LD i , I he p rogrammabl e logic aTfay ( PLA), , ,'hich has p rogrammah le connection~ f or Doth A ND a nd O R a rr a ys. T he p rodu ct t erms in t he A ND a rray may b e s hared by a n y O R g ate t o p rovide t he r~quired sum-()f_products i mpltmentation. ' ille nam<'$ P LA a nd P AL- emerged l or d evices f rom different v endor.; d uring tile developm~nt o f P LDs. Read-Only Memory A r ead -onl y m emory ( R OM) i . e ssenti.lly a d evice in which "permanent~ b inary i nfonn ati on i . s tore d . T he i nformation m ust be s pecified b)' t he d<'$igner a nd is t hen e mbedded into t he RO!\1 10 f orm t he requ ired interconneo:lion Or e le<: lronic d evice p attern. O nce t he p attern is <'$tablished. it s tays within t he R OM ~ven w hen p ower is tuTned o ff a nd 011 again; t hat is. R OM is nonvolalile. A block d iagram o f a R OM d evice is s hown in F igure 3-24. T h ere a re k i nputs a nd" o utputs. The i nputs pro~ide ( he addr(:loS f or ( he memory. a nd , he o utpul$ gi"e " mp"" ( add"",,) ---1 2' o x n ROM t--- . f l GUKE 3-24 B Iocl Di_vam o f ROl>! " "tP"" ( dota) 1 28 0 C HAPTER J I C OMIlI N ATIONAL L OGIC OESIGN words in a ROM device is d eter m in ed from the fact that k a ddress input lines can specify 2 ' words. N ote that ROM d oes nOI have data inpu ts.. because it does not haye a wrile o p,,,.tio n. Integrated circu it R OM chips have o ne Or mO re enable inpuls and come with t hreesiate OUlput~ t o facilitate the c onstruction o f large arrays o f R OM Consider. for example. a 32 X 8 R OM.1be unit consi.ts o f 32 words o f 8 bits each, T here a rc r,,'e input lines that f<:>rm t he binary numbers from 0 Ihroug.i> 31 for the address. Figure ) 25 s h ow< the i ntcrnallogic construction of this RO M. T he five inputs a rc dec<:>dcd into 32 d istinct o utputs by means o f a 5 - to-32linc dcc<:>der. Each o u tput o f the dec<:>der represents a memory address. T he 32 o utputs a re c on " "cIcci throug ), p rogrammable connections t o each o f the eight 01{ gate>. The d i. g ram t he array logic convention used in complex circuits. (See Figure 322.) Each O R g ate mu.1 be considered as ha"ing 32 input ~ Each o utput o f the dec<:>der is connected through . fuse to o ne o f the inputs o f each O R gate. Since eac h 01{ gate has 32 intoTnal programmable connection . . and since thore a re eig.i>t O R gatcs. the R OM c ontain, 32 X 8 - 256 p rogrammable c onnection, In g ene"' l, " 2* X n R OM will have an i nlernal k- to-2' li ne d ecoder and n O R gate~ Each O R gate h ;>s 2" input . . which a re connected throug.h programmable c onneclions to each o f the outputs o f the decoder. !'our technologies a re used for ROM p rogr.m ming. If milsk p rogramming is u sed.thon the ROM is call ed si mply a R OM . I f fuses a rc used, the R OM Un ' be p ", . gramme<! by the user ha"ing the pr<:>pcr p rogramming equipment. In t his case. the RO.\1 is referred to as a prog"''''mnble ROM. o r P ROM . If tl ,e 1 {0.\1 uses the eraSable floating-gate technology. then the RO M is r eferred t o a. a n erasab/~. progrom_ m ubl" 110M. Or E PROM , Finally. if tho electrical ly e rasable technology is used. the """$ , '. " " " -. $ - ,.,..]2 , " , , '" " " N o n GURi:,l.Z5 Internal Logic o f. 32)( 8 R OM ROM is referred t o a n eieclrictJlly ~rasab~. programmtlbl~ ROM. o r E EPROM o r E lp ROM. A . discussed previously. nash memory is a modified >ersion o f E1 PROM. 'The c""""'" o f programming Ied!nology <kpend$ 011 many factors. including t he num b er o f identical RO.\h t o be produced.lhe desired permanence o ftM p rogramming. (he desire for rcprogr;lrrunabili(y. and (he desired performance in lerm$ o f delay. P rogrammable L ogic A rrav The p rogrammable logic a rray ( PLA) is . imilar in ~pl 10 the P ROM, ex""pt (ha( t he PLA does nOi pro>i<k full decoding o f (he , ariable. and d oe!; not g enerale all Ihe minlerms. T he d ttodcr i . repla""d by a n array o f A ND g ales thaI can b e p rogrammed 10 g enerate product lerms o f the i nput ,. . riahles. The product t erm. are thCD selc<; lively c onnected 10 O R g ates 10 provide t he Sum of p roduct. fo r the required llooIean fnncti""s. 'The internal logic o f a P LA "';Ih three inpuI' a nd twO Onlputs i 0 0"" in Figure 3-26. Such a circuit is 100 small 10 b e cost effective. but is pre5<'nled h ere 10 d emon ,l rale the Iypical (og;.; configura lion o f a PLA. 1'lte diagram uses t he a rmy logic graphics symbols f or complex circuits. Each i nput goes through a buffer a nd a n inverler. r epresented in Ihe d iagram by a composile graphics symbol Iha! h a. oolh Ihe t rue .Dd lhe complement outputs. Programmable connections r un from . --c " . --c " , }---1~+-- ~ , )----j---<f-- XBC " , " o f11G U RI,;j..16 P LA with 1 bra: lnJ>U "- Four P roduct T<mr.. . 00 T wo QutJ>U" no 0 C HAPTER J I C OMBtNATlONAllOGlC D EStGN each :npu t a nJ :1$ c omplement t o tbe :nputs of each AND gate, as :nJ :cated by the intersections between the vertical and horizonlat tines. The o utputs of the A ND gates have programma bl e connections t o the in pu ts o f each O R gate. The OU1PU1 o f the O R ga1e goes 10 a n X OR gate. where Ihe o ther input can be programmed 10 receive a signal e qua l 10 either logic I Or logic 0,--The outpUl is in>'ened when Ihe XOR in put ;' connected t o 1 (since X $l - X). The output does not change when t he X OR in put is c onnected t o 0 (SiDce X $O . X ), The p anicular Boolean fu nclions im plemented in the PLA of t~e figure a re F, A B+AC+A8C F l A C+BC T he product terms g enerated in each A ND g ate are lisled by the o utput of the gate in t he diagram. The product term is d etermined from 1he inputs wilh C LOSED c ircuit connection s. Th e output of an O R gate gi>'es the logic s um o f t he $C l ect~d prodncl terms. The o ut put may be complemented o r left in its true fo rm , d epend . ing On lh~ programming o f t he connection associated wilh the X OR gate. T he size o f a P LA i ~ spec ifie d by the n umber 01 inp uts. the n umber o f produc\ terms. and 1he n umber o f outputs- A typical PLA h as 16 inputs. 4 8 p rodu c1 terms. and eight outp uts. For n inp uts. k producl terms. and m outputs, the i nt ~rnal logic o f the PLA consists o f" buffer_in,'erter gates. k A ND gates, m O R gates.. and m X OR gates, T here a re 2n X k p rogrammable connections betwe~n th~ i nputs and t he A ND array, k X m p rogrammable connections between the A ND a nd O R arrays, and m p rogrammable conneclions associated with the X OR gates. As with a R OM. t he P LA may I:>e mask programmable o r field programma ble. With mask programmin g. the cuslOmer s ubmits a P LA p rogram table to l he m anuf ac turer . The table is u wd by t he vendor t o p roduce a c ustom_made PLA t hat h as t he int ernal logic specified by the customer. Field p rogramming u se. a P LA c alled" j idd'prvg'ammal>ie logic array. or FPLA. This d evice c an be p rogra mmed by the user by m eans of a c ommercial h ardware p rogramming unit. P rogrammable A rray L ogic D evices T he p rogrammable array logic (PAL"' ) device is a P LD wit h a fixed O R a rray and a p rogrammable A ND array. Becauw only the A ND gates are programmable. the PAL device is easier t o p rogram than. but is not as flexible as. the PLA, Figure 3-27 p resents the logic configuration of a lypical programmable a rray log ic device. T he p articular device shown has l our in put' a nd four o utputs. Each input has a bufferim' crter gat", and eac" OUlput i . generated by a fixed O R gale. T he de" ice bas four sections, each c omposed o f a t hree wide AN D-OR array. meaning that t here a re t hree programmable A ND gates in each se clion . Each A ND g ate has 10 p rogrammable input connection s. indicated in the diagram by 10 vertical li ne. inteJ'$ecting u ch horizontal line, T he ~orizontal line symbolizes lbe multip le -input configuration o f an A ND gate. O ne o f t~e o utputs shown is connected t o a b uffer.inverter g ate and t hen fed back into the in puts of the A ND gates lhrough programmed connections. This is o hen d one wit h all de>'ice outputs. 3 -6 I I'n:>gt~l'IIm.ble I "'plemen"' ;"", Tedutologie. 0 131 A ND ~"'" i nputs mI, , , o - 1' J 4 ~ 6789 i< 1 ;::: J , 3 ;l- I, _ A , , c. , , , ;:: I / ; :: c. L , -Ql ~ c, J I, - C " - J\ " " ~ 01 o 2] 41 I c. 6 789 FlG U RE Jo21 PAL" D e.ke with Four Inputs. Fou r O u tput" a nd . Three-wide AND OR St ructure Th~ p articular Boolean functions implomented in Ihe P AL in Figure 3 2] a re F, = AB -t AC-tABC F: - AC -t BC - AB-tC Th ese functions are t he . arne"" lhose implemented u,ing the P LA. Since the o ut p ut c omplement is n ot available, F2 is conveTted t o a ,urn o f p roducts form. 1 32 0 C HAI'TEfl3 I C OMIHNATIONAL L OGIC D ESIGN L JIHULJ" mw .". L.to~, to, L~."" ll! A small PAL integrated circuit may have up t o d ght inputs, d ght O\Itputs, and eight sections. ~ac ll consisting of an eightwide Au"lDOR array_ Ea~h PAL device output is d rh'en by a t hree-state bulfer and also sen'es as an inpu t. These in put/outp ut s can be programmed 10 be an inpul only. an output only. o r bidireC1ional with a variable signal flops are often included in a PAL dri,ing the three . . tate huffer enable si gnal, Flip_ de,-ice belwcen the array and Ihe three-srate buffer at t he outpu ts. Since ea<ll output is fed back a , a n input through a bulfer-inverter gate into the A ND programmed array." SC<Iuential cirruit can be cilSily implemented. ,tJ::,., VLSI PAOOR....M...OLE LOGIC DeVICEs ~ This s upplement . which covers the basics o f lwO t}'p ical Field Programmable G ate A rmy. ( FPGAs) u sed in course labora to ries is ava il able on the Companion Webs it e for the tex t. T he supplement uses multi plexers, adders. fli p-flops.. latc ll cs. and SRAMs, A n appendix to tho supplement provides a b rief introduction to these components, 3 -7 C HAPTER S UMMARY T hi. c hapter began with the introduclion Ol l wO i mportant design concepts. design hierarchy and top..Jown design. t hat a re u",d throughout the remainder of the book, Computer-aided design was briefly introduced. with a focus on hardware description languages (H D u) and logic sy nt hesis. In Section 3-2. p roperlies of thc underlying gate technology were introduced. Two component t ype' with an add~d o ut pul '-alu~ called bighimpedance ( HiI). Ihree-<Iate buffers, and transmission gates wer~ described. I mportalll technology parameters, including fan-in. f anout. a nd propagation dela}'. were defined and ill um aled . Positive a nd n egative logic convent Io ns describe two different relation'hips belwccn '-011 ago Icyel, a nd logical valu cs. T he core o f t his c haptcr is a fivest ep design procedure described in 5e<otion 3-3. These steps apply 10 both manual and compuler-aided design. The design begins wi th a definmg specification a nd proceeds through a fonn ul ation step in which the speciflCalion i , convened t o a table or c qualion" The optimization step app li es two level a nd multipic_level optimization to obtain a circuit comf>'.'Sed o f A ND gates. O R gales. and im'erlors. Technology mapping c om'em th i' circuit into c ne that cfficiemly uscs the gates in the availabk im plementation tech nology, Fi n ally. vcrificaliQn is applied to assur~ that the final cireuit satisfies the in it ial specification. T hree ",,"mpiC'S illu,trate the f im three of t hese ",el"In order to discuss Icchnology mapping. fl~cd impicment ation tcchnologies including full custom. s tandard celL a nd g ale array approachos were introduced. Cell specification and celT librarics aloo wCre introduced. a nd mapping t echniques resembling those used in C AD lools were prescnted a nd ill ustrated for single cell typcl and multiple cell types. T he final section of the chapter dealt ,";th programmable logic technologies. - mrce basic technologie ..... readonly memory. programmable logic arrays. a nd p ro g rammablc array logic d e,ices-provide technology m apping altcrnatiycs, R EFERENCES I. HA(Tl.. G . ASO F . SolotENZI. ~ SyttlhtJUDitd Vmfiration AI60rilhrm. BoolOll: Kluwer A cademic J>\Iblidl.ers. 1!196. 2. D B M ICHEll. G . S ymhuu ami Opllmi.alilm o f V isual Circuiu. N c'" York: M cGr awH ill. Inc., 1994. 3. K", ,",pp. S. Frequfnll y.A5bd Ql4tJtioliS ( FAQ) AI>ouI P ros,mnmablt Logic ( hnp:llwww.o plimagicoomlfllq.html).Opli M .g icTM . Inc .. 0 1997 2001. 4. L Al"rICE SEM I OO.~DUcroR C oIlF'Q Il"T1ON. LAttiCt! G A L J( R)(htlp:llwww.lalliccsemi.oomJproo ucu/5pldl GAUindex .cfm). Latlice s.;,miconduClor C orporalion, 0 19952002. S. TR1MIlEROE R. S. 1.1 ., ED. F/tldProgrammilblt G alt A rmy ThtlOlaSY. DOI!ilOll: K luwer A cademic Publil hers. 1994. 6. X IUSX. I sc.. X ilitu S par/an""/1 Data S hut ( h Up :lldirecUil in x. com/b,docs/pu b lie, t ionslds077_2 .pdf). X ilinx, I "'"- 0 1994-2002. 7. ALTEItA(R) COIU'OltAll0)l. A lten F L EX IOKE E mbedded P 'og,.,.",mabk L ogic O n-ict R lmilyl)ala S httl ~er . 2.4 ( hnp:l"'........ aUera.oorni1'terat u reldtldsflOle.pdf). A llera C orporation , 0 1995 2002. P R08LEMS .t:1J::A The plu. (+) indicates II more advanced problem a nd the asteri,k (0) indicates u ~ s olution i , a vailable o n l he J - I. t e~l web$ it e. D esign a circuit t o i mplemenl t he following p air o f B oolean e qu llt ions: F _ ,l,(CE+O) " A 0 F _8(CE .. O ) .. 1i C T o s imp lify dra,,-;ng t he s chematic. t he c ircuit i110 us<: a h ierarc hy b ased 011 t he f aaoring in l he e qua1ion. T hree i n.lances (oopie<) o f single hierardlic.aJ circuit c omponent m ade l ip o f I".., A ND gales, an O R g ale. a nd an inve rter are 10 be used. D ra .... t he Iogjt: d iagram f or t he h ierarchical c omponen l and f or l he ~rall c irculi d iagram using . symbol for t he h ierarchical c omponent . .00-..,., J -l. A h ierarchical c omponem wilh l he rlll>Ction / I-XY.XZ ; s 1 0 be u sed a long w iTh i nv.ncl"$to i mplemem 1he fo !l owing e q uation: G - A I iC+A B D+A 1i C +ABD T he o vera ll c ireuil can be o blained b)' u si ng S hannon ', e xp an sion F_ X 1i!..X) + X 1h ~orem. F ,(X) , ,here F,j X ) i. F e valualed wilh , an.ble X " 0 a nd F ,(X) i< F e valll .1ed with variable X . I . This u pan$.ion F c an be i mplemen1ed with fu nction / I b y ielting Y _ Fo a nd Z _ F l' T he u pansion t heorem c an t hen be a pplied 10 t J4 0 C HAPTER 3 1 C OMIlINATlONAL L OGIC D E5IGN each 01 r~ and 1', us1ng a vadable 1n e a ch, preferably o ne that a ppears in b oth true and con' plcmentcd form . The proceS'> can t hen b e r epealed until a ll ,,-;. a re .ingle literals o r conslants. For G, u se X _ A to find Go and G, and then u se X _ B for Go and G ,. DTaw t he t op 1c,-cI d iagram f or G u sing I I as " hierarchical c omponent. J -J. A n imcgratcd circuit logic family has NAND g ates with a fan_out o f 8 s landard loads and buffers w ith. fan-out o f 16 . tan dard loads. Skelch a schematic showing how l h. o utput signal o f a single N AND g ate can be applied t o 38 oth~r gat~ inp ut. us ing as few buffers as possible. A ,sume t hat e ach inpul is one s tandard load. J---4, The N OR gates in Figure 3-28 h ",'c p ropagation dclay Ipd ,. 0.078 nS a nd the inverter h . . a p rop"galion d e lay IpJ ~ 0.052 ns. WlIat is t he propagation delay o f the longest p ath througJ' the circuit? J..-S, T he waveform in Figure 3_29 is a pp lied to a n invertc<. Find the output of l hc in vener, a .suming thm ( ~) it has no delay. ( b) it h as a t ran spon dcla}' o f 0,(16 n5. ( e) it has a n inertial del")' o f 0 .06 ns with a rcjection timc o f 0 .06 " I;. 3 -4. A ssume lhat tpd is the a ,' crase o f ' PHl a nd inp ut 10 the oUlput in Figure 3 30 by o , o , , - ,, , , 0.6 "" - 0.6", o l'inJ the d d.y from e ach Fl GU RF. 3-28 Circui, to< Prob lem 3-4 n,, ,, ' PI,H ' f lG lJ RE 3-29 W .veform for P roblem 35 , , , 7 Tom<: ( "') Pml:>lcm. 0 1 35 " C o n C;UREJ.JO Ci , enil fo, rmblem 3--6 Finding I pHl a nd 1 ",-,. f or each p a th a "um ing 11'111. = 0.30 nS ~Dd I plH = 0 50 n , fo r e ach gale. From t hese values, find IpoJ fo r each path. ( b) Using 'poJ _ 0 ,40 ns for e ach gate, Ie) C ompare ),on, answers in p art (a) and (b) a nd discuss a ny d ifference . . ( a) 3--7. J -a +The r ejection time l ot in ~niaJ dela)'s is r equired to be less tnan o r e qual t o the p ropaga tion delay_ [n t erms o f t he discussion o f t he e xample in F igure 3-7, why is (n is c ondition n ecessary t o d etermine t he delayed out put O + For a given gate, 0.05 ns " nd I plII = 0 .10 n<. S uppose that an inertial d elay m odel is t o b e d eveloped from this i nformation fo r t ypical gate d ela)' b eha,ior. '.,.L _ ( a) A "um ing a positive o u tput p u lse ( L H L). what would t he propagation d elay a nd rejection l im e be? ( b) Di scuss t he applicability o f t he p arameters in (a) assuming a n egalive oUlput pulse ( H L H ) J.-9. J.-IO. J.- ll J.-12. J.-Il. . S how t hat a posilive logic NAN D g ate is a ncgalive logic N OR galo a n d vice ,e[Sa. A majori ty function h a s an oUlput value o f I if t here a ,e m ore l ' s tnan O's On i ts inpul . . T he out pul is 0 Ot herwise. Design a Ihrce-input majMity function, Find a function 10 d elect an e rror in t he r cpresentalion o f a decim al d igit in BCD, In o t her words. write an equal;on wi th value 1 wnen l he inputs are any o ne o f t he six u nused bit c ombinations in t he B CD code , a nd '-alue O. other"iise, Design a n E xccs.<._to---- BCD c ode converter t hat gives o ut p ut c ode I )))) for all in valid inp ut combinations( a) A low-voltage lighting system is t o use a binaTy logic control for a particular lighl. This li ght lies a t t he inter<ection p oint of a T-shap"d hallway. T here is a swilCn for this light a t e ach of t he thT~e e nd points of the T. T hese , w it ches haye b inary o utp ut s 0 a nd I d epending on their position a nd a re 1 36 0 C HAPTER j I CO'\\BINATIO N A~ l OGIC n ESIGN named X,. X,. a nd X l ' T he light is contro ll ed by an amp li fi er dr ivi ng a thyristo r. W hen Z . the input to the amplifier. is 1. t he light i , O N a nd when Z i , O. the lig ht ;, O FF. You ore t o f ind" function Z = f "(X Io X ,) SO that i f a nyone o f Ihe switches is c hanged. t he value 01 Z c hanges turning the light O N o r O FF. x,. ( b) T he function for Z is n ot unique. H ow many different functions for Z are l her e? 3 -14. .. A troHic light c onlrot " , a . impk i nlcr..,ction u se, a binary c o unl er 10 p roduce t he fo ll owing sequence o f c ombinations o n lines A. B. C. a nd D ; OCIOO. 0001. 001 I. 0010.01 10.0111. 0 101.0 100. 1100. 11 01. 1111. 1110, 1010. 1011,1001. 1000. A fter 1000. Ihe sequence r epea t s, b eginning again wit li OCIOO. forever . E ach combination is p resent l or 5 se~o n ds b efore the n c~t o ne "PPC"T"S. T hcse line, dri,c combinational logic with o ut puts to lamps R l\' S ( Red. N orth /S outh). YNS (Ye ll ow - Norlh/South). GNS ( Green NortIllSouth). R EW ( Red E ast/We.I). Y EW ( Yellow . Ea,IIWeSI). a nd G EW ( Green. E""tlWeSI). T he lamp cOnlrn \\ ed by each o utpu t is O N for a I a pplied a nd O FF for a 0 a pplied. For a g i"en d irection, a s. u me Iha t gn.:cn i . 0 11 f<Or 30 secon ds, yellow is o n for 5 s econds. and r ed is o n for 45 seconds. ( The fed i ntervals overlap l or 5 sec<>nds.) D ividc u p Ihe s o s econds availa ble for the cycle t hrough t hc 16 c ombinalions into 16 i ntervals a nd d elermine which lamps sho uld be Ii i in e ac h in(erv"l b~scd o n u pec tcd drive r beh,(vior. A sw me thaI . f or inlerval OCIOO. a c hange h a. j ust occurred a nd t ha t G NS '"' 1. R EW '"' 1. a nd all o ther o utputs " e O. Design l he logic to p mdutc lhe s ix oulp ut ' using A ND a nd O R g ates a nd invertcrs, 3 - 15. Design a c omb in ational circuit thai accept. " 3bil n umber a nd generaleS a 6bit binary n um ber OU lput e qu .' t o t he sq uare 01 l he inp ul n umber. 3 - 16. . . D e,ign a combination al circuit t h ~ t a crepts a 4 -bit number and generates a 3-bit binary n umber OUlpUI thm approximates the S(luMe root 01 the n umber. For u ample. i f the sq uare rool is 3 .5 o r larger. g,ivc a result o f 4 . If t he square root is < 3.5 a nd 2! 2.S. g,i"c " result o f 3. 3 - 17. Design a circu it with a 4 b it O eD inpul A. B. C. D thot produces nn o utput W. X . Y, Z t hat is equal to the input . . 6 in binary. For example. 9 (1001) . . 6 ( 0\10);15(1111). 3 - 18. A t raffi c metering system for controlling the r elease o f traffic from an e ntrance ramp o n to a s uperhighway h a, t he l ollo"'ing specifications f or" p art of its controller. There are Ihree parallel metering lanes, e ac h with its Own SlOp ( rcd}-go (green) light. O ne o f t he", lanes, the car pool la nc. is given priority for 8 gree n light over t he other Iwo lane . . Olherwise. a '-ro un d rob in" scheme in w ~i c h the gree n lights altema t ~ is lI'<C d for the o t hcr t wo ( left a nd right) lanes. T he part of the co ntroller thm d etermines w hich light is to b e green (rather than red) is t o be designed . T he specificalions lor the c ontroller 101101": I 'robICm> 0 t3 7 Inpucs: " - - Car pool lane sensor (car present - I; c ar absent - 0) - - left la ne sensor (car present - I: car a bsent - - 0) RS - Right lane senSOr ( car present - I : car absent - 0) RR - - Round robin signal (select left - 1: select right - 0) " O ulputs: ' L _ C ar pool lane light (green _ I: red _0 ) LL - Left lane lig hl (grccn - - 1: rcd - - 0) RL - - Right lane light (gree n - I: red - 0) Operutinn, 1. I f there is a c ar in tho c ar pool lane, PL is I . 2. I f there a re no cars in the car pool lane a nd the right lane. a nd there is a car in t he left lan e. L L is I . 3. l flhore are n oc"" in lho car pool l"no and in tho left lane. and there is a e ar in the righl lane. R L is I, 4. If there is no e ar in the c ar pool lane. l here are c ars in b oth l he l eft and r ighllane . . a nd RR is I . t hen LL = 1. 5. I f thore is no car in tho c ar pool lane. there a re c ars in b ot h the left and rig hl lanes, a nd RR is O. t hen R L _ 1, 6. I f any PL. LL. Or R L is not specifIed to be I abo,'e. then il has value O. ia) Find the trulh table for lhe controller part. ( b) Find a mi ni mum m ull iple-Ic,cI gale implomentalion wit h mi ni mum g"te in put count using A ND gat es, O R gatos a nd i nverters 3 -19. C omplete lhe design of thc BCD _t()-!;C\"cn_segmcnl decoder by p crfonning the following .1eps: i al Plot the seven maps for each o fthc o utputs for thc BCD--to--sevcn_ segment decodcr ,pc~ i fid in Table 3-2. ( b Simplify the seven OUCput functions in sum-<>f- prod uC1s form, a nd d etermine the total n u moor o f gate inputs t hat will be needed t o implement lhc decoder. (~ ) Verify that the S C'Cn o u tput fu nclions listed in the text gi,c a valid simplification. C ompare the n umber of gat" input. with Ihm o btained in p art (1)) and explain the difference , 3-~O. + A N AND gale wit h e ight input' i , required. For each of the fol lowing cases. minimize the n um"", o f g ates u ",d in the multiple-level result: (. ) Design the 8 input N AND g"te using 2-input NAND gates and N OT gates. ( bl Design the 8-inpm N AND gate using 2-inpul N AND gates.2-input NOR g ate" a nd N OT gat e, only if needed. (0) C ompare the number 01 g ates used in (a) a nd (b) , 13 8 0 C HM'T ER I I COMUINATI ONA L LOGIC DES IGN , , " 0 " :~ D ~' I CU k E Ci ,~" , "' " , " j .J I fo' P,obI<m 3--21 )~ :::] V , ;r D n CU KE j .31 CirCuit fo< l'roblcm J.--22 ' -11--;::=[7,1 , D " I CU K E j .jJ CimU, for Problem J.--23 3--21 . Pcrfonn a minimUn) CQ61 (use m,"'m~m tOlal n ormalil ed a rCa a t 005t) technology m apping u ,ing N AND ce il , and i nveners from Thb le ) .) fo r t he circuil shown in " 'gure ) 31. J..-2 2. P erform a low-<:Ol'I ( use minimum 100 ai nonnali t cd .r~a as COl'I) le<:hll0logy m apping u ~i n g ail cells fmmThble 33 f or I he c ircuit.hown in Figure 332, J..-lJ. By u ,;ng m anual methods, verify Ih"1 Ihe c irru it o f f i gure ) 33 g enerales ' hc ud ~"; ~c. NOR funclIon. J..-U * Manually ,'crify Ihal Lhe f unctions f or l he output< F and G o f I hc b ierarrhical circtUl m Figure 3-34 a re F -= X Y +XY Z +XYZ G .,\ 'Z+XyZ+ XYZ , - 1-, , I w_ , ~ v o ' -" F IGUJI;f. J...,W an-u" for f'l'oblenu }-2A.nd 3-25 Manually "crify that the truth table for Ihe o utpull F and G o f (he h iuarchical c ircuit in FI gure 3-34 i$ a s f ollow" ,,, ,, , ,, , w l--26. T he 1Of,ic diagram fur a 74 11 CIJ8 MS! C MOS <l<cuit is given in ~18ufe 3 )5. Fmd 1M Bool ea n f undioo for """'h o f I he output$. Describe t he circuil fun<:lion carduUy. 1 40 0 C HAl'TER J I C OMBINATlON",L LOGIC DESIGN G< - - - , o F IGURE 3-35 Circuit for PrOO lem 3--26 an d Problem 3--27 3--27. D o Problem 3 -26 by using logic si mulation 10 find t he o utput wovefonns o f t he circuit o r a parlial truth table listing. r ather t han finding Boolean function s. 3-28. In Figure 321. s imulation resu lts a re gi,en for t he B CD-lo-fuccss3 C ode C onverter for the B CD i nputs fo r 0 t hrough 9. P erfonn a similar logic s imulation to d eunn ine the results for BCD inputs 10 through 15. C OMBINATIONAL F UN CT IONS A ND C IRCUITS n 1M. chapter, we will lea rn a boula " umber a! runCllon. and t he COO'~ i"9 f undamental c ircuM that ara very use ful", des>gn ing large< dig ital cir<:uilS. T he fundamental, reusable " rou lt . w hich"", c all functional t.-ocI<& , im!>emem hJncIions o f a ~ngle v ariable, OOooders. encoders, c ode cOIweners, m ultiplexer., a nd program mable logic. A side 1 m", b eing Important bu il d ing bIock5 l or l arge' cifeuits and ")'StaInS. many 01 ~ functions are s~y load to the various components of hardware description languB9"s a nd s a"'" a s a ""h",,,, for HD!.. pr e.enta l""' , A . a n a lternative to 1I1,Jth tables, &qtJalions. a rid scMemalics, V HDl a nd V&rilog h ardware dO$(;ripti(ln lar>gua~ a ra Intrl)duc &d. I In 111. . gene<ic c omp uter d "'!J'sm at the beginning 01 C hapte r I , m ultiplexers a re v ery impon a nt l or " """'l ing d ata i n t he p)C<)S$Of, in memory, a nd " " 110 t>oards . De<:oders a r" u oed l or selec tir>g boa rds a ttached 10 the Input-output b us a nd to d<!(:odI> in structions to d et erm;"" th<I Operations perlorrned in IIle pr<)Ce$$Or_ Encoders a.... '-'Sed i n a n umoo r 01 c ompooents, s uch as ! he keybOarIJ . P rog rammable logic is u sed 10 h andle c o mplex i ""truc~""s w ithin p<oceSSOfS a $ _ ~ a s in many o the r oomponents o f too comput er, 0 ...", 1, funct""", ' biocI<S are w idely ...sed, $ 0 c oncepl$ 1 from t his chapter app~ a cross most c omponenls 01 the generic computar, ir.:JC'di ng memor ies. 4 -1 C OMBINATIONAL C IRCUITS In C hapter J, we defined and ill ustrated c o mbinational Circuits a nd t heir dcs ign_ In this section, we define spoc i/i c combinational f unctions a nd c orrespond ing o 141 1 42 0 CI-I~I'TER' I C OMUIN"nON"1. FUNCTIO NS " NO C IRCUm .". s "" .,,0'0 , ..... o n GUHE 41 Bl<>ck D i.vom o f. Sequen'i. ] Circuit CQmbinalional cireuits. referred t o n. fi"'~';()"al hlocks. In som~ cases, wc will gQ througb thc design process for obtaioing . circuit fr<lm t hc function. ",hlle in other " "5I:s, we will simply prescnt the funet ieln a nd a n i mple_ntatiOll o i il. ~ func: lions ha"c .pecial imponance in digilal design. In thc p;I.l. the funCironal blocks "'ere manufactured as small and medium s c.le integrated cireuits. Tod .y. in very large scale integrated ( VLSI ) circuits. functional b Iocb a rc uoed t o dc$ign circuils with maoy such b loch. CombInational functions and their implementalions a r.. f unda_ntallO Ihe undentanding o f VLSI circuits. By . mog a h ;"no",hy. we typi. cally construct circuils a , in , lancet o f t "- functielns o r lhe u sociau,d functionaL blocks. Large-scale alMl very l ar,c ' lCIllc imelVated circuilS a re almost a h,'sy' s equen circuits 3 $ dcscribi:d in Secl iQn ),1 and det .iled ! xginning in C hapler 6. The functions and functional block. diICu!scd in Ihi ' c hapler. are combinational. I [ow ever, they Me " ften combined with ' Iorage cleme n' , to for m Sl:qucmial ci . cuit. a , . hown in Figure 4_1. Inputl 10 the ""mbinal ioo al circuit can come from both the external e nvironment and froo; the 5lorage elements. Oulputs ffQnl the combma. tiel"81 circuit go t o both lhe exlernal e nvironmcntand tQ lhe 5lorllge ele Oienti. In later chapters. we usc the combinational functions aod b Iocls d efined here. in Chapter S. and in Oapt~r 6 with storage d ements 10 form J;eq . .. ntial circuits Illat perform very useful fu nctiorK. Fun ...... the functions and b IocU defined he", and in C hapter S Sl:fV(: as a ba~is for dncnbi!l& and understanding both combinalional and seq . .. ntial cin:ui'" usin& ILardwarc detcriptioon Ian&uagcs in t M and ,ub5eq . .. nt chapters. ti~1 4 -2 R UDIMENTARV L oGIC F UNCTIONS Valu e-fixing. Iransferrin" invening. and enabling are among the most elementary of oombinat;onallogic functiont. The fint IWQ operations. valuefixing and t ran!fe . r in" d o nQl i nvoln any Boolean opera t<>rs. They usc only variables and (OnS t .nlt. A . " consequ ent... logic ga tCI Are not ;n"Qlved in Ihe implementaliQn Qf theSl: o pe ralions. In verling ;nvQlves only one logic gate per . 'ari.ble. And enabling involves one o r t "'o loilc i ln c1 p er variable, V alue-Fixing, T ransferring , a nd I nverting If. 'ingle-bil function depends on a single variable X. at mOM. four different fune tielns a re poss;blc. 1l!bIe 4-1 &ives the t ruth t.ables for th ..... functions. 1bc f int and lasl c ol"""" o ithe t able a ni", e ithe. a m . . a nt value 0 o r oonstant value I 10 the 4 _2 I R udirn<n''''Y l eg "' Functioo>. o 0 1 43 T ARL.: 4_1 r"n<lions of One Variable o o , ,o o funct ion. th us performing "alue-fixing. In t~c second column. the function is simply the input variable X. thus rrans/er-ing X ffOm inp ut to output , In t he third column. the function is X. tbus i n"ming input X t o become omput X. The implementat io n. for I he~ four functions a re g i"en in f igure 4 -2. Value fixing is im plemented by con necling a conslant 0 or constanl 1 to o utp ut F as s hown in Figure 4_ 2(a). Figure 4_2(b) Sho .... S alternative representation, used in logic s chemalin For tbe posit ive logic convention. conslant 0 is r epr= nt ed by the eleelrical ground symbol a nd e onstanl 1 by a power supply " oltage symbol , The latter symbol ;'; labeled with eit her V ee o r Vo ". Transfe rring is implemenHxl by a s im_ ple wire connecting X t o I ' as in Figure 4-2(0). Fina ll y. iO"erting ;,; r epresemed by a n inverter .... hich fonns I ' = X from iOpUl X as shown in FIgure 4-2(d). M u llipl.Bi t F unctions T he functions defined so far can b e applied to m ultiple bits On a bitwise basis. We can think of these multiple-bil function, as VeClofS of si ngle bit fu nct ion& For example, suppose that ....e have fo ur fu nction& 1'" F" F" and 1'0 thaI make u p a four-bit function F: We can o rder the fo ur functions with 1', as tbe most significant bit and F~ the least significant bit. pro\'iding the vector I ' (1'" 1',. 1', . 1'0)' Suppose t hat F coosislS of rudimentary functions F, = O. 1', = 1. 1', = A and F~ = A ,Theo we can .... rite F as the vector (0, I ,A, ::4) , For A _ 0. 1' _ (0, 1,0. I ) a nd for A _ I , 1' _ (0.1. t.O) . Thi~ multiple-bit function Can be referred 10 as F(3:0) o r . imp ly as I ' and is implememed in Figure 4-3(a). For c on"enience in schematics. we o ften r epresent a se l o f multiple. related .... ires by using a single li ne of geealer t hiche., ,,>jt h a slash aCrOSS the li ne. An integer giv ing tbe number of wi res repr~nted accompanies .he s lash as shown in FIgure 4-3(b). In order 10 connect the values O. L X . and X to the 5 v0 : or v"" - --, -, T _ _ p _ \ x---,_ , L 0 - - ' -0 - x -{)o-p -x ,., o ,,) '0' ", F IGURE 4-2 I mplementation o f Func ti on. o f S ingle Va ri. ble X 1 44 0 C H APTER 4 I C OMBINATIONAL f UNCT10NS A ND C IRCU ITS .. . , " .~.' ,:~' , ", , , ,., " ,., o F IG U RE 4-1 Implemcn .... j,on 01 Mul.i bi. RudiIJ'H:ntary Fb"",ion. approrri3le bits of f ; we break f up i n.o four wires ,,-jih each wi re labeled wiih Ihe bil o f F. Also, in Ihe p ross of lransferring. " "e may wish 10 U $e only a $ub:\.el of Ihe elements in f . for exampl e, f l and f ,. The nola lion for Ihe b i" o f f can b e used fo r Ihi' pur~ a s , hown in Figure 43(c)_ In Figure 43(d), a more comple> case illu, tral e. Ihe use of Fl , F I, Fo al a deslinal inn. NOle Ihat , ince F~ F" and Fo are nol all logelher. we cannOI US<: Ihe ra nge nol81ion fU:O) 10 denote this s ub,"e<:tOT_ Instead, " -e muO! usc a combination of 1\0"0 subve<:ton. F(3), F(I:O) d enoted by subscri pts 3, 1:0. The aclual notation used for ' "'tors and . ub,'eciors ,'aries among the schemat;'; d rawing tools o r H D L lool$ available. Figure 4-3 i llu"r a",,, just o ne approach. For a specifIC tool, the d ocumenlation . hould b e ronsulled. Value-fixing, Iransferring and inverting have a variety o f applications in logic de,ign. V~luefixing involve. replacing One or mOre variables with COnSI"nt v alue. 1 and O. Value fixing may be p ermanent or temporary. In p ermanent valuefixing, the value can never b e changed. In temporary value-fixi ng, l he v alue. can be c hanged,oflen by mechani~. thaI are somewhat different than Ihose e m ployed in ordinary logical o peration. A m ajor application of fixe<! a nd t emporary value-fixing i~ in p rogrammable logic devices. A ny logic function thaI i5 wilhin the c~pacily o f the programmable device can be i mplemcnled by fi.1ing a set o f valu es. a , illustrated in the next example_ .:X AMPI. 4-1 \'.lue.H~inK r n. I",plcnlcnting " unctio. C onsider the t ruth lable shown in Figure 4-4(a). A and B are Ih e input variables a nd 10 through I , a re also variabl es. Values 0 a nd 1 can b e aloSigned 10 10 through I , d epending upoo the desired funcl i<MI. NOIe Ihal Y is a ctually a funclion o f six variables giving a fully-expanded truth table containing 64 rows and !Ie,'cn columns. But, by puning 10 I hrou gh I , in the o utput column, ,,'e considerably red uc<: I he si~e of the table. The e q uation for the OUlput Y for this truth lable ; . Y (A.B,/(),/I,I"J,) " A Ii 1 0+A 8 1,+A Ii I , + ABI, T he implementation of t hi. e quation is gi,..,n in Figure 4-4{b). B y fixing the values o f 10 through I" we can implement a ny funClion yeA, B). As !>hown in Table 4.2. we can im plement Y . . A + B by using 10 0 ,/1_ I, I ,. I, and I ,. I . O r, we can im pbnent y .,A I i + A I lby using 10 " ,1, . l , I,~ I ,and 1,~O.Eit h croft h ese functions can 4_2 I R udi me,,",y I.ot:k Func';"n, 0 1 45 v "" o " 1 ( .) , I, " , U " " > " " " , ~ " ,..--, , )- Fe '. o n ClJWE 44 h npkmont'lion o fTwo FU"ct;oo. ~~ U.; ng V.lue_ ing Fix o T ,\.lIlE 42 I'un<1ion I n.plcmenta,;"n by " " 0 "" VarDe.~I.in g " (, be implemented pcrmanenil)', o r can I>e implemented tem po rarily by fi xingjo" Q /, . usi ~ g I , as a vari.ble wil h I , _ I for A . . B a nd I , _ 0 f orAB .. A B. T he final circuil is shown in Figure 4 -4(.). = 1.1) = I ,a nd 1 46 0 C HAPTIiR. f C OM BI NATIONAL F UNCTIONS A ND C IRCUITS Enabling The concept o f e nabling a 'ignal first a ppeared in Se ct ion 2 -9 where Hi-Z o utputs and three-slale h uffe . . were i ntroduced. In g eneral. enabling permi!!; a n inpul signal 10 pass l hrough to.n o utput. In a dd ition t o replacing the i nput sign.1 wilh l he H i-Z . tate. di~ab li Tl g al$O can r eplace the i nput sign.1 wilh a liJ<ed o utp ut value, e ither 0 o r I . T he additional i npul ,ignal. often called E NABLE o r EN. is re quired t o d elerm ine w hether t he o ut put;s e nab led o r not . For example. i f E N is I . t hen the input X reaches the Oll! pll! ( enabled) b ut if E N is 0, t~e Oll!put is fixed a t 0 ( di,ab led). For this case. with the d i,ahled value at O. the i nput signal is A NOed wi th the E N signal as shown in Figure 4- 5(a) , If the d isabled value is 1. t hen the inp ll! signal X is O Rcd with the oomplen,ent o f t he E N s ignal., s h own in FlguT 4-S(b). A lternatively, the signal t o the output may b e e nabled with E N. () c inst ead o f 1 a nd t he E N signal d enoled a . E N as EN is inverted as illustrated in Figure 4-5(b). t ;XAMI'LE 4-2 Enahling A pplinlion In m ost automobile<. the lights, radio. a nd p ower windows o pera te o nl y i f the ignition switch is t urned on. In t hi . case, lhe ignition sw it ch acts as a n " enablin g l ig_ na !. S uppo6C that ",'e model th is a utomotive subsySlem u~ i ng t he following va,iahles a nd definitions: Ignition switch IG _ Value 0 i f off a nd value 1 if on U ght Switch L S Value 0 if off and v~h , e I if On R adio Switch RS _ Val ue 0 if off and value 1 if o n I'I)wer Window Switch W S Val ue 0 if off and value I if o n Lights L . Value 0 if off and value I i f o n Radio R _ Value 0 if off and value 1 i f 00 Power Windo . ..,. IV Va lue 0 i f " ff and value 1 jf on Table 4-3 contains the condcnSl'd t ruth t able for Ihe o pera tion o f Ihis automobile subsystem. Note that when the ignition switch IS i ~ off (0). a ll o f the controlled acce",ories a re off (0) regardle", o f t heir swileh settings. T hi' is indicated by the firlt row of t he table. With the use o f X '" t h i' c ondenStd trut h table with just nine E~=O-F ,., , ' - ,,-- EN ~ ,., o F1G U II. 4-5 Enablin& CiTeui" F +-3 f 1 )oo;ng o T ABLE 4- 3 T ruth Table ror E""b l ia~ 0 .., A pp li ca tion tnpul .... C CflSOry Switch. . Conlro1 " " w, ,,, 0 0 0 0 0 " " 0 0 , "0 0 " ,, W 0 0 0 0 0 0 0 0 " 0, , 0 0 0 0 0 rows represonts the . ame i nformation as the us u all6 -row truth table. W herea, X's in o ut put column$ represent don't-care cond itions. X'8 in input columns a re used t o represont product terms that are not mi nt erm For example. O XXX r epresents t he p roduct term I S. J ust as with m interm" each variable i, c omplemented if t ht c orresponding bil in t he inp ut c ombinalion from the t able is 0 a nd is n ot complemented if Ihe bit is l . If the c orrespond ing bit in the input combination i , an X. Ihen the "ariable d<:>e$ n ot appear in the prod uct term . When t he ign ition swi tch IS is on ( I). then lhe acce,"ories a re c onno ll ed by t heir respect iv e switche" W hen IS is o ff (0) . all acce<sories are off. S o IS replaces the norm al values o f t he o u tputs L. R. and W with a filled value 0 and m eets the definition o f an E NABLE signal. 4 -3 D ECODING In digital compulers, discre te quantities of information are r epre",n ted by binary A n ,, -bit binuI}' code is c apable o f represonting u p to 2" distinct e lemem, o f coded information. D ecoding is t he conversion o f an n-bit input c ode to an m bit o utput c ode w ith" S m S 2" such that ~ach valid input cod~ word produces a uniq ue output code. Decoding is p erformed by a ,Iecmler. a c ombinational circu it wilh an n _ binary code applied to its inputs a nd an m-bit bi nary code appearing bi' a t the ou tput:!. T he d ecoder m a y have un u:sed b it combinations On its inputs for wh ic h no corresponding m-bit c ode a ppears a t the OUlputS. A mong all of the specia li zed f unctions do6ned here. decoding is the mOSt import am since th is f unction and thc c orresponding functional blocks a rc illCOflX'rated into many o f t he o ther functions and functional b loch defined here_ In this section. the functional blocks that implement decoding a re called r Ho-m -linc decoders.. whcre m S; 2". T heir purpose is to generate the 2' (or fewer) mint erm, from the n inp ut variahles. For n * 1 a nd m * 2 . we obtain the ]-to-2-line decoding f unction wit h input A and o utputs D o a nd D ,. Th e truth table for th is cod~ .. . 1 48 0 C HAI'TF.Il4 I C OMBINATIONAL f UNcnONS ... N O e lllcu rTS .", " " ,., [ >0- 0. - ;;: 0, _ A ( .) o n G U R F, " -6 A 1-lo.2Line D eeuder d ecoding funclion is given in Figure 4-6(a). If A . . O. I hen D . _ I a nd D , .. O. I f A ~ I . lhen O. ~ 0 and 0 , ~ I. From I hi' l rulh lable. D A a nd 0 , .. A giving Ihe circuil shoVin in FIgure 4-6(b). A second decoding funclion for " s 2 . nd m ~ 4 " 'il h Ihe lrulh lable given in Figu,", 4.7(a) M iler i llumales Ihe general nalUre o f d ,odcrs_This t able has 2, '.ri.ble mint erms as ils o utput s, wilh each row c onlaining o ne ou tpu t value c qualto I a nd I hree o ul pul va lues equal 10 0 , O utput OJ is e q ua l 10 I wh eneve r l he 1\0'0 i nput value. o n A , a nd A . a rc t he b inary c ode for I he n umMr i . A~ a c onsequence. Ih e c ircuit implements l he four p os,ible m interm. o f 1"'0 var ia bles, o ne m interm for e ach OUlput. In Ihe logic d iagram in Figure 4 .7(b).uch miDlerm is i mplemenled by a 2 inpu t A ND g ale. The"" A ND g ares a rc conneeled 10 I wo 1.lo2.1ine decoders, o ne for e ach o f Ihe lines drivi ng Ihe At>:O g ale inputs. Decoder Expansion Large decoders can M conSTructed by si mply implementing each m interm funclion using a single A N D gale "';Ih mo,", inpul s. U nfortunalely. as dlXO'krs become ~ " " " ". ", ". ". " , ~ v 0. - A, .... o, - A, .... ( .) O,- A, A.. I>, - A, .... ( 0) o n G U RE 4-7 A 2-lo-4- Li ne Deeoder 4 _3 I D<fl><Iing 0 149 larger, this approach give, a hi gh g ate inpul coum. In this = Iion, we give a proce d u re t~at uses design hierar<~y a nd colloctions o f A ND g ates t o c o nstruct any decoder wil~ " inputs and 2" o u tput <- The resulting d ecoder h as the sa me o r a lower gate inp U! coum than the one constructed by s imply e nlargi ng each A ND g ale. Th construcl " 3 -lo-S. JJ ne decoder (Ii 3). we can use a 210-4 lioe d ecoder and a \ -t<>-2 li ne d ecoder fceding eight 2 inp ut A ND gales to form Ihe minterms. Hi erarchically. the 2 t0-4 lino decoder can b e impleme med using IWO \ -to-2 Jin e decoder, feeding four 2. inpUI A ND gales as observed in Fig ure 4 7. The resulting structure is shown in Figure 4-8. 'Th e gener.1 proe<:dure is as fo ll ows: E L elk E Ii . 2. I f k is e ,'en, divide k by 2 to o bta in kn. Use 2' AND gates driven by IWO decode rs o f o utpu t size 2m. I f is k is odd. o b tain { k + 1)J2 and (k - 1)12. Use 2 ' A ND gat es driven by a d ecoder o f o utput size 21 " lYl a nd a decoder o f o utput size 2(' - 1 Y!. 3. For e ach decoder result in g from s tep 2, repe at s lep 2 wilh k equal to the values o btained in s tep 2 until k = I . For k = I. use a \ to-2 d ecoder. ~ i~ )- )- " , , ~ , " ] -I , , ] , o ~lGUKE4-S A ) '0-8UIlC [)eroder I SO 0 C HAPTI'R 4 I COl>\ IUN ATlON AI. f UNCTIONS A NIl CIR,C\JITS o I'IGU Il r. ... 9 A 6-,Q-64U . .. I>rcod<r J: XAMPU: 4-3 (H<>-4;I..I.iM l >oder For a l Ho-M-line d ecoder (11. . . " .. 6 ). in Ihe l im e XUlion Qf S1ep 2, 64 2.inpul A ND g ales arl: driven by IwtI d ecodenQf QUIPUI $ itt 2 ' '" g (Le..by IWQ )1()-8..1iM d eroden). In Ihe second e~eculi<>ll Q f ! lep 2..1< ~ 3. Since I< is odd , l ~ r!:Su l! i f (I< .. 1)12 ~ 2 a nd (ot _ 1)f2 . . l . Eig.I\I 2 jnpul AN D g ales a re driw=n b y a d eld er ( )f 001, put s iu 2 ' . . 4 and by a decoder of OOlput size 2 ' . . 2 (i.c .. b y a 2 104 line dect>dcr and by a l -to-2 li ne deroder, res~etive l y) , Finally. o n the nexl execution of s lep 2. k .. 2. giving four 2;np ut A ND , ate. driven by twO de<:o,ltrs with o utpul .i~c 2 (i ,e., by two 1 lo2line decoders), Since all de<:odcrs h ave been expanded. Ihe a lgorithm terminates with s tep) 81 this point. T he resulting . twcture i . shown in R gure 4 -9, Thill StruCt Ur e has Bg ale input r oun ! o f6 -+- 2 (2 '" 4) -+- 2 (2)( 8) -+- 2)( 64 ~ 182. If a single A ND , ate for e~h m inlerm ...ere used. Ihe resulting g ale input r ou nt would be 6 . . (6 '" 64) . . 390.10 a s ubstantial g ate i nput count red""tiQn has been . ehieved. A . an a lternall"c u pansion situation. $ tlppo5C l hal mul!iple decoders a re n eeded and IMt the d ecoders h l\'e r om"",n inpul variables. In this ease, in.IC-'! ( )f 4_J I D <roding 0 l SI i mplementing s eparate d ecode,,- parts o f t he decoders can be ' hared, F or e xam ple, , uppose that three decoders d dt.o a nd de " re f unction, o f i nput variables os follow" d .(A.B.C.D) '/b (A,B,C.E) d ,(C,D,E,f) A 3-t0-8-line d ecoder for A . B. a nd C c an b e . hared b elween d . a nd dt.o A 2-10-4lin e d eeoder for C a nd D can be s hared between d . a nd do. A 2 t0-4line d ecoder for C a nd E c an be shared b etween I i" a nd d,. I f we implement all o f t his sharing. we would ha,'e C e ntering t hree different d ecoders a nd the circuit would be r edundant. To u se C jusl o nce in . h."cd d ecoders larger Ihan I 1 02. we can c on,id. . I h. following distinct c a..,,, I. (A. II) s h.red by d. a nd Ii", a nd (C. D) sh ared by d. a "d d, 2. ( A. B ) s hared by d . a nd Ii", a nd (C. ) , hared by II" a nd d", o r 3. (A. 8 . C ) s hare d by d . a nd dl>Since ~aseS I a nd 2 will d ear ly h a,. the same costs, we will c ompare the cost o f cases 1 a nd 3, F or c ase I . t he coots o f f unction, d . d . . a nd d, will b e r educed by the cost o f t wo 2 to-4l in o d ecoder, ( exdus iv e o f i nverters) o r 16 g ate inputs. ,-or case 3, the costs f or functions ,i. a nd d " . re reduced by One 3 t0-8line d ecoder (exchl' $ive o f i nverters) o r 24 gate inputs. S o case 3 s hou ld be implemented. Formalizalion o f I hi. p roce,lure in to an a lgorit hm is b eyonJ o ur c urrent $<:(Jj)c. SO only t his il lustration o f Ihe a pproach i . given. Decoder and Enabling Combinations Tho function. , , tomline decoding with enabling. can b e i mplement ed by a ttach_ ing m e nabling circuits 10 t he d ecoder OUlpUIS. T hen. m copies 01 t he e nab ling sig nal EN a re a ttached to the e nable c ontrol inputs o f the enabling circuits. F or" . . 2 a nd ' " ~ 4, the result ing 2-t0-4line d ecoder with enabt<: is shown in ~i gUTC 4 10. a long Wilh i t$ t rut h table. For E N .. 0, all o f l he o utput. o f Ihe d ecoder a re O. F or E N ~ I . o ne o f t he o utputs o f the decode> d etermined by the value o n (AbAO). i . 1 a nd a ll o thers a re O. If t he d ecoder i . c ontrolling a sel o f li ghts. the n with E N O. aU lights a rc off. a nd with E N. I, exactly o ne light is o n, with the o ther t hree off, For large d ecodors (II <: 4). the gate i nput count Ca n b e r educed by plac in g the e nable c ircuit' on lhe inputs t o t he d ecoder a nd their complements r ather l han o n e ach o f l he d ecoder o utp uts. In Section 4-5, s e lection using muhiplexers will b e c o'ered. T he inverse o f s ekctio n is distrihUlion in which infonnalion r ecei,'ed from a single line is t ransmitted t o o ne o f 2 ' possible o ut put line . . The cirC uit which i mplements such distri_ b ut ion is called a d mw/lipluu. T he specific o utp ut t o which lhe i nput signal i . tra nsmitt ed is c ont rolled by the bit c omb in ation o n" selection lines. T he 2-1O-4 -line d ecoder with e nable in Figure 410 is an implementation o f a I _to -t line demulti_ plexer. F or t h e d emultiplexer, i nput E N p rovide. t he d ata. while t he o ther K 15 2 0 C HAI'TER -I I C OMBINATIONAL F UNCTIONS A NlJ C IRCUITS , " ', 0, ", ", " ,,, , "", , ", , "", , , ,,,, , ~ --f ~ ,.," " , ". ", ., o n GURE4 10 A 2- lo-l Une Decoder wilh En able inpulS act as t he se lection variables. A lthough th e two c ircuits h a,'e d ifferent a pp li cation$, t heir logic d iagrams a re e xactly t he same. For this reason . a d ecoder with e nable in put i5 r eferred t o as a d ecoder/ demultip le xer . T he d ata inpul E N has a path to aU four o u t pUlS. b u t the inpul in formation is directed to o n ly one o f the o utput" as s pecified by t he two selection lines A l a nd Ao. For example. if ( AhA . ) _ 10, o utput D , has the value applied 10 input EN. while all o ther o u tputs remain inactive al logic O. If the decoder is controlling a sel o f four lights, wi th ( A , .Ao) _ 1 0and E N pcriodicaUy changing between I and O.the light controlled by D , flashes on a nd off and all o ther lights are o ff. 4 -4 E NCODING A n encoder is a digit al func1ion that performs the inverse o peration of a decoder. A n e ncoder has 2" ( or fewer) input lines and n o utput lines. The o utput lines gen era te t he binary code corresponding 10 t he input value. An example o f an encoder is the oclal t<}obinary e n coder whose t ruth table is given in Table 4-4. This e ncoder has e ight i nput" one for each of the octal digit" and tl1ree OUlputS t hai g enerate tl1e corresponding binary number. I t is assumed thaI o n ly o ne input has a value of I a l any given lime. so that the table has only e ight rows with spec ified o utput " alue" For the remaining 56 rows. all of the o utputs a re d on't care s. From Ihe 1ru th table. we can observe t hat A; is 1 for 1be columns in which DJ is 1 only i f s ubseript j has a binary r e presenlalio~ wi th a I in t he ith position. For example. o ut put A~ = 1 if Ihe input is 1 or 3 o r 5 o r 7. Since all of these values are odd. they h .,'e a 1 in the 0 posi1ion o f their b inary r epresentation. This approach can be used 10 fi~d the truth table. From the table. the encoder can be implemenled with n O R gate s, one for each o utput variable A;. Each O R gale 4--4 I I'A<oding o ~ 0 " " " " 0 , 0 T ABLE 4-4 Tno tl> T . .... r. .. O rta!.t. . B ina.,. ..... t~ : "" " ,,,,, ,,,, """", """, , "",,, " " " ", , ,, """ """" 0, 0, 0 ........ ," , "" ,, "" " ,, , '" ., " 0, " "" " ," " , " " " """ , " , combines the i npul v ariabk$ OJ h avinl. I in the 1'0"" for ",hieh A ; h a. value I . r..,.. Ihe S-lo-J-Iinc encoder. the r ewllinl o utput e qua l ions.'" A o . . O , + O J+ O ,+ Or A , - /), + 0 , + / ). + 0 , A , - 0.+D ,+ D6 +D , ,,hich can be implement ed with I hru 4 inpul O R gale$. The enCQder jusl defi ned has Ih e limilalion Ihal only o ne input can be ~cl i vc al " ny given li m e: i f two inpuls are aClive Ji mullaneously. I h e oUlput produces Mn incor'e<:1 CQrnbinalion. For c nmp lc . if OJ and D . are I simultaneously. I he output o f I he encoder will be I II because all the I h"'e OUlPUt< a re e<juallo I. T hi. rep re se " IS n eilher" binary 3 . .or a mnary 6. To rew!>c tbi, "mmguil)", \.Qft1e e ncoder eir. e uil' mllSt eslablish an inpul priorily 10 c n'u'e Ihal o nly one inpul is e!>COded. If .... e e slabli.h a higher priorily f or inputs " ilh hi gher subscript numbers. a nd if b olh / )J and D. a re I 311be g !lle lime. lhe OUlpul "'ill be 110 because O. h as higher pri o rity Ihan / ),. A m)lhcr ambitu'l)" in I he octal.lo-binary encoder is 1hal I n OUlpul o f .110 , is g enerated when all the i"pulS are O. b ut Ihis OUIJ>llI is lhe same as " hen 0 0 is e<juallO L l" isd~p"'ncy can be resoh-ed by providing a separale OUtput t o .ndicale Ihal a ileasl o ne i nput is e qual 10 I . P riorlly E ncoder A pri{>T it )' e ncoder is " conlbi" "tio,,"1 circu il Ihal implements" priorilY fu n CI.on, A . mentioned in the preceding paragr~rh. the o peral ion o f t he priorily ~"codcr is such Ihot i f Iwo or m ore inputs I rc e qual t o I at Ihe same lime. Ihe Inp ul having Ihe h;gh~" priority tak"" pr"""dence. The lrulh lable for a four.input priority eoooder ;" gi,cn in Table 45. Wi lh Ihe use o f x . . Ih;" condemcd l rulh l Illie wilh JUIII Ih e " "'. . r epresem, the s ame informalion u Ihe usual 16-row Iruth lable. Whereas X . in OUlptJl coIumn ~ r epresenl d""I-eare condilion$. X', in inpul I S4 0 C HAI'TER 4 ! C OMBINATIONAL F UNCIlONS A ND C IRCUITS o T ABLE4- S T .u lh Table o f I'riorit)' EJ>C<>der Outputs tnputs 0, 0, 0, 0, 0 0 0 0 0 0 0 0 , , 0 , , , 0 , , " , 0 0 ~ , , , 0 0 0 ool um ns arc used to represenl p .oduct terms that are nol mi nte.m s. For example. OOIX r~presents the p.oduct torm D , D, D,. JUSt as wit ll mi nttrms. cae ll , 'ariable is complemented if t he corresponding bit in t he inp ut combination from the table is 0 a nd is n ot complemented if the bit is 1. If the c orresponding bit in the inp ut combination is a n X, t hen the " ariable d oe, not appear in the p.oduct te.m. ThUs, for_OO!!. the variable D o. oorresponding to the position of the X, d oe, not a ppear ;n D,D,D,. The n umber o f . ow, o f a full truth table r epresented by " row in t he con densed t able is 21'. w here ( ! is the num ber o f X"S in th e row. For e xample. in Table 4-5. I XXX r epresents 2 ' - 8 t ruth t able row .. al l ha"ing the same value for a ll o ut put . . In f orming a c onde nsed truth , ab le. we m u.t i nclude each m interm in a t least o ne of t he rows in t he sense t ha t mint~rm can be o btained by filling in I ' , a nd 0 ', l or t he X's, AI,o. a m imerm m u s, never be includ ed in m ore t ha n o ne row such that the rows in " 'hich it a ppears have o ne o r m ore conflicting o utput va lue., We form Table 4 5 as follows: I nput D , h a, the highest priority: re gardIe . . of the va lues o f t il e ot h er i nput . . when this i nput i. l . the o utput f or A , Ao i< I I (binary 3). From thi< we o btain the last row o f t he table. D2 h a, the next priority level. T he o utput is 10 if Dl = 1. p rovided to Ol D J = O. r egardless o f the value, o f Ihe lower p riority input,. From thi,. we o btain t he fo urth row o f t he t able , T he o utput for D , is generated o nly if all inpu ts wi th h igher priority a re O. a nd . 0 o n d own t he priority levels. Fr om t hi . . we o btain the r emaining rows o f th e table . T he valid o u t pu t d esignated by V is <et t o 1 o nly wh en o ne o r more o f the i nput. are e q ual t o I . If all in pms a re O. V i , equ"1 t o O. a nd the o t her t wo o utputs o f t he circui t a rc n o t used a nd a re specified a< d on't-care c onditions in th e o utput p art o f the table. The maps for si mplifying Outputs Aj a nd Ao are shown in Figure 4-11. The minterm, for the two f unction. are d eri"ed from Table 4-5, The output values in t he table can be transferred dir""tly to the m aps by plac in g t hem in the squ are. c o"cred by the corresponding product term r epresented in the table. The o ptimized e q uation for each funClion is listed und er t he map for the funct ion. The '0. ~,o. ,0, 00 .. , "' " , , 0, 00 "' , , , , ," .. '" '" ", - 0, 0, o ,,,, ..... o,~ o , l), Fl GU Ht; 4 11 Maps for Priorily Encoder e-qua(ion for OUl pul V is a n O R f U i"" o f a ll Ihe iDpu l ~a r iableJ. ' I he priorilY n(1 en<:Oder it implemented in Figu . .. 4- 12 a coord'ng t o ( he follo"',n, n oolean fUMtiort'l: A O - 0 1 +0,'0, A , . . 0 J+ O) V - Du+O ,+ D, +D ) Encoder Expansion T h"" far, "" h .,'c CQRSide.ed only . ... all encode . .. E ncodeR can be u pan<ied (0 larger n umben o f inpu!1 by u panding O R gal .... In Ihe implcmcnla!1on o f D t"I GU HE 4-1 2 Logic Di"" om o f . 4.lnput m on ty Encoder 1 56 0 C HAI'TEIl 4 I C O MBI NATIO N AL F UNCTIONS A ND C IRCUITS decoders, Ihe use o f mu lt iplelevel c irtu its with O H gates beyond t he o ut pul lcvels s hared in implementing the more significant bit, in t he o mput c odes red uce, Ihe gale i npul oo uni a , n inc rc~s f or" <: 5. For n ;" 3. m ultiple l evc! c ircuit' r e,u lt from technology m apping anyway d ue to lim ited gate f anin. Designing multiple_ level circuits with shored g ate. reduce. the cost o f the e ncode rs a fter technology mapp mg. 4 -5 S ELECTING S election o f information to b e used in a o omputer is a " ery im po rt ant fu nction, not o nl y in oomrn unicaling between the parts of Ihe system. b ut a lso within the p arts as wel l. A mong o ther uses, selecting in c ombination wit h value fixi ng can impleme nt oo m bi national function s, Cin;uits th;> t perfo rm s election typically ha"e a set o f inputs from which selections a re made. a single nutput. and a sel o f oo1\trol lines for m . king the selection . Fir>!. w . c on, id er selection using mulTiplexers: then we b rie ll y exam ine selection circuits im plem enled by uo ing Ihree-1;tatc drivers Or t ra ll smi ssion g .te . . M ultiplexers A m ult iplexer is a combinational circu it t ha t selects bi n a .)' i nformation from o ne o f many input lines a nd dircc ts t he inf" rmation 10 a single o ut put line. T he sele<:ti on o f a p articular inpul linc is c ontro ll ed by a set o f i nput variable s, ca ll ed selec l ion i llpm.,. Nonnnily. there a re 2" input lin . . a nd n s election i nputs w hore bit combinations d eterm ine which input is selected . We begi" witb I I . I . a 2IO Ilille m uhiple,cL T his fu nction has two information i nputs, 10 a nd I ,. a nd a single sek'Ct input S. The truth table for t he d rc u it is given in Ta bl e 4.6. Examining the tablc. if the select inp ut S ~ O. the output of the multiplexer takes o n t he values o f [ 0- and. if inpul S . I . the o utp ut o f the multiplexer t akes on t he "alues o f I ]. T h us, S selects e it her inpu t 10 o . inp ut I , to a ppear at o utpul Y. F rom th is discussion. we can see t hat the e quat ion for t he 2_to_ I. li" e multiplexer OUlp ut Y is o I"ADLE-w. ' rnlth Tabl~ f . .. 2to IUn e ]I.Iultipl""~, , " , ""o o """ """ , " " , " " , " " -I--S 0 151 L . . b~" 1 r-C ' ~ , O rcu", )- )- " o I ~I<rt;ng F lGURE4-B A single bi t 2-to-l Li nc Multi plexer This same equation can be o btained by using a J -var iable K- map. A s s how" in Figu,~ 4-13, th~ implcm~nlation o f t he p,,,,,,,ding cqualion can be d<oe<>mposed i nto a l -t0-2-hne d ecoder, two e nabling circuits a nd a 2-input O R gate. S uppose thaI w e wish t o des ign a 4_tO-I line multiple _.r. In Ihis case. the function Y d epe n d, On f our inputs f". f, . I ,. a nd f ) a nd two select inputs 5 , a nd 50. By placing the va lu e. o f f o Ihrough" in the Y col umn . we Can form Table 4- 7," c ondensed truth l able for this multip le xer. In this table. t he information , ariable. d o nO! a ppear a s i nput colum n. o f t he table b ut a ppear in the o u tput column. Each ' ow " ' prese n,s multiple rOWS o f t he full truth tahle. In Table 4_7. t he row 00 f orepresent. all ro"'.. in which ( 5 , . So) ~ 00 a nd. fo, ' 0 - I. g ive. Y - I a nd. for ' 0 - O. g i"es Y _ O Since t here a re si x variables. a nd o nly 5 , a nd 50 a re fixed, this single . ' ow rep'~'5Cnt. 16 ro",.. o f t he co.-responding full truth table. From the table. we can write the e quation for Y a s - - Y . . 5 , 5 010+ 5 , 5,,1,+ S, S o},+S , So l, J { this e quation is i mplemented directly. two i n,erters. f our 3-input A N D gates. a nd a 4-inpul O R g ale are , equi T gj"ing a gate inpul cou nl o f 18. A d ifferem i mple ed. menta!;"n can b e o btained by factoring lhe A N D t erms.!o gi,-e This implement at ion ca n b e c onstructed b y combining a 2-to -4- line d ecoder. fou r A NO gates used a s enabling circuits a nd a 4 .input O R gate a s show" in Figu,e 4- 14. We will refer t o t he combin~hon o f A N D gates a nd O R gate> as a n o T ABLE 4 7 C nndn oed Trut h T ol>! e fo< 4-, . .. I Linr Mul , jpleUT 5, So Y " 0 1 , I, o '. o '. 1 58 0 C H.}.PTER' I C OMBINATIONAL F UN=IONS A NU C II<.CUITS , -, V 4 x lANDOR V , )" "> " " o ~'I G UR""14 A Single Bil 4 -(o-l line Mu lliplexer m x 2 A ND OR. where m is the n umber o f A ND gates a nd 2 is the number o f inputs t o the A ND gate~ This res ul ting circuit has a gate input count o f 22. which is Ihc more costly. Nevenheless. it p ro"ides a " rucmra l basis for construct in g larger nto-2" line multiple_en; by expansion. A mul tiplexer is also ca ll ed a dam s decm, . ince it " ,Iects one o f many infor_ mation inp uts and stcon; the binary information t o the output line. The term mul tiplexer" is often abbreviated as " MUX:' Multiplexer expansion Multiplcxen; can be e xpanded by considering larger values o f n vectors of inp ut bits. Expansion is based upon the c ireuit strUelure given in Figure 4 14 consisting o f a d ecoder, enabling circuits., a nd an O R gate. Multiplexer design is ill ustrated in E~amples 4-4 and 45. I E XAMPLE 4 4 64-to-ILine II-lulliplexer A mul tiplexer i . to b e designed for n = 6 . T hi, will require a 6-10-64_lino decoder as given in Figure 49. a nd a 64 x 2 A ND-OR gate. The resulting s tructure i, , hown in Figure 4 15 . This structure has a gate input count of 182 + 128 + 64 = 374. [0 con trast i f t ne decoder a nd t~e enat>ling c ircuit are r eplaced by ; u.erters plus 7 input A ND gat es. the gate input count would b e 6 ... 448 + 64 = 518. For single-bit multiplc~e,.. , uch as this one. combining Ihc A ND g ate g enerating D; with the A ND g ate d rh'en by D , into a single 3-input A ND gate for every i = 0 through 63 r educe, the gate input count t o 310. For multiple-bit multiplexers. t his reduction t o 3 input A NDs c annot be p erformed without rep li cating the o utput A NDs o f t hc decoders. A s a result. in almost all cases, t he original str uct ure ha< a .j... 5 I klor<rin& 0 159 ~------ --- ------- --- ---------- ----------- --- ------- -, A-f ,, , , , , A, ---+ , , , , , ~-t , '1"""""""ccJ"""~-::=t~~~~~::::Jlcccc"",,,J ------------------- ------- ' ,-f ,------------- --- o n G UIU, 4-1 5 A 64to-lU"" MultiplUC! I """,r , ate ' npul COIiI. T he nexl example mu slntes the expansion t o a multiplebit multiplexer. E XAMPU: .... 5 41 .. I Litte ( }gad Multipl. ." . . A q uad 4 I()o I linc m uhipleur . ",hieh has two 5<'1""IOon inpul< and each infOfma lion iopul rep l a~ed b y. '-ector o f four inpUIs. i5 10 b e d e. igned, Sin~ Ihe informali on in pu l. I re a ,'cctor. Ihe out p ut Y a lso l.>e<:omes a !o ur-.,Ie menl vcolor. The im plemenla!ion for Ihi. multiplier req uire. a 2'10-4-li no docoder, 8~ given in f i gure 4-7, a nd {ou r 4 >c 2 A ND O R gales. Thc r ew lling S1ruc\ure is shown in ~Igu", 4-16. This ot. ructure has . gole input " ""nl o f 10 ~ 32 16 '" 58. In contraSl, if four 4 input multipluers i mplemented , ,;th 3-input l i tes ..-ere p laced . ide by . ide. the g ate i nput COlInl would be 76. S o, by sharing Ihe d ewdt r ..-e reduced t he g ale inPUI c oun!. A lternative s election I mplementatlon8 By us in g Ih ree-5lale drivers a nd I r~ n smiSJion gates. il i . possi b le to i ",plc",cnl d ala selcclors and mull iplcxe . . wi th e "en 10" '.' COSI Ihan is achievable wi llt gales. 1 60 0 C HAPTER 4 1 C O MBINA TIO N AL f UNcnONS A ND C IIlCUITS o n GU R fo:4-16 A Quad 41<>- I Une Mul,jplexer T HREE-5TATE IMPlEWE~AT100S T hreestate dri>cr" introduced ill C hapt er 2 . p ro vide an a lternative im pleme ntation o f mu lt iplexe .... In the im pl ementat ion giye n;n Figure 4.17(a}. four ) . <late J ri," rs with their outputs connected to Y Teplw:e enabling ci rcuits and the output O R g ate to give a n impleme nt ation wit h a gate input co unt o r 18 . 'n ,e log ic ca n b<: " duced rUT ther by distributing t he d"ooding acTOSS 1he 1hree-st~te drivers as shown in Figure 4-17(b). In t his case. 1hree pairs of e nabling eircuit<. a ll with 1WO . o utp~t d ecod.rs c o nsis1ing of s imply a wire a nd in,wler. drive Ihe e na ble inpu t ~ T he gate input coum for t hi. circu it is reduced to j ust 14. .n As a modi fication of t~e J -s1a te approach in Figure 4. 17(b}. ""I~ction ci rcuits can be constTucted with transmission ga les. This implcmcnlation. shown for 4-to -1 selccrion in Fig ~ re 4 -1 8. uses transmi>sion ga les a , . w itehes. Th e TG circu it pro_ides a transmbsion path be tw".n each / input and the Y oU1put when the two selecr in puts on the transmission gates o n the p ath ha>e tbe val ue of 1 on the terminal without a b ubbl" and 0 On the terminal wi1h a bub ble. Wit h the opposite "alue o n a selecr input, o ne o f t be 1ransmission ga te , o n the TRANSMlSSlOt! G ATE IMPLEMENT AT10N , " 0 ,' " 'f C- "-I .., " " o ~l GU K E4- 17 Scleclion O =,to U. ." , llI~"""te Dr;"" . . p alh beh.a\'CS ~ke a n o pen " " . . c h. and the 101 11 ; . d iMonnected. 1 be two '!election inpuls S, a nd So c ontrol t he tnn~miS$iOn p aths in t he T O circulll.!'Qo- uample . if So - 0 a nd S, = O. I Mr" is a dOOlCd pIIlh from input I . t o o utput Y. and 1M OIlier th ree inpu~ a ,e d isconnected by Ihe m her T O circuil>. T h" c ost o f t ransmission &Btl' i . c q uivaleOl to a g ale i nput c oun , Qf one. ThUs, t he g ate i npul COOn, o f I lln transmission galc-baoed m ul,i plner is e ight. 4 -6 C OMBINATIONAL F UNCTION I MPLEMENTATION lftcodCfS a nd m ultiplexe. . can be u sed t o impleme nt B oolean f unction!. In addi lion. the p rogrammable logic d evi~$ inlfoduced in C hapler 3 can 1M: viewed as c omaining f unct ional b lock. sui'able for implememing combinational logic funelions. In this = 'ion. we cover the u se o f decr>ders. multiplexer;_ rcad .<.>nly m emo o riel ( ROMs). programmable loVe arrays ( PLA.). prosramm.bl~ a rray logic dc~kel ( PALs). a nd l oo~ ~p t .bl~s ( LUTI) f or u nplemcming o omb'M ll ona l logic function .. 1 62 0 C I-I/wrel<. ~ I C OMBINATIONAL F UNCTIONS A ND C IRCUITS , V , V I ro (So - Q) '. I TO ( S, _ 0) ro (s. - I) TG (So - 0 ) 1 '0 ( S, _ I ) IU (50 - I ) '. T o n GU R F, 4- 18 ' -1o I Lin< Mull;pl<, er u ,;ng TTan>m;";",, G ale, Using Decoders A d ecoder provides (he 2" m imerms o f " in pUl variables. Since any Boolean function can be c .pres..,d a , a Sum of n ,i ntenn s. o n" can use a de~oder t o g enerate the minterms a nd c ombine t hem wit h an external O R g ate t o form a sum ofmintenn$ impi<:menlnl ion. In this way, any combination~1 circuit with II i npuls a nd", OUIPUI, can be implement ed with an II . to2" linc d ecoder a nd / Ii O R gales. The p rocedure for implemenling a combinational circuit by m ,.ns o f decode r a nd O R gales requires I hatthe B oolean function. be expressed as a sum o f min t crm~ This form can bc o btained from Ihe Iruth lable o r by ploning each funclion on " K-ma p, A d ecoder;' chosen o r designed Ihal g enerales a ll Ihe m int erm< of Ihe inp ul ,'ari.ble$. The inpulS t o each O R gale a re s elected as the a ppro priate mimerm o ut put, accord in g 10 the lisl of mi nt erm, of each funclion. This proce. . is , hown in Ihe n Ul e~amplc. ~; XA~lI'LE 4-6 D erockr . .... O R G. t ~ Implenlf:nt.tiOll o r. BilllOr)' Adder I IiI In Chapt~r I . "'~ consid<:.ed binary addlllOll.ll>e sum bit o utput S .nd the carry bit output C for a bit " "" i.ioo in 1M addition a re given in .errI15 o f Ihe 1..... 0 bi ts being added . X a nd Y. a nd 1M incoming t arry f.om the ris.hl. Z. in Table 4-8. o T ,\BL F.4--3 tru.h T.hle f "l" l lHt Bin ..,. Adder ,,,,, ,,, ,,,,, ,,,", ,,", ,,,,, ,, , , , I '.OOllhi r u.h lable ...... e o b.ain Ihe funel;on. fot: I he ""mbinalional cir<;uil in sum ofminlenns form: SIX. Y.;!) _~ "'(1.2.4.7) C (X,Y.Z) "' ~",(3.5.6,7) Since there are I h.ee i npul. a nd 8 l olal o f eight m;nlerms. " 'e need a 3-10-8 Ii"e de<:ode . l l>e implemenlalion '5 . ho,.n in FIgu,e 4-19. 111 c dtt-odcr generales all e;glll minterm, for inpulS X . Y and Z. T he O R g ale for OUlpul S f o.ms lhe logical . s um o f m inlerms 1 .2.4. a nd 7. T he O R g ale for o utput C forms the logical ~um o f m 'nle . .... 3. 5. 6. a nd 7. MinlCnn 0 " n O\ w.ed. A funl."tion wilh " long los t o f m[nlerms ' '''lui"" an O R g ale , ,i ,h l uge n umber o f inpUIs. A function h a',nll lIS t o f k m intenn. can b e expreW!d ,n ilf complement form ..... ilh 2" - k min,cnns. If Ihe number o f mime . .... in a func.ion F i ,veale. Ihan 2"f2.lhen Ih e co.nplemcnl o f F. F. c .n b e c"pr~ ,.ith fe....-c. minl e.ms. In , ueh a C8S<'. il is advantA geous 10 use a N OR gale instead o f an OR gale. The O R p ortion o f Ihe N OR g ale prnduccs Ihe logical , um o f Ihe minl e. "" of .;;-. The OUlput bubble of Ih e 1'1011. g~le complements Ihi. sum and generales Ihe normal output f: llI e dcooder melhod can l>e uoed 10 ""plemen! any combina1lonnl circuit. 1 lowe,er. Ihi. implemenlalion mOSI he co mpa",d ,.;111 olh~ 1" " "",ible implemctlla. lion. 10 d elermine !he " "'. solulion. The: deoo<kr melhod may provide lhe b" , 1 solution. p ankularly ir 1M combinallOnal circuit II many OUlpu~ based on Ihe same in p "l~ and each OOlpul function is expr~'<l \\,Ih a <maU n umber ofminlenn$. 1 6" 0 C HIIVTER ' I C OMUINIITIONAL f UNcnONS A NO Cll1.CU lTS a n GU R E 4 19 Implemenling ' Ilulary AddoT U si ng> De<:odeT Using M ultiplexers In S eaion " .j. " 'C l eamed Ihal I decoder oombin~d " ';Ih an I II" 2 A ND-OR g a le i mplemcnu I multiplexer. The dc<:oder in lhe multip lcur g eneralcs Ihe minlerms o f Ihe s ellion inpulS. The AND-Oil. gale pro,ides e nabling cin:uil~ Ihnt determine " helher the m inlem,. are "all"ched It> the O R g ale with Ih e info rm .lion in pulS (/,l used . 5 Ihe enabli ng , igM Is. If I , inpul is I. Ihe n mi nlerm "" i . allached 1<.> th e Oil. gate. and. if the I, input i~ a O. Ihen minterm rII i i , replaced by ~ o. V~lt j e_ h ing applied 10 the I inpu1' provides a melhod f<.>< im p l."",nl,ng 8 O()Olean funcI.... n o f ~ variabl. . with a muhiplexer h~vil1g II selection inpul5 a nd 2" d ala II1p u lS, one for each m inlenn. F unhcr . an ",-oUIPUI funclion can be implclnC'nlW by using value-fix'ng o n a m uhiplexer " 'lb m_bil informalion vecto,", iMlead o f Ihe indr.idlIall bilS-1S i ll",'nIW by the nexI e nmple. E XAMPU: 4-7 M ullipluer Imple n,e n'Mli od o f. Hina.,. A dde. Ril The values for S a nd C from Ihe 1_b il binary a dder Irulh lable si,en in n.ble 4 -8 can be gencTIIled by USing v.lue-fi~in8 0 11 Ihe i"forma lion inpulS o f a multiplexer. Sin.oc ' hc", arc Ihr~e sel~clion inpulS and a 10lal o f . igbl minlerms. .... c need Bd ual S- lo-I-Iine multip le xer f or implemenling Ihe 1...0 OUlpulS, S and c.1"he ; mpl."",n . lalion based o n It..: uUlh labie is d \o.... n in Figure 4-20. E ach I"'ir o f values. M>Cb as (O. I ) o n ( I". I,M. is l aken direclly from Ihe corresponding row o flhe laSI 11.-0 t rulh lable columns. A I1Wre efficient m dhod i mp1tmcnl~ a Boole a" funchon o f" variables "';Ih a m ul\'plu er Ihal has only II - 1 sel""lIon inpUi s. The f irst" - 1 v ariable, o f Ihe fu nction ~re oonn cckd t o the selecliml jll pu," of Ihe m~hiple~cr. 11,e remaining ,ari;,ble o f Ihe fUII Clioll is u ,ed lor Ihe infor ma lion i!puts. If t he fina l vuriable i5 z . each dalu inpul of Ihe mu ltipluer wi ll be ei lher Z. Z . I. o r O. The funclion can be im p lc"",nlW by 811aching inlplemcnl at;Qn5 o f Ihe four rudimcnlary fU"",, l ion. from . _6 I Combin>tion.1 Fon,ction Impl.nt.nution , ," , =" "=" , "" '" "='I" = ,., 'I" ,., ,='. . "- ''". "" , ',. ='" ='. 0 1 65 ~" 8 "0-1 SO M V" 11.< , '. ~ , " 1" , o n CllR !;; 4 - 2(1 I mpicmcnling . l-bil l ),nary A<kler ... i," a DuaI8 _to-l _Line MuhipleT T.. bl~ 4_1 t o the information in puts t o the multiplexer. T he next example demonSlrnK"l this pTOC<'durc. Alt~mati"e M ulliplcxcr III'plclncntuliun " f M MinaI')' A dder Hit This function can be i mplemented with a du~ l 4_to _J_li ne multiplexe r. as shown in Fi8ur~ 4_2 1. T he d esisn pToc<:d u r ~ can be ill ustrated by considering t he SLlm S l he Iwo v"riablc< X and Y a re applied to the selection l in~ $ in Ihat o rder: X is conne<:led 1 the S , inpu1. and Y is c onnected to the SG input. T he '-alue< f '" the data 0 input linc. a re d etermined fTOm ' he (TUtlt (abl~ o f (h e function . Whcn ( X, Y ) - 00. the u ulpul S is <XJuallo Z because S _ 0 wh~n Z _ 0 and S _ J when Z - I. T h is E XAM P....: 4-H " Sl Y SO D tal ~t(>-' M UX , , o n eUR E 4-11 I mplementing' j _bit BinaT YAdder wi th. D ual S-tt}-l _Li ne MultiplexeT 1 66 0 C HAI'TER 4 I C OMBINATIONAL F UNCTIONS A NI) C IRCUITS requircs that the var i abl~ Z be applied t o informalion input foo- The operation o f the multiplexer is such tha t. when (X. Y ) 00. informalion input foo has a p ath 10 the o u tput that makes 5 equal t o Z, I n a similar fashion. we can determine the required input 10 lines ' ,. . f>n- and I)IJ from Ihe vat ue o f 5 when ( X Y ) 01. 10,and I I. respecti,'ely.A similar approach can be u ",d t o d etermine the valu,," for [O!' f ll , . ~.~~. T he genoral procedure for implementing any Boolean function o f" v ari.bles with a multiplexer w"th n - I sdeetio n inputs and 2"-1 d ata inputs follows from the preceding example, The Boolean function i . firs! l i.ted i n" t ruth table. The firs! n - 1 variahles in Ihe lable a rc appliN t o Ihe seleetion inputs o f tne mu ltiplexer, For each combination of the s eleetion variables. we evaluate the o utput as a function of tlie last variable. This function can be O. I, the variable. o r the complement of the variable. These values are then applied to the appJOpriate d ata input s. This process i. illustrated in the next example. E XAMPLE 4-9 Muhipk>. e . I mplementallon o f 4Varlable Function. As a second example, c onsider Ihe implemenlalion o f t he following Boolean function: F (A. B, C. D ) = ~",(1. 3, 4. J I. 12. 13. 14. IS) This function is implemented with an 8 x I m ultiplexer"" shown in Figure 4-22 . To oblain a c nrrect rcsul[, Ihe variables in t he truth table are c nnnecIN 10 selection inp uts 52' 5 " a nd 5 0 in the o rder in which they appear in Ihe table (i,e .. such Ihat A is cnnnected t o 5,. B i , cnnnc>ctcd to 5 ,. and C is c n"""" ted to So. re<pectively). T he value< l or the data inputs are d etermined from the truth tablo. The information line number i . d etermined from the b inary combination o f A, B, and C. For u ample. when (A. B. C ) - 101, the truth table shows tbat F - D: s o the input variable D is applied 10 information input f J' The binary const ant. 0 a nd I c orrespond t o IWO fixed signal ,alues. Recall from Section 42 that, in a logic schemat ic. these constant values are replaced by the ground and power sy mbol' a , , hown in Figure 42 U sing Read-Only Memories O n the basi. o f the d ecoders a nd multiplexer> covered th us far. Ihere are Iwo approaches 10 the implemenlation o f r ead-only memories. O ne a pproach is based o n a d ecoder and O R gates. By inserti ng parallel O R gate,. o ne for each ROM o utput. to . um the minterms o f B oolean functions. w w ere able t o g enerate any 'e desired c ombinational circuil, The ROM can be viewed as a device that includes both the d ocoder a nd the O R gates within a s ingle unit. By d osing cnnnections t o Ihe i npuls o f an O R gate for those m interm. that a re included in the function. the ROM outputs can be p rogrammed to represenl t he Boolean functions o f t he o ut p ut variables in a c nmbinational circuit. The a lt ernative approach i. b a",d On value-fixing on a multiple-bit multiple,cr, Th e I, " .tuc. are u ",d as e"abling , "' 0 ", , "" " "" " ,, , ", " " , ","" , "" , " ,-" , " ,-o , , c 8 xlMU X ' ,. , , - o ," , , ,, , " , -, " ,, " " " , " " , " ,-, , "" , " " ,, , , , " , , " , -" " , , , -, ,, , ,", , " , " , ; L, , " ' -- , r- L ,,,, , , , , , , , -, o " 'CURE 4-11 I mpkm<nting 0 R:>u,-lnpul Funtlion , ,;111 " M ulliple.er signals t o d etermine whi ch mimcrms arC connected 10 (he O R g.lC$ wilhin {he m uh iplexcr bilS. This i< illu<lrated by E xample 4-8 which is e<Juivalent t o a ROM wit h three input' a nd tW<J ou{plllS. The " programming" o f l hi' ROM a pproach i , d one by a pplying l he trUlh , able to th e in/(lTm",io" inputs to (he m ultiplexer. Becau:;e Ihe d ecoder and O R g ates approach is j ust a di fferen t m odel. it 100 can be ~progra mmcd " by us ing a trul h l able t o d etermine the conneelions between thc d ecoder and the O R gates. ThUs. ;o practice. when a comb in ational eireuil is designed by m eans o f. R OM. il i . n ol necc<sary to design the logic or 10 show {he i nlernal connectio"s inside the uoit. All that (he design er h a, 10 d o i , ' p"cify Ihe p anic ular R OM hy ils name a nd p ro, ide Ihe Iruth l able for Ihe R OM. T he Iruth l ah le gives a lll hc i nformal;on for programm ing (he R OM . No inl ernal logic d iagram ;s n eeded (0 a ccompany Ihe l able. Example 4 - 10 shows I hi' usc o f a R OM. t :XAMPn: 4-10 lmp(ementJn~ a Combin~lional C irmil U'i"~ a ROM De,ign a combina li ona l circuil u ,ing a R OM. T he circuil accepls a 3-bil n umber a nd g enerales an OUlpu t binary n umber e qual t o Ihe . q uare <.>f Ihe i npul num ber 1 68 0 C HAPTER 4 I C OMBINATIONAL F UNCTIONS A ND C HtCUITS T he first s tep in d e,igning the circuit is 10 d erive the truth t able o f t he combi"lOtion" I cin;uit. In mo>\ cases. t hi' is a ll t hai is n eeded, I n oth er ca:;cs. we can use a p artial truth table for I he R OM by m ilizing c erta in p ropert ies i n the o utput variables. Table 4 -9 is t he t r uth tohle for the combinational circuit. ThTCe inputs a nd six o ut puts aTe n eeded t o a ccommoda te .11 o f t he possible b inary numbers. W . n ole thai o ulpul 8 Q i . always eGual t o in put A o,so t here is n o n eed t o g enerate 8 0 with a R OM. M oreover. o utp ut 8 , is . Iwa)'s O. S (l this o u t put is a k nown c on,tanl. T h U s. we a ctua lly need t o gener-ne ' m ly f our o utputs with the R OM; t he otheT lwo are TC;>dily o blained. T he m inimum size o f ROM n eeded TII ust have t hree i nputs a nd four o utputs. T h ree inputs specify eighl words; SO t he R OM must be o f size S x 4. T he i mplemenl al ion o f I hc R O M is shown in Fi guTe 423. The t hree in puts specify eight words o f f our bits each, T he block d iagram o f Figure 4-23(a) ' hows t he req ui red c onnection. o f Ihe comhinational ej'CIIit . T he t ruth t able in ~-;gUTC 4-23(b) specifies t he i nformation needed for programming the R OM. o T A8LE4-9 Trulh T~bl~ f or CI ..... lt u r E u n'ple 4-10 . " .. '. " ,'. '. ," ,'. O utput. I nput . , ,,, ",,",, ", ", , " " " , ,, " , , "", ", ",",, ,,, ", "" "" ," ,,,, " "" D ecImal " , ,. , 0 , , -- " 8 x '''OM " '. " " o ~ ~ " '. " ' . '. " ',. 0,, , ,,0 ,,,, "" ", 0 " , , " 00 0 , , ",, , " , "0 ", 0 0 "" ( b) R OM " "'h lObi< F IGURE 4-23 R OM Implom<"lation of Example 4 10 ROM d ev ic es are widely used to imple ment c omplex c ombinationa l circuits directly from the ir t ruth t ables. T hey a re u seful for conve rt ing from one code. such as Gray c ode. to a not her. s uch as BCD. T hey can g ene rate complex arith metic o peratio n s. such as m ultiplication or division, and in general, t hey a re used in a pplications requir ing a moderate nu mber of inputs and a large n um ber o f OUtputs. Usin g Programmable Log ic Ar ray, T he P LA is similar in concept to lhe ROM. except that the PLA does not provide fu ll decoding of the variables. so it does not generale all the minterms. The d C>der is replaced by an array of A N D g ates.each o f which can be programmed to gener_ a le any p roduct term o f t he in put variable . . T he product lermS a re then selectively connected t o O R g ates as in a R O M to provide the sum of pr od ucts for Ihe req uired fu nction s. Th e fuse map o f a P LA can be specified in tabular fOnTI. For exa mple. the programming table tbat specifies the PLA o f Figure 4_ is listed in Table 410. T he 24 table con,iSlS of three soclions. T he 6rs\ section lists the product term numbers. r ;' , , , , , , o " " X F. .. in,",,' ~ F u b Ion "' ABC V F IG U RE 4-24 P LA "'i,h Three Inputs. Foor Proou<1 Terms. and T "" O",pUlS , " 1 70 a CHAPTEJl ~ I C OMurN"TlON"L f UI'CTrONS ...r":D C UI.cun'S D T ARLE4- IO " r""",nmlftJ T. ..... r Of lbe I'LA I . Fogure 4-2.1 .~~ ,,~ A' AC ,e ARC , , , , ""'" ~ .... , , I'n '" .. ", The second $ lion lopCOlks rhe r equ"td palhs bell" ttn inpulS and A ND &lites. 1'11 t hird $ lion s~ilks the paths between the A ND a nd O R p Ies. For n ch o utput variable . .... e may have a T (for t rue) Or C (fOT c omplement) for c ontrollin, the OUlpul exdus;veO R p te. 1 'he product I c"", listed o n the leh a re n01 p erl o f the table; they are included for reference only, F01- each product t .rm. rhe Inputl are mar~.d wi th I. O. o r _ (dash). If a variable in t he producl t.r m a ppears in ils true form . the correspondIng i "put variable is marked with a I . If t h. variabl. in the product term a ppearJ compic men ted. Ihe corresponding inpul variable is marked wit h a O. If t he v"ri"ble is al)$C tl1 in Ihe p roo uct tcrm. it is ma'ked with a dash. n ,c paths between the input. a nd the A ND gates " rc s~ified und er I h. col . umn heading " Inpuls" in the table. A I in Ihe inlmt column ' pedfiel " CLOSED cirru;t from 1 M: inpur variable 1 0 the A ND g ate.A 0 in I h. inpul column specific. a CLOSED cirruil from lhe complemenl o f lhe variable t o the input III the AND gale. A da$h specifie. O I'EN c rrruil' for both t he inpul variable and itl complemen1. I t . . assumed that an O PEN lerminal On Ihe input III a n A ND p tc b ehl".,. like a I . The p ath. h etween the A ND a nd O R gales a re specified u nd.r Ihe column h eadin, OutPUIS. - 1"htc ou tput variables a re m arked with n for those product ter m, t hat a rc included in the function. Each pToduCI l eno Ihal has a I in Ihe o utput column r equires a C LOSED palh from the o utput o f the A ND p Ic 10 Ihe input o f Ihe O R gale. ThO$C p roduct t erm, m arked wilh d ash specify an O PEN circuit. II is 3nun>cd Illat a n o pen terminal on Ihe input o f ~n O R g "le bellaves li ke a O. Fin.lly. " T ( true) output diclOle, th aI the <>Ihcr , nput of I h. c orre'pon ding XOR gRle I", conn~ c ted to O. a nd a C (compl emenl) ' I",df,es " conneclion 1 0 L The size o f a I'LA IS s pedO.d by Ihe n umlxr o f inpUI s. the n umlxr of prod uct lenos. and t h. number o f out put s. A typical P LA h al t 6 i npu". 48 product tern,s. a nd eight OUlputS. FOr n inpulS. I< product IUms. and m OUlpuU. the inlernal logic o f lbe P LA consist, o f " buffer_Inverter gales. k A ND gales. m O R l ales. a nd m XO R gates. 1"htcre a rc 2 n)t k p r"".mm.bl. conntthOru: between lhe inputs and the AN D arra~. k ) t ' " programmable connections b et"".n the AN I) . nd O R arra)~ and m pr<>&rammabl e ronnectlOn' ~3ttd " ith the XO R p tes. 4 _6 I Combin>cional Fu",c\ioo Impl<m<ntooo" 0 1 71 In designing a digital system with a P LA. t here is nO n ted to show the ,nter_ nal connections of t he unit. as was d one in Figure 4_24 . A ll t hat is n eeded is a P LA p rogramming t able from " 'hich the PLA c an b e progra mmed t o s upply t he required logic, As with a R OM , the P LA may b e m . . k p rogrammable o r fi eld p rogrammable. [n impleme nt ing a combinational d rcuit with a P LA, a c areful inycstigation must be u ndertaken in o rMr t o rcduce thc number of d istinci proouci term . . 5 0 t hai the complexity o f t he circuit may be reduced, F ewtr p roduct I~r m s c an b e achie, 'ed by si mplifying th~ B oo lean funclion to a minimum n um ber of lerms. T he n umber o f li t eral, in a t erm is less i mportant, si nce a ll the input variables are ava il able anyway. I t is wi.." h owe"cr. t o avoid extra literals. as these may cause p roblems in t esling the circuit a nd may reduce Ihe speed o f the cireui!. Both the true a nd c omplement forms o f each function shou ld be simplificd 1 0 s ee which one can be expressed with fewer prooUCI l erms a nd which one provides proouci t erms Ihal a re common t o o ther functions, This process is shown in E xample 4-11. E XAMPLE 4-11 Implementing a Combin~lional C irruif U'in~ a P LA Implement Ihe fo ll owing Iwo Boolean functions with a PLA: F ,(A,B . C) _ :!;m(O.I,2,4) F ,{A,B.C) - :!;m(O ,5,6,7) The 1wo funclions a re simplified in Ihe maps o f Figure 4 -25 , Both the true a nd c omplement outpulS o f the functions are si mplified in s umofprodu ct< form The combin ation that gives a mi ni mum n umber of proouci t e rm, i, F , _ AB+AC + BC 1'1 - AB+AC+ABC T he simpli fi calion gives four distinct proouci lerms: A B, A C. B C. a nd A BC. T he PLA programming lable for th is combination;'; shown in t he figure. NOle t hai outpul Fl. is I hc true o ulput, e,'en Iho ugh a C is marked o ,'er it in Ihe lablc, Th;,; is because F , is g enerated with a n A ND -OR circuit a nd is~vai l able a l t he o u tput of thc O R gate, Th e XOR ga te complements Ihe function F , 1 0 produce the true F, output. U sing P rogrammable A rray Logic D evices In d,,", igning wilh a PAL de,jce. Ih e Boolcan funclion, must be .implificd to fit into e ad, "'Clion as ilill5 traled by the example PAL device in Figure 4 26. Unlike t he a rrangement in the P LA.a produci lerm cannol be shared among Iwo o r more O R gates. Therefore, each funclion can be simp li fied by it,elf. withoul regard t o 1 72 0 C HAPTER 4 f C OMBINATIONAL F UNCTIONS A ND C IRCU I TS " , ; :;;, 00 01 oc ' ~OOOIIlIO to II , G::EEE] +~ c A I:. c F\ _ AB + AC +BC F, _ AB+AC +ABC F, _ AB~AC ~ BC F _ AC ~AB +ABC , Out""" f'<odutt term 1o""" (C) A BCF, ( I) F, , , AO , ,,, A BC " o FIGURE <C , OC 4-ZS Solu tion to Exampk 4-11 common p roduct term .. T he number of product l erm, in each ..,ction is fixed. a nd i f the n umber o f t~nns in the function is too large, it may be neceilSary to use two o r more ..,C1ion. to im plement o ne Boolean fu nction. In , u ch a ca.." common lennS may be u seful. This p roass is illustraled in Example 4 -12. E XAMPLE 4-12 iml'lenlenting a COInbinational Circuit U ,ing M PAL A s a n example o f a PAL device i ncorporaled i nto t h e design o f a c ombinational circuit, c on,ider t he following Boolean functions. given in s um _of_ minterms f onn : W(A ,B,C,D) _ :E " ,(2, 12, 13) X (A, B ,C,D) - :E " ,(7,8,9,10,11,12, \3, 14. 15) Y(A, B ,C,D) ! " ,(0,2,3,4,5,6,7 ,8,10,11,15) Z (A,B.c'D) - ! m (I,2,8,12, 13) Simplifying the fo ur functions ing Boolean function" to a minimum numt>er of terms results in t he follow- W = A BC+ABCD X - A + BCD , o w F lGUKt: 4 U; Coou.k>f, M .p for P AL. Do .. "", for E umple 01.-12 t 74 0 CH~i'TUl-' I CO MIIIN~T10N~l F UNCI"IONS ~ND C I><'C UITS y - AB+CD+BD z . A BC+ABCD + ACD+ABCD - W+ACD+ABCD NOle Ihat Ihe funclion for Z h as f our prodllCl lerms. T he logical s um o f 110'0 o f Ihe se l er ms is e q ll;l l 10 IV Tllu", by using W, il is possible to r educe Ihe n umber o f l erms for Z from four 10 Ihree, s o Ihal Ihe funclions c an fil i nlo the P AL device in f igure 426, n.e PAL programming t able is sin,ilar t o t he t able used for the P LA, Cepl that o nly t he inpu15 o f t he A ND g ales nC<:<! to b e p rogramme\!, Table 4 ] 1 lis", t he P AL programming t able for the p r.a.ding four ! loolean functions. T he t able is d ivided i mo f our s ections "'ith t hree p roduct terms in e ach. t o c onform with the PAL device o f Figure 426, The first twO sections need only two product t erms t o i mplement the Boolean function. By placing W in t he first section o f t he device. Ihe fecdb3Ck conne<:tion from FI inlO t he a rray is avai lable t o reduce Ihe functi on Z to thT"" tenns. T he c onnect ion m ap fo r thc P AL device. as specified i n t he p rogramming t able. is s hown in Figure 4 26. FOT e ach I o r 0 i n t h t able. we m ark t he c orre s ponding i ntersection in t he d iagram with the s ymbol fo r a C L OSED c iu it COn n ect;on. FOT e ach d ash. we m ark t he d iagram with O PEN circuit c onnections f or b oth t he t rue and c omplement in puts. I f th e A ND g ate is nol used. we lea " e all o f i ts i nputs as C L OSED circuits. Since the c orrespondi ng inpul recei,'es b oth the l rue a nd I he c omplement o f e ach i nput variable. we ha'-e A 'A x O. a nd t he o utpul o f t he A N I) g ale is alwa)'1 O. o TAHI.E .... 1 t I'AI.- 1'."V"n.mlnl Tobie for F..an.ple 4t1 , , Produc. , , " U " AND Inpull ,, , "" " , 0 0 " " " " """" W D Ulpuil w_ '"< + A8CD X- X + BCD ,- " ,- ' CD + 8D W + ACD + AR CD 4 _61 e omblla,ion. l Fun<tion Impl<mo;n"tioo 0 1 75 Using Lookup Tables Field-programmable gate array~ (F'PGA~) and complex programmable logic devices ( CPL Ds), often use lookup tables ( LUTs) for i mplementing logic, Programming a ~ingle function w;th m i nputs is the same as p rogramming" single o u tput R OM (Le., the look up table simply s tores the truth table o f the fun~lion). An m -input lookup t able can implement any function o f ' " o r fewer v ariables. Typically, ' " ~ 4, The key p roblem in p rogramming lookup tables is dcaling with functions w ith> ' " i nput ,-ariables. Also. , haring o f l ookup tables among multiple functions is i mportant, T hese problems can b e d ealt with using multiple _ level logic transformnlions, primar il y decomposition and extraction, ' ll1 e o ptimization goal i. t o implement lI'e function o r functions by using a minimum number o f L UTs with the constraint t hat a single L UT can implem ent a . u bfunction o f a t most m variables. This ca~ b e accomplished by finding a minimum n umber o f equations. each with a t most m variable~ t hat i mplcmem the d esired function o r funct;on~ This p rocess is ill ust"ted for s ingle-<>utput and multiple-out put fu n ctions with ' " ~ 4 in t he following examples. I I<:XAMI'Lt; 4-13 I m" lcn,enting .. Single-Output . 'und;oo " jlh L.K.ku" T.hlco I rnplem"ntth t fQlIow'"g Boole"n functIOn w;th lookup tables' F t(A,R,C, 0 , E, F ,G,H,I) - ABCDE'" F GIIIO E; T he n umber o f input variable, for a function is called the s upport s o f the fu~ctio n . T he supporl for F, is s .. 9. I t is "Pl"'rent that the minimum n umber of l ookup tables k n eeded i, a t least 914 (i.e., k . . 3). Further. for an m_ output function, the minimum n umber o f lookup tables for a single-<> utput function mll5t o bey an even more stTingent relationship, m k ~ s + k - I, SO k must . . tisfy 4 k ~ 9 + k _ 1 Solv ing, k ~ 3, s o we wi ll loox for a decompos ition of F, in t{) t hree oqu"lions. each wi!h at most J " 4. Factoring F,. we obtain F , _ ( A/JC)l)l;.' ''' ( FG I/I)O : Based o n t hi' c quatiM, P, r un be decomposed into three e q uations with.,,; 4, F ,(D,E,X"Xl ) X ,DE+ X ,DE X ,(A . B.q _ A BC X ,(F,G,fI,I) _ F GIII Each of these thTCC e quation, can b e i mplemented by o ne LUT. givi ng an opti_ m um implementation for Ft. 1 76 0 C H AVTEII. ~ I C OMnlNAT IONAL F IJ"' CTI ONS A ND C IRCU I TS EXAM PLE 4-14 Irnplc'O>enting _ l'tIullipic:OuIPUI Function " llh Lookup Table,; Irnplernenllhe foUowing pair of Boolean functK>n with loo~up lables, F ,( A.B,C,D,E.F.G , II.1) - ABCDE+FGIIIDE F:( A,B,C,D ,E.F.G.fU ) - ABCEF + FGHI Each of th e.., functions req uires a suppo rt s ~ 9, Thus.. at leasl t hree L UTs are required for each funetio n. Ilut t",o o f the LUTJ can be shared, SO the minimum number of LlTfs n eeded is k , . 6 - 2 , . 4. Factoring Fl with sharing o f e quations witb the decornposilK>n of F 1 from the prevK>us u arnple &i'-es F, _ ( ABClF+(j.GHI) This produces an u traction for FJ a nd f i e F ,(J),E,X" X1) - X , OE+X,J)E F ,(E,f:X,.X:) = X ,EF + X , X ,(A,B,Cl - ABC X ,( F.O.JI.I) _ F Oil' In this = . t he extraction requires four LUTs, the minimum number. Note that in general, there is n o g uaramee t hat a de.:omposition or e ,t,"clion can be found t haI requires the minimum n u mber of LUTs calculated. 4 -7 HDL R n'IU' ''ENTATION FOR C O .\ lRINATIONAI. C IRCUlTs--VHDL Since an H OL is u sed for describing and designing hardware, il is VCT)' important to ~eep the undcrl)ing h:u-dware in mind as you wrile in t/ll: language. This is p"-I1irularly cri6ral if your language description is to b e s ynthesiud. For example. if you ignore lhe hard"....-e tbat "'ill b e generated, il is very easy to specify a large complex gale >lTUClure by using x (mulliply) when a much simplcrstTUClure usin g only a few gates is a ll tbat is needed. FOr this reason. we initially emphasize description o f deJailed h ard""re " irh V HDL a nd proceed to more abslract, higher.le""l d =riptions later. Selected e xa mple. in this chapler a re u..,ful for imroduc;ng V HOL as . n a lternative m ean. for r epre""nting detailed digital circuit . . Initia ll y, we show structural V HO L de5criptK>ns t hat replace Ihe schernal ic for the 2-!0-4-line decoder with e nab le giv~n in Figure 410 o n page 152. This e xample a nd one using the 4-to-l -line multiplexer in Fi gure 4-14 on page 158 illuslrale many o f Ihe f undament al conct!pls o f V HDL We then p resent higher level functional and behavioral V HDL descriptions for these circuits that further Hl usuate fun damenta l V HDL concepts. t :XAMI'L 4-15 Structural V IIDL f nr a l - tn-4-Llne D eroder Figure 4-27 sho"'.. a V HDL description for the 2-10-4-line d ecoder circuit from Figure 4 10 On page 15 2. This example will be used 10 d emonstrate a n umber of general V HDL fealures as well as s tructural description o f circuits. The te xt between t wo dashes -- and the e nd of the line is interpreted a , a comment. So the description in Fi gure 4 27 b e gi ns with a twolin e c omment id e nti . fying t he description and its relation, hi p to Figure 4- 10. To assist in discussion of _ _ 2 _ ~ o _ ~ L \"" D<K:D<kr w it h E nobl., S~ ruc~ur41 VHIlL """,,cr iptiC<l _ _ {S<><> F igur. 4 _1 0 f or l ogic d i"9"'""1 l ibr a ry i . ... l cdf_ vhd l, i _ . . t <Llog;'c_ 1 164 . 1 1 . l cd C vhdl . fWl<;J>r imo d l, e n~in d ecode c LtO_ ' _w_ en<Obl . h p ort (~ . 11.0 . A l , i n 3 tQJ.ogic , 0 0,01 . 02, D3 , o v.t 8 tdJwic l' ''I'" e"" deccdec:Lt o_4 _",_~1." a rchit e cture s t ruc tura l-1 o f ~nt deccde~-2_to_4 _w_ ~l e i. lUM c~tAND:l p ort {inl , i n :l , i n ~t<l. l og i c, o uU , o ut . teI_log i cl' . nd cooopon<Ont ; -'" --,, ,.0 , , ,1 , ,,:l , ,,3 , ,,40 ,,5, \ /6, ,, 7, "a, ,.9, " Ln . =, =, -, " -" ~ ~ W' ~ ~ ~, ~ ~, ~>, -, -~ ~ ~ ~>, ~ o -, t i n1 t i nl t inl t inl t i nl t in l l inl li n1 l i n1 li n1 ~ ~<Llogic; - > , " , ~U - > A OJlI: -> -> 0' 0' 0' " -" - > A lJlI, ~U 'M, " ,~ ,~ ~> . .0_ ", ,~ M, ,~ 0 ' -> ~ , W -> ~ , W .. -> ~ , w ~, W -> ~ -", _ u - > NOI ; - > N 11' _> A l.outl - > N 21, ~, - > N31, Al -", _ u -0' -0' -0' " 0 m , -0' _ m , _u . , rn, -, m , 0' ., ._.0 DOl , 0 11 , 021 , 031 , N GUR4-Z7 Stru<tur.>t VIIDL " " " " " '" " " U 0 0, 0 0 , 0 0, N 1, -, -, -, -, -, , " U U U p ort tinl, I n s t dJogic , o utl , o ut s tdJogic l, _ c <:epO.".nt , . ign.ol , , , , , , , , [>e ", ripllOO o f 2 t 0-4 Un< De< od< r - - 21 -- 2' - - 25 " " '" " " " 1 78 a C HAPTER 4 I C OM IllN AT10NAL F U N CTIONS A ND C ll"CUITS t e J1J t tb [s descriPt ion, c omments p roJJi ng numL . l ave L e n on , !gL , As a language. V HDL has a s}'nta. that descril:>cs precisely the valid constructs that can I:>c u<ed in the language. This example wi ll illustrate many aspects o f the syntax , In parlicular. n me the use o f " 'micolons. COmmas and colons in the description. Initially. " 'e skip li nes 3 and 4 of the description t o focus on the o vera ll structure. Line 5 I:>cs,ins the d eclaration o f a n . ",ity. " hich is t he f undamental unit of a V HD L d es ign. In V HDL . just as for a symbol in a schematic. we n eed t o give the design a name and t o define ils inputs and o utp u!$. This is the function of the . ",ily decloralion. J:n ~i~y a nd h a re keywords in V HDL Keyword" which we show in bold Iype. have a . pec ial meaning a~d cannot b e used 10 na me objects such as enti_ tie s. inputs. outputs o r signal<. S tatement . ntity decoder~2 _to_4_w_enable i . declares that a d esign exists wilh the n ame decode~_2_~0 _4_w_en . . b le. V HDL is c~ inse ns iti" e (i.e" names a nd ke y,,'ords a re nm distinguished by the use o f u ppercase o r lowercase leners), DECOD ER".2_4_W_ ENAB LE is Iho " "me as D ecoder _ 2_'_w_Enable and d ecoder _ 2_ ' _w_en able . Next. a POTI d iXlam/ion in lines 6 and 7 is used to define the inputs a nd o ut puts just as we would d o for a symbol in a schematic, For thc e . . mple design. there a re t hree input signals: EN. AO . and A t. The fact I h.t these a re inputs is d enoted by thc mode i n . Likewise. DO. D l. D2 and D3 a re denot~d as outpUIS by the m ode o ut . V HDL is a strongly.lyped language, so t he type o f the inp ut s and output must I:>c declared, In this case, t he t}'pe is s~<Llogic, which repreS(;ntS " ""dard logic. This tJ-'P" d eclaration s pedfie, the values that may appear on the inputs a nd the o ut puts. as we ll as the operations Ihat may I:>c applied t o the signals. Sta nda rd logic. among its nine values. includes the usual binary values () a nd 1 a nd Iwo a dd it ional " alues X a nd U. X represents a n un known value. U a n u ninitalizcd v .lu e, We h s"e chosen 10 use standard logic. wh ich in cludes thesc ,atues. since these values a re used by t ypical si mulation tools. In o rder t o u se the t}'pe s t <Llogic, it is necessary to d e fin e the values and the o perat ions. For C(l Tw enience. a p tldage consisting o f p recompiled V HDL c ode is e mp loyed. Packages a re usually stored in " d irectory referred t o as a libraTY, which is sha red h y $Orne o r all o f the tool u sers. For s td_lOlJ i c , the basic package is i eee. s t<Llogic_1l64. This package defines the ,'alues and basic togic oper. a tors for Iypes s td_ uIOIJic a nd s t d_ IO\Iic , In o rder to use s t <Llogic. we i nd ude line 3 to call u p the l ib r ary o f packages called i eee and include line 4 conta ining i eee . s~<Llog i c _1 164 . 1 1 to indicate we want 10 use a ll o f the p ackage s t d_lO\lic_1164 from the i eee library. A n additional librar y. l cdf_vhdl. conta ins a package cal led f unc-llri ms m ade up of basic logic gates. latchcs and nip. nor< described us in g VHDL, o f w hkh we use a U . L ibrary l cdCvhdl is available in ASCII for copying from the Prentice Ha ll C ompanion Webs it e fo r th e t e>t NOI e that the stateme nts in lines 3 and 4 are lied t o the entit y that follo "s , I f a noth er e ntity is included that uses type s t<LIO\lic and t he e\e. mellls from f unc-prims. these statements must I:>c r epeated prior t o t hat ent it )' declaralion, The e ntity dedMation ends with keyword " nd foll owed by the entity na me. Thus fa r. we h",'c discussc<l the equivalent 01 a schemat ic sy mbol in V HD L for the circuit. 4 _7 I I tnL R .ep","'n""on Ii::.. C ombino"on. l C ircui,.-VHDL 0 1 79 STRUCTURAL DESCRIPTlOH Next. we want t o specify Ihe funclion o f Ihe circuil. A parlicu lar r epresenlalion o f Ihe funClion o f a n enlily is called Ihe " "hilee"'", o f Ihe ent ily. ThUs. I he c onten . . o f li ne 10 declare a V HDL a rchileclure n amed 9 tructural _ l for the enti ly d ecoder _ 2_ to _ 4_ w_ enable 10 exisi . The d elail, o f t he "rc l1 ilect ure follow. In th is c a"" we use a " ",cwral "",crjption that is e quiv alent to the schemat ic for Ihe cireait given in Fogure 410 First. we declare Ihe gate ty(><..,. we a rc going 10 use as c omponents of our description in tines 11 Ihrough 18. Since we a re b ui lding this architecture from gates. we d edare a n inverter ca ll ed NOTl and a 2-inp ul A ND g .te c .llcd Illi02 as mmp.,,,ents. T hese g ale Iypes are V HDL descriptions in package func""p rims that conl~in Ihe ent ily a nd archileC 1Ur~ for e ach o f 11"1 " r a te>. T he name and the pori declaration for a CQmpoMnl mus t be idenlical 10 t hose for Ihe un derlying e nt ily. For N OT1.port giv~", the input n ame i nl a nd the o u tput name o utl . The < "mponent declaration fo r I\N02 )!!VeS in put n "m eS i nl and ; n2. ~nd OUlpul n ame o ut!. Ne~l . b<;fore specifying t he i nlerw nn cction o f t he gate\; which i5 eQ uivate nl t o a c ircuit netlist. we n eed to name all o f t he n et. in t he circuit. The inpuls and oulpulS already h a,. n ame . . 11,e inlernal nelS a re Ihe oulp ut$ o f I he Iwo i",crt_ CIS and o f Ihc teftmost fo ur A ND g ates in Fi gure 4-10. These o utput nets a rc d eciared as . jgnoi. o f Iype std_logic. AO _ " and A l _n a re t he signals for the two i ",crler oatpulS a nd NO. t ll. N2. and N3 arC the signals f "r Ihe four A NI) ga le outPUIS. Likewise. all o f Ihe i nput. a nd o utputs decl"red as p ort. a rc sign"ls. In V HDL. t here a rc I>oth signa ls and variables. Variables are evalualed inslanla_ neousty. t n c ontrast. signats ~rc c v"tualed at ~o m e fut ure p oi n I i~ lime. Thi~ ti me ntay be p hysical tinte. such as 2 ns from the current t inte.or may be w hat is called d elw limp. in which a . ign.t is evatualed o ne d elt" lime f rom Ihe curre ~t lime D elta lim e i . v iewed as a n infin it esimal a mount o f t ime. Some time dolay in evalualio n o f . ignals is e ssenlial t o the i nlernal o pera lion o f Ihe typica l digilat simu_ lator and. o f COUISC. b ased o n t he d elay o f gat es. is realist ic in p erforming <i m ul.ti,,"s o f circ uit s.. For simplicily. we ,,illlypically b e simutaling cirouils f ", c orrecl function. n ot for p erform"nce ' " d etay probtcm s.. F "r <uch fu nction"l si m_ u lation. it is e asiesl 10 lei Ihe delays d efault t o d elta times. ThUs. n o d e lay will b e explic it in o ur V HDL descriplio~s o f circuils. alt hough delays may a ppear in Icsl benches. Fo llowing Ihe d eclaration 01 Ihe internal sig na ls. th e ntain b ody o f t he arch it ecture . I''' t' with the k cyword b egi n. T he circuil dcscribed consislS o f Iwo i n"cr lc rs a nd e ight 2-i np\!1 A ND gales. Line 21 g ive. th e l abel gO t o I he lirst in>"<:rlcr a nd indicates t b al Ibe i nvert er is c omponenl NOTl. Nexi is a por~ . .p . which m ap' t he i nput a nd OUlp ut o f Ihe i nverter t o the signals 10 which Ihey a re c onnected . n ,is p ar ticular form of p ort m ap uses _> with Ihe p ori o f the g a te o n I he l eft a nd t h ~ . ignat t o , ,"hid il is co~n ~ctcd on Ihe right. For exampte. Ihe inpul 01 i nverle, gO is 11.0 a nd th c o utput is 11.0-". Lin es 22 I hrough 30 give Ihe remaining nine gales a nd the sig ~ ats c onnected t o Iheir inputs and o utput,. F or e xa mple. in tine 24. 11.0 and AI _ n arc in puis and N l is the o utput. Th e archi t ecture is c omple ted with the k eyword e nd followed by ils n ame s tructural 1 1 80 0 C HAPTER 4 1 C OMIJINATIONAL FU NCTIONS A N I ) C I R C U I TS E XAMPLE 4-16 SlnKfural V Hl>t fo, a 4-1 .... 1 M ulliplner In Figure 4-18. Ihe s trutlu rn l d esaiplion o f t he 4 -1<>-1 li"" mulliplcxc. from ~ u re 41 4 o n page ISS illu5lralel lwo a <kl ilK> nal V H D L ooncepl$: Ild_ losk_,'( tIO' lg a nd an aile rna live a pp roaclilO m"llPins p orls In lincs 6 a nd 7. inSlead o f s p ifying S a nd I as individual Sid _logic inp OII s, Ihcy a re specified a. JtJJogic_vt<wrs. In s pecifying ,'eClo, s, we usc a n ind ex. Sin ce - - 4-t o -l Li ne IIY ltipl.,..r, S~""' tu.al I IHl:t. D uc .iption - - IS- Figura 4 _U C or 1 "",le d.l~ . ... 1 1 11>ra rr 1 _ , Io:;I.Lv!><I.l: . ... 1 _ . at<Ll"",le_l16-4, aU . ledLvhdl . C""""-l><' ~ . all : a ntl ty .ultlplexar_4_to_l_a~ 1 . p on IS : 1 . . a t4.).Oql<:.-v..:t(,rIO ~o 1 ), I : h . _ t4.).ogl<:.-v..:..,..IO t o I I: V : o ut a ULIogicl: _ . ..1 t!pl""'_'_toJJot: a rcb1t..:nn a tnx::tuuU o f . . l t lpl.-r_ '_ to_ Lat 1 . c~.nt l OTI p ort l inl: I n a t<LlOqle: " " U: o ut n ",-!ogle): a nd e _. nt , e _ . n t 1IND.2 p ort l i nl. I n2, I " a t<LIOqlc, o u t l, o ut a t<L1Oqle), . n<! c I ' . .... t : C I . .... t aR' _ rt l l n l . In<!, t ill, I n', 1 . . a t<Lloqie: o ut! , o u.t n 4..1"",le), a "" " , _ n t : a i".... 1 S -,, : a t<LIOqI<:.-v..:t.orIO t o I I: 0 1"....1 D. N, a t.d...logl<:.-v..:torIO t o I I; ... ~ g O , l OTI p ort _ p ( SIO), \/ 1' NOTI \12 : N m \ / 1: M m g " AND:.l g 5, g f;, AND. " ' , 1IND.2 \/s , 1IND.2 g 'j , N fD2 g l O, O R' = _ 5.J>IOH: p ort _ p I SU), , -,,(111: p ort _ " 15.J>UI. 5-"101. 0101) , pO~t _ " ( 8-,,111. 5 10) . 01111 : p ort _ p I SIl) . 9-"1 01. 0 12)1 ; p ort _ " l SI],), S IOI. 01 1 11, po~t _ " ( 010), t l OI , N IDII, po~ t _ " 1 011), t i ll , NII II: pO~ t _ " 1 01ll. I lll, N1211 : p ort _ " ( Dill. 1111 . N Oli : p ort _ p I N(OI, N U). N (2). N IlI. V I, at"",~uraU: o Fl GU kE .... UI s.ru.-...... VIIOl. o..rnpuo. o f _ I _Lin< .... ullipkKT , , , , , , - -10 - -11 - -12 - -u - -U - -15 - - 16 - - 17 - -18 --19 --20 ~" __ 2 2 - -23 - -u - -25 __ 2 6 ~" --~8 - -2 9 - -30 - -31 --32 __ 16 ~" - -35 - -36 --37 --38 4_7 I H Dl R<p . ... n . .. .,., fm Combimt;o".1 C if<ui.>-VHDL 0 18 1 s c onsist. o f t wo input signals n umbered 0 a nd 1. the index for S is 0 t o 1. The c omponents o f this vector are S ( O) a nd S ( 1) , I consists o f f our input s ignal. n umbered 0 t hrough 3, , 0 t he in dex for I is 0 t o 3. Likewise. in lin"" 24 " nd 25. we ' pecify signals S _n. D. a nd N a , std _Iogic _veclO~ D r epresents the decode out_ p ut s. a nd N r epresents t he f our imernal .igna l ~ b etween t he A ND gates a nd t he O R gate. Beginning at line 27. note how the signal, "'ithin std_logic_vectors a re r eferred t o by giving the signal name a nd the index in parentheses. I t is also possi_ ble to refer t o s ub.'ectors (e,g., N ( 1 t o 2 1, which refers to N 1 1) a nd N 1 2). the e enter t wo , ignal, in til. A lso. if one wishes to h ave the l arger index for a VectOT a pP""r first . VI 'ID L uses a somewhat d ifferent notational . pproach . For cxample. s i '1",,1 N , s td_ log-ic _ vector ( 3 d ownto 0 ) defines t he first bit in signal N a s N 1 3) a nd t he I. .. t . ignal in N a s N 10 ). In Hne s 27 t hrou gh 37. an .ilem;>ti,e m ethod is u sed to specify t he p on m aps for the logic gates. Instead o f c xpHdt ly giving t he compo~cnt i~put a nd o u tput name.;, we assume t hat these nameS ;>T~ in t he p ort m ap in the same o rder a , gi.'en for the c omponent. We can then inlplicitly specify the signals a ttad,ed to t hese names by listing t he s ignals in s ame o rder as the names. For example. in line 29. S --" ( 1 ) a ppears first. and s o is conn""'t~d to ; n 1 . S --" I 0 I a ppea ... second. a nd s o is c onncct"d t o ; . . 2 . Finally. D I 0 ) is c onnected to o ut 1, Otherwise. this V HDL d =ription is similar in s tructure to that for the 2 -t0-4lin e d:oder.except t hat the s chem.tic represente<l i .th" t in ~Igurc 414 on page 158, DATAFl.OW DESCR'PT>ON A dataflow dcscrip ti(>n describe$ a circuit in t erm, o f f unction ratheT than structure a nd is m ade up of con CUfTcnt as<ig.mllcnt s tatements o r t heir e qu i" alent, ConcurTcnt assiYl1" cnt statements a re e xecuted CO~c\lfTcn.ly (i.e . in paml1e1) whenever o ne o f t he values On the right .hand side o f the state_ ment cha nge . . For c~amp l c. wh ene"eT" c hange occurs in a v alue on the rightha ~ <! s ide o f a B oolean e q uation. t he lefthand side i , evaluated. T he use o f d a t.How descriptions m ade up o f Boolean equati oru; i . iUustrated in Examp le 4_17. I ~:XAMPU'; 4-17 I)KM1 . ... V III)L rur M 2-t . .. 4-Linc D croder FiguTe 4 19 . how, a V HDL d escription f or t he 1 to4 line d ecoder circui t from f igure 4-10 on p age 152. T hi' e xamp le " 'iII he u sed t o d cm<mstr.tc a d ataftow dc~cription m ade u p o f Boolea~ c<.juati,m<. T he library. use. a nd e ntity St" t Cments a re i dentica l 10 t hose in Figure 4-27. s o t hey an;' ~ ot r epeated h ere. T he d ata How d escription begins in lioc 9. 'Ille . ignals AO_n a nd A 1Jl a rc defin~d by signal " "ignments t hat a pply t he n ot o perat ion t o t he input signal AO a nd A i, r espective ly. In line I I. AD_n . ! H_n a nd EN a re c ombined with an a nd o perator to form 0 0. D1. D2. a nd DJ a Te si mil ar ly d efined in lines 12 t hrough 14, N otc t hat !hi~ d ata no,,' de'-<ription is m uch simpler t han the . tr uc tura l d escription in Figure 4 -27 , 1 82 C HA I'T EI'. 4 I C O MBI NATIONAL F UNCnONS A NI) C I R CUITS 0 - - 2-to-4 Line Do<:;oder, o..t afl"", VHlL D escription 4 -10 f or l oqic d iagra:,,) H brary, u n , a nd . ....t ity . ".tri. . f r<n L to_ 4_ do<cler. ot' (S- Fi=~ -lJ~Q .., .. .1",1>411 AOJ>, A lJ> ' " td,.. l oqic, , M J> <= n ot M , ; .1--" <= n ot A l, 0 0 <_ M J> . 1>4 111--" a w1 E:J ; D l < _ 110 . 1>4 / U--" a w1 EN; >0 n n n D2 , _ A O_n . "." Al a nd E :J; D3 < 0 AO a nd ; .1 a nd E :J, . nd d.o.t~flow_ l , o , , , , , , , " " H GU R E 4-2'1 D" .1Iow VHDL D =;ri p';oo o f 2-r0-4-Li n< Dtuxlc:r In lhc nexl lwo exomple .. we describe the 4-1O -I-li nc mul1 iplcxer 1 0 i llu.lrale lwo a hernal ive fo rms o f da1a How descriplion : when _e lse and with_sclect. E XAMI'LE 4-18 V IIDL for a 4- to-I-Lille Mu ltipl ucr Usillg When- Else In Figme 4-30_ in . . e ad o f u ,i ng B ool ea n e qualion -like . t,temenl. in the architeclure 1 0 d escribe t he rn u l l iplex~ r, we use a ..." m-ds" sI81~mcn!, Thi s . {. {erne"l i , a --- ~-to-l L ine Nux , C cnditiC<lal D o.tafl"", IIH!X. D e=riptiC<l ( See ~le 4-7 f or f unction t IDle) U ~ in. . ~en-Els e l 1bnry i~, u . . i _ . st d.l oqic_1l64 _all, . nUty . ..,ltiple.>;"c L t"_L. ... h p ort ( S 1 " , t<Lloqic_vec t or(l <l owneo 0 ), I , i n ~t<Lloq icvector(J d owneo 0 ) ; y , o ue ' "<Llogic) ; . nII f tl ltiple""r_4..toJ _"" , a rch it . ct u r. , f~tiC<l_tabl. boo-g- i n < - HO) I ( l) I ( 2) .... . .h . n ~ ~ I (3) . .h . n , , , , 0 of mu l~ ipl . . . r_'_to_l_~ 1_ ' 00 - d . . ' 01' . 1 . . - la- . 1 . . - 11 - . 1 . . ' X' , .~ o f unct io,,---tID l e ; ~' IG UR[ 4 -30 C()I'Id;{ioo,) D,,,,M ow V HDl D<.",,;pc ;oo o f 4 -l<>-1 l ire \ \ul'; plexo , U .i n8 Wt.en _E l. . 7 I H D L R<p",,,,ntatioo f()< C "",b">t;o" . 1 C iui.>-VHDL 0 1 83 representatio n o f t he function table given a , Table 4-7 on page 157 . W hen s lakes on a particular binary value. t hen" p art icul ar i nput I ( i I is aSiiigned t o output Y. W hen th e ,alue on S is 0 0 . t hcn Y is a'-Signed l {O ). Othe,.,.i..,. th e . 1 is invoked SO tnat when th e value on s is 0 1. t hen Y is a "igned I ( 1). a nd so on. In s tandard logic. each o f Ihe bits can take o n 9 d ifferent values. S o Ihe p air o f bits for S can take o n 81 possible values-onl) 4 o f whien have ~en specified s o far. In o rder 1 0 defme Y for the remaining 7 7 values. the final . 1 followed by X (un~nown) is giv e n. T his a ssigns Ihe ,aloe X 1 0 Y if any o f these 7 7 values o :urs on S. This OUlput val ue <x<; urs only in s imulation. however. since Y will always l ake on a () o r 1 value in an actual d rcuit. EXAMPLI:: 4-19 V HDL rOt ~ 4 to_ILine Multipl~xer U.illg With_Select Wit h_,e lect i , a variation on when else as iIIuslraled for the 41O I-li ne multiple>er in Figure 431. The expression. Ih e val ue o f which is 1 0 ~ used for the d edsion. f olloW'lwith and p reeede, I .ct . T he valu"" for t k e >pre" ion thai causes the altemalive assignments then follow wh an with each of the assignment-value pairs separated by c omma . . In t he e >am ple. S is Ihe signal. the value of wh ich d c,er mi n e, the value selected for Y. When S _ " 00 ". 1 I 0 ) i , assigned to Y. W hen S = " Ol " .I (l ) isass ignedlo Y andwon. X isass igntdl(> Y when o ther . w here o ther. r epresents the 77 s tandard logic combinatio ns n ol already specified . _ _ 4 _t o _\ L \"", , """, C ond i t ional Doota fl "", VHDL D eecd p t i on U .i"" w i t h s ..\QCt I S- Tabl ~ 4 - 7 t or f unc t iCXl t able l l ib r . . r y i eee; " . . i _ . nd_ log i c ll M . .. l l ; . ntit y m ultipl e xer_ 4_ to_ l_ws 1 . p or t ( S i n . td_l og i c _ v<octorU 4 ownto 01 , I i n et d_l ogi~_"""t o r(3 4 ownto 0 1, Y . ..., .,.,t . t d_\og l~l ; "'"'lt ip lex.,r_ ~ _ to_ l _'.., ,, ...'" u chit.ct"r. f un~t i CX\_ < abl . ._..... . .i tl> S h c t Y < _ I IOI _ t o.lltip l llX@ r _ 4 _t o _ l...."", h " 00 " . I( l l _ I (21 I (3 1 of . . " 01 " . " 1 0 ". " 11 ". _n _n x _ n , " U U U U U ,". U ott..~.; U . nd " '-""'ti"*'_tllhlQ_ws ; o n G U HE 43 1 Cood i,ion al D".How VHDL , , , , , , , De!.crip<i"" o f 4 l<). 1 U "" M ui1 .ple"" U .i ng Wi,h S<i..." 1 84 0 C HAPTER 4 I C OMBINATIONAL F UNCTIONS A ND C IRCUrrs NON t hai whenelse permils dec is ions on mu lt iple disi in ci signals.. For e xam pie. for Ihe demultiplexer in Figure 4 .\0. t he M t wh en can be conditioned on inpul EN wilh the 'Ubscqucnl when's c ond il ioned o n input S. In c omra't. Il1 c wilh W kel can d epend on only a , ingle Boolean condilion (e.g.. either EN o r s , bUI not holh). Also, for typical symhesis tools. whenelse Iypically results in a more com p lex log ical s tractUTe, since e ach o f Ihe decisions depend, not o n ly o n Ihe condilion currenlly being evalua led. bUi a lro on a ll prior decisions as well. As a consequence. 1 0 siracturc Ihal is sy nthesized takes into aceounl this priority o rder . replacing Ih. 11 4 x 2 A ND OR by a chain of four 2 to 1 multiplexers. In c onlras!' Ihere i, n o direct dependency between Ihe decisions made in wi th select. Wi thwleol produce< a d ecoder and Ihe 4 x 2 A ND OR gal e. We have now covered many o f the V HDL f undamemal, needed for describ ing c ombinalional circuils. We will c ontinue wilh more On V HDL by presenling mean, for de'-Crib ing arithmel ic circuils in Chapter 5 a nd sequenlial circuits in Chapter 6. 4 -8 H DL R EPRESENTATIONS F OR C OMBINATIONAL C IRCUITS-VERILOG Since an H DL is uscd for de'-Cr ibing and designing hardware. it is very impor!ant 10 k eop the underlying hardware in mind as you wr it e ;n Ihe language. This is p ar ti cularly crilicaJ if your language de'-Cr ;plion is t o be synthesized. For exampl e. if you ignore the hardware that " ill be generated. il is vor)' easy t o specify a large compl. . gate structure by using X (mulliply). when a much simpler slructure using o n ly a few g ales;' all I~at is needed. For tbis reason. ini tially. we cmpha<ize describing detailed hard,,'are with Verilog. a nd fi ni shing with m o re abstract. higherlevel descriptions. Sc le<\ed examples in Ihis chapter are useful for inlroducing Verik>g as an altema t;"e means for represcnting delai!ed digital circuits. First. we s how a 51ructural Ve ri log dcscriplion thu\ replaces the schemat;c fn.- the 2 t0--4-line decoder ",ilh enable given in Figure 4 10 00 page 152. This examp le. and one \I..ing the 4to-l hne mu ltiplexer in Figure 4 14 on page 15$, illus{rate many of Ihe fundamental concepts o f VerUng. We then present hi gher leve l fu nctional and b eh$ioral Verilog dcscriplions for these cir cuilS thai funher illustrate Verilog roncept~ t :XAMPLt: 4.2(1 SlruClural Verilo~ for a 2-lo-4-Line [)e<O<Ier T he Verilog descriplion for t he N 04line d ecoder circu it from Figure 410 on page 152 is given in Figure 432. This de'-Cription will be used 10 introduce a number of general Vcr ilog features. as well as 10 i lluslrlle struct ural circuit descriplion. Th e t ext between IWO sla< he, I I and Ihe e nd of a line as shown in lines I and 2 o f Figure 432 is interpreted as a comment. Rlr mulliline commenls, there i$ an a lternalive nOlotion using a I a nd " / ' 2 -to' L In<! D <!Codr w it h E nable, S uuctural V eriloq ( See Fi~u 4 _10 f or l oqic d i ao:;p:_l ' / oo.~c. 0 _ul. / I 2 -to- 4 L ine De<:o<ler wJ.th EnAble , S tructural v erllog O ne . , S; , , , -, " " " " " " " ~ II f fll (~Pigur~ 4 -10 t or 1000ic cl.1~"",) <loecod<>r---"_to_4 _~,,-vlm, .0.0, AI, 00. D l. 0 2. D JI, t RPU t EN. AO. AI ; o utput 00. 01. 02, 0 3, " iU A OJl. l UJi. NO. N l. 1/1, I ll, g oIADJI, ADI. g llAl.JI. A ll, g311.'O. AO--". A lJl). I I 12 II lJ . 11 16 I I IS C 6INl. A D.All. , ,7100. NO. m i. " SIDI. N l. m i. , ,9102 , m. E III. , ,10103 , N l. ENI , " II II II II u l. o , " " II 10 g UNI, AO. A lJ>). g 5 1N2. A OJl. A I). e n. . . . . . . ; 17 lS 19 20 t l GU R E4-J1 Slructu,,1 II<riI<>c De scripoiOll o f 240-4U . .. o..:oo.r To a .-i,{ in discussion o f {he Verilog d escriplion. c ommenls p roviding line n umber. h a" e b een a dded On Ihe right. A. a langu;lge. Verilog has a Synla> t hat descri~$ p recisely t he valid construcls ( hat can ~ used in the language. This e xample will illuslrale m any a spects o f Ihe syntax. In p a rlicular. nOle the uS< o f CQrn m3S 3 nd colon< in the description. C omma. ( .) a re typically us<d 10 s <paral e . Iement< o f a Ii.t a nd 5emicolons ( ;) a re u5ed to t crmina!c Verilog Slatcments. Line J ~gins the declaralion o f a _ uh. which is t he fundamen{ al building hlock o f a Veri!og design. "The r emainder o f (he description defines tbe module. c nding in line 2 {) " ' th . . - u l . Note thai (here is no ; ~fter . ndDodul . lU ll as for a symbol in a schematic. ~ need 10 give {he design a n ame a nd t o define it> inputs a nd OUtputs. Th is is lhe function o f {he ,noJul~ S'a"","'" in line 3 and II\<; inpul a nd QuiP'" <k<:/{mllioru t hat follow. 1 00 , ,<)rds _ u l . i npUt and o utpUt a re ~ (yW()rds in Wrilog. Keyword<. which ,,~ s how in bold t}" pe. ha"e a special meaning and cannot ~ used a . IlllIDCS o f o bjects such a s modules. inputs. outputs, o r wi res. The stat emen l _ u l . d "cod . . r_2_~o_4 j,~_v declares t hat a des ign o r design p an exists " ,th the name d ecoder_2_t.o_4_st_v . Further. Veril,,!! nam es arc case s<nsi.ive (i .e .. names a re d isti nguished by the use o f uppercase o r l owe""l", 1c1Ier1). OECOOER..2_ '_st_v . D ecoder _ 2_ 4_6t _ v, and d ecoder_2_4_s t _V are all distinct na""",ll>S{ as we would d o for a 5)mbol in a schema.ic. we give tbe names o f l be ,Icco;\er inputs a nd o u.puts in t he modu~ stal~ment. Next. an i flp'" <k<:k1r-alwn . . u sed 10 define ,,-t1ich o J tbe " """'" in , he module . ta t.rnen, a re inputs. F or!he e xample design. there 1 86 0 C HAI'fl'R ~ ' (:OMIII NA'IONM.. f UNCT I ONS!.Nl) ( : 11l.<::UITS ate three input oignal!t EN.AII. and Al.1 "" fllCl t hatthe3e arc inpulS is detlOO:d by t he keyword i _ t oSimilarly. a n OIl/pm ,/:Ia",tit., is u>ed t o define (lie ootput~ DO. 0 1. 0 2 . nd 0 3 nre d enoted as ootpulS b)' the h ywonl o utput . lnplIl ! and outpulS as we ll a t O I )I ~r binary signal tYI"'$ in Ver ilog e "n ta ke on o ne o f f our _a lues. T he t\lm nbvi()IJ$ " , 1 11<:$ nrc 0 a nd 1. A dded a N x t o represent unl no "'n >1I l ue~ a nd Z 10 replflent high impedance values. o n Ih e outputs o f 3 .ta t" Iogioe. Vc,ilog also has strength vplues Illal. ",hen c ombined with the four values given. p...,...ide 120 poso.iblc sjgnal ~tales. S trength values a rc u", d ill c llronic " ;=;t modd;n&- OOvo..,ve,.so ...illl>ol be: OO<Isidered , ",re. SllIUClUf\A.L Onc...-noN Next. we "'3nt 10 ~r)" t he lunelloo o f I he dero<!e,. I n thi$ (as<:, we u . .. a s m,ct llrol d~J<:rip,;on Ihal ; s e<ju;valenl ' 0 t he circuit " ,he ma tic given in A gure 4 1 0 on page 152. NOle that the ""he mal ic i . mAde up o f g alcs Vcr ilog p rovides 14 prim iti," g;r t c$ as keywords. O f t hese . we a r C inlereSled in eighl for n ow: b ut . n o t . a nd . O r . n and. n or. I<O r a nd x nor . b ut a nd n ot h . ,c . i ngle input s. 3t1d a ll OIhcr g ale types may ha_e f rom Iwo to a ny i megcr n um,",r o f inputs. b u f i:I_ buffer. " hich has lhe fune.ion : . ... , ,ilh .. os l he i npul a n d , lIS llIe o ut p u t. It is as a n aml'lilioer o f e lectronic " goals Iha, c an h e used 10 p rovide g rca , er fanou. o r lJl1al.." delays. >>r is I he u ciu.ivc. OR g ale a nd . ... o r i h e u ciusi,.., NOR &ltc. ' hc romf'!ernc nt o f Ihe u clus lvcO R. In OUr t umple. we " 'ill ...., iust I...... g ale ' lpes. not a nd a Dd a~ . IH:noo"" , n I",,,,, S a nd I I o f A Sllre 4 32. B e fore specifying Ihe im erconn:tion o f . h c gales. , ,'hich is IIIe sa"'" a . a c ir C1lit neHi . .. we necd to n "mc all o f Ihe IIcts in ' he cireuit. T he inpUIS a nd OUlputs already hove ~"m es. T he i merna l nelS lire Ihe oUlp ut S o f the tWo i nv~ rt e", a nd o f ' he fo ur I dtmc-.; t A ND & "es in Figure 4 10. In line 7. t il eS<' nell ore dl'elared a s wir~J by LI S<: o f t he Keyword . .i r . N an,e. A OJl a nd A 1_" " fc uS<'d for lhe in" er ler o utp uts a nd NO. H I. H2. a nd 3 for the o u tp uts o f ' h e A ND ga' es. In Vcrilog. "i". is , he d efault n e lt ype. Notably. i nput a n d o ut pu t p orts turvc lhe d cfalllll)' PC . .i . ... FOIIQVli", l he decLara,ion o f ' h e m lemal signat., , he d raoll d escnbcd 00<1. lain. tWO in,..,rtcrs and eighl 2 inpul A ND ga' es. A $ Ia,emcni consists o f a galc Iype follQVI'cd b y a Ii" o f in $l a n<;:a o f t ha. ga,e Iype "'jlIIra,ed by r omm .... Each i n".nee c onsis'l o f a g ale name a nd. cncloS<:d in paren'h~'Ses, t he g ate OUlpU' and i nputs Sl!par"'ed by commas, wilh Ihe OUl pUI give n lirst. T he Ii... t " "eme nt begins o n li 1l e H with I he n ot g ate Iype. Fo llowing is i n"erter gO wilh A O- " as t he o utpul a nd .>.O a s Ihe inpu, . T o c omp lete t he I ta tcme nt. g l is si mIl arly ~ribcd. Lin es II t hrougb 19 give the rem3inln~ eight ga'e s a nd l he sigoa", c onnee,e d 10 lh~ir o ul p uts a nd I nl'uli respectively. For n ampk . in line 14. a n i n5 l a~ o f. 2 ;"pu , A ND g ale n amed g 5 i . d efined. I t ILas OUlpUI 11 2 a n d in puts AO_ n a nd A l. 1loe m odu'" is romplc:t~'(j ,,'uh t be kel"'-ord . ' -11 1. . E XAM 1' 1..1: 4-21 SlnK"IlInl V~riloJ r. ....... 1... lLin~ M ultlp"'ur In ~lgure 4 33. the S1roccural dcscnp!ion o f Ihe 4lo--- l line IIIul,iplcxer from A gurc 414 On page 158 ill ustr"l eS Ihe V u ilog c o ncepl o f a \' e<;lor. In li tl e. 4 a nd 5. ; '\llead o f Il'eci f~ing s a nd I as li ~ gle bit wires. Ihcy are . pedfo cd as mu ltiple bit 0 I I 4 -to-l L ine l Iul tip lexer , 5 UUCtural V erllOl/ D esc rip tion I f ( See l'i<,lUre 4 -}4 t or l<l9 ic d iallT_1 . odul. =ultipl~r~4~to~1 _ _ t~vIS. I . Y I: i nput ! l:O ] S : i nput [ 3,01 1 : o utput Y ; w ir. [ 1.01 n (><_S; w ir. [ 0,31 D . N ; -, 187 " " " " " , , , , , " " " " "I "I II "" "" "" "" "" " 2"0 "" f f 10 g nOlnot..jl[OI. 5 [011 . g nl(not..jl[l]. 5 [1J1; - 110[0[01. I IHO!l1. 1 12(0(21. 1 13(0[31 . g Q(N{OI. 1I1 (N{11 . " ",t3!l1, o ot3[0]1. n ot3liJ. 5 10)). 5 (11. o ot31011. S [ 11. S IOIl ; 0 [01 1 [01 I . O U). I II I I ~( N {2J. 0 [21 1 [211. 1 13(N[3I. 0 [31. 1 [311 ; o r \JO(Y. N [OI. N Ul. N 121. I IIlI I; ff ff ff II II 21 22 2] 24 "" "" "" o n G U ME 4- 33 StrOCIu~ V.nlos Dcocriptioo 01 4<o- I L.....\lu ltJpk= wir"" ca [led " eClOrJ. T he bits 01 a veelor a re named by a range o f i nl.gers. T hi. range is given by maximum and minimum values. By specifying th""e t wo values. we s[>Ccify Ihe widlh o f Ihe ve<:tOT a nd lhe namCS o f e ach o f il> bils. Veclo, ran ge. a re i llustrated in lines 4, 5, g a nd 9 o f Fi gure 433, i nput ( 1: 0 1 S indicales Ihal S is a , 'e<:lor with a width o f IWo.. " .. til Ihe mosl signif.cant bil numb<cred 1 a nd l ea.l signifICant bil numbered D. The rornpoocnlS o f S a .e S O] a nd S (O). i npu t ( 3 , 0 1 1 d eclares I a s a 4 bit input , with t he mosl significant bil numbered 3 a nd leasl . ignificant bit n umbe.ed O. w i". [ 0: 3 ] 0 is also a 4b it VedOT r cp"""'nting the f our int ernal wires between t~c leftmost a nd Tigh t mOlll A ND gates. but in lhis cSe.lhe mDSl.ignif,can l bit is ~umbe.ed 0 a nd l he leaSI <ignif,<a~t bit i< numboored 3. Once a ~ector h a. b ee n declared, t~en t he e nlire ' ""lor o r its subcomponents can be referenced. r or u ample. S refers 10 t he t,,-o bilS of S ,and S11 J r ders 10 Ihe mOll! ,ignificant bit o f s . II refers 10 all fou r bits o f II a n d 1 1(1,21 refers 1 0 Ihe middle two bils o f N. T he", type< o f refercnces are u<ed in s[>Ceif)'ing t he o utput a nd inputs in inslance< o f Ihe galC< in linc< 11 Il1 rou gh 25. O therwise. thi, Vcrilog d c=iplion i, similar in SI.uclure 10 Ihal loT l he 210 -4 line d erodc . e xcepl t~al Ihe schematic rCPTesented i . that in Figure 4 14. 1 88 0 C HAI'TE1l4 I C OMBINATIONAL F UNCTIONS A ND C IRClJITS CUAFl.OW OESCRIPTIOtI A d .taHow d escriplion is " form o f Vcri log dcS(:ription Ihat is n ot baSl'd o n s tructur", b ut r ather o n f unction , A dalBHow d escription i . m ade up o f d ataHow stalomenls, For Ihe firs! d ataflow d escription, B oolean eq u._ tions a re used r alher than Ihe equivalent o f a logic schematic. T he B oolean e qua tion. g iven a re u ecute<l i n p arallel whene>'er o ne o f Ihe values o n Ihe righi_hand s ide o f t he Iua1ion changes. ~:XAJI.IPU: 4-12 l)at~Ouw Vcrilo_ rur a 2_lo4 _Linc O odcr I n F igure 4-34, a d ataHow descriplion is given for Ihe 2'1O-4-]inc d eroder, This p ar. t icular d .ta now d escriplion uses Ihe auigJlment Slatement COIlsisling o f Ihe key word . uign followed. in I hi' casco by a B oolean e quation. I n such e qual ions, "" c use Ihe bitwise Bool<:30 o peralors gi>'cn in Table 4- 12. In line 7 o f Figure 4-34, 1 m, - 1.0 a nd - .0.1 a re c ombined wilh an t. operal()l", T his t. c omb inalion is a ssigned 10 Ihe OUlpY! DO , 0 1. 0 2. a nd O l a rc s imila,I)' defined in lines 8 t hrough 10. In t he nexl Ihree examples, we d escribe the 4_10-1lioe multiplexer t o iIIus Irale I hree a ltem al i"e forms o f d ala now description: B oo le.n e quations, binary c omb inations a s COndit ion s. a nd b inary decisions a s w " dilion~ E XAMPLE 4- 23 l )ataH"",' \"cril og f ur . . 4-to- l- Line M ult ipl e, [n Fi gure 435. a , ingle B oolean e qualion for Y d escribe. t he mul, iplexer. T his el ]u alion is in sum-()f-produCIS fo rm " 'ilh ~ for A N)) a nd I for O R. C omponents o f t he s a nd I ' ecloes a .e used as ils " r iables. t: XAMPI .t; 4-ZoI " e ril'-'\C f m + t ... I- Linr Multipln~. V . in. C Odl ], i.... li...' " T he descriplion in Figure 4 36 " ,semble s the f unelion l able g i"en a s Table 4 7 o n p a ge 151 by using a c onditional o per.lo , o n b inary w mbinations If t he logical value " 'ilhin t he parenlheSC'l is Irue, Ihen t h. , alne b efore Ihe : is a"";gned 1 0 t he inde pendenl variable, in Ihis case, y , [f I h. logical " I ne is f a lse, th en t he value a fter Ihe : is assigJled. The l ogkal e q uality Op(:rolor is den<.>led by , S uppose " 'e w n_ sider condition s . .. 2 ' bOO. 2 ' bOO . epresenl.'l a wllSlanl, n.e 2 speci~c . thM Ih~ w nstanl w ntain s 1 "'0 digits. b I hallhe c on stanl is g iven in binary. a nd 0 0 gi>'es t he " "nSlant value. t he expresJiion has value t rue if . 'ector S is C<jualto 0 0; "'1lS.. D T i\ 8 1.f:4-1l 8 i, ,,;,,,, \'erit"ll 0 1"" 010", Openotlon " " - 0< -' O pe . . l or Di,,.i5<; ,,"OT Bi",'ioc: A ND Bi,wise O R Bn . .-ioe XOR [lil,,'ise XNQR ' -8 I H l)l "'~ "Pon ' fu< C"mbin. tion>l ~Ve~ 0 I ! l -tO-4 L iM Deo<x:loor . . I th E nable : D otaU"" V erll(;9 D ese . I ! I See F igure 4 - 10 r or l ogi c d i. ...c . .. ) <I<ocodo>r~_to_"-df...v( rn, AD. A I. DO. 01.~. O J), i nput r n . AD. A I, " "twt DO . D l. 00 . 01 ; _1 . , m , _M - AD ; . .. 1 "" r n' - M " AD ; m ,M ~AO: ru . .. d gn 0 0 m , M M, . ... i gn 0 0 ...."" " _I ~ , , '89 " " " " " " " " " , , , , , ; II 10 1 111 1112 d ul. a F I GURE 4-34 O N_ Vmlo!; D escn"""" ol2-<0-4 Li. . Dorod<r / I 4 -to-l L i n. Mo lti pl exer , ! :ootefl"" V eril cq D esc ri ption / I I SM P iqu n 4 -14 f o r l Ogi c d;<t<;Jr ""' ) _ u h . ... l tipl o>< ec4_wJ _df...vIS . I . Y) , b op" . [1 : 01 S ; b o_ t 13 : 01 I , o u t put Y ; ( _ S II) " ~S IOI " IIO])I I (S ill " - S (O] " I I 2 ]) (- Sil l " S I OI " I ll]) ISll l " S (O] " I I 3 ]): D t lG U R 4 3S 0 . . . _ V.rilo!; o ..criplioft o f . ;..... I _Lin< Mulhpl<-"" U , ;nl I:\00I<.., F _ioI> otherwise, it i , fal..,. If the expression is true. t he" 1 [ 0] i , assigned t o Y. I f the u prew;on is false. then the " exl e .pTessioo oo<>"ining a ? i . e valu.led . a nd 50 on . In Ihi. C3"'. fOJ a c ondilion 10 b e e valuated. all con<lit;ons preceding il must evalua le to fal .." If n one o f t he decisions evaluate t o ITue. then the default value 1 ' bx is a "';gned t o Y. R ecall thaI default value x r eprese nt. unknown. I . :XAM PU: 4-25 Ye .iI ~ rOO". 4 -lo-lLine Mull ip lue. U'iinK Binary 1)O"risi. .... The ~nal form o f " "ta Dow description is . 110"" in Figure 4- 37. 11 i . b ased on condi lional o pe rators used to form a decision tree, " hich cotrt$pOndo 10 a f""IOTed Boolean expression. In l hi. case. if S ( 11 is I . then S 10 J i . e valuated 10 del ermine whether Y i . assigned I 13J o r assigned I ( 2] . I f S f l] i . O. then S f 0 ] is evaluat ed t o d etermine whelhu Y i . assigned I ( 1] o r I ( 0] , For a regU lar < lruclure . uch as a m ultiplex. th i. a pproach. based o n , ,,,o,,,,y (b;nary) decis;on.. g;Ve!i a simple dataflowexpr.,."ion. 1 90 C HAPT ER ~ I C OM UI NATIONAL f UNCTIONS A ND C I RCUI TS 0 I I 4 -to-l L i".. ..... l tiplexer: o ..taflow V eriloq o .,scrip tiOCl / I I S- Tabl" 4 -7 f or f unctioct t ab l el - ... 1 . .,lt ipl exer3__t oJ.....cCv(S, I , Y I: i npu t [ 1:0 ] 5 , i npu t [ 3:0 ] I , o utpu t y : a u i"" ,. :I ; __ h ; I [ 0] ; I [11 " .. 2 ''bOOI , " 'bOll , " 2 ' blOI blll " :, I [ 21 I IJ I , ,.~ o n GURE 4.106 Cond ilioo. ] Dato now Veri log o " ""ril'tioo o f 4 ,<>- 1 \,.;". Mu lt ;p l<:= U.;ng Combin";oo, / I 4 - to - l Liruo MJ.ltipl -..r ; " "tan"" V erilw DelOCrip t i on I I I s... Tabl~ 4-7 for func~ion t able) _ u l . . " "ltlplexecL to__L tLvIS. I . Y ); i nput [ l: OJ S ; i nput IJ:OI I ; OOoItput Y ; . ulgn Y S [ll ? (5101 {S {OI 7 I [l] ? ll~] I IO]I 1 1211 o F IGURE4-l 7 C",\d;t;oo ,,1 D.o",~ow V., ;log o . ..,liplion o f 4",.. 1 Un< Mul l ipbcr U , i n. Binary [)ee",.,.,. This complete< o ur initial inlroduction t o Veri log. We will c ominue with more On Verilog b}' p resem in g m eans for describ in g ar it hmet ic c irtuits in CIlaptcr 5 a nd seq u ~nt i a l circuits in ChapteT 6. 4-9 C HAPTER S UMMARY Th i' chapter bas d ea lt wit h a num ber o f c ombinational CiTcuit lype . . c ,lled func tional blocks, thm arc frequenl ly used t o d esign larger drtu it ~ R ud imentary c ir cuits that implement fu nctions o f a single variable were imToduced. The design o f d ecoders that activate o ne o f a n umber o f o utput lines in response to a n input code was co>'ered . Encoders, lhe inverse o f docoder s. g enerate a c ode associated with t he act ive line from a set o f I ;ne ~ T he design o f m uh i pl~~~r~ wh ich t ake d a ta appli ed at the input selected and prese nt it a t the o ut put. was ill ustrated. T he design o f c ombinational logic c ircuit. using decode rs, multi p l e~e r s. a nd p rogrammab le logic was c overed. In combination with O R ga tes. decoders p rovide a simple min t erm _based approach t o imp l cme ~t ing c o mbinational c ir_ cuits. Procedures were gi,-cn for using an n -to-l -line mulliplexer o r a single i n"en er a nd a n (n - I) -t o-l-Iine mulliplexer t o i mplemem a ny n -in put Boolean function. R O Ms c an be programmed with truth tables. PLAs a nd PALs c an be p rogrammed wit h t heir O,,'n Sp""ialiled p rogramming table s. Mul tiple-level logic d eeomposition and e x lracti on from C ha pt er 2 map combinational equa_ t ions for l ooku p table implementations. The l all two section'! o f the c hapter introduced VH DL and Ve ri log descrip"tions for combinational circuit .. E ach o f the HDI..< was illustTated by descriptions ;o t st ructural. functional. and behavioT level. for various functional block. pre_ al sented e arlier in the <hapte,. R EFERENCES 1. M M<(l. M, M . Digimllk!.ign. 3rd ed. Englewood O i ffs, N J: Prentice H all.2002. l . W ... KERL Y. J, F . Digi,ollk!.ign: Princip/~. a nd Prn<:liu.<. 3rd ed. E nglewood Cli ff. . NJ: Prentice H .II. 2\XX.l. 3. //igh-Speed C MOS w gic DalO BQ{)k. D alla, :Te s IlI m Um enls, 1989. 4. I EEE Siandard VIIOL La"g"ag~ R rfut't!u .110"",,/. ( ANS I/I EEE Sid 10761993: revision o f I EEE Std 1076-1987). Ncw York, The i n"itute o f Electrical and E Itro ni cs E ng in eers, 1<)9.f. 5. S. . ITl!. D . J. H OL Cho'p lk!.ign. M adi""n.AL: D oone Publication" 1996. 6. I'E LLERIS, D, "SO D . T"VLO R. V HOL Made Ea.:;1 U pper Saddle Ri" er, NJ: I'rentice J lal l PTR. 1997. 7 . $ n;F... S , S. ... ND L. U NDIt, V II D L f or D~.igne,". London: Pr~nl"'" Hall E urope.I997. &. Y......... " NClULl. S. V IIDL S wnu'. G"jd~. U p per Saddle Ri,'cT. NJ: P rentice Hall. 1998. 9. I eEE S iam/"rd Descrip"-o" L a"g""ge /J".~d O il Ih e l'eri/"g (T M) lI"rd~'''re O~5crip rio" L tmg"age ( IE EE Std 1364 J995 ). N ew York: The l nslitutc o f Ele.olrical and E1~ctronics Enginee .... 1995. 10. PAI .~m;AR. S. Veri/OK I IDC A G ui,/e 10 [ )igila!l)e.ig" a m/ S y"",u". U pper Saddle River. NJ, SunSoft ! 'reM (A Prentice H all Title). 1996, I I . BIIASKE R. J . A Vui/,,!: I IOL Pri",,,,, Allen to",n. I'A : Star Galaxy I'ress, 1997. 12. T " O . . AS, D . . AND P . MOORBY, T he V~ri/og J/,,,,/w,,," Oeseri",;.", Lallglillge 4 th e d. Boston: K lu"w Academic Publi She rs, 14<}8, 13. CILETTl. M. M<x/elillg. S,.IIIII . ..i.<. ,,,,II Rapid ProlQ/ypin!: M'ilh Ih~ Vail,,!: II O L. U pper Saddle R ivu. NJ: P rentice ~Iall. 1999. ,& P ROBLEMS T he piUS ( +) indicales a lIIore advanced lex! ,,'e bsite. ~ solution is available o n the probl~m and the .~teri,k ( .) indicates. 1 92 0 CI-I"PT(M. 4 I C OMIJIN"TlON" L fUNCTIONS " NIJ C IRCUITS 4-- 1. (a ) D flI .... a n i mplemenlalion diagram for a c onstanl .octor funcllOn F .. (F,. F". F l. F. . FJ- F. . F,. 1',,) .. ( I. O. O. I . O. I . I . 0 ) usin ll hc , round and ['O"'cr ,),mbols from Figure 4.2( b). (b) D raw a n i mplemcn"lion d iagr.m for a rudimentary "cct()1" functiOOl G . . (G 7 G,. <!.!' G" G J G, G " Go) .. (A. A> o. 1. A , A.!. 1) using in pu ts I . O .A.and A , 4 - 2. ( a ) Draw nn impicmcI11ntion dingram l or r!:!,d i!!!cntary veclor funclion P . . (F,. Fo. P,. F. FJ F l. F,. 1-'0) .. (I. O. A. A. A . A . 0, I ) , u , ing tne g round and ['Ower sym boll in Figure 4-2 (b) a nd . hc wire a nd in~~r h:r in Figure 40 2(c) a nd 4-2(d), ( b) DflIW a n impieme nl ation d iavam for r udimenta l! ''eCtor lunclloo' G .. (G 1. Go. G,. G. G J- G,. G ,. G,,) . . (F,. F l. O. 1. F ,. F~ 1. 1). U. inl the g round and p owe r symbol. a nd c omponenlli oe"CC1or F. 4 -.l. ( a) Draw an implement ion d illfllm for the . ..am G . ( G,. G. . G,. G . G, . G1, G ,.G.) .. ( F,,, F,. . F. . F. F,. F,. F,. "'0). ( b ) D raw a o.in'I, lc impkmcntatJOd f or the " ,dim enlary .'ectOr I I . . (111. f l o. 11, . I I. I I,. I ll ' I I, . 110) . . ( I-J. Fl. P, . F. . GJ- G 1, G" G o). 4 -4. A h ome security lyStc m toM a m ., ter .witch t hat i , used 10 e nable a n al~rm. li ghts, . ideo cameras. and a call 10 local police in the c~c"l o ne or m or e o f si x sets o f s ensors deteol$ an in!f u,ion_ The inpUIs, OU lpUI . . and o peral ion o f t he ' ""bl ing logic a rc spe.:ificd as fo ll ows : Input s.: 5 ,. i ~ O. 1. 2. 3. 4 . 5 oignal. f rom.ix..,MOt s et, ( 0 _ ;ntr",1OIl detccted. I _ n o in . ...,ion d etected) M - master . ,,i.ch ( 0. lICC urity . ystcm on. 1 . " ""un ' y ')'Ste m o f0 o ..fpu o.: A a!ann (0 _. lann 0 0 . 1 . a la rm o f0 L lip,hts (0 . lighl' on, 1 . logbt. 0 11) V _ , idtocametM ( 0 ~id eocamera, o ff. 1 - video came n. 0 0 ) C . c aUto police (0 CIU o ff. 1 . c~1I o n) O penlljon: If One Or more o f the selS o f s -enso" d e.""" a n intrusion and Ihe RC Urily ' y,um i . o n,then all OUIPOIS nrc on , O lherwise. all o utput. a re o ff. Find a minimum SII te inpul COunt rea lization o f t h" e nnbhng 1 08k using A ND a nd O R g "te. "tid in~ erICrs. 4 - 5. Design a 4lo-l6-line d ecoder using IWO 3-t0-8-hne decode rs and 16 2_l nput A ND gat.,.. . .... Design a 4 -to-l6-linc decQdcr with e na ble " ""g five 2 ' 10-4-hnc d ttodcrs " 'lh e nabl a uho", 'n in A gure 4 10. 1'JOOIe. ... 0 1 9) 4 -7. ' Design a Slo.32-li ne decoder u si ng four } .to.8-li ne decoders a nd 48 2inp ut A ND gates. 4-tI. A spcci~1 4_1o-().li ne decoder is 10 be designed. T he inpu t codes uscd a re!n) l hrough 101. r'Or a gi"en code a pplied. t M: o utput D,. " 'ith i e qual t o t he decimal e<juivalent o f tit<: code. is I a nd all OIher outputS are O. Desi&" the decoder wi lh a 2-10-4-li ne d eroder. a l-l0--2-line decoder. a nd six 2 input A N D gates. such t ht all d ecoder o utptllS a re used at least once. 4-9. Draw the detail ed logic d iagra m o f a 3-10-8-linc a nd N OT ga tes. I ndude a n e nable input. d~oder usi ng o n ly N OR 4-111. " Design a 4-inpul prio ri ty e ncoder wit h in puts a nd o utpU" a s in Table 45. but with the truth table r epresenting t he ease in " 'hieh input Do has t he h ighest p riority and inpul D, h as tile 10"''''' prio ri ty. 4 - lf . Deri"e t he truth table 0 1 a BC D-to-binary p riority encoder. 4 -12. (M) Design an 8-to- l-line multiplexer using a 3-t0-8-line d ecoder and an 8 " 2 A ND_OR. ( b) Repeal part (a). using two 4 -to-l~ne multiplexe . . a nd One 2-io--l-line multiplexer. 4 - 1.1. Design a 1.... l o-lline multiplexer using a 4_10-1 .... line d ecoder a nd" 16 x 2 A N D-O R. 4 - 14.. D esign a d ual 8-to-l -line decoder using a 3-10-8-line decoder and t wo 8 x 2 A N DO R s. 4-1 ~ Design a d ual 4-10-1-line mu lt iplexer using a 2-10--4-line decoder a nd eight-3state b ulk,,- 4-16. Design a n 8-10--1-line m ultipl",er using lransmission gales. ..... 17_ C onsiruci a 10010-1_line m ultiplexer " ,ith. 3_t0-8 _line d ecoder. a l _t0-2_ line d ecoder. a nd a 10 x 3 A ND-O R. n , e selection codes OXIO Ihrough 1001 must be direcrly a p pli ed t o tile d ecoder inputs without add ed logic. ..... 18. C onstruct a quad 9_ to _I_line multiplexer with four si ngle 8-to-I -li 1l e mu l liple ~ ers a nd o ne q uadruple 2-10-1 -line m ultiple .. er. T he multiplexers should b e inlCraKlnected and inputs labe led SO t hai t he selection codes 0000 t hrough 1000 can be d ir\ly a pplied to the mul1iplexer selection inputs wi thout a dded logic. ..... 19. ' Co n' truct a 15-to-l-line mul1ip l "~er wilh two S-IO-I li ne mu lt iplexers. Intecronn""t the two mu l1 i plex~rs a nd label the inputs such t hai any a dded logic required t o h a"e selec' ion codes 0000 Ihrough 1110 is mi n;mi'.cd . .....2(1. R earra nge the oondensed t ruth l able for t he circuit o f Figure 4_10. a nd " crify thai th e circuil can [uncrian a , a demu lliple~er. 19 4 0 C H AI'n1\. 4 I C OMHINA110NA l F UNCTIO NS A N I) C IRCU I 'TS ;6-2 1_ A combinalional d rcull It d eftned by Ihe loI"""in~ I hree B ooIun fUnc1ions: F,_ X + Z+XYZ f-I " X + Z+XYZ f) - X YZ+X+ Z D esign Ihe d re uil with a d ecoder &nd external O R gate1- 4-n. A c ombinationa l circui t is .! pecified by t he fo llowing three Iloolean functions; F z(A.8.C) - ::: m(I.2.7) F)(A.8.C) . . Tl M(O.1.2. 4) ImplcmCnllhc circuil ",',.h a d ecoder a nd u l e ma l O R gates. ;6-21 Impl eme n! a b inary full a d de r w,lh a d ual 4-lo-l line si nglc in'crler. mulliplc~cr a nd a ;6-24. lmplcmenl t he followin, B oolo.n function with an 8 _ _I line mull iplexer lo a nd a single invener with "ari~ble D as its input : FlA. 8 . C. {)) - l.,,(2. 4.6. 9. 10. I I. 15) 4-25. Implement l he B oolean fU'ldio" F(A. 8 . C. D ) . . ~", ( 1 .3.4. I I. 12. 13. 14. 15) " ".h a 4 -lo-lline n,ull1p1exer a nd e~l e maJ g al .... Connect ' npul S A and 8 10 t he s eledion lines. T he i nput ffilu,remenlS for l be l our d a lB lines . . ill be a o t l C UMI; ....III BII"'l)'-lo-Decun.1 ROM Coo'~'\e' I'rOOIcnu a 19.5 funClion o f the variable. C and D. The val u e, o f these variables are obtained by " 'pressing f as ~ funclion of C and 0 for e ach o f Ihe four c ase, when A 8 ~ 00. 01. 10. a nd I I. These funClions must he implemcnled ,,ith e ,ternal gale!. 4-26. Repeat p roblem J 25 using two 3to-S-hne decode ... with e nab les. a n i n,uter. and 011. gates with . maximum fanin o f 4 . .....27. Gi,cn a 256 x 8 11.0 1.1 chip with an e nab le input. ' how the e xternal conneOion'S necessary 10 c on.truct a IK x 16 n O M with eight chips a n d a d ecoder . .....211. *"Ille 32 x 6 ROM. lOgclhcr ,,ilh the ~ line. a . , hown in Figure J 38. con,crt, a f>.bit binary n umher to ilS c orresponding I,,"o digil flCD number. For , ,,'mple. binary 100001 con'erlS 10 B CD 011 0011 (decimal 33 ). Specify the trulh lable for Ihe ROM . ..... 29. S pedfy the s ile o f a R OM ( n umber of words a nd number of bilS p cr word) lha l will acco mmooale the l rul h lable for Ihe following combinational circ ui l components: (_, A n 8 bil adder ..... u b"oclor wilh Coo and C _. fb i A b inary multiplier thaI multiplie, 1"0 8bit numbers. Ie) A c ode con'erlcr from a J digil B CD number 10 a binary number . .......lO. Tabulale the t rulh I.,ble for . n 8 )( 4 RO M that implemen . . Ihe followi ng fo ur Boolean function s: A (X.Y.Z) . . ~m(0.1.2.6.7) 8 (X. Y. Z) . . ~ m (2.3.4.S.6) C (X. Y .Z) . . : m (2.6) D (X. Y .Z) . . : m O.2.3.5.6.7) 4 -3 1. O btain Ihe P LA p rogra mm ing table for Ihe fo ur Boolean funct ion. (j.{ed in P roblem 4_30. M inimile the n umber o f producI (crm . . lJe sure 10 a ll cmpl 10 s hare pr<:>duCl lenn~ !>elween function~ that . re n ol prime implicants o f individual funclions a nd 10 c on,ider t he use o f c omplemented ( e) OUlpullO. 4 -32. Dcri,c Ihe r LA programming lable for the combinalion.1 circuit Ihat s quare. a 3bit n um!>er. Minimil.c the number o f prodLICI t erms 4 -JJ. Lisl Ihe I ' LA p rogramm in g \able for . BCD- Io-E , cc. .. ) code comerter. 4-.J.l. Repeal Problem ..... 33. u ,ing a PA L device. 4-35. T he following i , the lruth l able o f a Ihr"e-inpUl. four.<JUlput c ombinational circuit. Oblain the PAL programming {able for the circuit. and mark the ruse. 10 b e blown in a PA L diagram 'imilar 10 the one shown in Fi gure 4-26. t 96 0 C HAPTER ~ I C OMBINATIONAL F UNCTIONS A NI) C IRCUI'TS ...-, , """"" , ", """ , ,, , " , ", , , " " """" " "" , ~ All HDL lil<'S for cirUlil! refer red 10 In Ihe remaining problem~ arc ..... ilable in ~ A SCII form for simul~hon and cdlhng on lhe C ompanion Websilc for t he ICKI. A V HDL o r Veril~ oompilerlsimulalor ill neces53J}' for t he ~ms o r p ortions o f problems re<Juesllna: simul~lion, Descriptoons ClIn . . ill b e _ illen. bo ",'c'cr. for many probleTm " ilh. ... , u sln, compilalion or simulatio n_ ....36. Compile and . i mulale I he 2.11)-4. linc dCC<J<k r wilh enable in Fi gure 427 for sequence 0 )). 001. 010, 011 , 100.101.110. I lion E .fl. - '0. AI. Verify Ihal Ihe cirUlil fUnclions as a decoder. You will nee<.! t o compile librury l cdf _ vhdl. ~unc-prill\ll first si nce it is used in the sim ul ation. 4 -37, Rcwrile the VHDL giv en in Figure 4 27 for tne 2t0--4line decoder using ( \) Old_l ogicvector nOlutinn instead o f std.Jogic notation for A a nd D..n a nd ( 2) implicit opecilication o f . he c omponent input and o utput nameS by their order in package f unc-Pri . ... in lib. ary l cdLvh<:ll given in .he Companoon Wcb5 ile Gallery. See Figure 4-28 a nd accomp.;l"ying te~t for Ihe>c " """"pt. . Comp'1e a nd Simula te the resuhing file a . in pfOblem 4364--31l Com[lile and sim ulale lhe 4.t.,..I . ~ne multiplexer In Figure " '28 for the 5e<Juenor: o f an 16 combinations o f 00. 10.01, l ionS and \ 0)), 0100,0010.0001 o n D. You " ,n nc:cd looompole ~bn.!)' l cdLvhdl. f unc-pcl . .. Ii.... since il is u sed in iIw: sim ulahon, Verify that the ci"",il funclions " ". mulllple~er. 4-.l'iI. Fi nd a logic diagr~m thal correspond. to the V H DL OIruc1ural dCliCTip lion in Figure 4- 3\1. Note that complemen ted inputs ace nol av.ilabl e. 4-40. Using Figure 4. 28 a s a framework. write a . Iructural V HDL de$C1"iplion o f the circu it in Figu.e 4. 4(1. Replace x, Y. a nd Z w h X ( 0: 2 ). C on. ult p ackage it f unc ..... r i "'" in libmry l c:df_vh,U for information o n the " .ious gatc component .. Compile ~unc-p ci !fllll nnd )'o u. V HD L. a nd s imulalc your VHD L for all eight possiblo! inpul combinationo 10 verify your d tw iption'. oorre<:lne<s. " -'I. Using Figure 427 . , framework. wri'e a Mruc1ural V HD L dcW'PIlOO o f the cirUlil in f igure 4-41. CoMUit package h mc-prl. . in library I'n>bi.rm. 0 197 __ C ""' i"" <1",,,,1 C irauit 1 , S tructural VIIIL I lHCripUon l ibrary l~. l cd f_v hdl , " i eee . t <LlogicJ16 4.all. l cdevh<ll.!uncJl r imo. d l ; _ eiey ~_ckLl h p ort lx l. ><2. ><3. x ( , 10> a td,Jogic; r , o ue . tA-logic); a nd ~ckt...l; a~chtt.ct"c. s t ructural 1 o f ~c k t-l io ~t /Url p orel inl, il> o t<L!oqic; o utl: w t a td,Jogic), _~ ..."t' C -.-o"_t AND'.l p oct (inl. in<! , I n o td..).og1c, o utl , o ut o td,Joqicl; _ c--=-"e , c _ t CRJ p ort ( .tnl . i n2. I nl , I n . ~ l ogic, o utl , w t a td,Joqicl' _ c -.-o"_"t , d gnal n l, n l. n~. n4 . ... 5 . n 6 ...",',. ' oil' '012, Q~ ; 94 , '015, 96 , .= ~. -" -" = -" ---" " ~, _0 -" _0 ~ o trueturaV; ., ~u n il; ~n t ); ,~ , n 21; -" ~ .... .""", M'...... " M' .... .,. .... ." M' 'm' ... M' .. ., .. "" ...... M'.... "" "" _ 0 l inl _ 0 I i nl _ 0 ( i nl ( inl ~, ,~ n ll; u, ,~ n 51; _ 0 l inl ~" _ 0 ( in l i n3 .~ ... 6 1, ~, .~ ~, f) , o n G U R t: .....19 VHDL f or P robIrm 4--39 l cdf _vhdl for in foTm8t ion o n the v.rious gale cornpon~nt"- Compile func.,.l>rims a n d your V IiDL. an d . imul ale YOUT V HDL for ail 16 p o"ible input comb;nation< to ,,,,rify your dtscTiption' , co'rect n e$~ 4 -42. Find 8 logic diagram represenling minimum two-level logic n ceded 10 implemem Ihe V HDL d ala How description in Figure 4-4 2. N ote thai compl emented inputs a re availabl e. 19 8 0 C HAPTER 4 I C OMBINATIONAL F UNCTIONS A ND C IRCUITS , o n G U RE 440 C irt "il 10.- Pro blem. 4--40. 4--4J. 4 -51. an d 4-53 o n G U ME 441 O rtu it l or P rob lem 4--4J a nd 4-oW - - Corioinational C ircu it 2 , Do. tafl"" VIIl:L ! )'sc rip ti(X'l - 111>.-...,. i~, u i ...... . ~ td_1D(liCn64,a ll; . nOlt)' C <>'t'b_ckc2 h p ort { a , 1> , c . d , a ..n, b ..n. c ..n , d -"" i n ~t<L1D(l ic; t ,,, <>ut . t<L1D(licl, - - "..11. b....n, a re ccnpl......,.,U o f a , b , . . , r ""I*'UV<lly . " ., corrt>_ckt..:;!, ...,. a rchlt.ctur. r l4Uflow_ l o f c omb_ckU ia t < _ b " "" l a o r l a..n""" e ll o r I b....n""" c an<! <t,... . I ; 9 < - b . nIl I e o r (A_n ' """ c....nl o r (c....n """ d _nll' " "" d aun""_l; o H GU RE4-42 V HDL for P robk m 4-42 4 -43. ' Writ e a dataflo,,' V HD L description for the circu it in the Boolean equJtion for the output F Fig~re 4 40 by usi ng 4--44. +Write " dataAow V HDL description f or Ihe priori!)' e ncoder us ing Ihe "when else" dataftow conCept from Figure 4-30 , Compile a nd si rnub !e }'our P mbItm. Cl 199 d CKliplion . .i th a OCI o l.npul "1('1'$ Ihat a re a good lest fIX l he priority fu . .ehon it ~rfIXm . . "-4.5. Wrile a dataHow V HD L de5CTiplion for a n 8-to-l -~ ne m uhipkxer u~ln, l he "wllh ..,Iee!" datano-. roncepl from Figure 431 . C ompile a nd simulale y our d escription wilh a loCI o f inpul ... e clors t hl a re a g ood lesl for Ihe IoI:lcclion 1 """lion it p erlorm . . 4-46. . Compile a nd Slm ulale Ihe 210-4. \i ne d,~er in Figure 4-32 for " 'quell"c I xn 00 1. 010. 0 11 . 100.101 .110. I lion E. AO. A1. Verify Ihat Il ,e circui l funct ions as" d ecoder. 4-47. RC"'ritc t he Verilog de5Criptioli given in Figure 432 for Ihe 210-4.111\(: d ecoder using " eclor n otation for inpul .. OUlput . . a nd wire.. Sec Fi gure .... 33 a nd a ccompan)'ing t nt f or these conceplS. C ompile and SImulate the r .,.ullin, file " "n p roblem 4-46. 4 -I!l C ompile and simulate Ihe 410-1llne m uhiplacr in Fi g",e 4 33 10' lhe OC<I""IICC o f aU 16 rocnbinalloos o f 00. 10. 01. l ions a nd 1000. 0 100, 001 O. 0001 o n D . Verify I halthe circUIt f unclion.as a multiplexer. ~. Fi nd a logic d iaV"m lhal rorr<!5j)Qnds 1 0 Ihe Vcrilog s lr"" lural de!;Cnplion in Fi gu,e 4-43. NOle Ihnl rocnplcmcnled inputs are not available. 4-50. U,ing Figure 4 32 as a framework. " ,nle a , truel ural Verilog descripllOn o f Ihe circu it in Fl g" re 441. C o mpile a nd simulate your Verilog for nil 16 possib le inpul cnmbin"lion. 10 ... c r ify y our d escriplion', e orreclncn 4 -5 1. Using Figure 4 -33" ,,, f r"'nc",or ~ . w ", e a ' truel ll ",1 Verilog descriplion o f I he circ ui t in I ~gure 4 -40. Repll.cc x . Y nd:;; wit h l Dput [ 2: 0 ] X. Con,pilc I I C Od>inoti.,...1 C i.-cuit I , S troctu l V erilw n .cription ~c~~I(xl. x l. x l. , ,4.f), t _ t x l. x l. xl. x 4, oooo"" t f , . o4ul. w i .... n l. n l. n l. " '. 015. 0 6, -, I rDlnl. x l I. g il"'. n31 : - g2lnl. g llnl. ~. ~. n il. vL 11 4 1n5. V . , ,4 ) 1 , g 51n6. d . n 41. ) ; 0< g 6lf. _h ~ . "'. n 61. o n GU KE ' ..0 VenloJ for _ r n ~ 2 00 a C H,..PTER ~ I COMlfIN"'11 0N A~ F UNCfIONS AN ]) CI R CU ITS / I O OoIbiniltlon.t.l Clr<:ul~ 2 , o .un"", Ym-UO\I o -cription _ d . <XlIlI>_clU'... l l a, b , c , d , a..n, b...n, c Ji, " .ft, f . q l, / I a..n, b Ji, , ., . .... Q OIIPl_u 0 1 a , b , r toopte t lvoely, i"pu~ a , b . c . d . a..n, b .Jt, C JI. <lJ>: o utput f . g , ._ul. u d"" ~ ~ b ~ 1& . .. t "" \I ~ b . Ie 11"-,, . I 1"-'" e ll I c..n l I bJl . c . " '-"I: I { C.Jl . <lJ>1 I : [ J n (;U ME 4.-14 V lotl for F'robIcm 4--5 2 en a nd " mulale y our Vcriloa for all cigll! p ossible input combi ..... i<:>m 10 verify )'O\lr de:ocripiion'u'Orrecln"N. 4-S2. Find a Jogic diagram repretCnling minimum 2 lc>d Jogic n ttUed 10 im plement .he " c.ilog dalaftow description in Figure 4..(4 , Note . hat c ompic"",n ' cd inptl ' ~ u c _ nilablt. 4-S3, Wr;te a datafto", Verilog dcscrtplioo for the circuil in l'ig" . e 4-40 by uling Ihe Il ook.n "'IUal ion for Ihe OUlpu t F a n d using Figure 4 -3~ a s a model. 4-54. By us ing lit e co tl dllional d alano'" co nc ep t from Figure 4-36. " 'r'l e a Veri log d a la fi ow descriplio l1 for nl1 lI _lo- t line multiplexer. C o ml ,i l" H"d simulUlc your dt$<.iplion w,t h a sel o f illpUI "cClnTS Inal are a good l eSI for Ill e set""lion (uncliOl' il ]>c . fo .m ~ 4 -55, .. Wrile a dalaf\ow dcscriplioo for ' he p riority e ncode. in f i gure .1-1 2 using lhe binary declo..,n dlllal\ow c anapl f 'om I;;gu.c 4_3 7, Compiic a n d simula.e y our description , .ilh a sel o f i npul v ecton Iha. are a g ood leM for l he priorily (1I"""on;1 performs. A R ITHMETIC F UNCTIONS A ND C IRCUITS "'i. n c hapter, \ he!ocYs c ontllllJO' to b e o n f unctional blocks, specifically, a s pedal c lass o lluncbooa l blocks ll1a t .,orform arill1meli< operations, T he c oncept o f tte rall"" ei reu". maOO u p ol antly. 01 comI)ir;ational c e ll s I s introduced . B locks clesogned a s iterative arrays for p arlorm ing addition, addition a nd s ubtraction, and m ultiplication a re " """'00. T he simplicity 01 t hese a rithmetic C:;fl)lJ it. c omes f rom u s ing CO/TIIlffimem rep,,,,,,,matioos!Qf .... mt>crs and c omple""'tlt -based a r it hmet ic. In addllion, we Introd""" c i rcu~ con t,ac ~on that pe,mits uS to ~g n new lunch"",,1 blocks. ContrOOlioo invot\<es a w lica !io<1 01 va lue lix ing t o t he i nputs o f " xisting b lodts a nd simplification o f t he " ,su it ing circuit s. Thc$.o c ircuits perlo<m ope<ations stJCtl a s Oncreme nti r>g a n um ber, d ec rementing a number, Or m ulti ply ing a n umber b)I a c ons t ant M any o f t hese new I unc b"",, 1b lock. are used to constrL>;! sequentia l I luoc1ional bIocI<s In C hapl'" 7 In the gen(! ric c omp ut er dia!1'8m al t oo b e{jinni"ll o f C hapler 1, adclers. addersubtractors. and multlpljers a M u sed In t he p rocessor. I nc rementors a M " """,me nters a re used wiOOly in o!her components a s well, $ 0 concepts from t his d lapte r ~pp l y aC rOSS m ost o omponanlS o f t he IJOneri<; oomputar. 5-1 I TERATIVE C OMBINATIONAL C IRCUITS In this chapter, the ar it hmetic blocks arc typicall)' desigI1ed t o o rera1e on binary in pu t ,'cctOts a nd produce binary output , 'eelors. Further, t he funct ion implemem cd o ften requires that the same s ublunct;on be applied to each bit positio n. T h us. a f unct io n al block can b e dcsigI1ed for t it e s ublunetion a n d then used repeti _ tively for each bit posi1ioD' o f t he overall arithmetic b locl being designed. T here o 20 1 2 02 0 C HAPT ER S I A RITHM IOfIC f UNCTIONS A ND C lltCU ITS A.,B ,., A, B, jj X. ___ Y. -- Co ll oi "- ' ., " " <:< 11 I , " I C, C~I 1'1 <:<11 0 -- ~ - p Y, L D FrC lJ KE 5- 1 Block DIagram Qf an Iterallve Cil'<u ir w ill Qfte n b<: o ne Qr more connections to pass valu Cl; b et ween "dj~ccnt bit positions. These i nternal v .r iables arc inputs Qr Qut puts QI the subfu nctiQ n s, b ut nQt a c",". . ible outSIde o f the overall arit hm Clic bl ock. The , ubfunction b lock. a re referHd to as cells and the o \'era ll imple me ntation is a n M my o f cell. T he cells in t he array a re often, but nO! a lways. identical , Due to 1he repcti1iw nature o f Ihe circui1 and Ihe asscoe;alion o f a veclor in de x wil h e ach o f t he circu il cells, the o ver_ a ll fu nct iona l bl ock is referred to a n ilemll"'e a"a)" Th" use o f ilef3li"e arrays. a special case of h ierarchical circuits, is useful in h and li ng " ectors o f bi t s, lor e xa m_ ple, a circuit that a d ds IwO 32 bit binary integem A t a minimum. suc h a cireu il has 64 in puls a nd 32 outpUIS, A s a c on sequcn~e. beginn ing with (r u( h (abies and wTit i"S e qualions for Ihe ent ire circuil is o ut o f t he question , Si nce ilemlive circ uits a re based on repetitive cel~ the design p rocess is oo n ,iderab ly . imp li ficd by a basic struc1ure that guide, the design, A b lock dIagram fo r a " iterative cireu it Ihat operales on two II -input vectors and p roo uces an II -oulput veclor is shown in Figure 5 1, In this case. there are t wo lateral connections between each pair of ce ll ' in t he a rm)'. one from IclilO r igh t and Ihe o l her from right t o left. A lso, optional connections. indicated by dashed lines. exist at t he right and left en d> o f 1h" array. A n a rbitrary a rray e mp loys as many lateral c o nn ections as nee de d for a p articular design. Th e d e finition o f the funC 1io ns a,,,,,,iated wil h such oo nnecliom is very importa nt in Ihe design o f t he a rray a nd ils cell , In p artIcular. t he n umber o f connect io ns used and their lu nctions can affect both t h~ cost and speed of a n ilerali"e circuit . In the next section. we will defI ne cells for performing add it ion in in dividual bi1 posilions and then defme a b inal)' a d de r as a n a rray o f c d'" 5 -2 B INARY A DDERS A n arithmet ic circuit i$ a " ' mbinational ci rcuit Ihat p erfo rm. a rithmetic o pera t ion. s uch as a dd ilion, s ubtraction, m ultiplicalion . a nd division with bi nary numb<:rs o r " 'ith d e cim al n umbers in " binary code, W" wi ll d evelop ari1 hmetic circu it' by mea", o f hierarch ical. iteralive design , We begin a t the lowest le\'ol by finding a circuit t hat " "no rm s t he a ddition o f Iwo bi nary di gits. T his , imp l" a dd ilion consist' o f four possible elementary operation s: 0 + 0 - 0. 0 + I - 1. 1 -0- 0 - I. and I + 1 - 10. Th e first 1hrec operations produce a sum r equiri ng only o ne bil to represent ii, bur 5 -l I Bu...ry A M= o 0 2 03 T A8LE 5-1 Truth n bl e o f lI alf Adder Inputs Outputs ,, "" " , " " " " w hen bolh t he a ugend a nd a ddend a re equal t o I. Ihe h inary sum requires t wo bil s. Because o f t his ~asc, Ihe resui! is always r epr esented by t wo bits. the carry a nd t he sum. T he c arry o bla in ed from t be addition of IWO bits is a dded 10 t he nexi h igher o rder p air o f . igniflcant bils. A eombinational eircuitthat p erforms t he addition o f Iwo bils is called a f ull! alMer, O ne that r er fonns t he addilion of Ihree bils (IWO significant bils a nd a previous c arry) is called a 1,,1/ a ,idu. T he nameS o f the cireuits Slem from Ihe fact that Iwo half a dders ean b e e mployed to implement a luU a dder. T he h alf a dder a nd Ihe full a dder a rc basic arithmetic b loch wIth which o ther ar il hmelic circuits a re designed H alf A dder A h alf a dder is an arithmetic circuit t hat gen erate, the Su m o f two binary digils. T he cireuil h as 1 100 inputs a nd t ,,'o outputs. T he i nput variables a re t he augend a nd a ddend b it< 10 b e a dded. a nd t he OUlput v ariabks p rod uc e Ihe sum a nd carry. We assign Ihe s ymbob X a nd Y 10 Ihe IWO inp ut s a nd S (for "su m") a nd C ( for " carry',) t o Ihe o utp UI S. T he t ruth t able for t he h alf a dder is li sted in Table 5- l. The C o utp ut is 1 only when bolh inpuls are I. T he S o ut put r oprosent' t he least significanl bil of the s um , Tho B oolean functivus for Ihe Iwo outputs, easily o btained from t he truth lable. a rc S - XY + X y=x e y C- xy T he h all a dder can b e implemented wilh o ne exclu ,iveOR gale a nd o ne A N D gale. a s s hown in Figure 5-2. o t' IGURE 5-2 Logic Di.gram o f H,I! Add<r 2 04 0 C HAI'T'ER 5 I ARITHM~IC F UNCTIONS A ND C IRC UIT S o T A8L E 32 ,,,,, T rutb T abl e o r 0 0 0 0 0 , 0 0 0 0 0 , 0 0 ~' ull A dder Outputs ,, 0 0 0 0 ,, , , 0 0 0 0 Full Adder A fu ll a dder is a c omb inational c ircuit t hat forms the arithmetic sum o f t hree inpu t bit>. BeIlides t he t hroe input. . it h a, t wo OUlputs Two o f t he in pul ' ariablcs. de ~ oted by X a nd Y r epresent the t wo significanl bils 10 b e a dded. T he t hird input. Z , r epresents Ibe carry f rom Ihe p r evious lower , ign ifica nl position. Two output:s a rc ncee/lsary because Ihe arithmelic sum o f t hree bits r anges in v alue f rom 0 t o 3, a nd binary 2 a nd 3 n eed two d igits for their r epresentation. A ga in. t he Iwo o utputs a re d esignated b y t he symbols S f or " s um" a nd C for " carry": the binary variable S gi"es t he ' -alue o f the b it o f t he s um . a nd t he b inary variable C s i"es t he o u tput carry. T he t ruth lable o f t he fu ll a dder is listed in Table 5 2. T he " alues f or the o utputs a re d eter m ined from the a rithme t ic sum o f t he three i nput bits. ""'hen all the input b its a re O. t he o utputs a re O. The S o utpu t i~ e qual to I w hen only o ne input is e qua l to I Or when all three inputs a,.., e qua l to I . T he C o utp ut h as a carry o f 1 if two o r t hree input. are e qual t o l . The m aps fo r the two o u tpu ts of l he full a dder a re s hown in f igure 5-3. T he simplified s um . of. product f unction, f or t he two output< a re S = X YZ + X YZ + XYZ+XYZ C - X Y + XZ-l-YZ T he t wo leve l i mplementation r equ ire, " "ven A ND g ates a nd I wo O R gates. How e ver . t he m ap f or o utput S i$ r ecog ni zed a s an o dd f unction. a s d iscussed in S e ction 2 7. F u rthermore , the C o ut put function c an be m anip u lated t o i nclude the e xclus i,e OR o f X a nd Y The B oolea n functions f or the fu ll a dder in t enns o f e xclusi,e . O R o perat ions c an then be e xpressed a s S - (X $ Y) $ Z C - XY+Z(X $ y) 5 _1 I B;,,>ry A dd"" n ~ 00 01 II ' 0 2 05 10 ,[EEB5j :, , s _ XYZ: '" XYZ '" XYZ: ... XYZ _ X <!l YE!lZ C - XY+XZ+YZ - XV + l (XY ... XV) - XY+Z(X$Y) o F IGUK 5) M al" for Fu ll A dder T he logic diagram for t h;' mulliple-Icvol implememo t io n is shown in Figure 5 4, I t consists o f l wo half a d ders a nd an O R gate. Binary Ripple Carry Adder A p ara ll el b inary a dder is a digital ci rcu it I hal produces the a rithmetic s um of two binary numbers using only oo m b; nationallogic. The parallel . ddcr uses n fu ll a dders in parallcl. wilh all inpU! bits a pplied simultaneously t o p roduce the sum. T he full addc"l are connected in eascade. wilh the carry o u tput from one full adder c onnected to the c ony input o f the next full "ddeT. Si nce a I C~Try may a ppear ne.r l ~ e least significant bit o f the a ddcr and yet plOpagatc through many lull a dders 10 the most signiticanl bit. j ust a s a wa,...' ripplcs outward from a pebble d ropped in a pond . t he p a ra ll cl a dder is referred to as a ripple carry a dlin. Figure 5-5 .ho"'~ the adder b loch to forn> a 4 bit ripple carry a dder. T he inlerconnection 01 f our lu ll _ augend bits o f A a nd the addend bits o f B a re designated by subscriplS in increasing order from right to left. with subscript 0 d enoting the l e.s t significanl bit. T he c arries are connected in a d oin I hrough Ihe f ul l a dde .... T he inp ut ClIrry!Q t he p arallel a dder is Co. a nd the OUlput carry is C , . A n n-bil ripple carry a dder req ui res n fu ll adder&. with each o utput carry conMctcd to t he inpUl c arry o f the nexl-higher-<>rder , ------ lf O<l<lc r --------! l, I , , , , , , , , ./ , , , --------------H, llodd<, ~---------- o I ----------- F IGURE S'" Logic Diagrom of Full Adder '> c 2 06 0 C HAPTER S I A RJT HMET IC F UNCTIONS AN I) C IRCU ITS " " " c, " ! o C, " C, ! II " ! F IGURF.55 4Bil RiPl>Ie C"rry A<kIc:r fUll ad,icr. For u amplc. o onsider Ihe I wo binary numbers A _ l Oll and I I _ 0 011. TIleir . um. S _ 1110. is fOf'med ",ilh a 4bil ripple carry a dder as foU"",-.: Inpul carry Augend A A d dend B S umS OUlpul carry 01 \ 0 I0I I Q .Qli 1I I0 00 I I T he inpUI carry in Ihc l ea't Sign itie"nl position is O. Each full a dder receives the corresponding bi t. o f A a nd B a nd the input carry a od g enerate. II><: sum bit fo r S a nd tit<: o utput carry. The output c arty in e ach position is t he input c arry o f the ncxt . highcr-order f/O'Iition. as indi<: at ed by the blue lines. The 4 b it a dder is a Iypical example o f a digit al c omponen1that can be u""d as a building block . II can be u sed in ma ny applicalions inv ol"ing arilhmet ic o pera . tions. O bserve Ihal t he design of Ihi. circuit by Ihe usual mClhod would require a I tuth table wi,h 511 e ntrics,.i nc e tllerc arC ninc inpulS to the circuil. By c~scading t he four instanCCll o f the known fuU adders, it is possible t o o btain a simple a nd ' traightforward i mplementalion without dir~tI)' w iving this latg<:r p roblem. T his i . a n example o f Ihe power of ileralive c ircuit' a nd circuil reuse in design. C arry L ookahead A dder Th e ripple carry a dder. a lt ho ugh simple in concepL h as a l ong circuit d elay d ue t o t he many gates in t he c arty p ath from the least Significant b it t o t he m oo( sign ifi cant bit. For " typ;';al <k!;ign. t he longcs( delay p ath through an , ,hi t ripple carry a dder is 2n ... 2 gate dela}... ThU s. fOf a l6-bil ripple carT}' a dder. t he d elay i . J 4 gate dda~ l l1is delay lends 10 b e o ne o f the largest in typical oomputer ~ign. Accordingly. we find an a lternative dcsign. Ihe c~rry look~he~d ~i1der. ' \l facti, . l 'hi~ a dder i . a p ractical ~ign wi(h reduced delay a t t he p ri'" o f m ore c omplex S_2 I D in.ry Adde" 0 2 07 h ardwue. The c any l ookahead deSIgn can !:>c o hlained by a I ransfonnalion o f Ihe ripple carry design in which Ihe carry logic over fixed groups o f b its o f the adder is r educed 10 t wo-level logic. The l ransformalion is shown for a 4-bil adder g roup in Figure 56. First. w'e construcr a new logic hierarchy. separaling Ihe parts o f lhe full adde ... nol involving l he carry p ropagation p ath from Ihose containing l he palh, We call t he first p art o f each fu ll a dder a p ania/full a dd" ( PFA). This s eparalion is shown in Fig ure 56(a). which presenlS a d iagram o f a PFA and a diagram of four PFAs connecled 10 l he carry palh. We have r emo,'ed t he O R gate and one of lhe A ND gates from each of the full a dders 10 form Ihe ripple carr)' palh, T here a re IWO OUlpUIS. 1', a nd G from each PFA 10 the ripple carry p ath and o ne inpul C;. the c arry input. from the c arry p a th to each P FA. The funcrion p. = A, m Bi is called the propagale funclion. Wh ene"er P, ;8 equal to I. an inoom ing carry is p ropagated t hrough the bit position from C i 10 C ;+\. For P i C<]ua l t o O. c arry propagalion lhrough the bit posilion is b loeted . The function G, _ A, B, a nd is called l he genetdle function. W hene,'er G, is equal t o I. t he carry out put from lhe posilion is 1. regordless o f l he value of p .. so a carry has !:>cen g enerated in lhe position. W hen G, is O. a carry is not generated. so t hat C i + I i , 0 if Ihe carry p rop. gal"d Ihrou gh Ihe position from C ,is aloo O. T he g enerale and propagate funclions c orre'pond exactly 10 the hall a dder and are essential in conlrolling t he values in the ripple c arry p a t h. Also. a< in t he full adder. the PFA g enerates t he , um f unction by the exclusive -OR o f l he incoming c arry C, a nd the propagate function P,. T he carry p ath remaining in l he 4-bit ripple c arry adder h as a IOtal o f eighl gates in cascade. $ 0 l he circuil bas a dela)' o f eight gate delays. Since only A ND and O R g ates a re involved in the c arry path. ideally. lhe dela)' for each o f Ib e four carry signals p roduced. C, Ihrough C ,. would be just lwo g ale delays. T he basic carry lookahead circu it is simply a circu il in whi ch fu nClio ns C, Ihro ugh C , h ave a d e lay o f o n ly lWO g ale delays. The implementation of C, is more complicaled in o rder 10 a ll ow the 4-bil carl}' l oobhcad a dder to be e xtended to mu ltiples o f 4 bits. <uch as 16 bits. T he 4-bit carry lookahead Cifcu it is shown in Figure 5-6(b). 11 is designed 10 direclly replacc Ihe ripple carry path in Figure 5-6(a), Since lhe logic g enerating C, i . alrcady t wo-lcvel. i( r emain, unc~a n gcd. The logic for C" how_ e "er. h s four I e"ds So 10 fi nd the carry l ookahead logic for we musl r educe the logic 10 t wo levels. T he e quation for C, is found from Fig ure 5-6(a). and the distributi,c law is applied to obtain C,. This e quation is i mplemen ted by the logic with o utpul C , in Figure 5-6(b). We oblain the two-Icvel logic for CJ by finding ilS eq uation from Ihe carry palh in Figure 5.6{a) a nd a pplying the d istributive law, 2 08 0 C H APT ER ~ I A RITHM ETIC FUNCT IONS A ND C IR CUITS , , ---------------- ---, , , ~' ~ ~' , /'---r{ ---- < ~, '" i, --1 , , , , , , , , ~' " ~, J, r, C , G, P, C, G, r ----- G, ------ - ---- --- -- ---- - ------- - , , ", , -, , ,,' L--1 l C. P, - ~ t 'Ol____ _ L--' l 1" '" <!:o___ ~, --' - -., , , , '~ .--------------- - -- --- - - --------- ~ --~-- - -------- ------------------~ " ,.) I"' , I"' -, Ie - I" I"' Ie, ~ -<. I~ ~ Lot "~ ""f<,J r O I," Q r< 1-( Lof , I o ,., FIG URE 5-6 De,..,Iopm< nl o f . c a r l)' Lookohead Add<:r ~2 I Binary A dden a 2 09 o utput C , in Figure 5-6{b) implements this function. could impl.m~ nt C . using the . . me method . But " "me o f the ga tes ,,'ould ha" e' fan _in o f five, ,,'hich may incrn~ the <iclay. Also. we arc interested in reUI_ ing t his 5.lme ci", "it fOf higher num~red bits (e.g..4 through 7 .8 t hroop I I. and 12 t hrough IS o f a 160bi t lKIder). F or this a<kkr. in ~itions 4 . s ..nd 12 We ,"'OU1d like t he c arry t o be prod~ as fa!it as J105Sible ",ithout using excessi,. . fan, in. Accordingly. .... wan t t o repeat t he . .. me carry Iookaltead trick fOf 4-bil groups that " '0 u~d t o hand le the 4 bi . .. '1 . . will allo,.. U5 t o re...., the carry Iookalw::ad 11 circuit fOf eac h gruup uf 4 bilS. and also t o u sc: the Ioa me <;",uil for fou r4bi l i"0ups a . if they "' orC individual bits. So insl cad of ge nera ling C,. w produce ge nerale 'e a nd p ropagate functiuns tnat apply to 4-bit groups instead o f a , ;ng lo bit to act a , Ihe inpuls ( ur the i "0up c arry lookahead circuit. Tu p ropagale a carry fr um ~ to C " . . n~ed t o h ave all four o f the propagale functioo! " '1u.ll o I. &i"inllhe grollp p mpogatr function The two.l~vel l ogic "'i t ~ w~ P O- 1 - 1', 1'11',1'0 To r epresent lhe " ,nera tioo o f a c arry in po$ilionl O. L 2. and 3. a nd i tl prop.ap_ tion to C . we need t o consider the 8"neralloll o f. carry in each o f lhe position .. as represcnted by Go Ihrough GJ a nd the propallation 01 e ach o f the"" four ge ner, a ted carri . .. to ~ition 4. This give, the 8"'''1' g CliU(l'. function TI>e group propaaale a nd g roup g enente e qualioo. arc impiemcnled by the logic in Ihe 1....- .. part 01 Fogure 5-6(b). ] ( t here arc only 4 I); t. in the adder. lhen the . logic circulI u sed (or C , can be used 10 " ,nenle C . from theoc lwo OUl pU L$. In a longer adder. a a rry I ootahead circu't identical t o that in lbe figure . u :ept for labeling. is pl~d a t the scoond le>'el lO cenerate C. C and Ct>. This com:epl c an be extended " 'llh more carry Iookahcad circuiu in the 5CCOIld level and ,..ilh olle carry look8head circu,t in Ihe t hird le vel tu ge n cr~lc carries for positions 16.32. ,,"d 4~ in a 64 -bi t adde r. A ", um;" 3 Il ,at an . xclu,h'e O R r on tribul es 2 gate delays, the lon ge5l J e lay in t he 4_1>il e atry look" h e.d a dder i, 6 gale tklays, compared with 10 gate delays in the ripple c arry a dlk r. The improvemenl is very modest and p erhaps not worth all t h~ e xtra logic. ll ul ~ppll' i n g Ihe carry Iookah.nd c i",uil t o a 160bil a dder using h e copies in t" -o l e'cI. o f loohhead reduces the delay from 34 10 jus. \0 l ite dela~'S, , mprm'ng the p erformantt o f the a dder b y. f ,.lor o f d ose to Ihree. ln _ 64-bit a dder . ,,ith the usc: o f 21 c arry l oohhead circui ts in three Ie"els o f I ootahead. the d~lay . . reduced frOll1 130 g ale d elays t o 14 l ate d day:<. &I,ing more than 3 f~or o f 8 in improved perlonnanc~. In g enual. for the implementation we h n'. s hown. Ihe dd3)' o f a c~rry loo k"hcad . dde r des ign ed for Ihe o o t performance is 4 L + 2 g ate dela)'!, wh e re I . i . the nu mber of looka l1 ead Ic,'~I, in the d i:$ ign. 2 10 I 5 -3 0 C HAI'TEIl ~ I M \JTHMETIC F UNCTIONS A ND C IRCUITS B INARY S UBTRACTION In C hapter 1. we briefly examined the subtraction o f u n,igncd bin ary numbers. Although beginning tc~!S <xwer only <igned n umber addition and .ubtraClion. to the c omplete exclusion o f the unsigned a il crnative. un,igned n umber arithmet ic pla)'ll an im p<Jrta nt role in c omputation and comput er h ardware d""ign. I t i~ u"cd in ftoating. p<Jint units, in signed-magnitude addition and s ubtraction algorithms, a nd in e xtending t he prc"(; ision o f fixed'p<J;nt numbers. For t hese reasons, we wi ll t real u" signed n umber addition and s ubtraction h er e. Y.'e a lSO. however. choose to t reat it first s o t hat we can d early j ustify. in terms o f hardware cost. t hat which o th erwi,e appears b ilarrc a nd o flen is accepted on fa ith. "amely. the usc o f complement r epresentations in arithmetic. In Section 13 . u btmction is performed by c omparing thc subtrahend with the mi nuend arid s ubtracting t he . maller from the l arger. T he uSC o f a m ethod containing this comparison operation resuits in inefficient and cosily circuitry. As an ahemali,'C. we ean simply subtract the subtrahend from the minuend. Using the same numbers as in" . ubtract;on e~ aTrlplc from Seclion 1-3. we have B orrow. into: Mim,cnd S ubtrahend: Difference: C orrect Differe nce: I 1 HK) 10011 - 11110 10101 -01011 If no borrow occurs into the most significant position, then we know t hat the su[') t rahend i. " 01 larger than the minuend and Ihat Ihe resuh is positive and correct. I f a b orrow d oe. o ccur into Ihe most ~ign;ficant position. as in dicated in blue. then we knuw that the w btrahend i . l arger than the minuend . The r e.u lt m u.t t hen b e negal ive. and SO we n eed t o c orreet i t. magn it ude. Wc can d o this by e xami ni ng the r es"lt o f the caiculation ",hen a b orrow occurs : M -N+2 " Note that the . dded 2" r epresents the VAlue o f t he b orrow into the most sign ific.~nt position. Instead o f this result. the desired magnitude i . N - M. 11>is can be oblained by subtracting the pre<:eding formola from 2": 2 '-(M-N +2") - N - M In the previous u '",pl . I (((((J - 10101 ~ 01011. whicl1 is the corrcct mag ni tude. In g ene,al. the .ubtraction of 1wo n.digi1 n umb<:r<. M - N, in base I can b e d one as follo,",'S: I . S ubtract t he subtrahend N from t he m inuend M. 2. If nO end b orro,,' occur<. t hen , II ;., N. a nd the r e.u lt is n onnegati,. and correct. 5 -J I B;n..-y Snbt"cbon 0 2 11 J, If a n e nd borrow OCCUN, then N > M, and the difference, M - N -1- 2", is s ubuacled from 2", and a minus sign is a ppended to the resuh. I Subtraction o f a binary number from 2" to ob l ~in ~n , ,digit result is called taking the 2~ complement o f l he " umber. So in step 3. we a re ta~;ng the 2 's c omplement of lhe difference M - N -1- 2". Use o f Ihe 2 's complemem in . ubtr.ction i . ill u. trated by the fo ll owing example. XAMPL 5_1 Ulldgne<l Binary SubtrlKl ioll by 2 '. Perform l he binary subtr"~tion Cornplcrn~nt Subtract 01100100 - 10010 11 0. We h ave Borrows into; Minuend: S ubtrahend: Initial R esu lt 10011110 01100100 - 10010110 11001110 H Ie e nd b orrow o f 1 imp li es correction: ,. - I"itial Result Final Resuh ,== - 11 001110 - 00 11 0010 T o p erform s ub traction using this m ethod requiTe$ a $ubtr~Nor for t he in i_ tial subtraction. In a ddition, wh en n~ceS$ary. ~ither l he s ubl raclor m ust be used " s econd lime 10 p erform the correction, or s cpMate 2 's c omplemelller circuit musl b e p rovided. So, lhus fM, w e r~quire a s ub!raclor, a n a dder, and possibly a 2 '. c omp lemenler to perform b ot h odditi"n a nd ,ubITRclion. ' nle block diagram for a 4_bil a dder_<ubtractor using these f un ctional b locks is shown in Figure 57 . T he input s a rc a pplied to bolh Ihe a dder a nd the subtractor, s o b oth operations arl: p erformed in p aralle l. I f a n e nd b onow v alue o f I o "curs ill t he s ubtraclion, then the s elective 2's e omp lemen ler r ecei"es a value o f I o n il S C omplement ill put. This circui t then t akes the 2's C(lmptemenl o f l he ou tput o f I he s ubtractor. If t he e nd borr<>w has . alue o f 0, the selective 2 's complemenleT p asse. the o ut p ut o f the s ubtractor t hro ugh u nchanged. If s ubtraction is I he o peration, l he" a 1 is ~pplicd 10 S o f the m ultiplexer t hal selocts lhe OUlput o f t he complementer. If a ddition i . the o peration. Ihen a 0 is a pplied t o S. t hereby s elecling lhe oU lput o f l he a dder. As we will see. this circ uit is more complex Ihan necessary. T o reduce the a mount o f hardware, we would like 10 sharc logic belween the a dder and the subtmclor. Thi, can also be done using l he notion o f Ihe complemen t. So before considering the o ombi"ed adder--subtractor further, we will t ake a mOTe caT ul look d at complement .. 212 0 C HAPTER ~ I A R.I TI-L\ \f1C FUNcnONS A Ni> C IIlC UI TS B um), , ubl,.,;(", S , I,;", 2', oomp!<me n,er o f lGURES _7 Block D iagram of Binary Adder-Subl'OCIor Complements T her e are t wo Iypes of complement s for each ba", -r sJlS tem: t he radix complemem , whi ch we s aw earlier f or ba$e 2, and the <limin;,ite,/ radix complement, ' ne first is r eferred t o as th e r~ c omplemem a nd t he " ,"o nd a , t he ( r - l )'s c omplement . When the value o f Ihe base T is substiluled in Ihe n amtS,lhe Iwo types are referred to a , t he 2 's and l 's c o mplements for binary n umbers and the lO's a nd 9 's complements f or decimal numbers. , especti ,eiy. Sin ce Our int erest for the present is in binary numbers and opcrations. we will d eal w ith o nly l 's a nd 2's compleme nt s. G iven a n umber N in bina ry h a"ing " digi t s. the I :, e<>mplement o f N is defined as (2" - l) - N. 2" ;s r ep resented b y a bi nary n umber that c onsists o f. I followed by I t O's . 2" - 1 is a b inary n umber r eprese nt ed by n 1' s- For e xa m pIe, i f" - 4, we have 2" - (IOClOOJz a nd 2" - I - ( 1111),. Thus, the l 's c omplem em o f a b inary Dumber is o bta in ed b y s ubtracting e ach digit from 1. Whon s ub tracting binary d ig it. from L ""'~ c an have e ither I - 0 - 1 o r 1 - I - O. which c . use, Ihe o rig inal bi t to c hange f rom 0 t o 1 o r from I t o 0, rospoctivd )', Th erefo re, the 1 ', c o mple ment o f a b inary num ~r i . f ormed by c hanging all l 's to O's a nd all 0 ', t o l il-t h .t is, applyi ng th e N OT o r c omp lement o peralion t o each of th e b it'. Following are two n umerical e xa mp les : The 1', complement o f 101 1001 i. 01 0011 O. T he ls complement o f 0001111 is IIICXXXl. I n ' im il ar fashion. the 9s complemcnt o f a decima l n umber. the 7". c ompl. men! o f a n oct"1 n umber. and the IS, c omplen' ent o f a h exadecimal number are obtain~d by . ubtrActing c ach digit from 9. 1. a nd F (decimal 15). r c.pecti_dy. Given an n-digit number N in binary. the 1 "s c omplemml o f N i , defined as 2" - N for N ___ O a nd 0 for N - O. T hc reason f onhe special case o f N - 0 i . that the ","ult must ha'e n bito. a nd subtraction 0 10 from 2" gives an (n ... I)-bil rcsull. 100. .. 0 . This s pecial . -e is ""hi.,oed b y usinll only a n n bil . ubtractor o r o tllc",,_ d ropping lhe I in the n lra posiloo". Comparing " ;th tbe I , c omplement. " ' e n ote lhat the 2s complemenl can b e o blained b y ~'nK I t o lbe I , complemelli i~ 2" - N _ 1[(2" - I) - NJ + 11 For example. lhe 2, c omplemenl of binary 101100 i . 010011 + I _ 010100 and is o btained by a dding I to the I , oomp lemeOl value. Again. for N _ O. l h. r e.u lt of lh is a Jd ition is O. achieved by ignoring the carry o ut of the mosl significanl position of the addilion . lllese COnC<.'plS h old for o ther ba se. a , " ell. As ...c ",ill se c l aler. they are ,"~ry u seful in simp li fying 2, c ompl.men l a nd . ub traclion Imrd"are. Alw. t hc 2'1 complement can be formed by lea'ing s l i least oignificanl 0 , and the f im I unchanged and t hen replacing Is " '''h 0 , and 00 , ,ith l 's in all o th er hIgher signitkanl bit .. Th . ... , he 2 , complement o f 1101100 is 0010100 Bnd is oblained by leaving the Iwo Iow..,..d ~r Os and the first I u nchanted a nd then replacing I 's wnh 0 , a nd 0, with \ ', In the ot ~ ef fo ur most ,igniticanl b;lS, In o the r ba~ the first non7.cro digit is ; ubtractcd from the base ' . and l he remaining digil5 t o the l eli arC r~placed wilh r - 1 minU$ t heir values. I i i , nl,o worl h II I"ntioning , hat the cOlllplement o f lhc complemenl restorc.s t he n umber to Its o riginal value. To ..., thi s. nOle t hai the 2 , oomplemcnt o f N i$ 2" - N. a nd Ih e coonplcmeol o f the compl~mCn1 i . 2" - (2" - N) - N. giving b ad , he o nginal n umber. S ubtracllo n wit h C o mplemen t. E arhu. we u prcssed' d c,ire 10 simpl ify h3Tdware by s hanng a ddcr a nd s ubtrac tor logic. Armed "'i th complemenls. we a re p repared t o defin~ I binary subtrac tion p rocedure lhal use, a ddition a nd Ih e co.responding oomplement logic. The s ub traclion o f two Itdigit unsigncd nU "1bers. M - N. in b inary Ca n be d one a , follow s: I . A dd the 2 '. o ompkmenl o f Ihe . ubt rahcnd N 10 I he mlnL>end M . This per f orms'" + (2" - N) - M - N+ 2". 2". O i"",.d ,IN: e nd carry.lea>inK r e.ull M - N. 3. If , II < N. the Sum dooca n o' produce an end carry .ince it i. Iual t o 2 "(N - M ). the 2, complement of N - M. Perform a c orrection. taking the 2, complemem o f l ht sum a nd p ladng a minus ,ign in front to obtain lhe r e.u lt - (N- M). l . I f,., l ! N. the . um p rod""'" a n c nd carry, 2 14 0 C HAPTER ~ J A RITHMET IC F UNCTIONS A ND C IRCUITS T he examples t hat follow f urther illustrate the foregoing procedure. Note that, although we are dealing with unsigned numbers. t here is no way t o get an unsigned result for the case in s tep 3. When working with p aper and penc il , we rec, ogoire, by t he absence o f Ihe e nd carry, that the answer must be changed t o a negative number, I f the minus sign for the result is t o b e p resef"ed, it muSt b e , tored separalely from lhe c orrected ~,b it result. E XAMPLE S-Z Un,igne<i Binary Sublract;un by 2 ', Cumplem~d l Addition G i,'en t he two binary numbers X - 1010100 and Y = 1 0000]], perform the sub traclion X - Y and Y - X usiog 2 \ comp lement operation . . We have X= 1010100 2 'scomplementofY - 0 11 1101 Sum - l001(X)O I Discard e ndcarry2' - - ICXXXXXXl A IlS"''': X - Y = 001(((11 Y- 100001 1 2 'sco mplement o f X = 0101100 Sum _ 110 1111 There i . no e nd carry, A"$w<r: Y - X - -(2'. c omplement 011101 111 ) - - 001(((11, SUbtraction o f unsigned n umbers a l.o can be done by means o f the I 's com plemem , Remember that the I ', c omplemem is one I ",s than lhe 2 ', complement. Because o f this. Ihe result o f adding the minuend t o the complement of the s ubtra hend produce, a , um that i, one less than the correct difference when a n end carry occur>. D iscarding Ihe e nd carf)' and adding o ne t o the , um ;s referred to as a n e nd ara""d carry. E XAMPLE S -l Unsigned Binary S uhtnctlon by 1 ', Comp l ~ment A dditio" Repeat Example 52 us ing I ', complement operations. Here, we have X - Y - 1010100 - 10000 11 X- 1010100 l 'scomple mentofY - -t01i1i00 Sum _ 10010000 E nd.around carry An.,...'er: X - Y _ L -+ 1 001(((11 y - X - IOCOOII - 1010]00 y~ ]OCOOl1 l'srompl~m~ntofX " +0101011 Sum - 1101110 There is nO end carry. A ".....~r: \' - X . . - (l's compl~ment o f ]101110) . . -0010001. Nore that the n~ga'ive reo ul! is obtained by taking the I ', this i , t he rype o f compleme nt being used. romplem~nt o f tbe s um ,~inee 5-4 B I NARY A OOER-5UBTRACTORS Using either t he 2 \ o r l 's tOmplem~nr. we have eli minated rh e subtraction o pe ra_ rion and need onl y the a ppropria re r ompleme nter a nd a n a dder. When performing a , ubtraction we complement the s uba ahend N. and when performing an addition we d o nOl c omplement N. These o pe", . ions ( an b e a cromplished l>JI using a ,(:lective complementer and a dder interconnecred t o form a n adder-subm.crOT. We have US! 2's r ompkmcnt. sinee it is most prevalenl in m odun system$. T he 2 ', c omplement ca n b e obrained by raking rhe I ', c omplement a nd adding I ro rhe least ~;8nificant bi!. 'l'he l 's r om pl cmenr can b e impl~mented ea~;ly wirh ;nverl er circuits., and we c a n a dd 1 t o Ihe sum l>JI making l he inpur c arry o f rile f"'rallel a dder e qual ro 1. ThUs. by us ing I ', complement and a n unused adder inpur, the 2 ', c o mpleme nr is o btained inexpensi"ely. In 2 ', comp lem ~nt s ubl "'ct ion, as the cor rection st ep a fter a d ding. " " complement rhe result a nd a ppend a minus sign if a n ~nd c arry does nOl o crur. The correction o pera rion is p erfo...n ed by using eitller the adder~ublraC!or a s erond l ime " 'irh M - 0 Or a select"" complemen rer as in Fi gure 57. T he circuit for s ubluc ting A - 8 c o nsists o f a paran ~1 a dder ru; , hm.n in Figure 5-5. with i nverleB p laced berween each B l erminal a nd rh e r orrespond in g full adder i npul. The i npul oarl)' Co must be e qual 10 1.1'11e o peration thar i, p e r f ormed b ecome. A plus lhe I ', r ompl emenr o f B p lus ] . This ;s e q ual 10 A p lus t he 2 ', c omplement o f B. For unsigned n umber . . ir gives A - B if A ;O: B o r rhe 2 ', c omp le me nl of 0 - A if A < 8. T he addi ri on a n d subuacti on o perarion, can b e c ombined i nto One d rrui t wilh o ne r ommon bina!)' add~r. This is done by including a n exclu,ive -O R gate with e ach full a dder. A 4 bil addcr~ubl r" ct o< circui' ;s sho,,'" in Figure 5-8. Input S o onlrol, lhe operalion. Wh en S 0 rhe circuir is an adder. and ....!ten S K I lhe circuir becomes a , ubrract or. Each exclu. i,'e- OH gale rcce i,'es input S and one o f lh ~ inpulS o f B. OJ. Wilen S . . O .... e have B , III O. ff the full a ddeB receive l he v alue . u f B. a nd lh e i npul c any is O. ' he c irruit p erform. A p lu. 8. When S . . 1. we h a"e 8 , III 1 ~ Ii; and Co " l . In t hi, case. the circuit performs the o pe rar;un A plus the 2 ', c omplement o f B. 2 16 0 C HAI'TER ~ I A R.lnIMETIC r UNcnoNs A ND C IRCUIT'S . " . " r-1 " c, " I C, " I o F IG U RE S-!! " C, I " " f-. " I Ao.I<Ier--SubU.ctor a,,,,,il Signed Binary Numbers In Ihe p reviou, section. we dealt " ith the addition a nd s ub traction o f unsigned numbe .... We will now e~lend Ihis approach 10 sig<led numbc .... indooing a f urther use o f c omplemenl' Ihat elimin ale, the correction step. Pos'li,., integers and the number z ero can b e r epre",med as un~ign"d numbe .... T o r epr=nt negati~e intege .... we need a n otalion for negalive ~alues. [ n ordinary ar;lhmetic. a negali,'c n umber is indicated by a m inu' sign and a positive number by a pl u. , ign. Because o f h ardware limitations. computers mu", r epresenl e verything " ilh 1'5 and 0 ' . . including the Sign o f a number. As a cons.cquence. il is customary t o r eprcscnlthe , ign " ith a bil placed in the moo;t significanl position o f a n " -bil number. The con"enTion i , t o make Ihe , ig<l b il 0 for posili"e n umbers a nd I for negalive numbe .... 11 i , imponanT 10 realize that botb 'igned and unsigned binary munbers c on,i'l o f a Siring o f bil~ when represenled in a computer. The user deterrninL'S whelher lhe number i , ' igned o r unsigned. I f tbe bina ry n umber is signed. lben the leftmost bi t represcnl~ t he sip> a nd the rest o f l be bils r erre"'nl Ihe number. If t he b inary nUm _ ber i . assumed t o b e wISigned. then the leltmoo;t bil is tbe tnO:'ll ,ignificant bit of tl>e number. For exa mple. tbe m ing o f b it, 01001 can b e considered a , 9 (unsigned binary) or + 9 (signed b;nary). b<:cause tbe lefttnO:'lt bil is O. Similarly_ Ihe Siring o f hi. . tlOO! r epresent. tbe binary equivalent o f 25 when c on,idered ' " a ll unsigned numbcr o r - 9 wbcn considered as a s ig""d number. The laner is because the I in Ihe leftmost position designales a minus s ign and the remaining four b it' represent binary 9. Usually. there is no confu.>ion in identif)ing the bit~ b caluse Ihe t)"" o f number representation is k no.... n in advance. TIle , epresentation o f . igned numbers just diseuw:d is referred t " a~ Ihe Jjg"~'I."'~g,,;tud~ S)'SICm . [n this S)'S km.the nUm_ ber consists o f a n,agnilude a nd a ,ymbol ( + o r - ) o r a bil (O o r 1) indicating tbe .ign. Thi. is the representation o f signed numbel'S u s! in ordinary arithmetic. In i mplemcn'ing signed-magnitude ad(lil;on and SUbm,clion for ,.-bit num b<:n. the si ngle sign bit in the leftmost position a nd the n - 1 magnitude bits a re processed separalOly. T he magnitude bits a re processed as unsigned binary numbers. ThU s. s ublraclion involves Ihe correction . tcp. To avoid Ihis ,Icp, we use a d ifferent system for r epresenting negati,'e numb<:n. r derred to a s a signed_com_ p lemem s)'Stcm , In Ih is s y,'em, a n egali"e n umber is r epresented by its comple ment. While the s igned-magnitude s~tem negates a n umber by changing i l' sign, ' he signed-<:<.>mplemc nt '~tem n egates a n umber by taking its complement, Since positi,'e numbers always s tan wilh 0 ( representing a p lu, . ign) in the leftmost pollition, Iheir c omplements will alwa)'. SIan with a I . indicaling a negative numbe r. The signcd-<Xl mp1cmenl '~tem can use eit her the l 's o r the 2-, OOmplcment, but the l aller is the most common , A . an example, consider the nnmb<:r 9, repre _ sented in b in a'}' with eiglll bit . . + 9 is represenlcd ",;th a sign b it o f 0 in the leftmost position, followed by the binary equivalent o f 9, t o give 00:01001. Note that all eiglll bilS musl h a"e a value. and t hcrefore.O. a re i nsened helween Ihe sign bit a nd the firs t I . A lthough there is only one way t o r epresent + 9 . we ha"e three diffcn:nt ways to r cpresent - 9 u.ing eighC bits: [n signed-magnilude r epre..,mation: In signed_l's complement representation, [n signed-2's complement representation: 1(0) 1001 111101\0 111\0111 In signed magnin""', - 9 is obcained from + 9 by changing the sign bit in l he left"","t position from 0 to L In signed l's complement, - 9 is o btai""d by complementing all the bits of + 9, including the sign bi1.ll>c signed 2's complement representa ti on of - 9 is o btai""d b)' tsking the 2's complement o f the positive number, including the 0 sign bit. Table 53 li,ts all possible 4 _bit.ign~d binary numbers in the Ihree representations. T he equivalent decimal number is al50 shown. Note that the polliti'' '' numbers in all three represenlations are identical and have 0 in Ihe leftmos' position_ T he signed 2's complement system has only o ne r epresentation for O. which is always positive , 11,e o ther two s ystem. h ave" positive 0 and a negative 0, which is someth in g n ol e ncoumcrcd in o rdinary arithmel;';' NOle ' hal all neS"!i"e numbers have a 1 in the leftmost bit position; this is the way we d i" inguish t hem from positive num hers. With 4 bits- we can represent 16 binary numbers. In t he signed-magnitude and the I 's c omplemem r eprese"'ations. t here a re . . ven pollil;ve numbers a nd seven negati,. numbers, a nd two signed lOro. In the 2 's complement representation, t here a re seven pollili,. numbers. Onc zero. and e ight ncgalivc n u mbers. T he signed-magnitude s~'ste m is used ;n o rd in ary ar it hmetic, but is " "'kward when employed in c omputer arithmetic d ue t o the !.Cpa mt. handling o f the sign and the correction " ep required for subtraction. Ther efore.lhe . igned c omplement is normally used . The l 's c omplement imposes difficulties b ttause o f its two r epre _ sentations o f 0 and is seldom used for arilhmetic o peration .. It i . useful as a logical operation, since the change from I to 0 o r 0 t o I i . equivalent ! o a logical comple_ ment o perat ion . '11,. following discussion o f s igned binary a rithmetic deals exclu_ .i,ely wilh the signed2's complemenl rcpresentahon o f negalive numbers because il pre "sil. in actual use. By using r. c omplementation and the e nd -around carry, 2 18 0 C HAPTER 5 I A RI1 1t ME11C f UNCTIONS AN t) C t RC UtTS o TA BLE Sol ,.... --, ._.-.., S iJMd Kin...,. /'I' ~m ' ~ " S Igned "I ~-, H ., ., H ..., 0111 0110 0 101 011l 01 10 010 1 0<00 0 0" 0<00 0<00 OOW . ." 00" 00" . ." . ." 0000 0000 -0 -,,, -,, -, - -. -. 1111 1110 1101 oow 1111 1110 1101 0 1t ] Ot 10 0101 OOW , '" ".., ",n 10tO "00 tOll " 00 lOt I " 00 1011 1010 1010 '00' "'" 1101 1110 1111 ,.., ' 00' (h e ~a rne p rocedores as t hOle for s igned 2 ', oomplemen! l ' s oomplemen(. e ll t1 be applied to s igned S igned B inary A ddition a nd S ubtraction Th e a dd ition o f t wo numbe!'$, M + N, in the s;gnr:d-mag,n itudc .~tem follOW! th e r uks o f ordinary a rithmet ic: If the , ians a rc the " ''''''. we a dd th e t ....o m aanitudcs and give the sum the , ian o f M. If the lians a rc differe nt . ...- e s ubln.a the rnaan;' tude o f ,'II from the nUianitudc o f M . T he a~nce o r p ",scnce o f a n e nd o o.row t hen d ctenn i""" the sign o f the " ,suh. b ased 0 0 the .ign o f M. a nd de termines ,,'hethe r o r not 2'1 c omplemen t wrrc<1ioo is p trformed. For example. since the "'8M a n: different . (0 0011(01 ) + ( I 01(0101 ) cau . ... 0100101 to be ..,bt.loCted from 001 1001. Th e resu lt il ] ] ] 0100, I nd an cnd b orrow o f I occurs. U t e e nd bo ... row indicates that the maanitude o f M is I malie. than the magnitude o f N. So the s ign o f the result i. " """"lte lhat o f M and is lherefore a minu~ Th e e nd borrow in dicates that the ma gn it ude o f the .~uh, 1110100, must b e c orrected by ta king it5 2 ', c omplement. Combining Ihe sig n and the c o rrected magnilude of the rcs ult, we o btain 1 ( 0:11 100. In COn(.ru;1 to thi s signed-magnitude case, the rule for adding numbers I n lhe signedcomplement ' ys tem does not require c ompariwn Or subtraction. bU l only addi tion_ The p.-.x:edure is !.i mple a nd can be staled as folio"", for b inary numbers: 1 bc addition o f Iwo !.ign.ed binary numbers " ,Ih negalive n~mbe" " , pre!;Cnted in signed2', romplc:nlenl tonn is o btained frolD the addition o f lhe two num ben. includin&lberr !.ian bits. A o:arry Q U( o f ( be sign bit " ", ilioo is disearded. Numerical e ump lr$ o f s igned binary addition a re giv.. n in E~ample 5-4. N ote t hat negati,-e numbers will a lready be in 2's complement form and that the sum o btained a fter the addition, if negative, is lell in t hat same form. I E XAMPLE 5 4 Signed Binary Addition Us ing 2 ', C omplement + 6 OOOXII IO '" '" txXXlllOl (XXl10011 - 6 11111010 + n txXXlllOl + ; OOOXIIII -" B -, WJOOIIO 11110011 I llllOOI - 6 11111010 - B l lllOOIl -" 11101101 In each o f tbe foUT cases. the o peMion p erformed is addition. in duding the sign bit .. A ny c arry o ut o f the sign bit position is discarded. a nd n egati,-e results are aU10malically in 2 ', c omplemenl form, The complemcDI rorm ror repre . . nting negalive n umbers is unfamiliar 10 p eople accustomed to the s igned-magn;' ,, "e system. T" d etem,ine t he value o f a negali'-e nUmbeT in . igned'2's c omplement, II OS n e$$ary to c onvert the n umber to a positive n umber in o rder t o p ut it in a more familiar form. For e umple. the signed binary number 11111001 IS negative because the leftmost bi t i$ L Its 2-s c omplement is OOOXIIII , which is the binary e quiv.leDl o f + 7, We t herefore recog nize the original n umber t o be equal t o - 7. T he SubITaClion o f two s igned binary numbers when negative numbers aTe in 2's complement form is very simple and can be stated as follows: Take the 2's c omplemenl o f the subtrahend (including tlie sign bit) and add it t o the minucnd (including the sign bit). A c arry QUI o f the sign bit p osil",n i . d iscarded, This procedure stcms from the fact that a subtraction o pera tion can b e c hanged t o an addition <>pe ration i f the sign Qf the subtrahend is changed, That i .. ( = A ) - (+8) _ ( = A ) + (-8) ( =A) - ( - 8) ~ ( =A) .,. ( + 8) But changing a positive number to a negat ive number is c. .ily de",e by taking its 2's complement , The reverse is als<:> ITll(:, because the complement o f a "'-'gati,'e n umber that is already in complement form prod uces lbe corresponding positive numbe . Numerical example!; aTC shown in E umple ~,S. I E XAMPLE 5--5 Signed Bina.,. Su bfTll ction Using Z'. C omplement -6 11111010 - (-13) - 11 110011 +7 T he e nd c arry is dis<:ar d e<l . +6 OOOXIIIO OOOXIllO + txXXllIOI - (-13) 000XI1I1 + 19 - 11110011 + txXXlllOl 11111010 (XXllOOII 2 20 0 C I IAI'TER ~ I A R mlM Ef IC F Ur-;crIONS A Nl> C III.CUITS I t i~ worth noting that binary number.; in the ,ignc"<l-complemenl s)"tem a re a dded and subtracte<! by the s ame basic addition and <ubtr""tton rule~ as a re unsigned number.;. T herefore. c omputer.; n eed only o ne c ommon hardware circuit to b a ndle both types o f a ritb metic. 11,,, u.",r o r prog.rammcr o m,t i nterpret the results o f such addition o r . ubtraetion differently. depending on whether it is assun.ed that the number.; a re signed Or unsigned . Thus.. the s ame adder~ ubtractor d""igned for unsis,ned number.; can be used for sigJ1e<! number.;. If the 'igne<! number.; a re in 2 's complement r epresentation. then the circuit in Figure 5-8 can be used with n o correction s tep required. For 1' . c omplement. t he input from S t o Coof the a dder m ust be rcpl"ced by an inp ut from C . t o Cn. O ver1low T o obtain a c orrect a n.wer when adding a nd subtracting. we must e nsure that t he result has a sufficient n umber o f b it, t o a ccommodate Ihe sum, If we s tan with two n -bit n umbers.. and the sum occupies n + I bi ts.. we say t hat an O>'erjfow occur.;. This i . Irue for binary Or decimal number.;. w hcther sigJ1ed o r unsigned. When o ne per forms addition with paper a nd penciL a n o,'e.How is n ot a prohlem. since we a re nO! limited by the , ,;dth o f Ihe page. We j ust add another 0 t o a posilive n umber and another I to a negative number. in the most signiflCSnt posilion. 10 e xtend tbem t on + I bils and then perfOllll the addition. O " crflow is a p roblem in c omplllers because the number o f b iu Ibat hold a num""'r is fixed. and . result that e ' ''''''ds t he n umber o f bits cannot be accom modat e<!. For this reason, computer.; d etect and can signal t h. o ccurrence o f an o"nftow, The overflow condition rna)' be handled . ulomatically by i nterrupting the u ecution o f the p rogram and ta~ing special action. A n aUemati,'c is t o m onitor for o"erflow conditio"" using software. The detection o f a n " ,'erHow a fter the addition of two binary n umbers depends o n w hether Ihe numbers arc considered t o be signed or unsigned, When two unsigned number.; a re added. an overflow is d e tect ed from the e nd c arry o ut of Ibe mOSI SigJ1iticant position. In unsigned s ubtraction . the magnitude of t he result is a lways equal t o o r smaller t han the larger o f t he original number.;. ma~ing o ,'er How imposoible. In the case o f Signed 2 ', c omplement number.;. the most Significant bit always represents the sign. When Iwo signed n umbers a .e a dded. the sign bit i~ t reated a , a part o f the number. and a n end carry o f 1 does not neces.arily indicate an overflow. With signed numbers.. a n overHow c annot occur for a n add it ion if o ne n um ber is positive a nd the o ther is neg.tive:; Adding a positive n umber t o a n eg.tive number prodUCe!! a r.,,;ult whase magnitude is C 1jualtoor s maller than the larger o f Ihe original n umbe"- An overflow may occur i f the two number.; added a re b o lh positi,'" o r both negati,'e. T o see how this can h appen . c onsider the foIlO"'ing 2's complemCnt u ample: Two sig ned number.;. + 70 and + 80. a rc s torcd in two S-bit registers. T he range o f binary numbers.. expressed in decimal. t hat e ""h register can accommodate is from + 127 t o - 128. Sir.ce the Sum o f the two stored numbers is + ISO. it u ceeds the capacity of a n 8 -bit r egi",r. This is also true for - 70 and - 80. These two additions. t ogether with the two most significant c .rry bit ,'.Iues.. arc as follows: - - -->-~ I Bm.ry Molbpbo<>bon Corrie:!: 0 1 + 70 . 0 1000110 .~ ,~ 0 22 1 Conies: 1 0 - m l OlllOI O -~ , -,~ Note (hal the Sb;, resu lt that should ha,'e been posit;". bas a negal;'-. sign bit a nd t hat t he 8 -bil Wiult thaI s l>o uld h a,". b ttn n egative ha~ a p ositive sign bit. If. how_ e ver .the c arry o ut u fthe . ign bit p osition is t ak en as t he sign bit o f t he result. t hen t he 9 -bi[ anS" -er s o o btained will b e COrrect. B m s in t here is nO p osition in lhe T~SUIt f ur I he 9t h b it, .... e say tliat an " ,-ernow has ooxurTcd A n overflow condition can b e d etected by obsen--ing the c any i nto the sign b it position a nd Ihe carry o ut o f Ihe s ign bit posilioo. I f these 1"'0 carrie. are not equal. a n overflow has o ccurred. T h is is indicated i n the 2", c omplement e xample just r om p itIed. " ,her. Ihe tWO c ames a re explicitly shown. I f t he t wo c arri es a re a pplied t o a n e x cl usive_ OR gate. a n " ,'.rfto .... is d etected w hen the o utput o f t he g ate is e qual 10 I. Fo. this m etbod 10 w ork c o . ",clly for 2 's c omplemcnl, it is n ece..ary e itber t o a pply t he I 's complement o f t he s ubtrahend t o t be a dder a nd add I o r t o ltave o ,'erIl ow d et eclion ( Kl Ihe circuit thaI f orms the 2 ' s c omplement, n.e l aller condition i. d uc t o o verflow , ,-hen c om plementing Ibe nlaximum n.gat;~e n umbe., Simple logic thaI p .ovides O\'erflo,, ( ktectinn is s hown in Figure 5, 9. If I he number!l ore c on.i(kr cd u nsigned, t hen I he C o utpul b eing e qua T t o I d etects 0 ca rr~ ( an o ,'crHow) f or a n add ition and i ndicates t hat n o c orrect ion , tep i , " 'qui r cd f or a s ubtraction . C b eing e qual t o 0 d e tect, n o c arry ( no o"er1!ow) f or an a dditi"" a nd indicat es I hat a c or rection s tep is r equ ired for a s ubtraction. If the n um bers a re consi de red s igned, t hen I he Qutp"t V ts used t o d etect a n overflow, I f V 3 0 a fl er a s igned a ddilion O J s ubtraction. it i ndicales I hal n o o ve rnow h as o ccurred a nd I he ..." ult is c or rect. If V ' " I, t hen t he resull o f t he o per ation c ontoins" + I bits, bUI o nly t he rightmOSI n o f t hose b il. fit in t he n -bil r esult, s<> a n o verflow has o ccurred , T he ( n + I) lh bit is I he actual sign_ b ut it c annot o ccupy t he Sign bit p osil ion in the res ult. 5- 5 B I NA R Y M ULT I PLICAT I ON M ultiplication o f b inary n umbers ; s p erformed in t he s ame way a s w;th d ecimal n "mben T he m u ltiplicand is m ultiplied by e ac h bit o f t he m ultiplier. s taning f t,,", t he least significant bit. Each such m ult iplication f orm. a p ani a l prodllCl , Successive p artial p rodu cl< a re s hifled o ne bit 10 t he le ft. T he final prodUCI is o blain ed f rom t he s um o f t he p artia l producl'- ' "<- ' _ __l--~"i I" o FI GU R E 5-9 o . e .IIo ,,' D e, eCl ioo Logic; for A dditioo a nd S ub"""l ioo 2 22 0 C H APT Ul S f A RITHMETIC F UNC'nONS A NI) C l It.CU ITS T o s u h ow a binary muhiplier c an ~ i mplement"" with a combinational cir cuit, OOf\sider t he muhiplicatioo of t,,-o 2bit num~~ a s sho ,",," in Figure ~ 10. l l>e multipli.:and bi~ a re 8 , a nd 8 0 I he multipl;"'r bilS a reA, a nd AQ,and t he p roduct i , C ,C, C ,Co. The f j"" p anial p roduct is formed by m Ultiplying B , Bo by A o_ The multi. plicalion o f Iwo b its Such," Ao a nd ilo produ""s a I i f b oth bilS a re I: othcrwi!oe it p roduces a 0. This is identical to an A N D o peration. Therefore. Ihe panial p roduct can ~ i mplemenled ,,;th A ND g;>tes as s hown in t he diagram_ T he s econd partial p roduct is f ormed hy muhiplying B, Bo hy A land is shifted one position t o t he left , T h e Iwo partial productS a re a dded wilh two half-adder ( HA) circuits. Usually t here a re m ore bilS in t he partial products. a nd it will b e necessa ry t o u .., full a dders t o p roduce t he ,urn o f t he pa n ia! products. N ote thai the least significant bit o f Ih e p roduct d oes not have to go t hrough a n a dder. since it i . formed by t he o utp ut o f the firs t A ND gate. A c ombinational circuit binary m uhiplier with more bits c an ~ c onstructed in a s imilar fashion . A bit o f the multiplier is A NDed with each bit of the multipli c and in as many levels as t here a re bits in Ih e n, ultiplier_ T he b inary o utput in e ach le>-el o f A ND gates i . a dd"" in parallel with t he partial product of tlte p revious Ie>'el 10 form a n ew p anial p roduct. The laSlle>-cI prod,..:es I he p roduc t. For J mul tiplier b it. a nd K m ultiplicand bit s. we n eed J x K A N D gates a ~ d (J - 1) K-bit a dder> 1 0 p roduc e a p roducl o f J + K bit s. A , a n e xample o f a c o mb in alional eir c uit b inary multiplier. c o nside r a circuit thaI m ultipli es a b inary n umber o f f our bilS by a n umber o f l hree bit . . Let t he multiplicand b e r epre . . n led by B 1Bl B,Bo a n d the multiplier by A l A,A o_ Since K ... "' a nd J ... 3 . we need 12 A ND gal e, a n d l wo 4-bit add ers t o p roduce a p roduct o f 7 bit s. Th e logic diagram o f Ihis ki nd o f " " " ," , A,B , <, <, '" ~ " ~ " '\., <, <. " " '" I o F IGURE S- tO A 2Bi, b y2 . Bi, Binary M~I'iplicr '" ~ . < """ , "" y 'r y ,-- j ,~. ' bo,. dOe, C. ~ ". ""'I"" """ y yy ,-- ~ '" 0''1'''' ' Au", '" 4-1'; , a dde. ". . c, a c, c, c, ~' r GURE A ~ Bit 5- 11 by ] 8i, B inary M uh'plie. m ultiplier C; ' CU;\ is s hown in F igure 5-11. N ote thaI t hc C arry O utput b it e nters t he a dder al the nc~t level d own in t he multiplie . 5 -6 O THER A RITHMETIC F uNCTIONS T here are o ther a rit hmetic fUnc'lioo, beyond + , - . a nd ><. t hl a re quite imporlant. A mong I h"'" f unction. a re i ncrementing. d ecremen ting, multiplication a nd d ivi.ion by a constant. greater Iha" comparison. and less Ihan comparison. Each o f these f unctions c an b e i mplemented f or multiple-bit o perands b y using a n i terati.'e a rray o f l obi, cells. InStead o f u sing I hese basic appmach(:$. a r ombinalion o f r udimentary func t ion. " '. .. a new technique called c ontraction is u sed. C omrac.ion begins with a circuil such a s" b inary a dder. " carry- lookahcad a dder. o r a b inary multiplier. T his a pproach ~implifies dC"Sign by o onwrting e xisting cireuit< i nto u""ful. leSS"""",,"pli . c ated circuits insle!id o f (Ie>igning (he l aller circuits direcUy. 2 24 0 C HArTa<.; I A RITHMETIC F UNcnONS A N!) C IItC UITS Contraction Value-fixing. transferring. and i m-ening o n inpull; can ~ combincd with f unction blocks as d one in O tapler 4 10 implemenl new funclions. We can implement new funClion, by U'ling similar technique-s on a given circuit o r on it, equalio,,, and then comraCIing it for a 'pecific applicalionlo a simpler c ircuit We will call the procedure COII"tK:,i<)n. 'The gool o f contmClion is to accompli,h Ihe design o f a log>: circu it o r functional block by U'ling , e.ults from past designs. I t can be applied by Ihe designer in designing a target circuil o r can be applied by logic s)'nthesis tools to simplify an inilial circuit with '-alue-fixing. transferring. and in''e'ting on its inputs in o rder t o obtain a target circuit. In both cases. comraclion can alSO be . pplied ' 0 circuil Oul puts that a re unused, t o simplify a s ou"", circuit t o a target circu it First, ",'e illustrate contraction by u,ing [loole.n equations. t:XAl\1 I' LE s -6 C ontnodion o f Full Adder E'I IIY l ion. The circuil A ddl t o ~ designed i . to form Ihe Sli m S, a nd carry C;'J for the si ngle bit a ddition A ,,, I -t C,. T h is . ddilion is " special case with B, _ I o f thc addition performed by a full a dder. A ; + / J, + C" ThUs. c q uati'm, for Ihe new circuit can b e o blained by laking thc full a dder equations.. S,. A ,Eil lliEilC, C A , II, -tA,C, + /J,C, ,.,. s elling B,. 1, and simplifying the resuhs. to obl.in Si - A,1!lI I!lCi Ci.,~ A i - A ,eC, I + A,C, +IC,", A, -tC, Suppose Ih"1 this A ddl circuit is used in place o f e ach o f Ihe four full a dders in a 4bil rirple carry a dder. Instead o f S ~ A + / I + Co. the computation being performed is S ,. A + 1 111-tCo- fn 2 '. complemcnt. this computation i sS ., A-1 + 4 I f Cu= O. t his implements Ihe dec","'e'" o peration S ., A - t, using consider.>bly less logic than that used for a 4-bil addilion o r sublrOClion. C ontraction can ~ applied t o equalions. as d one here. o r <lireelly on circuil diagrams ",ill! r udimentary funClion. applied t o function block inputs. In o rder 10 ,uCttssfull}' appl}' c ontr.ction. the desired function must b e a ble t o be o btai ned from the initial circuit by application o f r udimentary f unction, on its inputs. Next we consider contraclion b ased On unused OI1tpUts. Placing an unknown ,alue. X. on the o utput of a circuit mean, that output will not b e use<l. Th Us. the o utput gate and any other g ale, Ihat dri~c only that oUl pUI gate can ~ removed. T he rules for oontmcting e quation, wilh X' s On o ne Or mOTe o utp uts a re as follows: I. D dcte all e q uations wilh X ', 00 Ihe circuit o ut PUIs.. 2. [ f an intermediate variable d oes n ot a ppear in a n y rcmaining equntion. d elcte it . equation. " J . If a n i nput v ariable d oes nOi a ppear in a ny r emaining e q uation, d elete it. 4 . II. cpea\ 2 a nd 3 until no n ew d eletions a rc possible. The r uk s for ooolr.Cling a logic diagram wilh X's o n o ne o r mOte o utputs a rc a s follows: I. B eginning a1 (he o utputs, delete all g ales Wilh X', o n t heir outpUls alld place X'. on t heir input wires. 2. I f all input wires driven by a g ale a re la~led wilh X'$, d elete Ihe g ate a nd p lace X 's 011 i ts inpm>. J. If 311 input wires d riven by an e~lernal i nput a re la\>tled Wilh X'So d elete ( he i npu t. 4. Repeal 2 a nd 3 until n o new d de!;on! a re possible In Ihe next subsectio n, c ontraction o f " logic d iagram i . illustrated for the incre ment o peration Incrementing I" CT<n'~"'ing m Un S a dding a fi . ed v alue 10 an arithmetic v ariable. most o ften a fixed .-alue o f I . A n " bit incremmle, t hat p erforms the o penhon A I c an b e o btained by using a binary a dder t hat p erform, t he o peration A -+ B with /J " 0 ... 01 . Th e use o f n ~ 3 is large e nough 10 d elennine t he i ncremcmer logi<:: t o CQrlSlTUct t he circuit needed f or an n_bit i ncremente r. Figure ~.12(.) Sho",., a 3 bit a dder with the i nputs f iud to r epresent t he c ompurationA I a nd with Ihe OU l put from I he m ost significant c arry b it C, lhed at , 'alue X. O perand B .. 001 a nd t he i ncoming c arry C .", O. 5 0 t hat A + 001 -+ 0 i . c omputed.Ahema tively. B " ( l(X) and i ncoming carry CO" I coUld h c b een used. :-- -:":"~";"~"i":"J"i"i":";~~~",~f ----; --- --- --- --- -,,~f --- --~ --------;-- --,, ~ , ':;~~J::t:::!:::'~-iI - -----,, :1:::'::;:'+0 (-. ', e,' :" : " ", ,----------'' , , " ' , - ------- --' , , , , , , ' - ----- - --, ", o n GU RE S 1l Contraction <>l A<kkr to Increme"'OT ~ 2 26 in Ih~ 0 C HAPTE R S / A RITHMET IC F Uf\;CT IONS A NI) C I RCU ITS Based on vaJuefi:<ing. Ihere a rc t hree dislinct c ontraclion cases for Ihe cells adder; I. 111e least significant ""II on Ihe righl with So _ I and C o" O. 2. The Iypical <:<;11 in Ihe middle wiln 8 , = O. and 3. The mOllI si&nificanl cell on the left with B l ~ 0 a nd C ) " X. For Ihe righl cell. Ihe OUlpul o f g ale I " "comes Ao SO il can I:>e repl a ced by a n i n'erler. T he oUlput o f .&.ale 2 be<:ome. A Go s o il c an be re placed by a wire c onnecled In A o- Applying A o a nd 0 10 ga le 3. il can b e r eplaccd by a wirc. c n n_ n eclingA" 10 the o utput 50- The nUlput o f g ate 4 is O. s o it c an be r eplaced wi th ~ II v alue. Applyi ng Ihi $ 0 a nd A o from g ale 2 10 g ale 5. galC S can t>e r eplaced by a ".. ire c o nnecling An 10 C,. T he r esulting circuil i . s hown as Ihe righl ""II in F igure 5- 12(b). Applying Ihe samc lechnique to Ihc Iypical c dl with B, . . 0 ) 'idds 5, .. A, eC , Cl - A,C , giving the circuil shown as Ihe middle cell in Figure S-12(b). For the left cell wilh B , .. 0 a nd C , _ X. I he effects o f X aT<: p ropagaled firsl to 1ja"C effort. Since gale A has X On i l' OUl put. il i . removed a nd X's a rc placed 00 ilS Iwo iTlpu,,_ Since all gales driven h)' gales B and C have X 's on their inpu ls, they can be removed and X's " Ill be placed on their in pUIs. G ales D and E c annot be remo'ed. since they arc each dri"ing a gale wilhoul an X on ils i"puL The resulting circuil is ,n()Wn as the left cell in Figure 5-12(b). F or a n incremenlor wilh n > 3 bils, Ihe leasl significanl i ncremenler c tll is used in p as;l;on O. the typical cell in p as;l;ons I lnrough n - 2. a nd I he mosl significant ccll in p osilinn" - I. In Ihis ~x a mple.lht r ighlmost cell in p osition I is contracled. b ut . if d esired . il c ould be r eplaced wit h the cel l in posilion 2 wi th Ho = 0 a nd Co ~ I . Li kewise. Ihe OUIPUI C) c ould b e g enerat ed. but not used. In holh cases. logic "Olll a nd p ower cfficienC}' a rc s acrificed 1 0 m a ke all o f I he cells idenl;cal D ecrementing Decrementing is the addition o f a fixed negative val ue 10 an arithmelic variable. mOllt o flcn. a f,xe.! value o f - I. A deeremenler has already been designed in Example 5-6. Allernatively. a decrementer could be de!;;gned bji using an adder-$ ublraclor as a Slarling cireuil a nd applying B _ 0...0 \ a nd Co z O. a nd selecting Ihe . ubtraction o peralion by selling 5 to L Ilcginning wilh a n a dder-$ublraclor. wc c an also usc conlraction 10 design a c ircuil Ihat increments for S z 0 a nd d ecrements for S _ I by applying B a 0 ...01. Co _ 0, a nd letting S remain a . ariabk In Ihis case. Ihe resull i s. c e ll o f Ihe complexilY o f a full a dder in the typical bit posilions. In fact. by going bac~ to baSICS a nd redcfining ' hc c arry funClion and d esigning Ihe c dl using ,his redefinition. the COSt can be l owered somewhat. Thi. illn,mnes that oon(T1'Idion, while il yields an i mplementation, may not p roduce a r""ull with t "" le~t CQSt o r b est pcrfonnallCl:. M ulUplieation b y C onstants Asou min g t he ci rcuil in f igu re 5 11 i . u sed as a b a si. for multiplication, mulliplication by a c o nstant can be . chiewd by s imply applying t he c onsta nt a s the multiplier A If t he value for a p articular bil p osilion i. I. t han I he m ulliplicand will be a pplied 10 a n adder. If the value for a p anicular b it position i . 0, ( hen 0 will be a pp li ed to a n a dder a nd the a d der will be r emo.'ed by c onlraction. In hoth cases, Ihe A N D g" I<:$ will be removed. The p rocess is i llustrated in Figure 5.13{a), F or this case. t he mul t iplier has b een se t 10 10 1. In t he contr'C1;on process. si nce 0 + B ~ B, t he c arryoul value is always O. T h e e nd r""ull o f t he c ontraction is a circuit Ihat conveys Ihe t wo lea.t signific ant bits o f B t o Ihe o ut p ut s C, a nd Co. T he circuit a dd . the l wo mOl t .;gni~canl bi t. o f B t o B s hift ed t wo p osition, t o t he lefl and applies the result 10 p roduct o u t pUI< C. t hrough c" An imporl nnl s pecial c ase o ccu'" w hen the c onstant e qual 2i (i.e .. for nlu lti p li catiOfl 2 i)( B ) . I n this c ase, o nly o ne 1 a ppears in the m ulliplicr a nd a ll logic is e liminated from Ihe circuit r csull ing in only wi res, In t hi s case, for the 1 in p osi tion i, the r es ult is B f ollowed by i O's, T he f unctional block t hat r esulls is simply a c o mbination o f s kewed l ransfers a nd value f i' ing t o O. TIl e func ti<>o o f ( his block i . c~lIed a 141 s h'fl b y i b u p<>siliol1> ,,';<1, I;~ro /ill. Z~ro fill r efc," t o t he additiOfl o f O's to the right of ( or t o t he left of) a o o perand s uch a s B. Shi fling i . a " c ry in 'po r. tant o pera t io" a pp li ed 10 o ot h n u merical a nd nonn um crical d~ta . T he o o ntractio n r esu lt ing from a multipheation by 21 (i .e.. a left s hift o f 2 bit p ositions) is s hown ill Fig ure 5 I3(b). D IvIsIon b y C onstanta Sine<: we h ave n ol c overed t he d ivi.ion o peration, o ur d iscussion o f d ivision by c onSlams will b e r estricted t o d ivision by p owe", o f 2 ( i.e .. by 2' i n b Inary). Si nce m ulliplicalion by 2 ' r es ults in addi tion o f; O's t o l ho r ight " fthe m ultipli c and, by a na logy, d ivision by 2i res ults in r emov a l o f t he i le ast s ignificant b its o f the d ividend. T he r emai n ing b its a re t he q uolient a nd t he b its d iscarded a re rhe r emainde r. T h e funClion o f this bloc k is " " li ed a ri/illt .\1Iilt by i h i/ p mit;"".. JU SI a s for left s hifting, r ight s hifting is l ikewise a very i mportant o peration. T he f unction b lock f or d ivision by 2 ' ( i.e .. r ight ' hi fting by t wo bit p OSit;"ns) is s h own in Figure 5 13 ( c) . Zero Fill aOO E xtension Z ero fi ll. as d ef,ned p reviously fo r multip li cation by a con Sla nt. can a lso be used to i ncrease the n umber o f b its in a n o perand. F or n ample, s uppose Ihal a byle 01101011 i. 10 be used a s an i nput 10 a c ircuil t hat r equires a n i nput o f 16 b;\5.. O ne possible w ay o f p roducing t he 16bi t i nput is t o ,-erofi ll with eight 0 ', o n the left t o p rwuce (lOO{)()((I()() I IOIOII. A n other is to , .ro-fi ll o n the right to p rod uce 22 8 0 C HAPTER ~ I A RIT HM ETIC FUN Cl 'IONS A N I} C IRCU ITS ( , ( , , ~'c ( I -' l - I- ::r::r::r , c,,'. ''''ru' / -p~' ~c ,~ H ,,,A<lder ,." '""ru' ,.) 11, 11, 11 , 1\0 ~~ C, C. C, C, C, C. ''l ~ C, C, Co C, C, c, ( ,) o F I GU R.: S I J Conor.01ion. of Mult iplie r: (oj for 101 ~ B. ( b) for 100 , B. and (ej for B .. 100 0 110101 100iXXlOOO . T he former a pproach would b e a ppropri al e for o~ralion. s uch a ddition o r s ubtraction. The l aller a p proach c ould b e used 10 pTOduc e a low.preei~ion H,bit m uhiplicalion T"suh in which t he byte r ep r esent' t he most s ] I H OL R ep",,,,n"""".-VHOL 0 2 29 significant t ight bits o f t he a ctual p roduc t with the lower hyte o f t he p roduc t discarded, In c ontrllSt ( Q z ero fill. s ign a'I~ . ... i m' is u~d t o increase the n umber o f hits in a n o pera nd repre""nted by using a complement r epre""ntation for signed numbers. I f t he o pe rand i . positi,e. t hen bits can be added on the left by e xtending the . ign o f the n umber ( 0 for posi t ive a nd I for negative). Byte 01101011. which reprrscnts 107 in decimal. e xunded to 16 ~15 beoomes 000000000110101 L Byle 10010101. ",hich in 2 's compleme Ol represeOls - 107 . eXlended to 16 bits b ecomes t 111111110010101. T he reaSO n for us ing s ign eXlension is to proselVe t he com p ie meOl r epresentation for u gned numl>ers. Fo r example. i f 10010101 were u tended ""ith 0 '" Ihe magnitude r epresented would be " ery large. and furth . .. the leftmost bit. which s hould be " t for a minus sign. would be incorrect in . he 2's-complement r eprcsen.allon. D~C""'l A RmIMUJ(; T he s upplement that discus.\.CS decimal a rithmet ic functions and circuit implementations is available o n Ihe C ompanion Web$ite fo r t he text. 5 -7 H OL R El'RESENTATIONS-VHDL Thus far. all o flhe VH DL d escriplions us.ed have contained only a single e ntit y. O<!scriptions that r epresenl circuits using hierarchies h."e multiple entities, o ne for each dislinct element o f . he hi erarc hy. as s ho"'n in the next example. I E XAM PLE 5-7 Ilienorchical W IDL for _ 4 -8il Ripple C_r ry A dder The example in Figures 51 4 and 515 uses t hree e n, it ies 10 b uild a hierarchical de""ription o f a 4 bit ripple carry adder. T he s tyle used for the architect ures will b e .. mi ~ o f Struct ural a nd dataflow d t""ription _Th e three e nt iti es ore a half adder. a full a dder Ihat uses half adders., and l he 4bil a dder it se lf. The archite<:lure o f h al f_a dder consists o f 1"-0 dataflow . ... ignmen t" o ne for _ a nd on e for c. The a rchitecture o f f Ull_adder uses h alf_adder as a CO'"p""tnt. In addition. t hree i nternal s ignal" h . .. h e. and t e . a re declared. These signals a re applied t o IwO half a Jd cn a nd a re a lso used in o ne dataftow a,sign",ent t o c on, truct t he full a dde r in Figure 5 4. In Ille / ldder_ ' entilY. four full adder c omponents are simply ronne<:ted to~ther using Ihe signal' given in Figure 5 -5. N ote thai CO a nd C4 a re an inpul a nd an output. respeclively. b UI C (O) through C ( 4) a rc internal signals (i.e .. n eit her inputs nM o u lputs)_ C(O ) is a s,igned CO and C4 is a>signed C ( 4) , T he u se o f c ( 0 ) a nd c (41 separately from CO nnd C4 i . n ot cS$<.'nti.1 h ere. b ul is useful to illUSlra'e a V BD L cons traint. Suppose "'.., w anled t o a dd o"erHow d etecliOllto t he a dder as . hown in Figure 59_ If C (41 is not defined separately. then one might aHempl t o ""rile V < _ C I31 " O r C4 2 30 0 C HA I'TER 5 /II RITHMETIC F UNCTIONS A ND C IRCUITS - - 4 - bit A dder: H ie rarchic a l " "taflowlS t ru ctural - - {se. Pi !iUres 5 -4 a nd 5 -5 f or l ogi c c liagr".,. 1 l ibrary i eee ; u i..e . ~ tdLlogic_1164 . "Uty h aH_ad1er i s p ore I x. y : i n _ al l, ~ t<Llogic, . c o ut s t Vog icl; . Ad h al C adder, a r~bit<octur .o data f low_~ o t h alf_adder 1 . - '" _ r y, . <_x _ e < _ x . n<'! y : dO-t<o!low_3 ; l i hr _ry i_ , u . . i _ . s t<LloglcJl64 .aU, . ne1ey full _~r I . p ort: I x. y , z , i n n Vogic , . c o ut s Llogic l, _ Ad f ulL<>OOer, c_. . rcbit . etur. a truc_ dataflow_ l o f ful~dder i. h alfJ'<ldar p ort { x , y , i n s td.-logic: s , c , o ut .~loglcl: . .., e arponent, . 11JIl&1 h s. h e, t e , n d..-logic, - '" HAl: h alCad<le r p ort _ p I x. y . h o . b el: HA2 : h alf_adder p or t 0I&l> l ho. ' . , t el: e <"te or be : . "" Btft1C _datafl""'~ : l ibrary i _, u i eee . _Llog i c..1l6 4 a ll: a "tity a ddor_ 4 i . p ort (B . II i n o t <Llogic_ vectorD e o : 1 n . "<Llogic; S : o ut: * t<Llogic_ """torD e 4: o ut s Llogic l; . ..,4 a <Her_4: o f iGURE ~to ~to 01 , 0 1, S I~ H ; er"",~ i<al S 'ruc'u",lID.a"iIQw Oes<ri pOioo o f 4 B;, Full AckI<r 5-7 I H I)I. Rq>r<><n . . r ion>---VHl)l . rc4it.etur t ruc t ur.I_' o f ~r_ 4 0 2 31 i. ca.pone~e ful~r p on 1x. y . z , i ll _ t.<L1ogic; c , o ut a t<t.)og;c); .<14 " '","""",ent; d qna l C , _ t:d..logi c _"""tor(4 d c.onto 0 ) ; b egin B itO, f ull _ adeler p ort _ p (BIO) . 1 0) C (O) 5 10) C (l)); B iU, f ull_""""r p ort _ p ( B(l). " (11. c nl. S (\) . C (2)); B it2 , f Ull.ftdder p ort _ p ( 8(21 . " (21 . C (2) S ( 2). C (311; B it], f ulV<ld<>r p ort _ p (B I 3 I " 131. C ll) S O)' C it)); C 1 0) .~ " ~. ~. C O; C I'I; . tructural_', o F IGURE 5-15 In V HD L. t hi. is incorrect. A n Onlput eannol be used a . a n i nternal s ignal. ThUs, it is necessary 10 define an in tcrnal s ign.lto use in place o f C4 (e.g.. C (4 I ) givi ng V < = C O) >c.". C (4) Behavioral Description T he 4-b it a dder p rovide. an o pro n unity 10 ill ustrat e dcserip!ion o f circuits at a levels high cr Iha n Ihe logic leve l. Such levels o f deseription a re r eferred to as !he b eb avioral level Or the registe r transfer l evel We ,,;ll sp<:cifically ~ Iudy r egist~ r t ransfers in C ha pler 7. Without studying register Iransfen. however. we can still Show a b ehavioral le~el d escription. I E XAMPLE S-S s.-ha~ioral V HDl for a 4-Bil Ripplc Carry Adder A behavioral description for t he 4 -bit add er i . given in Figure 5 16. In Ibe arch ite<:ture o f Ih e t ntity " """r_ 4j>. the addition log;< is d e=ibed b y a singJe statement using + a nd .I. . T he r epresent' a dd it ioo and the ~ represenl$ an <>peTation c an ed eo"cale~Uljo" . A c oncalenation Op<:ralor combines two signa ls i nto a singJe . ;gnal h aving illl n umber or bits c q ual to t he . u m o f the nu mber of h i'" in the original , ig_ nal s. In the e xam pl e. ' 0 ' ~ A r epresents the , ign.l vector ' 0 ' A (31 A (2) A (l) A IO) I II 0 C IIAPTI:R 5f A R ITt IMTIC f U ~CTIONS AN I) C IR.C UIT'S - - 4-blt Addoo~, B ehavioral D ucdpdon l ibr"ry 1 _: ~ 1 _ , 1t<1-1og l c I16 4 . 1 1 , ~ . . 1 _ , It <L logic"""ign<><"l . l l , .n ~lty ~r_t -p p ort ia. A , h . co , I. ,,~ol._ logi.c_vecurl) _ t o 0 ): I . . s!:<l_ logic, S , _ t e t.<Llogicvecurll _ t o 0 ): C 4: _t . uLlogic), . nd _ r_tJ>: .,,~bH..,tu . ... _." . ig n "l I tUfI\ : b eba"i o ul o f _ r_Cb I e a t<Ll og i c _v<>ctor 14 _ t o 0 1, . ... < .1 ' 0' ' A I 1 '0' .. B) 1 '0000" C t <. ..... 1 4), S < 0 _ I ) _ t o 0 ), " nd b eN"!,,..... , CO), ( ] F lGU R!! !o l6 B ffia,. """, l ln<ripI. .. o f .... 8 " " " II A .-. Wil h I ~ 4 = 5 ~ ignals. NOle I hol ' 0'. which a ppear. o n Ihe left in the c oncatena lion c xpr ~ss ion a ppears o n t he left in Ihe sign al li sling. T he i nputs t o t he addition a rc all c onvcrltd 10 3-bil q uantili C"l lor C(lnsist~ncy. i nre lhe o utput , ,,,,ludi ng C4 is 3 bilS. T his ronveT3ion i . not esselltlal, but i$ a " "Ie a pproach . Si~ c an not be p erformed o n t ht st~logic Iypc. , ,'e need a n a dtiilional p ackalc 1 0 define adtiilion IOf Ihe I t<Llogic I~pe. I n thIS c ase. "" e a rc using s td....loglc_. .. ith. a p ackage preso:=m ;n l he i ee e l ibraf)'. F unh tr. " '"e ",;s h 10 .pe<:ir.cally d cline I h~ a ddi lion t o b e un sign~d . ' " " .c U$C Ihe W lligned c xlension. AI . ... r oncalen . .i on in V HD L c ann Oi be u sed 011 Ihe lof! side o f a n assignmem ,1. lenlent. To o b la in C 4 a nd S as l he rCl ul1 01 I h~ a dd, lion," ~ , bit l igna l " urn i , d eclared. The signal Bum is aSll;gncd the r~s u h o f lh~ a d dilion inel ud ing the c arry o u l. R>lIowing a ", IWO a dd ilional al$ignment Slal omenls whi ch ~ plil aum inlo o UIpUIS C4 a nd S. T h " compicl es o ur inlroducl00n 10 V HDL l or a , ilhme hc circuit . . We wiU c onllnue ""'lh more 0 0 V HD L by p resenhng .neallS for dc5cribing sc: quenlial cirCU,IS in Ch~pte' 6. 5-8 H OL R EpRESENTATIQNS-VERILOG T hus far. a ll o f t he d escriplions ulled have c o ,uuined only a , h' glc module. Descripti on. lh ~t r cprcscnl .i.cuilS using hi ~ rarchy ha>' e mu hip lc m od ul es. o ne for e ach d iSiinct ( letnenl 01 l he hi~ra"'hy. 3.lho wn in l he n~xt e xa mp le. 1/ o - bl< ~r, Hi era r Ch i ca l Dot>fl cw !"~ ct u <~ l ~ 3 - 5 10< l~lc di~r"" I I I so. . i gor . . 5 - 0 _ 1. 1IIo1C_ __v l x, y < ), x. y , 1"",,~ .,..,.... . c, ~ 0 1 . ... . . K o 1 . ... e Y' ~. y, _ b f ull ....., tJor_V(x. y , z . c ), i DI"'" ~ . y . . , " "t . .... .. e , . ... I f--''''''''._v alg ~ < c e he,. " "1 ( x, y . Il10. K>.l l ba , z , ' . <e" h c, _ 1 . ...... r _....v l . .... CO. S . C o), ' _ t [l,OI a , . . , , . ...... CO, .... ' .... ' [) ' Ol S. " " . ..... c o, w lul J 1 ] C , B lcOlalO]' >.[ 01. CO. 8 101. C illO . j <lIIO] . .. [1 ]. C illo 0 [11. C [11f . 1<~lat~1. A!~1. CI~L " Ill. C illO. B i<JI'(lt. A (J], C (ll. S ill. C4 h o n G URE 5 17 Hi=hk.1 u ".o.,..'/S'ruct"",1 V. .. iloj: De scr iptIOn o f 4 -1>i, A<kI<r ~ XA.\I : P U: 5-9 Hio...... n:hkool VerilOl: fo 4-Bil Ripple C. rry A dder T he descriplion i~ Figure 517 uses lhree modules 10 r epresent a hierarchical design for a 4 -bil ripple carry adder. The Slyle useJ for l ne modules witt b e" m i. o f 51ruciural and d ,",I Iow dcscriptio~. T he lhree m od ule. a re " ha lf a dder. a fu ll a dder built . round half adde~ and the 4-bit a dder itself. T he b a l f _add . . r module <onSi & o r iwo dataflow 3$< ignment $.. one [0' iS and one for c_ T he ful l_adde ~ moo~1c uses lhe h alC a dder as " component as in Figure 5.... In lhe f Ull _adder . l hree i nlemal .. ir es, b " . h e. and t~ are d eclared . Input$.. o utputs a nd these wire namCS a rc applied 10 the l wo h~l[ adde~ 2 34 0 C HAPTER ~ I A RITHMETI C F UNCfIONS A ND C IRC UITS a nd t e a nd h e a re O R ed to form carry c . N ote that the SlIme n ame. c a n b e uscd o n d ifferent mod ule, (e.g.>x, y, s , " od e a re uscd in b oth the h . . l f _ . . dde~ " nd f u l L . . d der), [ n the a dd . . ~ _ 4 module, f our f u ll a dd ers a re si mply connected together using the sig n al, given in Figure 5 -5. N ote t hal CO a nd C4 ore a n input and an o utp ut. respectively, but C ( 3) thro ugh C O) a re internal signals (j ,e .. neither inpu t. n or o utput.), Behavioral Description Tho 4-bit a dder p rovides a n o ppor tunily 10 ill ustrate description o f circuit, at a levels higher than t he logic le,'ct , Such levels o f d escriplion 3re r eferred 10 a s Ihe behavioral le,'el o r th e r egister Iransfer level. We will spe.o ific ally st udy r egister t ra nsfers in C hapter 7. """,thout st udying register transfers. h o wever, we can st ill show t he b ehavioralle"el d escrip ti on for the 4-bit adder . I EXAM PL E ~-1(l fk, hu ,ioral Ve rilo-g f or a 4,Bit Ripple C a rr) A dder Figure 5-18 , how'S t he Vcrilog description for the adder. In m odule . . dde~_ 4 JJ_v . the addition logic is desc, ib<:J by a sing le s latement u ,i ng a nd i ) , T he , e present a ddition a n d the i ) r eprescm an o peralion ca ll ed conCUIenal ioll, The o pera tion + p erformed on wire data type, ; . un signed , C oncalenation combines two signals i nto" single s ignal h a,'ing its n umber o f bits equal t o t he sum of the number of bilS in t he original signals. [n the example. { C4, 5 j r epre,e nts the signa l " cctor C 45[3] 5 [2) S 11 ) S [ O] with I 4 _ 5 SIgna ls. Note t hat C 4, which a ppears o n the left in t he c oncateMtio n e~p re", i on. a ppears o n t he le ft in the signal li Sl ing, Th i' completes o ur int roduction to Vcrilog fo, aritbmetic circuilS, We will c ontinue wit h more On Vcrilog by prescming means for d escrib in g scquent i~l circuit, in C ha pter 6. _ 1 . e Mor_"J>_V{A, B , O J, . , C f), l _ _ t [1,O ) A, B , ' <>wt CC, " "t"". [] , O) . ; < Nt .,." C O, " gn { c. , S ) A B O J, . _~ l. o n GU RE S_ l l1 8 eho vi<l<al Do:s<;,ip<ioo o f 4 B it Fu t! A<Id<r U' Jll~ Verilog S-9 I a...po S....... ..,. 0 5- 9 2 35 CHAPTER SUMMARV T h is c haptc r introduccd c ircuit' for p erforming "r i th m ~tic. T he I mplementation o f b in ary a dders. includin, the car ry lookahead .. d der f or i mproved performonce. was t reated in detail, T he I~btraction o f u n,ign~d b inary n umbers u , in, 2's a nd [ 's c om plement.! was p resented , as was t he r cpresentation o f signed b inary n umbers a nd I hdr a ddition a nd su btraction . T he adde r~ub\ Ta<."lor . de~doped for u nsigned b inary. ... ' " found t o a pp ly d irtttly 1 0 t he a ddition and s ub\,*"ion o f signed h c omplemenl n umbers . ...... eU. A v ery b rief m lrod..aion t o b inary m ultiplicaIJon. using " """bi .... l ion.l c in-uits m ade up o f A N O &a t"" a nd b inary adders. "-as given. Addilional arilhmetic o perations inlrodUd i ncluded incrcmcnung, decre me nling. multiplicalion and division by a c onstant. and . hifling. T h e i n'plcmentaliom f or t hese o per.tions were o b tained by a design tC<"hn ;.qu e we caUed contraction. Z ero fi U and , ig" e xtension o f o peran ds WIIS also int roduced. T h e l"'Ittwo $Cetion' o f the ch apte r provided an introduc tion 10 V HDL a nd VerilO& d eKription s f or arithmetic circuit!.. Both H D 1.. w ere il1 ustroted by s tudying descripliOll$ ot t he func tion al a nd b ehnionll le"c I1 fo.- "anous fUuellon.1 b Iocb in t he c hapter . I. MANG. M . M. O igi,allNsign. 3rd c d E nglcwood Oiffs. NJ , Prentice I iali. 2m2. 2. W AKaRl. V. J . F. Oigllal De.ign: ( "i"dlile. " ,,,I Prac.ic<!S, 3 rd ed. E nglewood O iff. . NJ: I',en tice H aiL 2 (0) , 3. HiKh Spud C MOS Logic Daw 80()k . I )~lIa " Tcx a. I nstrumenl " 1989. 4. I EEE S ,allda,d V / IOL La"g,~ge R t/trt:nct Manual. ( ANSI/ I EEE S id 1076199): r evision 01 I E EE S id 1076-1987). N ew York , T he I nstitute o f ElCC1 rical a nd E lectr(ln i(:s E ngineers. 190M. S. r rH. D . J. f fDL C ltip Oesign. MlMlison .A L: D oon e Publicati ....... 1996. 6 . PE LLE ll t. .. D . AND D. T AYlOR. V flOL M",I~ ED.'!! U pper Sadd le:: R," cr. N J, ",""nlice l I all PTR. 1997. 1 . ST1'.FAr< . S, ANn L L '''DH. V flDL f o, D~si8"uJ. L ondon: P rentice Hall E urope.I991. s... .iI. 8. I EEE S """/",,I D~fC'iplioil L;mguagt Bast'/ " " V.,Uo!? lIo,d",,,,~ D Na/p'io!! u .llg"a8" ( I EEE SId 1,l64 199S). N ew Y ork:The Instilu, c o f E lectrical a nd E leclr0nic5 E nginee rs. 1m. 9. P AI.,nkAR . S. I 'tri k>g H DL"A G uM, f Q D t,i'allJaiK" " "d S}'mh,-,is. Uppt"r S addle R ",c r. NJ . S unSof\ Press ( A PJ en tioc Ha IITitle). 1996. 10. BII AS KU . J . A ~'~riJog I JDL Prtm~ . A lkntown, PA: S lar G alaxy Press. 1':197. I I. n IOMAS. 0 .. A"D P. MOORB Y. T ht Vui'''11 flord"'"rt: O~'ipllon ' ,,'' ''KUlig. 41h e d. Il oslo n: K luwcr A cademic P~bli ~ h cn. 1998. 12. CILl.1T rt. M. /I/",I<U"g. Syn.he.i<, /II/pili J>ro'OIyp;ng wi,h , Iu Veri/og H f )L . U pper S addle R iver. NJ: P rem ice H a ll . 1999. ("Il' 2 36 0 C HAPTER S f A RITHMETIC f UN=IONS A ND CUt.CUITS P ROBLEM S The plus ( +) indicates a more ad"anced p robkm a nd t he a steri," ( * ) ind icates a solut io n i . a "ailable on the C omp"nion Website for the text. 5 -1. D esign a c ombinalional circuit t hat forms t he 2-bit binary , urn S,Soof two 2 bit n u mb<:r< A ,Ao a nd B,Bo a nd h as I:>oth a e arry i nput Co and e arry o utp ut C:: , Dosign t he e mire c ircuit implementing each o f the three out puts wit h a two I e,'" circuit plus inverter< for the input ,a ri ah les. Begin the design wit h the following oquations lor e ach 01 the two bits o f the a dde r: S, = A ,B,C, + A ,B,C, + A ,B,C, + A ,B,C, C,., - A,B, + A,C, + B,C, 5-2. *'The logic d iagram of the first stage o f a 4_hit a dder. 8 S implement ed in imegrated circu it type 74283. is . hown in Figure 5 19 , Verify that t he circuit imp lements a full adder. 5-3. ' Obtain the 1's and 2's complements o f the fo llowing unsigned bi nary numb<:rs: JOOI 1 100, 10011101. IOIOIOOJ, ( (((((0), and 1 00X0XI. 5-4. Perform the indicated subtraction with the following un'ignod binary numbers by taking the 2 ', complement o f the suhtrahend: ( a) 1111 1- 1((((1 ( c) 10 1111 0-101 11 10 ( b) IOJIO - IJlJ ( d) JOI - IOJOOJ ) -I ] V V o F IGUK S 19 C if mit for P roblem 5 -2 5-5, Repeat problem 5-4, assuming the numbers are 2's complement signed numbers. Use extension 10 equalize t he length o f the operands. Does O\wftow occur d uring the c omplement o perations for any of the given numbers? Does owrflow occur for the overall subtraclion for any o f t he given n umbers? ~ . Perform tne a rithmetic o perations ( +36) + ( -24) and (- 35) - (- 24) in binary using s igned-Z"s complement rep resentation for negati,'e numbers. 5-7. The following binary n um bers ha,'e a sign in the I dtmost position and, if nega. li,'e. a re in 2's complement form. Perform the indicated arithmetic operations and verify the answers ( a) 100111 + 111001 ( e) 11(0)1 - 0 10010 ( b) 001011 - 100110 ( d ) 101110 - 110 111 [ndicate if o ,wllow occurs for each computation . 5-41. +Design three " ersions o f t he combinational circuil "'hose inp ut is a 4-bit nu mber and whose output is Ihe 2 ', c omplemenl o f the input number. for e ach o f the following caws: (R) "llIe circuit is a simp~fied Iwo-level d rcu it. pl us inverlers as n ceded for the inpol variables ( b) T he d rcuit is made u p o f four identical two_ inpul. Iw'o-output cells. one for each bit. The e<:lIs a rc connected in cascade, with linc~ , i mi lar to a c~rry b elwun t hem. The value applied to t he righlmost c arry bit is 0, (c) The circu it is redesigned with cor,y lookaheadlike logic in o rder ' " s peed up the circuit in pari (b) for use in larger circ ui lS wilh 4" inpul bit" 5-\1. Use cont raction beginn in g wilh a 4 bi t adder WiTh c arry o u t t o design " 4-bit inc rcmcnt.by-2 circuit witb c arry o ut that ~dds Ih<: binary value 0010 10 its 4 bit in pul. The function 1l> be implemented is S '" A + 001 0, 5 - 10. U"" contraction beginn in g wi th ~n ~ b it adder_subtraClor without carry " ut to d e,ign an gbit d rcu it wit hO UT carry oul , hat increments it s input by 00:OX110 for input S ~ 0 and decrements its input by 1)())Jt))1O for input S . I, P erfonn the design by designing the di s ti nct I_biT cells needed and indicating the l)'pe o f cell use in e ach o flhe eight bit pos it ion" 5 - 11. +(a) Us c contraction beginning WiT h a 4 bit carry l oobhcad . dder with input carry and group carry a n d g roup propagate funCl ioru; 10 design a 4 bit carry.lookah ead . based circuit that i ncrcments its 4-bil inpUT b)' thc bi nary equivalent o f2. ( b ) Repea t part (a), designing a 4 bi t carry lookahead-bascd circuil thaI adds 0Cl t o i I' 4-bit inpUl. Ie) Construct a 16 bit carry. loohhead circuit thm i ncrement' it ' l 6 bit input by 2. giving t h. I()'b it o ut put pl us a n oU1put carry. by us ing the circuilS d e' ign t d in (a) and (b) a n a dd it ional contraction o f a 4 bil 2 38 0 C HAPTER 5 f AR1THM~TIC F UNCTIONS A ND C IRCUITS " 'ith inputs PO-J GO-J P<-,. p. ..... and P 2-'" and t he a ddilion al logic needed 10 p roduce C ,. ( Nole Ihal. due 1 0' p an (b). G ... GS- II ' and G ,1_ " " are equal 1 00.) 5--- 12. Design a c ombinalional circuit Ihal c ompares 1 "'0 4-bit uns igned nu mbers A and 8 10 see w hdhcr B is grealer Ihan A. ' The circuit h,lS Onc o ut pul X. so Ihat X - I irA < B a nd X - Oif A ~ B. 5---13. " 'Repeat Probl em 512 by using threeinput, one-oulpul cir~uits. one for each of Ihe four bits. T he four circuits a re co nn ""led l ogether in cas<:ade by carrylike . ignals. O ne o f Ihe inputs t o each c e ll i , a carry inp ut . and Ihe single output i$ a c arry outp ut. 5---14. R epeat P roblem 5 \2 by a pp lying cont raction t o a 4-bil subtractor and using the borrow out , s X. 5---15. D e sign a combinational circuit Ihat compares 4 b it unsigned nu mbers A a nd 8 10 see whether A _ 8 Or A <: B. Use , n ilerative circuit as in Problem 514. 5---16 . "'Design " j bit signed'!n"gni' ll dc addcr---5 ubtra<:lor. ! )i,;de l he circuit for design imo (1) sign g eneration and add---!l ublract comrol logic, (2) an unsigned number a JJer_$ublrac10T usi ng 2's c< ,mp lemcnl o f l he min uend for subtraction. and (3) seleclive 2', complement resu lt correction logic. 5---17. ' The a ddcr_$ubtrac t<> r d rcuit o f Figure 51) has lhe f"l lowing val ue, input select S and d ata inputs A and B: 0 0 1J1 0 1J1 (,' ,, , , moo Oil' 1101 ( 0) 0 O ill ,,, 1010 , 010 (., ( .) (,) =, ,= Delermine. in e ach case. the "alues o f the OUlpulS S,. S,. S ,. So, and C . 5---18. ' Design a bi nary multiplier t hai multiplie. two 4 b it unsigned numbers, Use A ND gales a nJ binary adders. 5---19. Design a circuil Ihal multiplies a 4 b jl multiplicand by Ihe consta nt 1010 by applying conlraction 10 ,he sol ution 10 Problem 518 , 5--2 0. (y) Design a circu;t llial mu lt iplies a 4-bil m ult iplicand by t il e oonstanl lCO'J. (II ) De,ign a circu il Ihat divides an g b; t divide nd by Ihe constan1 ICO'J giv ing bolh an g bil q uolienl a nd a n gbit r emainder , I"robkm. 0 2 39 All files r eferred t o in the remaining problems are available in ASCII form for s im' ulation a nd editing on the O:> mpanion Website for the t ext A V HDL o r Veri log complier/simulator is ne""s.sary for the problems o r p orlion, of problems request ing sim ul ation. Descriptions can still b e wr itten, however. for many problems without using compilation o r simulation . 5-2 1. O:>mpile a nd simulate the 4 bit adder in Figures 5-14 and 5- 15. Apply combinations that check o ut the rightmost full a dder for all eight inp ut c ombinations: this also serve, as a check for the o ther full adders. Also. apply comb in ations t hat che<:k the carry chain connections between all fu ll adde.,; by d emonstrating that a 0 and a I can b e p ropagated from c o ( 0 C4 5 -U. ' Compile a nd simulate lhe behavioral description of the 4-bit Adder in Figure 5- 16. Assuming a ripple carry implementation. apply combinations l hat check o u t the rightmost fu ll a dder for alt eight input combinations. Also apply combinations that check the carry chain conne<:lions between all full adde . . by d emonstrating that a 0 a nd a 1 can be propagated from CO10 C4 . 5 -23. +Using Figure 5-16 as a guide and a " when e l"," on s . write a high le,cl b ehavi", V HDL description for the adder-subtractor in Figure 5-8. Compile a nd simulate your description . Assuming a ripple carry imp le mentation. apply combinations that check o ut one of the full adder---'Subtractor stages for all 16 possible inp ut combinations. Also. apply combinations 10 check t he carry chain conncetions in between the full a dders by d emonstrating that a 0 a nd a 1 can be p ropagated from c o t o C4 . 5---24. +Write a hierarchical dataflow V HDL description similar to that in Figures 5- 14 and 5-1 5 for the logic of Ihe 4bit can)' loohhead adder in Figure 5-6, Compile and si mutate your description . Devise a . . t of te.ts that does a good job of exercising t he logic mIhe adder. 5---25. Compile and simulate the 4-bit A dder in Figure 5-17. Apply c omb in ations t hat check o u t the rightmost fu ll a dder for atl eight input combinations: this also . . rves as a check for t he o ther full adders. Also.apply combinations that check t he carry chain connections between all full adders by d emonstrating lhat a 0 and a I can b e p ropagated from c o t o C 4 . 5 - Z6. 'O:>mpile a nd simulate the b ehavioral description of the 4-bit a dder in Fig. ure 5-18. A ssuming a ripple carry implementation. apply all eight input combinations to check o ut Ihe rightmost fu ll adder. Also. apply comh in ations to check Ihe carry chain connections between . tt full adders by demonstrating that a 0 and a 1 can be propagated from c o to C4 . 5-27. Using Figure 5 18 as a guide and a " binary dcci.ion-- on s from Figure 4-37 . write a high-level behavior Veri log description for the addcr---'Suhtractor in Figure 58. O:>mp,le and simulate your de>;cription. Assuming a ripple carry implementation . apply input combinations 10 }'O U design that will ( I) cau. . r all 16 possible input comhinations t o b e applied 10 thc futl a ddcr ---'S ubtractor stage for bit 2. and (2) simultaneou sly cause the carry output o f bit 2 10 2 40 0 C HAPTER ~ I A RITHMETIC F UNcnONS A ND C IRCUITS a ppear at o ne o f )'our design's outputs. A I", . apply comt>in"tions t hat c hed the carT)' chain connections between all fuU adders by d emonstrating t hai a 0 a nd a 1 can be p ropagated from c o 1 0 C4. 5--28. +Write a hierarchical Verilog dataHow description s imilarto that in Figure 5- 17 for the logic o f the 4-t>it carry lookahead a dder in Figure 5-6. Compile a nd simulate your description, Deyise a set of tests that does a good j ob 0 1 exercising 1he logic in 1he adder. S EQUENTIAL C IR CUITS 1hII poIm, - """" studied o rIy COI'I'IbIIIationlollogic. AlthougI'I s uch logic II c apable ot i nl_1ing opetal101'1S. s uch . . ..:kIIIIon and s ubtraction, t he ~rlorlllllncoo 01 . ....1'" s equanc. . 01 _ ",no"a u sing C OITIbInI.l_ l ogic ak)ne requl, . . case.CIing many S\ ,UC1 Ufa. l Ogel,*". T r.. hardware 10 de 11>11, however, I , very ~<nlly and in n. .xitMe. In onIe, 10 ~rlo,m u sel'" " r n. .1bIe . equ.m" 01 OJ)erllUon . we need to b e able te consl",,,! circuilatha' c an I tora in !ormation oe t""'" \ he QPera ti(lns. 5<J<:h clrcultl I r, ca lled " "q .... ml" ~ rcul t l, This c haple' ~In. wm, a n injroduc\lon to _ nlla l circuits, wI1lch I . k:H lowed II)' otucl\l o Ilhe b UIc elemenl. !Of otorlng bInIory InlOfmatioo. cak>d " !Chat . "" nip. ! lops. w& <I1str.gulsh n;p.nop. from l atchet Vod I l\ldy v a"",," ! )'pel 01 . .ell , W , ! hen a ni"'" MIIlHIntioIl c ircuits a >nIIlUng 01 b oth ntp.lIopsand comIIIn.Mk>nallogic. S ta1e " ' _ _ I Iate d iagrams P<tIide. m MM/or - .ibi'ijj!he behaolloo 01 s equent . ., CifC . .... SOobMql ...... MCIIont ot the c I\epIef - ..p the ~ " " d&signIng ~i., cit<:uol' and .... rlfylng 1 _ c orNCt.-a. In t he '<lal two stoCIionI., . .. ptovIde VHOI.. a nd ~rq h ardware dellCriplion lang.o..age " ""esentono,.. l or l lOr.ge e lements a nd tor l he t ype 01 ""'lIJ8I1tial clrcuitl in thO. 11 cI1apter. L atches. fll po llopll. and l&quontial . . r cuilt a re l undame m Bl c omponenla In t he !IeaIgn 01 almost . 1 digital 1Ogk:. In the g eneric C OInj)Ytlr ~ 81 \ tle I Jegirring 01 Chap1er I . letcI>es a nd IIIp-l\opI are wiI::I$$j><&ad In !lie d esign. T he e><cepIion isll'o(lomOly o;:Ir!;uils, since Iatge ponioooa 01 " """"'Y a m dooa;gooed a s e I8cItonic a n:uits IlIItMH It>In a s . circuits. ~ , d ue 10 the w ide use 01 ~ sto<ege. IhII Chapter oontaOs II.ondamen\IIII ....-.w l or " "V I n-Oe' ~ 01 c ompIIIM , lid digIIaI ~ _ - 1I""f are : !::'"g oed o 24 1 24 2 0 C HAPTER 6 I S EQUENTIAL C IRCU ITS I nl"''' Com.,; , . . ioo.1 ""u" L - Pre . . I a n' " . .. F 1CUKE6- 1 Block Diagram o f. SequeMial Circuit 6 -1 S EQUENTIAL C IRCUIT D EFINITIONS T he digital circuits considered t hu. f~ T h a"e been comb in ation al. Although every digita l ')"item i . likel y to include a c o n' \>i natiunal ciTcuit, must . )'ste m, encoun te,ed in practice also in clude , wrage elem ent" r eq ui rin g tha t the systems be described a . s equential circuit" A block diagram o f a sequential circui1 i, , hown in R gute 6-1. A cornbina1iunal cireuit and .torage clements are interconnected to form the sequential circuit. The storage clements are circuits that a re capable o f storing bi nary in formatio n. T he binary in formation stored in t h"", elcmcnt$ a t a ny given t ime defines the s Me o f the sequent;al circuit a t thlll time, T he sequen li al circu it receives binary in fo rm ation from its e nvironment via the inpul~ ' ln es inpu ts, togelher with the present state o f the s tot~e clements, determine the binary ,'a lue o f the ou tput ~ l b ey also d etermine the value, used t o sp"cify the nexl s we o f t M storage e lement" The block diagram demunstrates Ihat the o utputs in 8 SC<Jucnli.1 circu it " re a fu nction nut unly o f the input" but also o f the present stme uf the .Iorage e lement" T he next ,I tale o f the storage e le ment' i . a lso a function o f t hc i npub s nd the present State, T hu" a sequential circuit is specified by a time SC<J uence o f inputs, internal Slates.. a nd OUlputs. T here a re twu ma in I ype' o f seque nt ia l circuits, and their cla. . ification depends o n t he times at which ' heir inputs are observed and their in terna l slate change~ The behav;or o f a s ynchronous s~q '''!nlial cirellil Cnn be d e fln ed from the knowledge o f its signals a l di screte instanlS o f time- The behavior o f a n a sync/"on,m . > 'eqllemill/ cirCllil d ep"nds upon Ihe i nput' a l any instant u f time and the o rder in continuous t ime in ""hkh t he inpul$ change. I nformation is ' Iored in digil"l s)"items ;n many w ay" including the usc o f logic circuit" Figure 6-2 (a) shuws a buffer. This buffer h as" p ropagation delay I",. Sin ce information present a l t he buffer input a t t ime I a ppears a t Ihe b uf fer oU lpu t a t ti me I + I"" t he informat io n h"" effectiw,ly been stored for , ime I",. But, in generaL we wish 10 ' tore i nformalion fur an in definite time that is t ypically much longeT than 1he time dciay o f one o r even many g ate" Th i, stored value i , t o b e c hanged at a rbit rary ti mes ooscd on the inpul. appl ied t o Ihe circuit and , hould not depend o n t he sp"cific l ime delay o f a gale Suppose that the oU'pu, o f Ibc buffer in Figure 6 -2(a) is connected to its input as shuwn in Figurcs 6-2(b) a nd (e) . Suppose f unk, , hat the value on the in put to the buffer in part ( b) has been 0 for a l least tim e rpd' T hen Ihe o ut pul prod uced by t he buffer wi ll be 0 at time r + Ipd' This uutput is a pplied to lh e in pul s o ,., ,., ' 0) o t l GU RI: f>.Z LoJi< Structures fOf S,,,,,"S Inform"ion t hat I he OUlp .. ! wHl a lso I x 0 a t l i me I + 2 ' ",. T h is r e lat io nship b<:lwecn i np u t a nd o utput h olds f or a lii. s o . he 0 will be ~Iored indefinitely. The " ,me a rgum(nl can b e m ade for n ori", a I in the circuit in Figure 6-2(~). 1l><: u am ple o f l be b uffer i I!...,ra,C1 , h., Sforage c an b e OOflSlructed f rom logic w ith d elay r onnec led in a c losed l oop. A ny loop t hai p roduces ' '''''' SIOI"age mus, also ha..., a PfOP"rty possessed by t he bulfer. namely. lILa. , he.e m~ be n o inversion o f t he s ignal a round t be l oop. A bulfe . i!; u..uaJ1y i mplemented by .... ng ' '''0 ;nvcrle~., $ItO"-n in Figure &-2(d). T he , iJllal i , invert ed { witt, 1hal it. X- X giving n o nel inversion o f the signa l . round Ihe loop. In fac t. this e ump!" is an ill us tration of o ne o f the most p opular m elhoos o f imp l~m e nlin g storage in r omputer memories. (~Oa p 'c. 9.) H owever. Rlthough the circui ts in 1-Iguret 6-2(b) through (d) arc a ble Lottore information. t h~re is rKI .... a) for t h~ information t o b e c hanged. By rcplacin& the i n.",rten "'1lh N OR or N AND &ates. the informatIOn c an be changcd. /uynchronoU'l storage circuits .:a11W latches a re m ade in (his mallner anod a le discussed in t he ne~ t s ect ...... In , eneral. more o omplu a synchronous clfcuilS a re difticuh t o d e$i",. l lnce their behavk>r is highly de ~ t><knt o n the propagation dda)'S o f the gates and on the timing of the input changes. Thus.. circuits t hai fit the 'YIlchronoU'l model a rc the choice of "'O$t designers. Ne.'erth.I.$$, ~",e asynchronous design is /lece5l!ary. A ,'cry importanl CUe is t he use o f asynchronous latches as blocks to build s torage elements. called nip-nops. t hat store informllllon In synchronous circuit$. A synchronous K<l""'"tiaJ circuit employs signals that a fft t be SIOI'!\gc e lemellls only al dlJCrCte instant. o flUne. Synchronization is achie.-e.j by a tllnillg <bior: a iled. docl< ~lH " hid! produces a p "riodic t rain o f d ocl<"..bo. 1 be p ulses arC d i,"ibuted t hroughoul the $)'SIcm In s uch a way that synchronous Storage elements an: affected only in some o pcci6cd u lallons!tip t o evel)' pulse. In pnct..,.. the d ock pul5cs a re applied . .;,11 othe r Ioignals that opccify the u 'l uiu d change in Ille storage clement!. 'Tht OUlpU," o f S longe e le mellls Can change their va lue only in tile pre,..,nce o f clOCk pulscs. Synchr onOWl " "' Iueminl circuits that use clock pulses as inputs t o s tor.ge d ements a re ca ll ed d ocked . tlf"cnliu/ c;",,,;" , T h= a re the type o f 2 44 0 C HAPTER 6 I S EQUENTIAL C IRCUITS Combin.U"n>1 cire";! Oo:>::k p ul . .. ( b) Timin, d i. . ram 01 cJocK 1 "'1",. o t' IGlJRE 6,3 SYTlChfOTlOI" C k>chd Sequen ti . 1Cir<uil circuit most freq u~Dtly e ncoumered iD practice, si nce they " "",rate correctly in spite of wide diffe,..,nce< in circuit delays and are r dati"ely easy to design. The storage eleme nts u sed in d oc ked sequential circuits are called tl.ip ftops. F or si mplicity. assume circuits with a single clock signal. A flip flop is a binary storage device capable o f sloring one bit of information and h aving tim ing ~ha racteristi", to be defined in 5e<;tion ()'3. The block diagram o f 3 s)'nchronous d ocked sequential cir_ cuit is shown in Figu,"" 6 3. Th e fli p-flops re>ive their in puts from the c omb in .t ional circuit and alS(> from a clock sign.1 with pulses that occur at fixed interval, o f time. as shOWl] in the timing d iagram. T he flip _nops can change ~tate only in response to a d ock pulse. Fo r ~ynchronou, operation, when a d ock pulse is absen! . the flip ,flop o utputs cannot change even if the outputs of Ihe combin.tional circuit dri "i ng t heir inputs change in value. ThUs. the feedback loops shown in the figure bet,,'een lhe combination al logic a nd the ftip flC>pll a re bro~en, As a rosull. a transition flom one state to the olher occurs only at fixed time intervals dictaled by Ihe clock pulses. giv. in g synChronoUs op<:rat ion. The sequen t ia l circuit outputs are shown as outputs o f lhe combinational circuit. This i . valid ev~n when SOme sequential circuit outp ut' are actually the flip flop output~ In t hi' case, the combinational circuit part ~ t wun the Hipflop outputs and the seq uential circuit outputs consim o f connections only, A flip.flop has o ne Or twO outputs. one for the normal value of the bit s tored . nd an optional o ne for the c omplemented value o f the bit stored , Binary informa tion caD e nt er" fl ipflop in a variety of ways. a fact that gives rise t o different typ<:\ o f flip Oops. O ur focllS will b e On the mOSt prevalent fl ipfl op u sed today. the D fli p Hop. In " "'lion 6 6, o t her flip Hop types wi ll be considered. In p reparation for studying Hip . Hops and their op<:ralion, necessary groundwork is presented in the next section on latches fronl which the Hip. Hops a re constructed. 6 -2 L ATCHES A . torage e lement can maintain a binary <late indefinitdy (as long as power is deli,'ered to the circuit). until directed by an input s ig nal to switch sta tes. The m ajor d ifference. among the various types o f latches a nd HipHops are t he n umber f,-2 I !..a kh<. 0 2 45 o f inputs Ih~y poss.css a nd the m anner in which Ih e inputs affect the binary state. Th e most basic Sio rage ele ments aTC lalches. from "'hich flipflops aTe usually constructed. Although latches are most oft~n used within flipflops. they ca n also be used with m ore comp l~x clocking m elhods to imp \em~nl s-:quen li.\ circuits diT"\ly. The design o f s uch circuits i. . however. b eyond the scope o f the basic t re.tment g i"cn here. [n Ih;,; section. the focus is o n [ .tehes as basic primilives for con siructing storage clements. S R a nd ~R L atches T he S R latch is a circuil C<)nstruCl ed from two c,oss-c<>u pled N OR g . te . . It is d erived from the si ng[ e.[oop storage e[e mem in Figure 6-2(d) by s imply , epbcing Ihe invcnen wi lh N OR gates. as shown in Fi gure 6-4(3). Th is replacement allows th e $lored value in the latch 10 be changed. The latch has tWO inp'O!.. . labe[ed S for set a nd R for reset. and two useful stales. Wh en o utput Q - I and Q - 0, Ihe [atch is s a id to be in Ih e u t S tatl:. When Q _ 0 and Q _ I. il is in the r eu' slate. O u tputs Q and Q a T normally the c omplements of each other. When bolh input s are e qua l C to I a t the same time, a n undefined Slate wilh both OUlputs e qua lt u 0 ( ltturs. Und er normal conditiun s. both inputs o f the I"tch remain a l 0 unless Ih e stale is t o be c h.nged.lbe a pp Licali oo o f a [ 1 0 t "" S input causes the la lch t o go to Ih e sel ( I) Slate. The S input mUSI g<> hack to 0 before R i Hhanged t o I 1 av oi d occurrence 0 of II>c undcfinc-d SI. I" As sbo"" i~ Ihe function lable in Figure 6-4(b). lwo inpul conditions cause the circuit to be in 1M sel Slate.The initial condition is S _ I. R _ 0, to b ring the ~ircuil to the sct stat c. Applying a 0 to 5 with R - 0 leaves the circuit in the same s tat e. A fter both inputs return to O. il i , possible to e nter Ihe resel Slale by applying a I to the R inpuL The I t an Ihen b e T Cm('ed from R. and Ih e circuit remains in t M resel s l. te. ThU s. wh en boIh inpuls are e q ual 1 0 0 , Ihe [a lch can b e in e ilM' the set o r t M r esel. ' ale.dc""nding on wh ich inpUI was mOSI recently a I. If a I is a pp lied 10 b olh the inputs of the I"t ch. bul h OU lputs g o t o O. This produces an undefined stale becaue it violat.,. Ihe re<Jui . . m enl t hai the o ut puIS be Ih e compleme nt o f e ac h Olher. It also results in an indetermin ate Or unpred ict a ble nexl state "'he n bolh in puts return t o 0 s imulta neous ly. In normal o peration, Ihese p roblem, a rc " "o,ded b y " ,akins s ure t hat n a re nO! applied 1 0 I>olh inputs s imult aneously 11(11<><,) 0 L r 0 5 (Sc1) (.) LoP< " "' I ,om o ,, , , " ", , 00 , , , , Se, . .... ~ . .. , t:n<lerUl<d ( b) F \I"", "", , obit ~' I GUKE ()--4 S R Latch wit h N OR Gate, " ' t< 2 46 0 CHAJ'TEP. 6 1 S EQUENllAl CIII.CUITS L , L o " .,"" ". ," ",".,"' '',. ,''' ' "", ,,.. ,, ,,,, ,.,1 ,,,, ...,,,,,,,. ,, ",.,,,, ,,,,,. ,, ,1 ,,. ,, ,,, ,,... ,,,, ,. ," "","', ',. ," ",.,""'" o n ClJ K E 6-5 Logic S;mulat;on o f S R L atch Behavior T he b ehavior o f 1hc S R latch described in l he preceding p aragraph is illustrated by thc ModelSim "' logic sim~lalor w a,'cfom,s shown in Figure 6-5_ t nitiatty, the in puts . nd the SI,11. o f the lalch " r C unknown, as indica led by a logic level ha lfway b elween 0 and I. When R b ecomes I wit h S a l O. the latcb is reset with Q flrsl b erom ing 0 and. in response. Q _b (which r ep,esents Q) b ecomes l . Next. when R b ecomcs O. t he latch remains reset. s toring the (] . alue pTesenl on Q . W hen S bcrome~ I w;lh R a1 O. lhe latch is s el. wit h QJ> going t o 0 first a nd . in response. Q going t o I n ul. T he delays in tbe c hanges o f Q and Q _b a fter an input " ha ll g'" a rc directly related to lhe dda)'!l o{ l he lwo N OR g ate. u sed in the latch implemenlatio n_ When S r ctum s to O. the lalch remains set. slOr ;ng the I va lue present o n Q. W hen R becomes I wilh S e<:Jual t o O. the latch is resel wit h Q changing 10 0 and Q_h responding by changing to l . T he la1ch remains resel when R r elurn, 10 O. When S and R bolh b ecome I . bolh Q and Q _b b ecome O. WI,en S . nd R , imult. _ ncou$ly relurn to O. both Q and Q_b t ake On unknown value .. This form o f in delerminate stale behavior for Ihe (S. I i) seq uence o f ill PUI< (1. 1). ( 0, 0) Tesu ilS from ~ssuming s;m ultaneo us inpul c hanges a nd e qua l gate delay s. T he actual indelerminale b eha"ior thaI occurs d epe nds o n circ~il delays and slighl differences in Ihe limes a t which S and R change in lhe actual circuil. Regardless o f l he simulation results. lhese i ndelerminate b eha.iors a rc viewed as u nde,inble . and Ihe input combination 0 .1) i ~ avoided. In gen .nl.l he latch slale c hange, o n ly in respo nse t o inp ut cha ng~ and TCmains u nchanged o t herwise. The S R iJlch w it h Iwo cro:o;s--coupled N AND gales is sl10wn in Figure 6-6, It o perales wilh both inpulS normally at 1. unle ss Ihe stale o f the la1ch has 10 be changed. The applicalion of a 0 t o Ihe S input causes OUlPUl Q 10 g o 10 I . puni"g l he latch in the SCI s tate. When the S inpul goes back to 1. lhe circuil remains in l he scI slale. With bolh inputs a t I. lhe slate o{ Ihe lalch is changed by placing a 0 on l he R ill pU L This causes the circuit to go to the rescl state and May t here e "en aftcr both inputs return to ), T he condilion Ihal is undefined for t hi' N AND lalch is when both inputs are equal 100 al Ihe same lime. an input combinalion thaI should be avoided. Comparing lhe NAND latch wilh l he N OR latch. note thaI Ihe input signals for lhe N AND require Ihe c ompl.me nl o f th0SC . 'al ue! used for the N OR. Because the NAND latch requires a 0 ,ignal to c hange ilS Male. il is referred 10 as an SR 6 -2 I ' -ho< C .., ,, sc, ..... " " " QQ 5 (Sot) Q L r R . ... " . .. 0 R ( Ran) , .)I.<>p<.up- "~ (b) f<m<tioII taI!Io C n GURE6-6 51? U IOIi " ',h NAND G ., )mch. T he b ar above Ihe IeUCr1 designntes Ihe f llellballhe i~puI ~ muSI be in I hei' complemcnl form in o rder to a c1 upon . h e ci rcu it ~ I.Ie . T he OI>er at ion o f Ihe basic N OR a nd N AND laIChe~ .... n be modin~d by PfO.';ding a n additiooal control input .hB! d elerm ;IICl1 w hen Ihe Slale o f l he I c h can b e ch. n~. A n S R lalch wilh a c ontrol inpul 11 st.""'11 ill Fogure 6-7. 1l c onsisI' o f l he basK N AND lalch a nd lWO a<!dilional N AND p Ies. T he control inpul C acLS . . a n e nable . . gnal (QI" I he Ol/><" Iwo illpulL ~ o utpu. o f l he N AND p .es M aY''' t he 1ogic 1 Ie'lel as loog Ihe r onlrol inpul r emaiM a l O. T his is l he q uiekenl c onduioo for Ihe S R IM'e h c omposed o f lwo N AND ga.<$. When lhe conlrol input J oel II> l . i nformation f ,on' Ihe S a nd R in pul!; is allowed 10 affe<: t ' he S R lalch. T he SCI Slate is rcached wilh S - 1. R - O. a ~d C - 1.1b c hange t o Ihe r ese. ""IC. t he in pu," must be S _ 0 , / ( _ 1. a nd C _ l . In eil hcr c ase, "'hen C r eturns 10 0 , t he c ircll it r emains in itJ c urren t . I. te. ContrOl input C - Odi. . bles Ihecircuil SO Ihat Ihe , l ate o f I he ou.p<l! doeo n ot change. regardl~of Ihe values Qf S and R, Mor e.;...e r. wben C - I . nd b olh l he S and R in pllLS a re equ al t o O. (he s ta'e o f l he circuit does nOl change. oondilions Bre ~"cd ill Ihe function I .ble a a:ompanyillg Ihe d iapm. A n undefined $laIC O ttul'$ . ..hen all I hr inpulS a re e qual ' 0 I. T his condilion plac:csO', 0 0 hOIh i npubot the basic S f( l alch.aivin gan undefined $laIc. When l he c ontrol in plll ~ b ack 1 0 O. one c annot conclUSIVely del~'mine t he nexl sta.c, sjnoo n.ese ,,, 0 (oj ' _ _ .ro.v- , , "" , " C H GUKE6-1 SR U leh with Co n. roll np", " "e,"'''. 0/ 0 No'~.n . . ~<0 -0: "-,_ - 0 -1'5< . ... .. 2 48 CHAI'T~R. 6 f S~QUENnAL C IRCUITS 0 t he S R latch sees inputs (0.0) followed b y(l. I). The SR latch with c ontrol input is an impol1ant circuit because o tner lalches a nd Hip-Hops are constructed from il. S omc\imes the S R latch wi\h c onnol input is referr~d t o a . an SR ( or RS) Hip . Oop : however. a crording \ 0 o ur \~rminology. il d oes n ot qualify as a Hip Hop. since Ihe circuit d oe, not fulfi ll tho flip-fl op r equirements p resented in t he next section. D L atch O ne , ,'ay t o eliminate the undesirable undcfined . tate in t he SR latch is t o ens me that inputs S and R a re never e qua l to I a t t he $ame limc. This is d one in I hc D la\ch. shown in Figure 6 8 . This latch has o nly Iwo inputs: D ( data) a nd C (control). T he c omplement o f D input goes directly to the S input, ~nd D is a pplied to the R input. A . long a . t he c ontrol input is O. I he SR latch has both inputs at Ihe 1 level. a nd Ihe circuil cannot change , tale r egardl"ss o f t he value of D. T he D input i . s ampkd when C L II D is I. the Q o u tpul goes to 1. placing the circuil in I~e set slate. I f / ) i\ O. o u tput Q g"'-"5 te> O. placing the circuit in Ihe reset Slate. Th e D latch receives its designation f rom ils a b ili ly t o h old ,Ima il1 ils internal storage. T he b inary information p rescnt at t~e d ata inp ut o f t~e D latch is t ran. ferred to t he Q o utput ,,'he l1 t he control inpUI is e oabled ( I) . Th e o utput follows change. in t he d a ta input, as long a s t~e c ontrol input is e nabled. When t he control input is disabled (0). t he b inary information th~t was present a t the d~ta i nput ~t t he lime the transition o ccurred is r etained a l t he Q o u tput unlil lhe c onlrol ioput is e oahled again. T he D latch in VLSI circuits i$ o ften c onmuctcd with transmission ga les (TG5). as shown in Figure 6-9. T h eTG was defined in Figure 2-35. Th e C inp ut c on trols two TGs. When C - 1. Ihe T G conn ected 10 in pul 0 conducts, aod \he T G connected to OUlpUI Q disconnects. This p roduce, a p alh from input D through IWO M " 1- -r=:O>---';'= iJ.-,-o L J r , -+-- --1 l , ( oj o X o u .p: d;.grom N o clt.>"Il' Q 0 , R. .., Q I, .1>" $<""'e ( b) F u nctioo o ,.bIe F IGU RE6-8 D L. . c h o 6 -3 I Fhp-Fl"". 0 2 49 ,'7 '" -I ro Q ~ v o n GU Rt::6-9 D u ,<b . .i,h Trarumi . . ion G a' e> inverter> to output Q .l1ms. Ihe OU'PUI follow. the dala inpul a . long a . C remains active ( I). When C c hanges 10 O. Ihe 111'$1 T G di"'OllneclS i nput D from Ihe circuil. and lIN: se<;OrKI T G <XmneclS Ihe t wo invene~ a llhe OUIPUI i mo a loop. Hence. Ihe value Ihal wa. presenl al input D a t Ihe lime thai C wen! frorn 1 1 00 is r etained., Ih" Q oulpUI by lhe loop 6 -3 F LIP-FLOPS The stale o f a lalch in a flip-flop is allo",ed 10 SW; lch by a m omentary change in value o n Ihe con lrol inpul. Thi$ change is ca lled a "i88~T. a nd;1 enables. o r lriggers. the flip-flop. The 0 lalch ""ilh clock p ulse. on i l' c onlrol i nput is Iriggered e very lime a pulse 10 Ihe logic-l level occurs. A . long a s the puis<: r emain. a l Ihe active (1) level. any changes in Ihe d ata inpul will change the Slate o f the b 'c h. In this sense. Ihe latch is tT~t1Sp""nt. since i t. inpul value c an be seen from the OUlputS. As Ihe b k>ck diagram of Figure 63 $h o",'S. a sequenlial circuit h~$. feedback path from Ihe OUlpU," o f Ihe fiip-Oo[>$ ' 0 Ihe combinatioo circuit. As " consequence. lbe d al. inputs of the flip-flops a re derived in paJ! from Ihe oulputs o f 11", s ame and o ther f1ip_nops.. When lalches are used fo< l he s torage t ieme nts. a serious difficu lly arises. T he s latc Iransition, o f the laIches s tan as s oon as Ihe clock pulse changes 10 the logiC _I level. The new S1~le o f a lalch may appear a l its o~lp ut while Ihe pulse i till ac,ive. Thi, outp~t i . c onnected to the inputs o f SOme o f the lalches Ihrough a c ombinational circuit. I f Ihe inputs applied to the latches change while ' he d ock pulse is $Iill in Ih e Jogie 1 level. the latche, will respond t o n ..... J /al< "~/ l ie.!' o f o ther l atches i nstead o f Ihe or;g;nalltat~ ""{,,..s. a nd a . uccession 01 c hanges o f s tate instead of a s ingle o ne may occur. The result is an unpredictable . itual ion. since the Slale may k eep changing and continue t ochnoge until the clock r eturn. 10 0, The final sta le de~nd, on how long Ihe clock pulse stays a l le vel logic I. Bec.,,,se o f , his unre li able opermion. Ih e o ut put o f a latch Ca rlnol l>e applied directly o r Ihrouglt combin.tional logic 10 ' he input of ' he sa me o r a nother la'ch when all Ihe lalches a re triggered by a single clock signal. B ip.fiop ci.cuits are Instructed in sueh a way a s t o rIUIke them ope rm" properly when th ey a rc p an o f a !.Cquemial circuit thaI employ" a . ingle clock. 2 50 0 CIIAPTER 6 I S EQUENTIAL C IRCUITS Nore rhar rhe problem wilh (he lalch is (hat it is I ran'parent; A . OOOn as an input changes. shorrly rhereaflu t he w rresponding o urput c hange. 10 m alch ir. TIlis lransparency is what ano,.~ a change 0 0 a lalch o utpur 1 0 p roduce a dditional change< a l o ther latch o u tPUI . .. hile Ihe d ock pulse is a l logic L T h e key t o rhe p roper o pe ration o f Hip-Hops is t o p revent them from being transparent. In a HipHop. b efore an OUlput Can e ilange.lhe p ath from its i npuls 10 ils o ut PUiS is b roken. S o a fl ip-flop cannot "see~ Ihe change o f ils oUlput o r o f Ihe outpulS o f o lher. like /lip-Hops a t il' i npul d uring (h e S<lme cl ock pu lse. Thus. t he new . tiue o f a Hip.nop d epend, only o n Ihe i mmedialely p reuding Slale, a nd Ihe lIip-lIol's d o n OI go through multiple c hange. o f . I.te. T here a re Iwo ways Ihal l alches are C(>mbined 10 for m 3 lIip. Hop. O ne way is 10 c ombine 1 "0 l atches such I hal ( I) Ihe i nputs p resented 10 Ihe lIip-Hop when a d ock puis<, i . p resent control i l' . Iale a nd ( 2) t M s late o f t he flip.flop c hanges o nly when a d ock p ulse is not p resent. Such a circuil is c alled a rnasru-.I"v~ t1ip- H op. AnOlher way is 1 0 p roduce a fl ipflop Ihat triggers o nly during a signal rransirion f rom 0 to 1 ( or from 1 10 0 ) on Ihe d ock a nd Ihat is disabled a t all o ther limes, including for the duration o f t be d ock pulse, Such a ci.-cuit i . S<lid t o b e an ~<lg~. trigge~d /lip-Hop. Next. Ihe im p lern~nlalions o f I hese 1"'0 Hip . Hop Iriggering approach . . a re presemed. I t is necessary 10 c onsider t he SR flip-Hop l or Ibe rna ... lersla .. e triggering a pproach si~ a p roperly<nnslructed 0 Oip-Hop has t M s ame behavior for bOlb Iriggering Iypes. M asterSlave F lip-Flops The m asler-sla"e S R Hip-t\op, C(>nsisling 01 Iwo latch. . a nd a n i nverler, is s hown in Figure 6-10. 11le . ymbol with S. C. a nd R on il is l hal for the S R 1"leh , ,;th c ontrol inpul ( Figure 6-7). " ' hkb is r elerred 10 b ere as a c locked S R lalch. T he 1~ 11 d oc ked S R W eh in ~-;gu re 6 10 is c a lled t he m . .ler. Ihe r ight Ihe .Iave. W hen Ihe clock i npul C is O. l he outpUi o f t he i n"erler is I. T he s l"'e latch is l hen e Mbled. a nd ilS OU1PUI Q is e qual 1 0 Ibe m aster OUipUi Y.The master lalch is d isahled. beca use C is O. When a logic-! d oc k pulse is a pplied.lhe values on S and R c ontrol the value s lored in Ihe m a,ler latch Y. T he slave. bO"'ever, is diS<lb led a s l ong as the pulse r emain. al t he I 1<:".1. b ecause i\5 C i nput;' " 'Iual 10 O. A ny c h.ng es in t he e xterna l , , , , , , , , o , - , , n CU K E6- lO S R Ma<ter Sl"" Flil'""F\op o 6 -JI F~p-Fl"l" 0 251 5 a nd R i nputs change Ihe maSler o utpul Y. bUI c annol aff""l Ihe .la~e OUIPUI Q. Wh e n Ihe puls<: rei urns t o O .lhe masler is disabled a nd is i solaled fn)TTl (he S and R inpUIs. A t t he s ame time. the s lave is enabled. a nd t he current v alue o f Y i . I rans ferred 10 t he o utput o f I he ftip.ftop at Q A ModelSim logic . imu lation illustrating master sla.'. Hip-ftor SR b ehavior i . s hown in Figure 6-11. Initially. all values a re u nknown including the d oc k C. Wh en S and R b olh g o t o O. a nd t he d ock g oes frorn 1 t o O. t he o utput o f I he m aster. Y a nd Ihe o utput o f Ihe sla.(. Q. b olh remain u nknown. s in Ihe p rior value is eff""tively being s tored. 5 is a t 1 wi th R a l 0 to s et tile /l ip. Hop in r esponse t o Ihe next d ock pulse. Wh en C b ecomes 1. Y s ets to l . When C b ecomes O. h e s1a"e c opies t he value o f Y se lling Q 1 0 L A ller S rClurns 1 0 O. Y a nd Q r emain unchanged. s toring Ihe 1 ~alue . hrough t he next d ock ~riod. Next. R be.:<:>mes L A fter t he clock p ulse t ransition from 0 to I . Ihe maSler 1.lch is r esel with Y c hanging t o O. T he . lave latch is n ot affected. be ~" use its C input is O. Since t he m aste r is an internal ~ircuit. its change o f S I.lc is ~ 'I presenled at o Ulput Q. E ven if the inputs S and R c hange d uring I hi. i ntel'lal . "d t he Slate o f t he masler lalch respond'! hy c ha nging, . he OUlput o f t he f\ip-H I ' r emains in ilS p revi""" s la te. Wl>cn Ihe pulse r eturn. 1 0 O. t he " . . ~= :i<HI from the m aSler is allowed to pass throug.h to t he slave. F or t he si mulation e~ample. tl1c ~aluc Y _ 0 is copied to t he . Iave talch making Ihe extern.l o utpm Q - 0, N ote t hat these c hanges a re d elayed f rom the p ul,"" c hanges by g ale delays. Also. t he e xterna l i nputs S a nd R c an change anytime aftcr the clock pul"" goes t hrough i ", n egative tran.i1ion, T hi, is because, a . t he C i npul reach es 0, t he master is d isabled, a lld S and R h. .'e n o effect u ntil the n ut clock pulse. T he ncot sequence o f signal changes illustrates t he " 'one', catcbing"' b ehavior o f t he S R masterslave Hip - Hop. A n arrow pulse t o I o ccurs o n S a t t he " "ginnillg o f a d ock pulse. T he m aster latch respotlds t o the I o n S by Changing Y to I. ' [n c n S goes to 0 a nd a n arrow 1 puLse o ccurs <HI R. T he m asler latch r espond, to the 1 on R by c hanging Y back 10 O. Since I here a re n o f urther 1 " alu es On S o r I I, th e m astcr COl1tinue. 1 0 , tore 0 which is c opied t o t he s lave latch, changing Q t o 0, in response t o t he d ock c hanging t o O. ThUs, t he mas t er latch -caught" b oth the 1 On S a nd t he 1 " " R S in"" the 1 On R was caught c---" '0 Q " , I, " 1,,,,1 " t, too... "I" o n G U ME 6- 11 Log", S imu lation o f a n SR Ma"cr_S Ia\" t. l~ .. Fl i ~ Fl"" l SI 0 C IIII PT ER. I S EQUENTlIIl O RcurTS hm. lhe OUtput Q remained I t O. In g ene",l. t he Mcorrec t Mresponse i , aSii umed to b e tile response 1 0 t he i nput ~al u cs " 'hen the d oc k goes 10 O. So. in Ihi. ca"". the response h appen. to be correct. ahhough more by accident wit h Ihe changing va lu e. in Ihe " raster . For the n e. ! d ock p ulse. a n ar TOw I pu l..: oe<: urs o n S ",,{( ing the mas ler o u tpO! Y to I . T he d oc k I h ~!t s ocs t o 0 a nd t he value I i s t ransferred IQ t he slave latch a nd a ppears Qn Q, [n thi. case. the corr e<: t vn lue o n Q s ho ul d be O unce Q was 0 b do re the d ock pulse a n d botb S a nd H a rc 0 j ust b efore the d ock g oes to O. Since Q e quals 1. d ue to M S catching~ <>n S. t he n,p,fIop is in l be [ w~ s tate. For t he fina[ d ock p ube o f intere'll. both S a nd H b ome I b efore Ihe clock IJOC$ to O. T his a pp lies the InYlilill c ombinalion 10 t he masler [atch making b oth ) ' and Y e qual 10 I. W hen Ihe clock c ha nges w O. I he S H l atd\ w,t h in t he masler sees its inpuls c hange from ( 0.0) 10 ( I. I ). c a us,ng the m a,ter latch to e nt er M u nknown lilate wh ic h i . i mmediately tra nsferred t o th e i nputs o f t he slave which a bo e ntelS a n ullkn own ' Ia tc. T his d emo n strate, t h.t S " I , R _ I is an i n~a lid input com bin ation fm t he SH. mastcrsl ,,e Hi pHop, Now w nsider a seq uential sySlcm w ma iaing many master-slnvc flip-Hops. wit h t he OUlpU IS o f s ome Hip-flops g oin, t o inpUl' o f o lher nip-nops. Assume that Ihe t lock pulses t o all of t be Hip-n0p5 atc synchronized a nd occ ur a t t he same lime. At t he beginning o f e llth d od pulse. s ome o f t he masters t hange " ,ale. but all tbe sJa>'e5 " ,mai n in t beir previous ",ales. This means Ihat lhe nip-llop !.la~.,. a rc still in l heir original . . ate$. " hile l he n,p.fIop masters ha , ,,, ~hansed 10 lhe new states. A fter t he clock pulse returns t o 0, $Orne o f t he Hip-nop tLA~es c hange . ta iC. b ut n onc o f II\e ne,,' states ha~e nn d fcct o n a ny o f t he m Mters until t he next pu l"" , ThUs. t he St ate. o f Hipn0p5 I n a 5ync hron ou. system t .n cha nie si multaneously for the " , me d ock p ulse. e~e n Ihough ou tpUl S o f Ai p.nops a re c on nccted to i npu ls o f Ihe s ame or o ther Hip nops.lltis is p "', ib le because Ihe i nput. affect the state o f t he Hip.nap o nly while the clock pulse is I a n d the new Slate a ppears at tbe outputs. o nly a fter the clock pulse has ret urned t o O. e nsuring that II\e Hipflops a re n t)l t ransparentIU- , eliable "'"'Iuenrial circuli Operalion. all oignalll must J lfOpiple f rom l he outputS o f Hip-nops. through the w mbma"nnal c ircuit. a nd ba<:k t o InputS o f master-slave Hip-Hops. " hile Ihe clock pulse " ,mai n. at Ihe Iogie-O leve l. A ny changes thaI occur at t he inputs o f Hip-fk>p5 a fler the clock pul"" goes t o t he 100000Ilc'el. wh ether i ment ional o r not. af fectth~ Hip . Hop . tate a nd m ay res ult in Ihe storage o f ,n wrreet ,'a lu es. Sup P"' e t hat the delay ;n Ihe combina tiona l cirtui l is s uch tha t S is st,ll changing after the d ock pu lse has g o ne to t he logic ) level , Suppose a lso that. a s a w nseque nce. t he m aster i , s.ct t o I by t he p resence o f S " I. W hen S finally Slops changing. il is at O. in di<:.tinS Ihal tl\e s tate o f t he /I ip-nop " ,. . I1<>l10 be changed from O. T h ..... lbe I ~alue In t be masler. whi<:h " 'ill b e tran,ferre d t o Ihe !.lave. is in e rror. TI>e", a re t "" ronseqllCn<:e5 o f this beha~ior. First, Ihe master s1a..., n 'p-nop is a lso ",f~ n cd 10 a s al"'lJt '~rM Hil""nop..wnce it c an r espond 10 input values that cause a change in stale a nd OCCur a nyti"", d urina ,IS clock pulse. Second. the circuit mu>! be d~.igncd W Ihat combina tional ci",,,;t delays are sh or t cnough to p re"ent S and R from e h "n,i ng during t he cl ock pulse. A f n"stcHlave D fl ip. fl op ean Ix: oonstructed fr om the SI< mastcr . la,'c nip. H by si mply r~placing t he m"5ter SH la tch wit h a master D lalch, ' The result in g op 6-1 I Flip-Flop' , ,- , , " , 0 2 53 Q " o ~' I (;U Kt: N~gotiv~ 6-1Z EdSe-Triggered 0 flip-flop circuit is shown in Figure 6-12. T he resulting circuit changes its value o n the negative edge of lht clock pulse juSt 3S t he m aster., I.,e SK Hipf1op doc:s. H o"cver. lhe D type o f flip-flop does not demonstrate lhe usual pulse-triggered beha,ior. In stead il d emonstrates edge-triggcred b eha,ior. in this case. M gati"e edge-tr iggered behavio r. ThUs. a maste r- slave D flip-flop COfl'tructed as shown. is also an edge_triggered flip_lIop_ E dge-Triggered F lip-Flop A n etlge-Iriggertd flip-flop ignores tbe pulse " 'hile it i . a t a c o nstant le"el a nd triggers only during a Ir"n.sili{m o f the d oc k signal. Some e dge_triggered fl ip_flops trigger o n th e positi" e e dge (0-10- 1 transition). wh ereas o t hers trigger On the negati"e edge (l_to-O t ran' ition) as illust rated in the previou. subsection. T he logic d iagram of a D- type positi"e-lge-triggcred flip _flop 10 b e a nal r~ed in dNail hcre appears in Figure 6-13. Th is flip-flop takes exactly the form o f. ma.ter-sla,e flip-flop. with thc maSler a I ) latch a nd the s lave an S R lat< h o r " D la tch. Also, an in"u te< ;5 a dded t o the d ock input. De<;ause tbe master I,tch i s, D latch. t he fl ip-flop exhibit< edgc-trigg~red r ather than m a,ter . lave o r pulse-triggered behavior. For the d ock input e q u al to O. the master lalch is e nabled and l ranspa"nl a nd fo ll ows the " " v , o ,- 0 0 " v o "IGUK!:: 6-13 l'o\.iti Edge_Triggered D Flip.FIop , o 2 54 0 O lAP'TER 6 I S tQUENT IAl C IRCU m D inpUI ""Iue. The >Ia"e Jalch is disabled a nd holds lhe oIate o f the nip-flop flIed. W hen t he posill~ e dge 0 ttUf1.. Ihe clock ' nput change< 10 I . This disables the masICr lalch 5 0 t hai ,IS ~aluc is fi~ed and enables lhe lalch 5 0 t hai" copies the ""ale o il"" maS ler latch. The sla te o f t he master latch 10 b e ~ Il ihe litate Ihal il present B ltlle posilive edge o f Ihe clod<. "Illll5. lhe beha"ior a ppea", 10 be edgetri~red. With Ille clock inpul C<luIIIO I . the rna. . e r lalch i, di~bled and cannOt change. 5 0 the . . ale o f bolh Ih e m ailer a nd the ,Ja~e remain unchanged. Hnally, when t he c lod input changes from I 10 O. the master is c nabled and begins f,) li ow ing Ihe D value. ijut d uring IIie 1- I<Hltran,ition. the slave is diSllblcd before any change in the maSler can reach il. 11m. . Ihe value s tored in Ihe slave remai", unchanged during I hi, tran si ti on. An a llernalive imp le mentalion is s!vcn in I'rob tern 6 -3 31 1he e nd of the chapter. "a". S tandard G raphic. S ymbol. T he ""andard 8"'phics Iymbols for 11M: diffcrentlypes o I1alch", a nd ",~"ops a re sho>o." in FI gure 6-14. A nip-nap o r lalch IS designated by a rectangular block w "h , - - 0 , I ) " " h I C oo"", D ... , ,' 0 ( .... " ... ( I ) . .. " . ... , , - , , -, - - ~ - n~SR -~>< .fThw.w D 0 ~ U ,.,........ SX (b) - - -, n.1-,~~-~ o U '='-_'-' _ - cdD " '-.st.. . ~ " ~I>' _ L-.J 1. T,v<'cd U ) Edae-1;;,....... Fli.,.flopo o n CU K I: 6- 14 Stand&n:l Grap/IiaI Symbol< for .... , chet and F lip-flop 6-3 f f lip-flop. 0 255 i nputs OIl the left a nd o utputs on t he righ!. O ne o utp ut designate!; the n orm al State Ihe Hip _ nop, a nd Ihe o t""r, with a bubble. de!;ignate. t he c omplement o utput. T he g raphics s ymbol for the S R latch o r S R flip-H"" has i nputs S a nd R i ndicated inside Ihe block. In t he ca~ o f l he SR lalch. b ubb le!; a re a dd! ( Q l he inputs ( Q in<licale thaI s ell ing and reSClling occur for O-Ie\'e! in put.<. T he g raphics symbol for t he D latch o r D flip-nop has i nputs D a nd C indicated inside the block. Below e ach symbol. a descriptive (itle. which is not p an o f the symbol. ; . given. In the lilk$. J L d enotes a poo;;itive pulse. 1.1" a n egati"e puls(\ I a poo;;; _ tive edge. a nd 1. a n egative edge. Triggering by t he 0 level rather than the I level is d enoted OIl t he latch symbols by a ddi ng a b ubble at the triggeri ng inpul. T he master_slave is a p ulse-triggered flip _flop a nd is indicated a , such with a righI-angle symbol c a ll ed a P 05fpo"ed O Ulp'" indicator in f ront of the OUlpUI~ T his . )'mbol shows Ihat I he OUlput signal c hange. at I he e nd o f the pulse. 1 0 d enote I hat the master-1llave flip-fl"" will resp<lfld to a n egative pul~ (i.e" a pulse 10 0 with t he in:>cti"e clock value a t 1), a b ubble is placed OIl t he C in pul. To d enOl. t haI the e dge-triggered flip-flop r espond. 10 a n e<lge. a n a rrowhead _like symool in front o f t he I <:!tu C d esignates a dynamic i np"' . T his dynamic in,lie,,'or . ymbol denotes the facl Ihat the n ip-nop r espond, t o e dge l talUition, o f t he i nput clock pulses. A b ubble outside the block a djacent t o t he dynamic indicator d esignates II nega _ i'c...,d~ ~rMsi_ion for triggering . he cireui'The a bsence o f a b ubble d esignates a positivc -<:dge tra1\<;iti"" for triggering. Oft eo. all o f t he flip-Hops lIS<'d in a cir~uit a re o f t he J ame triggering type . uch as positi"e--edge t riggered. All o f t he flip-Oops will t hen c hange in relalion \ 0 t he U me cloc king e~c n'- When u$ing nip_nops having different trigger in g in t he J ame s cqucn l inl circuil . one may 'till wi.h \ 0 n il". all o f l he fl ip_ nop o utputs chaQge relati~e to t he J ame d oc ki ng e vent, T hose Hip-Hops t haI b ehave il\ a manner o pposite from Ihe adop_ed p olarity lransilion can be chan.ged b y llle a ddition o f i nverte", t o t heir clock inputs. A p referred pfOcedure is t o p rovide both positive a nd negative pulses ffOm t he m aster clock g enerator that are c arefully aligned. We a pply positi"e pulses t o poo;;itive-pulsc,riggered (master-,Iave) a nd n egati,eedge"iggered n ip-flops a nd negative pulses t o n cgati,'e-pulsctriggcred ( m.".r-sla,'e) a nd posi'i"e-<:dge-lriggered flip-Hops. In this "'"y. all flip _ nop Out pu lS will c hange at the J ame time. Fi nally. ' 0 p revenl specific timing problem . . s ome d esigners u"" flipnops having d ifferenl t riggering (i.e .. both positi~e a nd n egalive edge-triggered flip-lIops) with a single clock. In thesc cases, nip-flop o utputs a re pU.--p<:I'CI) made 10 c hange a t di fferent times. In , hi. lexl. i t i . a ssumed that a ll nip_Hops " rc o f the posili"e_edge_triggere d t)'jX. unless otherwise indiealcd, Th i' p rovides a uoiform g raphics symbol for the nip-Hops a nd c onSiStenltiming diagram .. Note t hat t here i . n o i nput t o t he D nip-flop ~hat p roduce, II " no c hange" c ondition. This condilion c an b e a ccomplished e ither by disabling Ihe clock p ulse. o n t he C input o r by leaving ' he clock pul~s undislurbood an<l c onnecting t he o ut put back i nto the D i nput u ,ing a mu ltip lexer when the s tate o f the fli p-flop must r emain t he !-lime. T he technique I hat di sable. d oc k pulses is referred to a s c lock gating. T his le<:hniquc 1)'pica~I)' u~s fewer g a'es a nd ""'es power. but is o flen a mided b ecause t he g ated clock pulse. i nto the nip-flops a re delayed. The delay. 0( 25 6 C HAI'TEIl 6 I SEQUEN11AL C llI.Currs 0 called d ock skew. c au"," galed clock a nd n ongaled d ock flip-flops 10 c hange a l differenl limes. This can make Ihe circuit u nre liable. , ince Ihe OUlp ' lIS o f some fliplIops may . e ach olhcrs ...hile t hei. inputs a re itill affecling Iheir Slate. D irect I nputs Flip.nups oflcn prov i d~ special inpulS for s elling a nd r~setting Ihcm asynchro-nously (i .e .. independent ly o f t he clock i nput C). The inp uts Ihal asynchronously set the Hip-flop ~Te called direct . et. o r p ",et. T he inputs t hat asynchronously re. . t the flip-llop a re called direcr US~r. o r d M . A pplication of a logic I (or a logic 0 i f. b ubble is p re. . nt) 10 l!lese inputs affeCls Ihe Hip-Hop oUlput withoul lhe use o f Ihe clock. When po .... er i . t urned on in a digital system.lhe Slales o f il> Hip-H"", can b e a nything. T he direct inputs a re u . .ful for bringing Hip-flops in a digital sY'tem 10 an initial , tale p rior t o Ihc normal d ocked o p"ralion. Th e I EEE standard graphics symbol for a posilive-edge-triggered 0 Ilip_lIop wilh direct set a nd direcl resel is . hown in Figure 6-15{a). T he nOlations. C I and I D. illustrate COfltrol dependency. An inpul labeled Cn. wlotre " is any number, controls a ilihe o ther inputs s larting with the n umber I I. In Ihe ligure. C I c ontrols input 1 0. S and R h a,'e no I in ffO<lt o f t hem,and therefore. the)' a re n ot controllC<.! by the clock a l Ct. T he S and R inpUis have circles on I he input li nes t o indicate t hat they a re active at the Ingie.{) level (i.e .. a 0 a wlied wi ll result in the set o r reset ac ti on). The function table in Figure 6-15(b) specifies the operation o f the circu it . The I i. . t t hree ro ..." in Ihe l able se.e.:: i1y tbe o peration 0 1 the direct i nputs S and R. T hese inputs b eha"e ~ke N AND S R latch inputs (oce Fi gur. 6 -6).operating independently o f the d oc k. a n d a re t herefore a synchronous inputs.. T he last Iwo rows in the function lable specify Ihe c locked operation for value. o f 0 , T he clock a t C i . shown with a n u p.mrd a rrow 10 indicale that the ~ip.flop is a p ositive.edgetrig. gered type. The 0 inpul effeCl. are controlled by the clock in the usual manner. Figure 6 15(c) s hows" less formal symbol for the positiveedge-triggered Ili p. Hop wilh dire<:t . . t and reset. T he positioning o f S and R at the t op and bottom of the symbol r ather t han On the left e dge implies that resulting output changes are not c ontrolled by the d oc k C. ,, , , , - '"" , ( 0) G""pl"" - Q ~O , , , ,, ,,, ,, ,,, , ,, , , , .,....boJj 0 F IGURE , A QQ - Q l Jot;kf .... J . ( b) F."","", t able - T (c) !>impl.i fied Symbol 61~ D ~l i l'""FIop wi,h >,, O;,ect Se, 'old Reset 6 -l/Flip-Flopo 0 2 57 Flip-Flop Timing T here a re timing paramet~ n lI$SOoOiated with the Qfl<'rati(ln o f both pulse-lriggered a nd edge-tr;gger~d flip-flops. Th~se p arameters ar~ ilJustrat~ d for a ma"er - sla.~ S R flip-flop and lor a negative-e<Jge-triggered D Hip-flop in Figure 6-16, The p "rameur'$ for th e po:s i tive-edg~_tr iggered D flip_flop are the same except that t hey ar~ r efere~d t o the " ", iti ve clock edge rather Ihan Ihe negat ive clock e<lge. T he timing 01 the response o f flip-Hop 10 its inpuls and d ock C m usl b e t aitn into a crount when using the flip-fk>ps.l'or b oth flip-flops,lhcre is a minimum time calJed the .~t"p time. t. . for which lhe S and R o r D inputs mu.1 be maintained a l a coDMant value prior t o the occurrence o f the d oc k transition that causes the o utp ut 1<:> ~ h "nge. O therwise. t he masler oo uld b e changed e rro neously in the case o f the master-slav" flip-flop o r be at an intermediate value a t the time the sla.'c copies it in t he case o f Ihe edge-triggered flip-fl op_ Similarly. then: is a minimum time calJed the hot.1 ljme. t for which the S and R o r D inputs must not change a fUr lhe application of the clock transition thaI causes Ihe o utpul 10 cha nge_Other.;ise. Ihe masler mighl respond 10 the inpul change and be changing a llhe time the slave latch OOpiC5 it _ In addilion. there is a minimum d ock puis< widlh I... to r--. . . "' . . . . c ---.J SiR _ I' , h::!.-I QI==========~=lI~~t=====J [ ( b) Ed&< -tri ucrl (. ." , ' i ve . .,.e) o f lGURE6- 16 Flip.flop Timmg Parorne ten 2 58 0 C H AI'T ER 6 I S EQUE.'ITlA L C [RCUITS I msure Ihal [he m asler Ita< lime e nough [0 caplur<: Ihe ;npul values c orrectly, A mong Ihese p aramelen. Ihe o ne Ihal differs m o.l b elween Ihe pU~.lriggere<! and e dgNriggcred Hip . Oops i Slhe ~IUp lime as shown in Figure 6-16, T he pulse Iriggered ni !>"ftop h as ils setup time e qua l 10 lhe d ock pu~ widlh. whereas Ihe sel up l ime for Ihe e<lgeuiggered nip nop can be much smaller Ih an l he d ock pulse widlh. A s. consequence. e<!ge.triggering Icnd< 10 pr()Vide faS lcr de~igns s in ce Ihe Hip ft op in PUIS can change l aler wilh respect 10 Ihe upcoming Iri gger in g d ock e dge , T he pTOpI1!!aliOH ,J~lay t ima tl'll1. t eu. OF 'pd o f Ihe fti!>" Oof'S a re defi ned . . Ihe imerval belwoon Ihe trigge ring clock edge and the . Iabi lioalion o f the 0 011'01 t o a new value. ' Ibese limes a re define<! in Ihe same fashion as Ihose for an inve rt er e xcepllhallhe valu,," arc measured from Ihe lriggering d oc k e<!ge r alher Ihan Ihe inverter inpul . In n gure 6 -16. all o f Ihese paramelers a re d enoled by rf'. and a re gi"en mi nimum a nd maximum values. Since Ihe chan gCll o f t he ftip.ftop OOlpuis a re l O b e se paraled from the c onlrol by t he fti!>"ftop input s. t he minimum propagation d e lay time s ho ul d be longer I h.ll the hold time for correCt o pera tion. "th ese a nd m her p mamelcrs a re specified in m anufaeturers' d a ta books for specifIC integra ted "i",uit proJucts. Similar timing p arameters can be defined for latches and d irect inpul$. ",ilh a<idil;nnal propagat;nn delays n u<led 1 0 m odellhe u an.parem b eha"ior o f latches. 6 -4 S EQUENTIAL C IRCUIT A NALYSIS ' lbe behavior o f a sequ~n t i"l ci r~ u il is d elermined from th e in puls. o utputs, and present slale of the ci",uit. The o utputs and the next slate are a fu nction of the in p ulS and Ihe prdoCnl Slate. T he a nalysis o f a sequemial d rcuil COflsislS o f o btain ing a . uitable descriplion Ihat demonSlrates th e t i"'" S tquence o f inputs. OUlputS. a nd s , ates. A logic diagram i . rerogni~e d a s a ~ynchrono u s seq uential circuit if it includes fIip 'fIops with Ihe clock inputs driven directly o r indirectly by a clock sig nal a nd if Ih e direct selS a nd reselS are unu sed d u ri ng the norm al funct ioning o f Ihe circuit. The fli pOops may be o f a ny type. and the logic diagram m ayor may nOi include c ombinat ional gale'$. In this section. an ~ I gebr.ic rcpre>;ent.lion for spe<;i fying the logic d iagram o f a s equential circuit is given. A , 'ate table and Slate d ia gram are presenled that d escribe Ihe b ehavior o f Ihe circuil, Specific u ample s will b e used Ihroughout Ihe discussion 10 ill uslral e the varimrs proc~ures. Input Equations T he logic diagram o f a seQ uen tial circu it consists o f ftip f\ ops and. usua ll y. combi..a. tional ga tes. T he knowledge o f I he type o f fli p.f\ops use<I and a lisl of Boolu n fu ncl ion~ for Ihe combinational circuit provide all the information needed 10 d raw the logic diagram o f the sequemial c i",uil. T he p art o f the combinat ional circuit Ihat g enerate. Ihe Signals for the inpuls of flipftops c an be desc ri bed by a set of Boolean f UIIClions c alle<! flip flop i~/"" e quflti",u. We "'ill a dopl Ihe com'cn tion o f using Ihe flipflop inpul oy mbolto d enote the ftipftop input ",! ual ion var i.bl e and using Ih e na me o f t he fIip.ftop OU lput as Ih e subscript f or the variable. From th is e>ampie. it b ecome, apparent Ihat a Hip-Hop input e quation is a B oolean expression for a combinational eircuil. The subscripted symbol is an o utput "~riable o f the combinational circuit. l bi s o utput is always oonnectcd to the input o f a Hipflop-Ihus the name -flip.flop input "'luat;':m. The flip-flop input e quation, constitule a convenient algebraic expression for specifying the logic diagram o f a s equential circuit. The)' impty the t)'f>e o f Hip-flop from the letter symbol. and they lull)' spe<:ily the c ombinational circuit Ihat drives the flip-flops. TIm e is nOi included e~plicitly in these equat io n-. b ut is implied from the clock at t he C input o f the flipnops. A n examp le o f a s eq uential circ uit i , given in Fi gure 617. T he circuit has t ,,o D-type Hip-Hops, an input X. and a n o utput Y. It c an be specified by Ihe following equalions: D. . ~A X+BX Y ~( A+B)X T he ~nt two e quaI;"n, a rc for n ip-flop i npul . . and Ihe Ihird equalion specifics Ihe o utput Y. N ote Ihat l he input e 'luation. use Ihe symbol D. which i . the s ame as Ih e input symbol o f the flip-flops. T he sut>scripl' A alKl B de!lignale Ihe oUlputs o f the respe<: l ive flip-Mops. 0 C "C ~ V a f lC lJ5I[ 6-17 E xampk o f. S equential Cireui, , , 2 60 0 C HAPTE R 6 I S EQUENTIAL C IRCUITS State Table T he functional r elationships a mong t he inputs. o ut puts. a nd Hip -Hop s tate. o f s equenti.1 circuit can b e e n umerated iTI a slale mbl~_ T he , ta te table for the cire ~ it o f Figure 6-17 is s hown in Table 6-1. T he table Con$ill\ o f f our ,"-""tioTIs. l abeled pre.oem ' lale . " 'p"l, " exl Sltlle. a nd , ,!liP''', T he p resenHlate " "'tio n sho ws t he s ta te s o f fl ip-flops A a nd I I a t a ny given t ime I . T he in put section give, each value o f X for e ach p ossible present stat~. N ote that fo r e .ch possible input c omb ination, e ach o f t he prese ~t s tates is r epeat ed. T he next-state " "' tion shows the . tates o r the Hipft ops one d ock p eriod l ater. a l l ime I + 1. T he o ut put sectio ~ giYes the value o f Y a l t ime, for e ach c ombin otion o f p resent , tate a nJ i" pul . T he dorivation o f I"le lable c onsim o llirst listing all posoible bi M 'Y combinations o f p resent state a nd input,- In n blc 6-1, t here a re e ight b inary com bi na_ tions. from 0 00 10 I II T h e next-state values a re t~en d etermined from the logic di~gram o r f ro m the Hip-Hop input c<.]u ;ot ions. F or a D flip-Hop. the relationship A {, + 1) . . D AI) holds. T hi' m eans t hat t he nexl st .le o f llipHop A i . e qua l t o t he pre sent value o f i t. i nput I ). 1 bc value o f the D i nput i . specified in t he ni p_ op fl input e q uation ", a f unclion o f the present st .l e o f A ~nd B a nd in put X . There_ fo re. t he n ext Slate o f fl ip_nop A m ust s atisfy l he e q uation A (I + I) - DA - AX + BX ' rbc ncx!-sw tc se<; tion in the s tate t able und er c olumn A h as thr ee 1 ', w here t he present state " nd input val ue satisfy t he c onditions ( A,X) _ II { )T ( H.X) _ 11. S im il"rly. the next Slate o f nip_nop I ) is derived from l he i nput e quation B (I + l ) - D H - AX a nd is equal to 1 u hen l he p resent Sla te o f A is 0 a nd input X is e q ual 10 1 T he o ut put c olumn i. d erived fTOm t he oUlput e quation Y _ AX+B X o T ABU: 6_1 S' a' e Table for C huit o f .1gure 6_ 17 P. ... nl State " " " " , 0 " , 0 0 Input , 0 , 0 " " Next State , 0 " " , " " " " " , " 0 Outpul , " , " , 0 0 " 6 -4 I o St.t~ ,-, , , " , " " " " " a tll ie , 0 261 TA 8 LE 1>.1 T " . .. n;m ~ n al " , " S<qu<nti.J e iK";' Anoly'li. T able ror Ih~ ,-. , - , , , ,, , , , ,, ", "" C lrroil in F ig"" 1>.11 ,-., ,- , , , , , , , , " " T he , me t able o f a ny sequenlial circuil wilh D-Iype Hip-Hops is o bl ained i n Ihis way. In general. a sequenlial circuil ,,<jlh m n ip .Hops a nd" inpulS n eeds 2~ ' " r(>WS in Ihe Stale table. T he b ina!)' n"mbeTll from 0 I hrough 2"'+0 - I a re l i,led i n I he c ombined p resent-s lal e a nd input oolum ns. T h e n exl slale seclion has m w i umns, One 10.- each Hip-n<.>p. T he b inary values for Ihe n exl Slate a re d e rived d irectly from t he D flip-fl<.>p i nput e<jualioM. T he o utput seclion h as a s m an)' 001 umns a s I here a re OUlput variable<.. Its b inary " alue s ~re d erived from Ihe circuil o r from Ille B oolean f unclions in Ihe s ame man ner as in a t ruth l able. Table 6-1 is o ne-dimcnsional in the sense t hai the p r=nl s latc a nd in put c ombination. are c ombined in lO a s ingle column 01 o ombinal ions. A Iwo-dimensional , tale lable having Ihe p r=nl s late laoo.lalcd in Ihe left oolumn and Ille inpulS tabulated across Ihe lop rOVl' is also frequently us.:d. '[lie nextSlale e mri.,. a re m ade in e ach cell o f Ihe lable for Ihe p resenHllate and i nput oombinalion OOf"'sponding 10 I he localion <.>f Ihe ""IL A similar Iw<.>-dim<:nsiona l I .ble is used for Ihe OUlPUt!; if Ihey d epend u pon lhe inputs. Such a s lale l able is shown in Table 6-2. S equenlial circuit!; in which Ihe outputs d epend o n Ihe ' ''puts. a s well as 0 1' Ihe slales, a re refeTT~d 1 0 a s M~i1ly m o;le/ circuil>. Olherwise. if the OUlputs d epend only on Ihe ' Ial"" l hen a o ne-dime nsion al c olumn suffices. In this case, l he circuit!; are ref~rred 1 0'" M{}()re " ,odd ~irouil~ E a<h m odel is n amed aft~, i l' <.>riginaIOT_ A . an example o r a Moore model circuil. suppose we want 10 obtain the logic diagram alld stale table o r a " 'l""nlia[ cirruit lhal is sp<:cifle<l by lhe lIip.1\op inpUi e qualion DA - A ffiXffiY a nd OUlput e qua li on Z =A T he DA symbol implies a D -Iype Hip-Hop w ilh OUlpul d esignaled by Ihe l ener A ,[lI" X a nd Y v ariables ar~ l aken " " inpul . and Z a s Ihe o ul pu\. -n,e logic d,agram and Sla te table 10< this ci,-cuil arC shown in FigUf~ 61~ . T he . Ia te , able has o ne c olumn for t he p resent , late an d o ne o olumn fOf Ihe inputs. T he n exi , Iale a nd o ut put afC also in s ingle columns. T he n exl Sla lC i . d erived from Ih~ Hip .flop i nput 2 62 0 C HAPTER 6 f S EQUENTIAL C IRCUITS ( b)Sl>'" M . , o FIG URE: 6 18 Logic Di.grom . nd Slot. Tabl. for D A - AffiXG! Y e q ual io n "'hich spec ifi~, a n odd funclion. (See Section 2-8.) The oulp Ul co lu mn i, simply a c opy of lhe column for t he presentstale variable A . State Diagram T he information available in a statc table may ~ represented graphically in the form o f a s tate di,gram . ln this t ype o f diagram . " Slate i. represented by a circle. and Iran silions between states are indicated by directed lines connecting the circles. Examples o f st"te diagrams are given in FiguTtl 6-1~. Ftgure 6-1 '}(a) shows the state diagram for the sequenti,l circuit in Fi gure 6-17 and ils stale table in T ,ble 6-1. T he stale d iagram p ro, ides the same information ", the state table and i< obtained d iTectly from it. Th e binary number inside each circle identifies the state of the f1ipHops. For Mealy m odd circuits. the directed lines .r~ labeled ",;th two binary n umber>; separated by a 'lash. T he input value during Ihe present stale pre<:~de, the , lash, and the value following the s1a sb gives [he outp ut value during the pre""nl state Wil h the gi"en input applied. For exam ple, the directed line from state 00 to , tate Ol is labeled l,u. meaning lhal when the ""quential circuit i, in the p ,ese n! 5tateOO and [he input is 1, the o utput isO. A fter the next clock transition. the cin; uit goes t o the next state, (11. If the inpul changes to O. then the outpul becomes 1. but if th~ input remains a t L the o utput Slays at O.l 11 is infonnalion i, o b tained from the state diagram along th e two directed 00 "' "' ,.,@-'''--< 01. 10 OO"I~IXl"1 .., ,., o 0 1.10 FI GU RE 6-19 Stale D ,woms lines e manating f rom t he ci",'" wjlb s tale 01. A dirl'Cle<l line c onnecting a c ircle wilh itsclf indirates Ihat n " change of slate OC<:u~ T he " 'He d i.'gram o r F igure 6-19(b) is f or t he . .,quc1\!;al d rcuil o f F igure 6-18. I lcre. only o ne fl ip-flOfl wilh tWO s laies is .,.,.,.;le<!. T here a re ' '''0 bina ry inpulS, and t he " ,,'PUI d e pe nds " "I)' o n t he <tale o f t he flip.flop. For stICh a M oor e model circuil, t he slash on t he d irected tines i . rK>I included. since Ihe O Utput. d epend only on the 518'" a nd n ol o n I he i nput value:.. Inst ead. t he o utput i. i ncluded u nder a s lash b elow t he , 'ale in a T here are ,wo inpUI C(Kldilions for each , Iale tran<ilion in {he diagram. a nd they a re separated by a comma. When t here are t WO i nput , ""iables, e ac h SlalC m ay ha, '. u p , ,, ( our d i rc.olCd l ines c omi n g o ul o f I he c orrespond i ng circle. <i,"'. depending upon the nu mber o f states and the next o',, 'e for c ach binnry combination o f thc input valU<$ T here i . n o d ifference between a sta le table and a , 1.le diagram, exccpl for their m anner o f r epusenlalion, The . Iale l able is e asier 10 <lcrive f rom" gi'-en logic diagram a nd inpul equ.lion~ T he . Iate d iagram follows dire<:tly from Ih e . Ia te lable. T hc sl8le d iagram giVC!l a piclorial view of state I ran,itiom ami i. the form I1Ior e sui table for human i nterpretalion o f I he o per alion o f Ihe drcuit. For exa mple. the ' tatc d iagram o f f igure 6 1'l(a) clcorly ,how< Ihat, starti ng at state 00. the o Ulput is 0 as long as Ihe in pul sta)'s al I, T he f "'t 0 inp ut a her a m ing o f I ', g i"e. a n o utpul <.>f I and send~ the circuit back 10 the inilial s tate o f 00. The state d iagram o f f igure 6-19(b) shows that the circuit .tay~ at a given s tal e as long as the 1WO i nputs h a," Ihe same "alue (00 o r I I). T hcre is a state transition b et"'een the Iwo , tate. onl y wh en the twO inputs a rc diffe ren t (01 <0 ,. 10). S equential C ircuit T im i ng In add it ion t o a nalyz in g the f un ction <of a circuil. it is a lso important to anal)",,, i t' p c rformance in terms of the maximu", i"rUl'IO~Ulrm delay a nd the t rnui,,"'m d ock fr~q'wl<'y.f. ., a t which it can o perate . f i rst o f all. the clock frequency is j ust ' he inverse o f the d ock pcriod '. shown in Figure 6-2t1 S o. I he maximum allowable clock frequency corr~. . p onds t o the minimum allowable cloek perioo ' ,r To dc!CT_ mine how small we can make Ihe clock period, we need to delermine Ihe longe.t 2 64 0 C HAJl'TfJI. 6 I SEQUENTI AL C IRCUITS C~ I J-'"'+~ ' I ' ~+ o " IC U KE (,,10 ! ;equen,i.1 O ,oui,' l1 rnin8 P n.mc'ers d ~lay f mm the t r;wring e dge o f l he clock t o the n extlriuerin, edge Qf the clock. 1l>c5c delays are measured o n all such paths ,n the c irw't dovoll ,,' hie-II c ha ngin, sig. n ab f""'.'9-Il'ue.. Each o f these p.1lh I klays " "" IlI rtt component:>: ( 1) a n ip-nop ~ .. on d e la Y.Ip4.FT-(2 ) a c ombina" OfIal I .lklay .lIrough.he c ha ,n o f g a.n along . he p ath.'.... C ID.I . .. a nd ( 3) a f1 ipfIop SCIUP time.l~ A s a signal dian&<, propa . gaiL . d o ",," ' h e pa.h. i l is dela)'ed sOCtt$$ iv c ly by a n amouILI e {fual.o each of . h= . delap . N o.e that we ha,'e u:ICd ' ''';' inslead o f the mOre d e'"iled ,a lue .. '",-" . nd tF'!IL.' for bolll the ft ip -ft ops and C Qlnbina'ion.llog ic g ale. to si mplify . he delay cal culations. Fi gure 6-20 s ummaril.c' the d elay picture for b ol h Ih e edge- trigg,,~ d a nd p uisc''''ggcred flip.flops. A hcr a I)()!: ,tivc edge on a clock. if a H, p.t\op is ' 0 c h a nge. ils <lU'PUI changes a t time ' "u... a f.er Ihe d oc\: edlJ". 'l'his cha nge e nt ers t he c ombinational logic p a.h . nd must propagale do..-n the p ath 10 a fli p-flop i nput This re{fUirCl a n a ddi tional lime. ' ....COMB. for t he SIg na l change 10 r each l he s ea)nd m p . nop. Finall y. before Ihe <>ex. p osil;"e d ock edge . his c hange " '...., b e he ld On ' he f tip.""" , npu' for s e lUp .im<" I~ This p aill . 1'F'P1'1' a . well a . o lher possible paths are iIlu.lrated in Figur~ 6--21. F or p aths p, ~ ..,. d riven by p rimary inpuli, ' pd.fl' ji r~placed by I ;. " 'hieh i$ the late<t . ime 111.1 the '"Vul changes a fler Ihe positive d oc k edge. For a f><1 th 1'.... ,0lIT driving primary QUl put S. ', i . replaced by t. . ,..hich "' Ihe latest . ime th3' Ihe outp ut i . p ermilled to c h~n ge prio r 10 the ncxt d ock edge. Fi nally. in a Mealy n.odel circuit . c omb, nat ional palM from in put 10 OUt PUI . / 'u<,our. t hai uoe o o.h I , a nd ,~ can a ppear . Each pal ll " "" a i lack lime. , _ Ih e c stra time allowed in the clock period b eyond Ihal rC<luircd by t he p a.h. From Fi gu re 6- 2 1. h e f ollo,.,ng C<lua,ion for a pa.1I o f .)'pe P W.fl' result>:: I I...... .. ( lpl J'f' '' ' pI.co. 'B . . I ,) In o rder 10 guara n,ee Ihal a changing vulue i . caplu r~d by Ih e r ej"ing Hi p. Hop. 1.-.. m U be great er thnn o r " 'lualt o ,.c ro for all of the pa.h" Thil req uire hat . St ' . ~ r na. (lpo1FP " ' COM"" t ,) ='..- 6-0 I Sequ<n"'" c;..,..;, A naIpo. C 2 65 , -::, , , '" r ,/ "" ; ~ / c n cu lu: 6-2 . Sequentia l Ci",u" T1minB p .,In w here (he m uimum i , t aken over all p a,hs down ... hieh signals propagn'e from HipHop ( 0 m p _ fk>p. T he n~XI e xample presents "'p..,..,ntati,.., ""leulalion, f or p alh. P ITW t:XAM I 'U; 6-1 C....., k ~riod . .. d ~'re"uenty C .kuboliom SUPP""'" t ll a! all nip - n~ us<:d a re (he sa me ~nd ha,'e I,.. 0.2 " " (nan~nd " 1O-9 se<:onds) and I, " 0, 1 ns. T hen t he l onge'l pm" b<ginning a nd e nding w i'h" /1;1' flop will b e t he pa th ... ilh Ihe largc.t r..... n >M H- Further. , uppose thnt t he I"rge", I""CO'>t8 i , 1.3 " " and that I~ has ! xcn s el to 1,5 n s. From Ihe p revious equalion for ',.. . .'" c a n write 1.5 lIS ~ I,.... .. 0.2 .. 1.3 . . 0.1 _ I""", . . l.6ns S oh;ng. we h a,'e , _ . ~ O.I ns.5O Ih,s value o f I , i , t oo . mall. In OO'der for I,.... t o b e g rea,er . Mn o r e qual t o z ero 100' t he I """". p ath. I . ~ I r-- ~ 1.6 liS. T he " ,;uimum fr equency f ...... 111.6 n s ~ 6~ M Hl ( mcg.tIcnz = 11I""},,,1a per ..:<:Ond). We note t hat , if 10 is t oo large ' 0 meet Ihe circullipecificatio ns. we mus, either e mploy faslcr logic o r c hange t he circu il delign ' 0 r ed uce t he p rohlc malic 1',,11, d elays I hrough (he eircuil while , I ill p erforming the dC$ ircd fu nction. ""I" 266 0 CHAPTER 6 I SEQUENTIAL ClItCUITS [[ is i nler e' ting 10 nOle t hai Ihe hold time for a fl ip-flop, I,. d oe, nOI a ppear in Ihe d ock period equal ion , h r ciales 10 a not her liming c onslraint e q ual ion d ealing wilh o ne o r b olh o f I WO specific sil ual ion~ In o ne case. o utpul c hanges a rriw at thc inp ul s o f o ne o r m ore flip-flops 100 soon . In I he o ther case. the clock signals reaching o ne o r m ore fl ip_ fl ops ore s ome ho w delayed. a c ondition r derted 10 a s clock ,l<ew. O ock s kew also c an affect Ihe m a,im um clock f req uency, Simulation Sequ ent ial circui l simulalion involves iss u e. n ot p resent in c omb inalional circuits. Fi~1 o f all. r ather than a s el o f i nput p alterns fo r which thc o rder o f a pplicalion is i mmaleriaL t he p allcms m u,t bo a pplicd in a s eq uence, This s eque nce includes timely applicalion o f inp ul p atterns a s we ll a s cl ock pulses. S econd. I here m ust " " s ome m e ans 10 plaC<:! t he circuit in a known s late . Realislically. initia li za ti on t o a kn own s late is acco mp lished h}' a pplicalion o f a n initialization subsequence a l Ihe k ginning o f t he s imulation. In Ihe simplest case. thi5 subsequence is a re se l signal. For flip-flops lacking a circuil r eset ( or s ct).a l onger s equence typically co nsisting o f a n inilial r eset followed by s eq uence o f n ormal input pal1erns is re<:juired, A si mu lator m ay also h ave a m ea n. 01 s elling t he initial stale wh ich is u scfulto a void long seque~ces Ihat m ay b e n eeded t o get to a n initial s tate , A side from g elling to an inilial state. a t hird issue is o bserving I he s late 10 veri fy rorre.orness. In s ome circ ui ts. a pplication o f a n a ddit iO M I s equence o f inpu t' is r equired to d eterm ine Ihe s tale o f t he ci rcuit at a given point, T he <imp lest allernative is t o s c i u p the s imulation SO t hat the s tale o f Ihe circ ui t can be o bse rved d irectly: Ihe a pproach 10 d oing this v aries d epending o n Ihe simu lator a nd whet~er o r n ot t he circuit r omains hierarchy. A c rude a pproach that works wilh all sim ul alors is 10 a dd a circuit o utput with a path f rom e ach s tate variable signal A final issue to b e d ealt with i ~ m ore d etail is t he timing o f a pplication o f inpUIS a nd o bservalion o f o utputs r eialive to I he a ctive clock e dge. Initially. we discus< t he l iming for i,,"C1ional simulation h aving as its o hi""li,'" d etennination o r , 'eriflcation o f the funcl ion o f Ihe circuit. In functional sim ul alion. c omponenls o f t he circuil have no d elay o r a " cry s mall delay. Much m Ore c omplex is liming simu lalion i~ which Ihe circuit c lement' h ave realistic d elay. a nd v. . ification o f t he p roper o peratio n o f t he circuit in t er m, o f t iming is t he , im ulation o bjective. S ome simulstOT$, by default. use a ,'ory s ma ll componenl delay for f unct ional simulation so t hai Ihe o rder o f changes in signals can " " o bserved p rovided that l he lime scale used for display is small e nou gh, S uppose t hat t he component delays and Ihe s elup a nd hold time, for flip-flops a re a n 0 .1 n s for such a simulation a nd t hat Ihe longest delay from posit i" e clock e dge t o positive d od: e dge is 1.2 ns in }'our circuit. I f you ha ppe~ to use a d ock period o f 1.0 ns for }'our simulation. when the result depends on Ihe longest d e lay. t he simu la tion resulls will be in error! S o for functional simulation with such a simulalor, e ilher a lODger d ock period should k chosen for Ihe simulalion Or t he default d e lay n eeds to " " c hang"" by Ihe user t o a s maller value. I n a ddition t o Ihe clock p er iod. t he time o f a pplication o f i nputs r elative 10 t he positive clock e dge is i mportant. F or f unctional simulation. t o allow for a ny sma ll . d efa ult c omponen t delays. t he inputs for a g h'en clock cycle s hould be 6 -51 S<q""n ,"1 C m ui, I k';g n I 0 2 67 I I ,- , , , " St ot . , " o I H G URE 6-22 S;mulalion T,ming c hanged well b efore I he posili"c d ock edge. pTcfcTably e.," y in Ihe clock cycle while Ihe d oc k is s(i ll ;I I a I value. ' l1 \i s is also an a p propriale lime to c hange Ihe resel signal values t o insure I hal Ihe re SCI >;gn,,1 i. c ont rOlli ng Ihe Sla te r ather Ihan lhc d oc k e dge o r a m eaningles, comb;nalion o f clock a nd rc..,t. A final issue i. t he lime 01 which t o e xan\ine a s imulation result in funclional s imulation. AI t he ve ry latest. Ihe state variable "alues and outpulS should be a l t heir (inal v~ l ucSj u SI t>cfotc Ihe po:$ilive clock e dge, A lthough il may b e possible 10 ot>serve Ihe values al olheT loc.tions, lh;s location pmvides a f oolproof obseTVaI;on lime for funCl ional si mulalion. T he i dea, j ust p re.e nt ed ;lTe <umrnarized in I ~g ure 622. I npu t c h ange, in R esel a nd Inpul. e ncircled in blue, <lCCUT a l a bout I he 25% poini in th e cloc k cycle. Signal v alue, o n S lale a nd O Ulpul. as well a s o n [npUI a nd R esel. all e ncircled in b lue a nd lisled. a re o bserved j usl t>cf"re Ihc 100 % (Xlinl ;n Ihe clock C)'cle. 6 -5 S EQUENTIAL C IRCUIT D ESIGN The design 01 c locked seq uenlial c ireui" s la rls from a sel o f specificalion. a nd CuImi nales in a logic diagram o r a lisl 01 Bool~an funclion' from which Ihe logic diagram can t>e o blained . In conl rasl to a c omb inal;onal circuit. which is fnUy specifoed by a l rulh lable. a sequential Circu it r equire, a s lalc lable f or i t' specificalion.Thus, Ihc fo rsl slep in Ihe design of a s equential ciTcu;1 is 10 o b t .in a , tale lable o r a n equivalent represent ation such as a s lale diagram , A , y nchron" us sequent ial ciTcuil i , m ade u p o f Hip_nops a nd c ombinalionai gales. Th e design o f the ciTcu;1 c on,im o f choosing the flip -fl o!" a nd fin ding a COmbinalional eirc llil Mruclure which. IOge t heT wilh Ihe Hip_ Hops, p rod uc es a circuil I~" ' fulfi ll . Ihe " "cd specifocations. n, . mi ni mu m n umber of fl ;r> -f!ops is d eter m ined by Ihe numt>cT o f s lales in Ihe circu;l: n fl ;p-flo!" can repr""ent up 10 2" bin ary s tales. T he c ombinational circu il is dCTi"cd from Ihe Male lable by cvalual in g t he flip _flop inpul e qual ;ons a nd o utpul e qual ions. [n faci. o nce lhe type a nd 2 ;68 0 C H APTIR ~ I S EQUENTIAL CIRCUITS numbo:r o f nip-liops . re d elermlned.lhe design proceM Iransforrrtll a s cquenllal cir cuil problem i mo a c ombinluional circuil problem. In this ,,' ay. t he techniques o f c ombinational circuit de!i;i,n can M applied. De sign P rocedur e T he following p rocedure for Ihe d esi", o f s equential circuit' ,n " mil . . t o that for c ombinational C;rcu;I' bUI h ns rome a dd itioMI " cpo: I. S p"" ;fi",tlon: Wrile a lipedfico tion for Ihc ClrcU; I. if nol already ava;l~blc. Z. t Ormul.lion: Obla;n e i.her a Sta,c diagram o r " >l aI c mble f rom l he Sla,c menl o f l he problem, J . Stale A..s' tam enl: I f only a Slate diagram is a "ailable fTOm lilep I. obtain the stalc table. A ... ign binary oodc1 10 Ihe ~Iat<$ in II><: lable. 4. n i .... Flop Inpu l [ qutlo. Oc lcnninalion: Select , he ni ....1IofI I)",e o r I)pes. o .,,,,c the flip-flop inpul C<j~lion. from t he ".,~tSlatc e nlries in Ille e ncoded s late table. S. O utput Equ a' iun Dt'crmillMtioll' o .,rivc o utput e quation, from tile QU'PU' cOlries in t he " alc . ablc. 6. Optimi,.ation: O p tim~e t he ftlp' lIop input e quation. a nd OU IPUI equatIons. 7. TechJlology Mappin l' O r.w a logic diagram o f t he circuit using nip.nops. A ND.. O R s. a nd in,'crtcrs. T unsform Ihc logic diagram 10 a neW diagram usi ng Ihe available fllp.flop nnd gale lechnology. 8. , "critiation: Verify t he corre<:tneM o f thc fi na l design, For con\'enien~. we u'ually omil t he I hnology m apping in . . ~p 7 flip-flops. A ND gat .... O R gales. a nd i n""neB in the " ,hema'ie. a~d use only F i nding S tate D iagrams Il"Id Sta te Tab les Tltc ~perification for circuil " often in t he form o f a " erbal d e"'nplion o f , he b eha,ior o f t he c irmit. T his deSC'ription needs t o M i nterpreted in o rder t o find a state diagram O f s tale t able in lhe formula,ion s tep o f t he design procedUre. T his is the often ,Ite mOSI crcD t "'e p art o f t he design procedure. with many o f t he subse q uent s teps p erform ed . utomalit:ally by c ompulerba ", d took. Fundamental t o Ihe fomlula,ion o f Slale diagrams a nd lables ;~ a n i~tuilive u nderstanding o f the c o"""pt o f a ,tate, A stale is used t o " remember" some' hing a bout t he hi Slory o f inpul c omb,nA,io", a pplied ' 0 t he circu it at either t ri"ering d oc k cdges o r during " iggering pulse!. In .... me cases. the $la le, may lilernlly s tore i nput "alue~ r etaining a c omple,e history o f Ihe "'quen~ a ppearing On Ihe inpu,s. I~ mOS' h owe.'cr . s tale is An " b>lm<;tion o f t he sequer>ee o f input c ombina. , ion. at ' he triggering poinl s. r...... u ample. a given " a,e S, m ay r epresent the fac, that am0ll8 the sequcnoe o f ~alues applied t o a single bil Inpul X . " I he value I has a ppeared o n X for t he last three oonsecutj,"C d od: e dga"Th . ... the a ram would be in s tale S , a fter SC(Iucnces ,.. 00111 o r ... 0101111. but would not be in , ta lc S, ca...,,,, ' uoUnq I""~' ~ ~U14Snd ~q J O "llU~l U OJ P~P P~ I ~A ] P~ ~ .IU Lil II 'UOIIIPPU ul 'dn p~J~,"OO . ] Iln ""'l~ 041 ua4" . ' lI c",WLiloln. P ~ IUfl!l ~" A uunsn ' ] l.u~I' la'Ol a 'll '31mS 13<3J ~4 1 p au"" U~IJO S] a lUI' IU] I]U! a'l l ' P"j ul ' HCI< lm" ul 'II U] I]n,,",!, 341 s ;"tld 1""01 a'l l ' "'''''' ~ 'I l 01 P~ ! lddu Sl ndu ] ' "410 II " JO . . alpm~~M 1~<t.>IS U <JJ JJI'Vlu ' 0 IJ<~J u ' ] w ' ] UU4'~W " 'lL " I"" ' 1 01U ! ~IUI' u."ou ~u n '11 ,'uu WO') I] n"''' ' 41 10~ 0 1 papIAo,d ~ l<nw WI! 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I" U!qwoo Ind u] JO " 'll onb"" l ,ed ) 0 I"" X'ldwoo lU,,"~l d.l AI~ n b!un l C(S!W I 01 1~ " ba:Z \>S o, " 41 u l , :0 I" ' X lI q SU 'I U011"U!q woo m d u! . 41 pUe ' I ' I " q m d",o 04 1 1"41 UOIP"Usq" ~41 I Uo;;~Jd.J l q~!W ' s ~le l '~ld w "x~ l Oci -'a ndu l .. . ql uo Ie II ~" I " ! n dmo ' 4 1 u o pa)ln:xw:> '~"4 1"41 ""UI"A 0 1 ~ UUJ") OJ ~q UO! 1 - ~")lsq" a 'll " 'I!l""P OIl '!'"' " 'l .low II ,,""OJ 31UO< UI '31"1' 'IJ "~ i\q p .lu"""dOJ UO,,'Ull'q. a'l l IL"OP QIU." 01 I "p, n ' ! I! ~lq"1 . I" 'S , 0 wu.ISe!p " lUI'. ~U! I " l n WlO) UI ' ! I ' ! 1 '10' 10 '00 '00 JO 0 1 ' O( ' II '00 ;s"~ u "nb",, )OJ ' s ' 1"1' til " 'l IO U PIU l mJ O'" - Jp " 'lL 'OJ ' II ' I I ' II ' 10'00 10 0 1 '01 ' ( 1 '10 '10 '10 '00 '00 ".JU~"""" . (dUlu. ~U ! -"olloJ J 4 1JOJ 'S JI"1S U! "'I PI"O ," ,," '11<1 "4.1 .. ' UOII"Ulq woo p. !ldd" A U>O.' lSOUJ ]l ' 'II , . 01 p uu p 'll ltw;xl UOU"U l qIUO~ ' I'". JO SUO! I! Ia<i,.l ' ,' !l nJasuoo JO ''''lWIlU .'U" 'I ll " OJ ' 11 ' 10 '00 J"p'O U .. "' " P~! l d d " ~UO ! I"Ul qw oo Indm " qZ 10 ""u~ n b'lS ! "41 1 '11 PUj oql lU"",)dal Iqi!UJ OS "'"1< V '001110'" .1 0 11 (0)'" ." ou ~nb"" l all" " 'z 6 9t 0 u:iI!,>(] l!n",!::> ( .!,u,n!s I ~-'I 2 70 0 C HAPTER 6 I S EQUENTIAl C I R CUITS '(""~D' Y( '+ I J- ,- Re",' 1.)'O"L---/ '--'i--- c- c R<s<' - "J Mjt>< hro""", ~ . .." o FIG URE 6-23 A,ynchwoou. "nd S),nCh'OOOLlS R e",' for D Flir-Hops T he resel may b e a w nchronous, la ki ng place without c lod (riggering. ( n {h is ca."".lhe reset is a pp li ed t o Ihe dir""t inpu t> On Ihe circuit fli p-flops. as s hown in Figure 6 23 ( a) . T h is d c, ign assigns 00 ...0 t o {he ini{ ial ' late o f Ihe Aip _A p' 10 b e o rescl. If a n ini{ial sl a{e Wilh a d ifferenl c ode is d esired. l hen the R eset signal can be s elec!ively conneelcd t o dirc"(:[ s et inputs instead o f d irect reset inputs. I ( i . important 10 n ole l hat t hese in puts sho ul d nO! b e u sed in Ihe n on na] , y nchronous cireu i{ d es ign p rocess. Instead, (hey " rc r eserved only for an asynchronou, r<:Se t lh. t relurns lhe sySlem. o f which {he cireu i{ is a c omponcn!. 1 0 a n ini! i.1 slate. Using these d irect inputs as a p an of t he , y nchrnnous circu i! design violates Ihe fund,, menl,,1 synchronous circuit definit io n. since it p ermi!s " Ilip-Ilop st OIC to c hange async hronously within direct clock triggering. A lt er natively. t he r eset m ay be s j'nchronou, a nd require a clock triggering n c nl {o occur. T he reset must be incorporaled in to lhe s ynchronous design of the eircuil. A Simple apprnirch In synohronous reset for D Hip-Hops. , ,;(houl forma ll y in cluding the reset bi{ in t he inpm com bi nation s, is 10 a dd l he A ND gale s hown in Figure 6-23 ( b) a flcr doing lhe normal circu it design. This design a lso assigns 00 . ( ) [ <, l he initial slate. I f a d ifferent inili~1 s late code is d e, ired . {he n O R g ates wi!h Reset a s an inpul c an selec(ively replace Ihe A N D gales wilh in'erled Reset. T o ill uSlrale {he f ormulalion process. lwo examples fo ll ow. e ach " "lulling in a d ifferent slyle o f Sla te diagram. EXAMPLE 6-2 Find in g. St ate llIagnrm rOt a S eque nce Re< ogni,e r T he firs l e ,amp le is a circu it {hal recognizes the occurrence o f a p articular , eq uence o f bils. regardless o f w here it occ urs in a longer sequence. T his sequcnce-"cognil.er"' has o ne in put X a nd one OUlpU( Z. I t has Rese{ applied 10 the d irect rescl inputs o n il s flip_ Aops {o in i{ia li,e t he Slale o f the cir<uit (0 a ll zeros. Tlle circuit i. t o " ,cogn ize Ihe o ccurrence of the s equencc o f bi . . 1101 on X by ma~ i ng Z C<Jua l to I ,,hen {he pre_ious Ihree inpul< 10 {he circuil were 110 a nd e nrrent input is a I . Otherwise. Z e qua ls 0. T he f I", s tep in t he f ormulalion process is (0 d elcr mine whether t he Slate diagram o r t able must b e a I "1ealy model o r M oore model circuit. Th e p ortion o f l he p rered ing specification {ha t saY' .. ... ma~ing Z e qual {o I when Ihe previous t hree inputs to Ihe circuil are 110 a nd {he c urrent inp ut is a I " implies (h a{ lhc o ut put is d eterm ined from not o nly t he c urrent state. bUI a lso {he c urrenl in put. A s a ~ (., ,. /,' , ,. , . c '" (,' ", o t lGURE 1i-24 C onstruction o fo SIO te D i.gram for E xample 6.2 c onsequen"", a M ealy model cireui! with the output d ependent on both s ta te a nd inputs i~ req ui red. R eca ll {ha t a key factor in (he formu lation of any s tate diagram is 10 recognize {ha t slates arC used to " remembcr oomelhing a boul1he history of the in puts. For u am ple, l or {he s equence 1101. to be able 10 p rod uc e t he o utput value 1 coin. ci dent wilh the final 1 in t he seq ut n"", t he circuit must be in a s tate t h.! M remem _ b e,," t hat t he previous three inputs were 110. With this c oncept in mi nd. we begin t o form ulate the state d iagram by defining an a rbitrary in it ial Sla te A a~ t he r eset stale a nd (he Slate in w hkh " "one o f t he . .,quonce 10 be recognized has o ccurred," 11" 1 o ccurs O~ t he input. , i nce 1 is I he firsl bit in {he s equence. t his e venl m USI be "remembered," a nd t he slale after Ihe d ock pulse c annot b e A. S o a s econd stale, B, is c stablished t o r epresent t he o ccurrence o f the first I in t he s.equence. Further. 10 repres.ent t he occurrence o f t he firsl I in t he s.equene", a ITansilion is placed fTom A 10 B a nd labeled wil h a I. Since this is not th e fi nal I in the sequence 110 1. its o utput is a O. T his in it ial portion of the stale diagram i< given in Fi gure 6-24 (a). T he next bil of the sequence is a L When lhis I occurs in slate B, a new s tate is n eeded t o Tepresent t he o ccurrence o f t wo l 's in a row o n t he input - t hat is. the o ccurrence o f an a dd it io n al I while in slate B. S o a s tale C a nd Ihe a<socialcd ITan _ silion are a d ded . as shown in Figure ~ _24 ( b) . Th e n e.l bit of the sequence is a O. W hen t hi, 0 occurs in s tate C, a s late is needed t o r epresent the o ccurrence o f t he two I 's in a row followed by a O. S o Ihe addilional slalC 0 with a transit ion h aving 0 , nput a nd 0 o ut put is added. Since state 0 ropreseDls t he o ccurrence o f 110 M 2 72 0 C HA!'TEIl 6 I SEQUENTIAL CIRCUITS J! ~ a . t he previous Ihree input bit values On X . t he o ccurrence a !n s tale COmpletes Ihe sequence 10 b e r ewgniud . $ 0 Ihe t,."n si lion for the input value 1 f rom s tate D h as a n o utput v alue Qf I . The resulting partial l Ia te d iagram. which c ompletely repre",nt! Ihe ClCCUrrence o f the sequence ] Q be rec<>gnized. i hQwn in Figure 6-24(c). N ote in Figure 6-24(c) t hat. for e ach Slate. a transitiQn i . 'pe<:ified f m Qnly o ne o f the t wo possible inp ut values. AISQ, t he state that i~ t he destination Qf t he transition from D for input I is n ot yel defined. The remaini ng transitions m u.t be b asttl On t he idea t hat t he r ogniur i5 t o idenlify Ihe " 'qucnce 1101. rcgardle $$ o f where il OCCU" in a l onger " 'quenee. S uppose that an inilial p art o f t he s equence 1101 is represented by a s tate in the diagram. T hen . the transition fr om thaI 51ftte for an inpul value that " "presents Ihe next i npul v alue in the sequence must e nter a . tate such that Ihe I QUlput occurs if 11K r emaining bil$ o f the sequence a re a pplied . f or exam p te. s tate C r epresents t he first t wo bit s. I I. o f s eque nce 1101. If the next input value, is O. t hen Ihe state that is e ntered. in this case. D. gives a I o ut put if the remaining bit of Ihe sequence. I. is apptied. Next. evaluale wh . .e t he transition for Ihe 1 i nput from I he D stat e is t o go. Since Ihe transition i nput is a 1. it c ould b e t he firs t o r s econd b it in t he s eque ""c 10 be rec<:>gnized. B ut b eeau", t he c irru;t is in s tale D. il is evident t hat Ihe p rior i npul was. O. So t h is I i npul is the l im I in t he s equence. since it c a nn ot be preceded by 8 1. 1 be s ta te that . epusents t he <>CCYfrence o f a firsl I in the sequence is a , > 0 t he t rans it io n wilh input 1 from sta te D is 10 Stale R This t ransition is shown in t he d iagram in Figure 624{d). E~a min ing s tate C, we ca n t race back thro ugh stat es B a nd A to " ,e t hat Ihe <>ccurrence o f. 1 i npul in C i . a l leasl the s econd 1 in t he s equence. T he Slale representing the <>CC UTTence o f two I 's in s equence is C, > 0 t he new transilion is to state C Since the comhinaliQn o f Iwo \ ', is nQ] Ihe sequence to b e rec<>gniled. t he output for the I ransition is O. R epeati ng this s ame analysis f or missing transiliQn, f .om Sla tes B and A . I he final Slate diagram in Figure 624(d) is Qbtained. T he resulting St ate table is given in t wodimens;onal form in Table 6-3 . O ne issue thaI a ri",. in the formulation o f a ny slate diagram is ,,-belher. in s pite of besl d esigner efforts. . .cess s lates h ave been used. This is n ot Ihe ~ in t he p rereding u ample. s i"". e ach Slate ""pr~nt' input history I hal i . e . ... ntial for O TA8L[6-3 Shlle Tab'" fo r Siale , -, ~. , A C D Di~gram i . Figu"" 6-2 . .-..-, , .-..-, N e" Stale O utput Z A A D A C C , r~cognition o f t he s tated s equence. I f, however. ex"'"s' stales a rc p resent, I hen il m ay be desirable 10 c ombine Slates in lo the fewesl needed. This can b e d one using a d hoc methods and fonnal sla le minimizalion procedures. D u e t o Ihe complexily o f Ihe lau er . p articular ly in Ihe c a.e in which d o n'l-ca' e entries appear in the state table, formal procedures a re not covered here. For Ihe inle rested studen!. Slate m inimizalion p rocedures a re fo und in Ihe referen","s listed at the e nd o f Ihe c hap ler. T he n eX I e xam ple iIluslrales a n additional melhod for avoid in g eXIra s la le . . E XAMPLE 6-3 .' Indlng a S tale D iagram for a B Co....o-Excess-3 Dc<:oder tn C hapler 3. a B CD-to-excess-3 d ecoder was designed. In Ihis example. Ihe func lion of Ihc circu it is , imilar e~cep l Ihal the input . . r alher Ihan being prcsen!ed t o the c ircuit si mult ane ously. are p resented serially in successi,. doc ~ C)cle . . leasl significant b it firsl . In Table 6 4(a).the in put sequen",". a nd c orresponding output . . que nces a re tiSled wilh Ihe least significam bi t first. For e~amp l e. d uring four sue cessive d oc k cydes. if 1 010 is applied 10 t he inpul. Ihe o u tput will b e ( ((II. In o rder 1 0 p roduce each o utput bil in the same d oc k C)"de a , the oorresponding i nput bil, Ihe output d epends o n t he prC&enl in put value as well a , Ihe slale. The 'p<."C ;fi ~a lions also s lale thaI the circu it musl b e ready t o receive a new 4-bil s equence as s oon as t he prior s equence has compleled. The input t o Ih is c ircuil is labeled X and Ihe outp ut is labeled Z. In o rder to f<xus On t he p an erns for past input . . Ih e ro"'~ o fTabte 6-4(a) a re s orted according t o Ihe firsl b it vatue. Ihe second bit value. and the Ihird bit value o f the input s equence .. Table 6..ol(b) resull . . The stale diag13m begins , ,;th an initial state as shown in FIgure 625(a). Examining the fi rst column o f bil s in Table 6-4(b) indicate,; that a 0 prod uces a 1 o utput and a I p roduces a 0 outpUI. N e,l, . .'. as k Ihe queslion. " Do we need 1 0 o T AliLE 6-4 S~ qu ence Tables for Code C onurler E. .. mpt ~ ( b) Sequen.,... tn Ordet o f C ommon Preli . .. (a) Sequence. tn O< der 01 DtgltoR.~ BCD tnput ,,,, 0 0 0 0 , 0 , 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCD tnput Exceoa-30utpul ,,, ,, 0 " 0 0 0 "" ," "" 0 0 0 0 0 ," " I 2 3 ~ o o 0 0 0 ,,,, 0 0 0" 0 o o 0" '0 0 0 " ," 0 " o , 0 0 0 o o 0 0 E.oeoa-3 OUlput 0 0 0 0 0 0 0 ,,0 0 0 00, 0 0 0, 00, , 0 0 6 _'i I S<qucnti.ol ( :i"u i, ] )",i&" 0 Z 7S AI Ihi. poinl, six polCnlial new . Iate. might r e.uli l rom Ihe Ihree , Iale. JU'I added. NOiC, however, Ihal Ihese , Iale. a re needed only 10 define thc o utpu t, for the fourth input bit since it i . known thai Ihe nexi Slale Ihereafler will be /,,;( in p reparalion for appl)'ing the " ext input s equence 01 l our bils. H o w many , Ia le. docs one need 10 specify the differenl possibilities lor t he output val ue in the las t bil? Looking at the final column. a I inpul alway, p roduces a I OUlpUt a nd a 0 m ay produce e ilher a 0 O r" I o utput. T hus.at mool two s tale. a re necessary. one thai has a 0 oUlput to a 0 and o ne Ihal h as" 1 outp ut t o" O. The output for a I input i, t he . . me for bolh states. In Figure 6.25(c). we have a dded these two .t~t~'" For the circuit to be ready to receive the next sequence. t he nex t , tate for I he", new Slates is ! nit . Remaini ng is Ihe delennination o f the btue arcs shown in Figure 6.25(d). The arcs from each o f Ihe bil H2 s lales can be defined based on the third bit in the inpul10utpu t sequence.. T he next . tme can be chosen based o n the r e.ponse to inp ut o in Ihe fourth bil o l the sequence, T he B2 Sla te reaches the 8 3 . tate on the left with 83 o r 8 3 I as indicated by B3 _ X on thc upper h ah'e o f Ihe B3 , Iale. T he o thcr two B2 s tate. reach Ihis same . tale wit h 11 3 = 1 as indicatcd On Ihe lower hatf Qf Ihe <ta tc. Thes<: sa me two 6 2 . tates re~ch thc 6 3 , Iote o n the righl wilh B3 '" 0 a s indicated by the label on Ihe s tate. _ M () M S tale A ssignment In c ontrast t o t he . t ate. in the analysi, exa mples. Ihe Siaies in lI,e diagrams Con Mrueled h .,e b een assigned I)' mhotic names r ather t h~n bi na ry c od"" I t i . n cce. . ary 10 replace the.., symbolic "arne. with binary codes in o rder 10 p roceed wilh the de.ign, In g eneral. if Ihere a re", . tates. then the e wc s m~'1 " ,,,,,ain n hit,. whete 2" 2: III. and e ach . ,ore m ., St b e ,"!>Signed a un ique code. So. for the circuit in Table 6.3 wilh four . ta tes. t he c odes as,igned to Ihe Slales r equire two bits.. We Ix:gi n by as'igning " <:<~le w the initiat reset swt", II 110 1 <lCCUt'S a . the l im four i nput. to the circu it a fter R eset. 1, it , hould b e r ecogni,ed . But if 1U1, 01. o r 1 occur> as t he fit'St ;nput 'i-C4ue ncc. they shoutd n<>l b e rccogni,et!. The " n ly . talc th at eIIn provide th i< prope r ty is . w te A . So. wit h d ircCl r . .,ts u..,d o n the fli p- fl ops. Ihe code 00 must be a ssigned 10 s tale A. A s a b a,i. for e ncoding thc t ema ining ,Iotes. eXlensive w<>rk !)n t hc a s,ignment o r c ode, to statcs eX ills. bu, it i. too comptex for o ur t reatment h ere. These met hod, have focused primarily on a tte mpli ng 10 selc..:t c ode. ill . uch a way Ihat t he logic requ ited to implemenl Ihe ni p. ft op input e q uations " nd o utp ut e quations i , mi ni mized. In o ur example. we ,imply assign Ihe . tate c odes in G ray c ode o rder. beginni ng wil h . Ia te A. ' ]1 ,e G ray c ode is s e lecled in t his case si mpty beca use it mak es it casi';r for the nC XHlate a nd o utput l uncrions to b e p laced o n a Karnaugh map, The . Iate ta bl e wil b Ihe c ode. assigned i , . how n in Table 6 5 with D F lip_ Flops T he r emainder o f Ihe ",q ~" nlia l circ~il deStgn procedure will b e ill ustrated by ! ht next example. We wiSh 10 de 'is ~ " docke d scq "c nti"l circuit Ihat operales according 10 t he s tate table for Exam pl e 6.2. thc " 'quence recogn izer, ,hown in Table 6-5. ~signing 2 76 0 C II AI'TER 6 I SEQUENTIA~ C IRCU ITS o T AIILE6-S Table 6-3 . .' il~ Names Kepi ....... by Diu I')' Codes P _StahI H eIl S tahl ., ,., ,-, 00 00 00 ""' '" 00 '" ""' ""' O utpul Z , . , , ., " " " " " " " T hi' s lale lable, wilh Ihe binary c odes assigned 10 Ihe Slales. specifies four Si aies. 1"'0 i nput values. and two OUIPUI values. Two Hip-flops are n eeded 10 represenllhe fo ur Slales. We label lhe Hip-Hop o utpul. with the ICller< A and B, lbe inpul wi lh X, and Ihe outpul with Z . Sleps I througl1 3 o f Ihe design procedure have IJ.ccn compleled for I hi, cir_ cuil. Beginning slep 4, D Hi p-H ops a re chosen. To complele ' tep 4. Ihe Hip-Hop input e quation, a re obtained from the next-stale values hsled in lite table, For s lep S. the o utput e qua tion is o blained from Ihe values of Z in Ihe table. The Hip-Hop input e quations and output equation can b e expressed as a sum o f minlerms o f t he pr<'Sent _sla'c v.riablesA a nd 8 a nd the i npu.va riabl. X: A (I + 1) K D A (A,B.X) ~ l m(3.6.7) B(I + 1) - D 8(A.B.q - l m(1.3.5.7) Z (A,B.X) _ :l' mrS) ' Ille Boolean funclions a re s implified by using the mnps ploUed in T he si mplified functions a re ~ u '" Ig D A-AB+BX D8 - X Z - ABX , , Z _ Aiix D~ _ AB +BX o n CUHE 6-26 Map' [ or I nput E Guatio",.OO O utput Z 6-26. J >J J , D , D ,, ., o F lGUMt: 627 Logic Diagram for S<~"ential Ci rcuit . ,i t h D Flip_F1ops T he logic di"sm m o f ' he ocquent ial circuit is s how" in Figure 6 27 . D esigning w ith U nused S tates A d rc u;t wit h" nip. Hops h a5 2" binnry SIMes T he 'IM~ , able from which t he circuit waS origi nally d er ived. howeve,. may have . ny n umber o f s tates",'; 2", S lat"" {hat a re n ot used in s ped/ring {he " ,que " t;al circuit a re n<>t li,;led in the ~I" t c , able. In si mplifying l he inp ut c quati(ms,l he un Ll :d . !a les Ca n be Irealed as don't-care condition" T he " ate t able in Table ( Hi defines three f lip./lops,A . 8 , a nd C, a nd o ne inpu t. K T here is nO OUlpul c olumn, w hi ch mean' t hai the flip-flops serve as o ut pUI. o f t he circ ui t. Wit h three Hip-flops, il is Jl'C'Isib le 10 s peeify eight states, h ut t he s tate {able lists " nil' five . ' l1, uI. lh ere a re lhree unu ,ed SIal'" l hal aTC nO! i ncluded o T ARtE 6- 6 S lale TKhie r. . , P re . . n l S "'''e f)e";~ning Input " ilh Unused S Ial"" Ne .t S late ,, ,, "" """ "" " " """ "" " " " " " " " " " " " " " " " " "" " " " " " " " 2 78 0 C HAPTER 6 I S EQUENTIAl C I "-CUrTS ,, x X X X , D. _ , , r, ,, ", , , , , , , :;;C'X: + i iiix o n CUK E 6-211 M .ps l or ( )pIimiling I nfl'l' E quation. in t he table: 000. 110, a nd I ll. W hen a n i nput o f 0 o r I is included ""ith t he unused p resenH late ~al..es. $i ~ unused combinations arc o btained for the p resemstate a nd i nput columns: 0000. 0001, 1100, 1101. 1110. a nd 1111. T hese six c ombinations ar<: IIOt listed in t he f l'IC I .ble a nd h ence may be t re.ted . . d oo 'H:are minterms. T he I hree input e quatioo, for t he D Hip-Hops a rc d eri"ed from t he next-Slale values a nd a re si mplifled in the maps o f Figure 6-28, E ach m ap has s ix d on' t-care mi nterms in t he S<Juar.s corresponding t o b inary O. I, 12. 13. 14, a nd 15. The o pti. mized equatioos are DA = A X -l-BX-l-BC D8 - ACX+AB X Dc - X The logic d iagram can be o btained direclly from t he i npm e quations a nd will n ot b e d rawn here. H is possible that oUlside i merfe rence o r a m alfunction wi ll cause the circuil to e nler o ne o f t he u nused states. ThUs. it is S Omdimes dcsira!:>le 10 specify, fu ll y o r a t leaSl partially. the next Slate values or the o utput values for the u nused s lales D epending On t he function and a ppl",al;on of the circu;l, a n umber o f i deas m ay be applied, First . the OUlputs for t he u nused s tale, m ay be specified s o t hat a ny a ct ion. t hai r ..,ult f rom e nl!)' i nto a nd t ransitions b et"'een t he u nused s tales a re not h armful. Second, a n " ddilion.1 OUlp ut may b e p ro"ided o r an unused out put c ode e m ployed " 'hich ind ica tes t hai t he d rcu;t has cn t ~ r ed a n i ncorrect state, Third, t o e nsure t hai a r eturn t<.> n ormal o pera tion i~ po<Si!:>lc with_ Out re""l1ing l he e ntir e . y.te m, l he nexl . . t ate b ehavior for the u nused Slates may be specified. Typically. nexl <lates ar<: s eleeled such t hat <.>ne o f t he lIormally ",""ur ring ~tales is r eached within a few clock c yde . . regardl~'" o f t he i nput values. The 6-S I s..qu"I\ti .1 Cirew, lJ<<ign 0 2 79 dec ision a s t o which o f the t hree o ptions to apply. e ither indi>'i d ua ll y o r in combi nation, is b ased o n t he a pplication o f t he circuit o r the p o li cies o f a p art icular design g roup. Verification Seq uential circuit, can be verified b y ' howi ng t hat the circuit produces the original s tate diagram OT s tate t able, In the simplest cases. all pos,i bl e input c ombinations a re a pp li ed with the circuit in each of the s tates a nd the state " ariables a nd OUlputs arc obsef"ed. For smoll circu its, the aClUol verification can b e p erformed manually. More generall y. si mu lation is used , In m anual $im ulation. i t is straightforward tQ a pp ly each o f t he sta te-inp ut c ombinations and ,'erify t hat the output a nd t he next state a rc corrcct. Verification with simulation is less tediou,,- but typically r equires a s eq uen ce o f input c ombinations a nd applied clocks. I n o rdor t o c heck o ut a s tate-i nput c ombination, it is first necessary tQ a pply a s equence o f i nput combinat,ons to place the circuit in t he d esired state, I t is moot efficient t o find a . ingle oe qu ence to test a ll t he s ta t e-i nput c ombinations. T he s tate diagram is ideal for g e ner ating a nd o p tim i'<ing such a s equence , A s e'luence must b e gen~rated to a pp ly e ach input combinat ion in e ach s tate wh il e observing the o utput a nd next s tate that a ppears a fter t he positive d oc k edge. T he s eque nce length can be o pt imized by USillg t he . tOle d iagram , T he re.et . ignal can be u sed", a n input d ur ing t hi' s.eq~ence. I n particular, it i . used at t he b eg in ning t o r eset th e c ircu it t o it s initial s tate. In E xample 6-4, both manual a nd si mulat io n-based ,'erification a re iII um ated, E XAMPLE 6-4 Verifying the Sequence R etugniur T he state diagram fot the s equence r ecognizer a ppears in Figure 6-24(d) a nd t he logic diagram appear> in Figure 6-27, Th ere a rc f our ' tates a nd t wo i nput comhina tions. giving a total of cight stote-input combinations to verify. T he ne xt state can be o bserved a s t be s ta te o n t he flip- Hop o ut p ut s a fter the positive clock edge. For D flip Hops. t he next s tate is the same as the D inp ut j ust before the clock edge. For o lher types of Hip - Hops, t he flip-flop i nputs just beforo the clock odge a rc used t o d elennine t he next s tate o f t he f1i p. fl op, Initia ll y. beg in ni ng wi th t he circuit in an u nknown Slate. we a pply a 1 t o t he R eset input. T his inp ut go,,, to t he direct reset input o n lhe two Hip -flops in Fig ure 6-27. Since t here is n o bubble on these inputs. the I ,'aluo reoets b oth fl ip-flops t o O. giving Slate A (0.0). Nexl. we a pply input O. a nd m ,n ua ll y s imulate the d rcuil in Figure 6-27 10 find t hat the o utput is 0 a nd the next state i , A (0.0). which a gree. with t he (ran,it ion for input 0 , ,' hi le in s tate A, Next. si mu lating statc A with inp ut L next . tatc B (0.1) a nd output 0 result. For . tate I I, in put 0 gives o utput 0 a nd nexl s tate A (0.0). a nd inp ut t gi,cs o ut pul 0 a nd nexl sta te C (1.l) . Th is . a me process can be cont inued for each of the two input combinations for s tatc. C a nd D. For ,'crification by si mulation. an input s equence that a pplie. all state_input combina ti on pa ir,; is t o be g enerated accompanied by the output s equence and 2 80 0 C HAPTF .Jl ~ ' SEQUENT IAL C IKCUJTS , 00 ,, . ,. , " , ,. , ,- , "'\ ., ~ <.10 "00 ,., , " 7 111 ." 00 " l' ,,, """" Input R: Input . . St ' .' 0.0' M , '.. '.' , ,.. '.' M O utpul ,~. Edge: X: U ( ".B): Z: o I'ICURE6-29 'leo' ~""ncc '" OeM. "ion 100- S,m ulation in e..:omple 6.3 , ta te se<!l>Cnce for c hecking outpu l aJKI n ut-s tate ,alues. O ptimitallO<l ' C<juires tha t the n umber o f clock p<:riods u~ u cced t he n umbe r o f s tate- input combin ation p airs by . . few p<:tiodt I S possible ( i.e.. the repetition o f s tate-i nput combin ation p airs should be minim~) _ T his ~an b e , nterpreted as dra-..;ns the s hortes' p ath through the state d ial"'m that passes through each state-input c omblnallon p air at teast once.. In Fi gure 6-29(&). for eorlVenience. the c odes f o. t he s tatc' .~ s ho .... n ~nd the p alh I hrough t he d iagram is d enoted by a $<: q uence o f blue inlcgcrs begi n1 ning wit h I . ' 1 ,"S4' integers COrTespo nd 10 Ihe positive cloc k edge nu mbers in ~ lgure 6 -29(b), where Ihe "criticalion ICquence is t o be d e.'elo p<:d. T he , .Iues . hown fo . the d oc k e dge nu mbers a rc t hose presc nt just b efore t he posit ive e dge o f l he cl ock (I.e., duri ng Ih e se lu p t, me interval). Cloc l: e dge 0 is a t 1 . 0 in II", , im ulatio n and give. ulIk nown va lue. f or a ll s ignal s. We b.!g in wit h va lu e I applied 10 R esel ( I) t o p lace Ihe circui l in . t at e A . 11I p uI .'a lue 0 is a pp lied firsl ( 2) s o t hat (he S1ale r emains A . fo ll owed by I ( 3) c hec ki ng t he s econd input COmbination for s tale A . N o w in State B.,.,., c an e ilher mO"( f o. ward to Slate C o r g o back t o Slate A , It 1$ n ot a pparent , ,-h ic h ch<:Me<: i . b esl. s o " "C u bit rar il y a pp ly I ( 4) a nd g o t o $ laic C In 5tate C. I Ii a pp lied ( 5) s o t he " Ia[e r emains C N ut . a 0 i. a p pli ed 10 c hed t he final input fo r S latt C Now in ! !ale D. " 't h a"e a n &-<; ' r'=' ~ ~~ I~ I 0."", F bp-FlcpTyp<, ~~ ~ ~ ~ 0 2 81 ~ ' ----.r ' ---.I " , I,,,,, ,,,,,,,,,, ,,,,, ,, .. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,, ,,,,,,,, ,,,,,,, .. ,,,,,, ,,,, ,, .,,, ,,,,,, ,,,,,, o lOOn , o lOOns .lOOn, ~l GU ME 6 -.l(I Simulation ror E. .. mple 6.S . rbil rary choice t o relUrn t o s tate A o r t o s tate B. [f we return t o ~Iale B by applying I (7). Ihe" we can cheek Ihe transition from B 10 " for in pul 0 (8). Then. Ille ollly Temaining I rans il iolllO check i . sla le D f or input O. To r each state D from s lale A. we m ust a p pl y Ihe seq ~ en"" ! . !. 0 ( 9) (10) ( II) a nd t hen apply 0 (12) 10 chcck t he I ransilion from D t oA. We havc checkcd cight Iransitions ,,ith sequence consist ing o f rcset p lus!! inputs. Although this test sequence i . o f optinl~m I~ngth. o plimality is not guaranteed by Ille proc<:dure ~sed. H owe"cr. it us ua ll y p roduces an efficient sequence. [n o rder to sim ulate the circuit. we e nter the schematic in l ~gure 6-27 u5ing the Xilin~ ISE 4.2 S<:hematOc E ditor and ente r the seque nce from Fi gure 6.29(b) as " waveform using the Xilinx l SE 4.2 H DL Bcncher. While enlering the waveform, it i5 i nlP0rtanllhat the input X ohange5 well before Ihe d oc k edge. This insures that the. e is time available t o d i'play the c urrent OUlput and 10 p ermil inp~t c hanges 10 p ropagate to the nip,nop inputs before the set up lime begins.. This i$ iliustTOted by Ihe INP UT w a,dorm' in Figure 630 in which X c hanges shortly after Ihe po!lilive doc~ e dge pro~ i ding a g ood p onion o f Ihe doc ~ Jl"riod for I he change 10 p ropagale 10 Ihe flip _ flops. T he c irtu il i5 s imulatcd wilh . he MT[ ModelSim simulator. We can then compare Ihe ,alue. just before Ihe po!liti~. d ock edge o n the STATE and O UT PUT wavefonns in Figure 6.30 wilh Ihe values shown on the slate diagram fo r eac h d oc k period in Figure 6-29. In Ihi s case. t he romp.1rison vcrifi"" that the circuit o peration ill correct. 6 -6 ~ O THER F LIP-FLOP TYPES This ""ction introd "" c. j K and T Hip-Hop< and Ihe repre""ntalions o f their behav_ ior u..,d in a naly.i. and d c.ig,n B"causc o f l heir I. ... r importance I n c ontempor ary deSIgn relative to D Hip flops. I he analysis a nd d "";gn example5 i llu'lrating t heir Usc a re g iven On the C ompanion W cbsi'e for the t nt. 2 82 0 CHAPTER 6 I SEQUENTIAL C IRCUITS J K a nd T F lip-Flop s Four ' )'pe5 o f Hip-fl""" a rc characler~ in T able 6-7_ including ' lle S f( and 0 from seclion 6-3 gi~ for refercnce. an ... llIe I K a nd T in.roduccd here. Wilh . he exceplion o f Ihe S f( flip-Hop ..-hic h ,s maslcr-.lave. tile .)'n,OOI f or a J'<1S"ive-e"'gC-lrig. ge.ed version of each Hip flop Iype is givcn. A logic diagram f or"n implemcnlalion o f each flipflop type is either r derenced or given. A new concept. tile r/r"rar''''is I k "'hie. defines I he logie~ I p roperties o f nipHop o peration in t abu l"r fO'1II. Specif. ica ll y. the t able defin e. the n c~ t I l",e a , a funclion o f the p resem ",a te ' '' td inp ut s. Q (I) refers to the p rese"t . tnte prior to the application of a clock pulse. Q(I + I ) representslhe s tale o ne d ock perioo laler (,.e., Ih e ne.<ISlale). Note thaI the !rigBl'ring e dge ( or pulse) al input C is IH>I listed in the characteristic table. but is "",,umed t o occur b e'wn time I a nd I + 1. Next t o the characlerl5.ic lable. tile ~MrtJt;'cmlic cquation for each nip.fIop type is g h'en.lbe$e e quations der.roe the nex. Mate a fler the d ock pulse fot e ach o f lhe nip-I\nps " ". function of lhe preset inputs a nd Ih e presenl stale before thc clock pulsc. T he final COlumn o f Ille .able consiSlS o f U CilJJlior! / ahkJ fot each o Ilhe Hip-Hop types. These l .bIes define the i npul value o r , .Iues rC<Juircd t o obIain each possible nexl " ale ,,,,Iue a fler the d ock pulse. given Ihe prescm Siale " alue b efote Ihe clock pulse. ExcilJlion tables ean be used 1 0 d elermlne tbe Hip -Hop input equalions from . tale l able information, Hisloricall y. the J K Hip -flop was a modi~ed version o f Ihe m aller-slue SR Hip-Hop. While the SI{ Hi p-nop p roolltts undefined o utputs a nd 'ndct~rmintlte b ehavior for S ~ R _ I . the I K nip_Hop e au"", the output t o complemcnl its c urrent value. The masler-. lave version o f Ihe J K Hi['-Hop has pul""-trisgered behavior and. in addi tion. e xhibil' a property called " 1's catchin g_" O nc e I = I o r K _ I occurs. such Ihat the master changes to th~ opposite " ale, the maSler ca nn Ol be changed back 10 its original ,talC before the clock pul", ends. regardless of Ihe "al_ ues o n I a nd K. This wOfSC IlS the " "lup lime problem Ihal already uiSIll for the pulse-triggered flip-Hop. The.salnl' soiulion appli"" as for l he SR nip-flop (i.e" making the setup lime. I" Ihe emire dUralion o f l he triggering [,ul",,). To . void . hi. addiTional contribulion 10 Ihe length o Ilbe clock cycle. . rc m e only e d,e-mw red I X nip-Hops built upon I n e dBl'.trigcrcd 0 Hip-flop. In Thble 6-7.11>e s ymbol f or. po!Jli"e-edge-triggered J K nip-nop is shovo'n as well as illl logic diagram !KIna a pO$itivc-cdge.lriggered 0 n'p-nop. T he c haractenstic table gi.'Cn <Ie.scribe. the h ch."ior o f lhe J K flip-flop. The J inpul b eha,cs like lbe S i nput to set Ihe nip_nap. The K inpul is similar 10 tbe R input for r~l1ing Ih e nip.Hop. T he only difference belween the S f( " nd J K f lip-n"", is theif response t o the condilion " 'hen holh i npu" are equal to L As can be verif,ed lfOm the logic diagram, Ihis rondition conlplemcntS Ihe st"'C o f Ihe J K flip. Hop. Wi len I " I a nd Q = O. then 0 _ I. oonlpl CIlIC li ting Ihe JK nip. nop outputs. When K l und Q 1. then 0 = O. c omplementinl the J K Hip-nop outputs. Th is d en",n"r"les Ihat. regard Ie ... o f the value o f Q. the rend,tion J - I a nd K - 1 cau""" the Outp u" o f the nip-llop to be c omplemented in respon"" 10 clock pulse, The rn:xt . late b eha.ior is summarized in Ihe characteristic table column o f Table (,.7. The clock input is , ",I explicitly ,hown, but , clock p~tse is assumed 10 have occurred belween the p r"",nt.late and l be n etl stalC o f Q. D TABLJ:~7 Hip n op " ~ +J . u , Logk,C~M ....... ~rh!kT~ h"" " , Q (l+l) ~,) S oxHpre6-10 , B ;~B:" 'i>o ., ., ~~ QI I ) ~ ,, , , ,, ,, , ,, , , , ~') ~,) c :0 ':5[J , , , 1.1\1 01) ~,) 01') [qp.lio~s. . .... EJ;ri!.lio~ ,,...,...... , ,, , ....., , ~, , k o l 'lf;u . ... I J QU+ l) " . nd -- ... '''''"II'' ,~ ..... 0 l1+1) - 0(, ) ~" Ol, +[) .5(1) + Ntl)-Q(') Q (t " ' ) - J(,j .i,'j(,) T KO) QII! ~ QI I ) , "" , " ," , QUI C""'fIItmo "t ~c --... , , \ )(1+i ) 0 ,.. . .... NoJ TI'!!",", Q I'.I) , ,, ,, ,, \ )(" ' ) Ott " 1) - 1(t)eQ\I) ~" ~,) " , .. -.. 0 . ....110. , 'M ,, " ~, " " ,, , ~, , , , ,, 0 ,.,0 ,.. . . ;.;." . .. N ochonl< ~~. , , ~C"opI<."'" o N e 2 84 [) C H AI'TEIl. I SEQUENTIAL C IRCU ITS Th~ T ( loggIe) n ip.nop is e qu;valem t o the J K Hip.1Iop ",ilh J and K lied togelher . .. Ihat J ~ K _ T. Wolh this ronnection. only the rombinations J = O. K " 0 and J .. l . K _ I are applied. If .... e take the characteristic equation for the J K nip. flop a~d make th;~ r onnection. the eqU3tion b<;C(mIe$ Q (I+I) . . 1'O" T Q _ ToIIQ T he . ymbo l for Ihe T fl ip-nop "lid ;15 lugi< diagram ba..,d o n thc preceding equa_ t;on are given in Thble 6_7. T he en"racteri.tie e quation for Ihe T IIip _nop is t hat ju~t &i"cn, and Ihe charOl:lcri~tic l able in 1 ,'ble 6-7 s ho". . thaI for T . O. the 'r n ip_ flop o ut puts remain unchanged, and for T . l . the o utpuU " rc c omplemented. Since the T flip.flop CIIn only hold ils I lale unchanged Or compltOlenl Its Sla te, thcre is no way to C5tablish I n ioillal state using only t he T inpul without addtng n temal sampling of Ihe curreol OUtJ>ll I in the n nl >laIc Jogic o utside of t he fl ip. flup. ThU$.the Tflip_nop is usually inilia l ~ to a k no... n s talc by using a d irea " "t o r direcl r.,;cl. 6 -7 H DL R EPRESENTATION F OR S EQUENTlAL C IRCUrrs- VHDL In C hapter 4, VH DL wa~ u..,d 10 describe combinational circuits. U kewi"", VH I)L can describe s torage e lement. and ""quemial circuits. In I hi' ""ction. dose,iprio". o f a po&it ive-edge-rriggcrcd D ftir> -flop And a s e'luc nc.., recognizer d rcu il ill ust,",e , uelt uses o f V U DL 1l,~ descrir>tio", h "'o lvc new V HDL concepts. tlte mOS t i mport.nt o f which is the prOC~J. Thus far. concurre nt statcmenlS have descril>ed C(mIhin8tions o f conditions and aclion. in V UDL. A conc ll rr~nt ~ I .temen t , however. is limited in tlte comr>luity that can b e represen ' cd.Typically. the sequcnliol cirruits 10 M de$cribcd a re oompr.,x enough t hat de$cription "'ithin I concurrenr >latement i . " ery difficult. A p roc:al CIIn h e v ie""d as a "'r>lacemcnt for a concurrent 5t~tementth31 permirs ronsi~nbly llreat~' descript;"e lK>""r. Mulliplc p roCCMCO may execute concurrenrly, a nd I process may u ccute coroc:urrenlly " lth c oncurrent state ..... nts. 'The body 01 a prOCCSltypically implements a s equential p rovam. S,gnal values. .... hich ar~ assigned d unna Ihe r>'~ h owe"e',chanJ(' o n ly wMn the r>'oce>S . . r ompleled.if the poniott Of "r>r0CC5S e xecuted . . B . ,_ A ; Cu B; t hen . I the comr>I(lion o f Ihe process. B will conta in Ihe origill.1 con ten ts of I'. a nd C will c ontain Ih~ original contentS o f B. In c ontrast. a fter excc "l io n o f these twO ' tatements in a p mgram, C would cont ain t he original con' ents of 1'.. l b achieve r>rogram -like behavior. VIID L ~ a nother construct c .lled a ,'uT;ahlr. In COntraSt t o a signal ,,-hich ( valu.tei a fter SOme delay. a .'ariable evalllat"" imorn:d,ately. Thus. i f 8 i . a variable in the c xUllon o f B , _ A; C , . B; B will instantaneously e~31"'le 10 Ihe COrllen\l; o f A and C "'ill t>'aluate to l he n ew c onte n ll o f s.!IO t hat C finally contains the o ritinal r onlents o f A. Va riables a ppear o nly ... it hi n prQCt'SeS. N ote the use o f ,. . ilL5 l ead o f < _ for , . riable o "'&"menl. E XAMPI..E 6-5 V lml.. fot Puslthe - .; d ~ Tri~", d D F lip-no, . .i th He l'O" t a~s k p rocess st ructure;' i llustrated by a n e xample process describing the arc hitecture o f a positi ve-edgc-triggercd f ) nip-flop in Figure 6-3 1. T h e process hegins wilh t he keyword p r oc:: . O pt io n ally. p r oe can be p receded by a process na me fo ll owed b y" r o lon. Following in parc nt hesc. a rc lwo .ignal$, e LK a nd R~SET. ' nl is ; ilhe M mjlivily lisl for the process. If d lher CLI': o r R ESET c hange.lhen t he pr~' i !exccured. In general . proc>:\S is c xccuted whene~er" sign al o r variable in itl s en silivlty list changes. It is im por lant 1 0 nOle lh ol lhe sensilivity list is not 0 p ar ameler lis! c ontaining all i npull a nd . ... tptl\l;. R>< u ample. Dd oes n ot a ppea r. since a change ill its valuc can ~ init iale. possible change in t he ,,,,Jut ofO_ FOIlO'wing t he sensiti . vi ty liS! at the Ixginning o f the p r1)CCM is t he keyword b eg i . . , a nd . llhe e nd o f t he ~ the k ey. ."Ord .1Id a ppears. T he word p r oc folk",,;ng .rod is o ptional. ....'ithin the body o f t he prOCCP. t he,e u e a dditional V H DI.. r o ndltional s tructure. t hat c an . ppear. Notable in t he f igure 6-31 e xamp le ; . If. thu _cl,.e.. l be g eneral s tructure O'f a n Ifthu _cll'O" in V I IDL i . - - _ltiV<ll-Edq.--rriwerrod [l , Up-rIO!> . . i th _t , I Il!IX. P roc ! )M(;riptlon l i brary 1 _ ; u l eeo . t~loqlc_1164 . l l, . n tit r d ff h p ort lClJ(. IIESE"I". [ l b n cLloqic, o , o ut . td.,.loqlcf I a reb.1 t.c t u r . ~ o r d ff 1 e l III>l-. . .. . ,.,.itlV<ll . . . trigger! W t . Ute . torlOlle . . . .I th a syncItrtlnouz ~ . ...... ...... " """ . . . lC:U<. RESB'l'I i r ( RESEr _ ' 1') t h4n Q <_ ' 0', . h i f 1CU< ~t and e LI(. ' 1') U ,. n Q <_ 0 , -, - o . nd i f : . ..... i f : p"""" '" t l GU MEo-J I '1H DI..I't-or:=r Ik!.<riplioo 01 " ""'i"".EdFTrilJtC,I f1i . .. ~lop wilh fteoc. 2 86 0 C H A PTER 6 I S EQUENTIAL C IRCUITS i f c ondition t hen s equence o f st~tement8 ( e1 a if c ondition t he n s equence o f st~te ment8) . 1 s equence o f st~temen t s e nd i f i The statements "'ithin braces { I can ap pe ar from " "ro t o any n um ber o f t imes. T he j fthenelse wit h in a proc~ss is si mil ar in effCCI to the ",hen e lse coneurren1 assign m en1 s tatement lIIuSlratin g. we h a"e i f />. _ ' 1 ' t he n Q x; <~ e l .if B _ Q <- '0 ' thoon Y; .1 Q <_ Z ; . nd i f ; If A is 1. then flipflop Q is loaded " ith lhe cont en t, o f X. If A i , 0 a nd B is O. the n tli p.Oop Q is l oaded wit h t he c ontents o f Y. Otherwise. Q is loaded with the c ontent, o f z. The end resu lt for the fou r c ombinalion o f va lue, on />. a nd B is , -, , , -, ,- , , ,," 0 0, 0, 0 - 0 " 0 0 0 Q 0 <0 <0 <- <- , , , , More c om pk . oo nditional execut ion o f state men], can be ac hi eved hy nesting i f t henelse struct ures. as in 1he foliow iTI g code ' i f A = ' 1' t nen if C _ ' 0' t hen <~ w; Q ,, _ x; Q e 1_e e nd i f , . 1 .if B Q <~ ~ ' 0' t hen Y, . 1 Q <= Z, . nd i f; T he e nd ,..,sult for th ~ eigh1 c om bi nation, o f value. on A . 8. a nd C is ,- ,- , , - , -, , , , , - , -" , -, , - ,, , " - , , , - 0, 0 0 0, 0, 0, 0, 0, " 0 C 0 0 0 0, 0, C C 0 Q 0 , , , , , Q <0 Q Q <0 W 0 <- ~~--~~~- ............. .. " 1 . B - t. C 0 A 1. B 1. C 1 Wilh t he i nformation i ~{roduced tit". (m, the po5it i , e~dge - {ril!.&tr ed 0 Hip Hop in Fi gure 1).3 1 can now b e s tudied . T h e sensitivity list for t he process includes e LK a nd RESET. s o t he proccM j. exe<: u t ~d i f e ither eLK o r RES er Q ' 00111 e ll""g" ,-aluc_ If 0 (h ang~"5 valu c, t he ,'a\\le o f 0 is 001 10 ch ange for an e dge _triggered nipHop. s o D doI:lo nQl ~war o n II><: . .,miti"i!)' li st lJased on t he i f-t h e n -e l ~ . i f RESET is 1. t he Hip./Iop OUtput Q is reoet 1 00. O tbe .....' , $<: . i f t he d ock " "I"" c hanges. . . hi eh i . reprc",nt! by a ppending ' e vent to eLK. l nod t be nC"'dod value is 1. .. hlch is r epresented by e LX. ' 1', a p<l6ilive e dge has occu(Y('d on CLK. T he . null o f t he po6itivc edge occurre nce i . the l oading o f the ""I\le o n 0 i mo lite nip-Mop iIO th aI i1 a ppears o n o utput O. Not" that. d ue 10 (he s UuC!"'" o f th e i f-then -eM. RESE'l' e< I,,"1 10 I d ominates the clocked b ehavior o f t he D l Iip.llor c au,ing Ihe QU lpul Q 1 0 g o t o O. S imila. $i mp lc descript ion. c an be used 1 0 re prescot o ther ftipll op t ype. _ ,md trigg~rina a pproaches. E XA.\If'U: 6-.(; VII OL for Ihe Seq~ . .... M. erop>""" m ore ro"' I )Ie~ ~xa mpl" i n l1,ur"C'$ 6 . 32 a nd 6 .33 n:r<e5enl. l he K qUCJ'K:C r ecos' Slate d , aa ram ,n n ,ure 6 .24(d). T he a n:hiteclure in this dc!cripllQn r onmu o f t hree d i't inct processes. which " an e~"'ute simult ane<:>u.ly a nd intcra<t v ia , harM signal value . . N ew c ontt pt, incl uded a rc I)'PC dc<;lMa,inns for d ennin, new 'ypes and c ak s l ~tcmcm. for handlin g r ond illo"" A oi ~"r u ' ' ll \e ' y pe d"<;I",,.lioo permits to define n cwtype' " "" logou. 1 0 e xi. tin, lyJl'C'l such a s a t<t-loglc . A type doclaration I>c ,i n< wilh tt>.> keyword t~ f()ilo "'~d by t he n ame o f the n ew typ<:o Ibe keyword h . IId. "'it hi" p arentheses, the Ii!.! o f v al""" for signals o r l he ne .... type. Using t he " .ample fro,n R aur e 6.31. " "e h ave t:n>ec B t&te_type 1 . I A. B. C . O J, T h e n am e o r t h e ne w t )1'" is B tat _ _ t ype a nd t he v alu es i n th,~ cac a rc I he n am es o f t he Slal es in Fis urc 6-24( d) . O nce. t ypo. bas b<:en d ecla red. ;1 c an be u sed for dec lari n, s ignals o r v ariable s. I'rom th c e xample in Figurc 6-31 . 1 gna l B eate, nl1 x t_state : Btate_ typl1: 'If" indicates th"t e ta t . ~ n d n ext_ata t e aru s ign"l. I ~ "t o f t he type I ta L a_t YP'! . TIm' t ate aod n ext s t&te " ' 0 ha>' c values A. B .C.a nd D. T he baSIC Ir 'h u ~ N ( "'t houl u~ing t he I h1 l ) m ake. a two . .ay <k,,,,, i<>" ~d 0 0 " 'helhe r & o oodilioo i< T R UE <>r FALSE.. I n conlra<l. .l he ~ s la tement can m ak e a m ulu"-,,y d ecision based o n " 'hieh 01 , n umber o f 'Ialemen ' ~ " TRUE. A simplified f orm fot t he B'""eri<: <ase Slale menl i . c as. e xprese10n i s ( when e hoice. .~ s equence o f s tatame nt s :) I nd c a." . .. . .... .. ... .. t , :" . ! ! A i< 1 o ; ::l ~g J; w " I f { 1>, 1. .. ~, ~ -.... C ",:", 15. .. ~ ' ~" i . .' .. .. ~, ~ > f:' A .8'" ~ ,' o ~ ' :0 ' ~ ". >; ~'! '" I!' , :- ...... V . .... ,~ . ~ ~ .. " i " "s !i : j ~;- t~~ ... 'B ~!!' , .... .. ~ 15 ><~ :. ... "" . ! : i~ ~ .. :;..I ! ~. , ! ~ , ', , 8 ~ .. , , ! 5. . .. ;- , , . ... " n ' ~5. .~::; I. ';!' 1I l" !N !~ i ~ ii . P. B"' .8 . . ... 1 ... .. _ " , . - ' Ii. ~:a:; .. ::; "'! ~~ ... .I ,..:;~., .'':.:: ~ ,; ;.e.il '!aii! " ~. " ", ~ ... .s '" ., " . , . ,. . i ~ i ;; j '~ ~ . rt " '"' !'oj .~_,; " ~ .. " 5.' ~e -" . , f f " ," !i:.?" O ~ i~ ~ e r ~i . .r.'r h "~ I i " , t t ~gl! i. S::1 . ~- I,... , n .. . ::- 0 ~ , l:! e~ ..s" r - .. .... . . .. t '. . ... .. o~ ! l'I ~ , ii " " ~ ~ o I , I Q ~ 6 -7 I H OL I V""". ....." "" f ix S<qu< . . <w C itcW<>-VHlJL 0 289 - - Sequenc. R =ogni=r , \ IHI:L I 'rocess D a8cripticm l<XIf\t i nuedJ - co> .h. if X 0 '\' ~be" " .".tJtate "" '" ", -. ,.h. r >excatat. .~ H; , " .> " '" " .> " "' nextJO tate t 'le><tJtate .~ H ; . "" c . ... ; . nd " roc. . . , -.. I 'rOcess ) - outl.l1:... f unction, 1 lII>1..,.,.,U <>.1t[:<1t a s f uncti"" c f J .r.p..t X at><I . ""too. " "tput:,..[u,""" " roc. . . IX . a tateJ c u t aU i . w ho" A _ > Z " ". " ~_ ' 0'; EI _ > ~< _ " ". .. C 'O'; _> Z < _ ' O' ; _ . . 0 _> i f X _ ' 1' t he<> Z . _ ' 1', .1. . Z . " '0 ' , . nd i t, . nd " . . . ; e nd " roc. . . , -, o F1 GU HE 6-33 VHDI.. I'roce>. D<scriptioo o f. Scq<O<nC< R:<>p>izer (oonti""""') The choices musl be v alue. Ihal c an be 1 .ken on by a s ignal o f tbe type U5ed in l he expression. T he""", S laumenl has an effect similar 10 the , ,'ilh_ 1ed c oncurrent a ssignment stalemenl. In Ihe e nmple in Flgu r'" 6-32 a nd 6-33. PrOC . ... " 2 uses a . .so: s ta tement 10 define the n ut S1ale funClion for the s equence r erogniu < T he ~ ~Iatement . m ak'" a multiway decision b ased o n the current . 1.te o f lhe circuit. A. B. C. o r D. If 'h e n ~ " " Sl atements a rt lIS<'d for e ach o f t he , tale a lternati .. e s t o m ake a b inary d~ci, ; on b ased On " 'helhe. i nput X is 1 Or O e oncum;nt assignmen l slatements a re . then used 10 assign the nexi slate b ased on the e i(l)tt possible combinalions o f >!ate value a nd input va lu e. For e .... mple. " ,,".ide, the $!ale alternalive w he" B. I f X 2 110 0 C H AI'TEII. 6 I S EQUENTIAL C 1II.CUITS e quals I . Ihen the next , tate will be C; if X equals 0, then the next , tate wil l be 1\, This c orrcspon d:s to the two transition< OUI o f s tate B in Figure 6-24{d). For more complex circu it " easc s tatement, can also be used for h anding the inp ut condition .. Wilh Ihis br ief introduclion to the ...... ' " statement. the o "era ll s equencer recog_ nizer can now be studied. Each o f the Ihree processes h as a d i'tinct fu nction. bUI the processes interact to provide the overall sc4u~ncc recogI1iler. Proce ~ s 1 describes the s torage of the s t.te. Note that the descriplion is l i~e that o f the po:o;iti'e-..dgctriggered Hip- fl op , There a re two d ifference .. however, T he signals im'olved a rc of typ<: s t<lt"_t:ype insload o f type s td_ lOQic . Six'ond. t k state that resu lts Irom applying RESET is state A " nher t han stale O. A lso. s;""" we arc u\ing stale nam..,,; s uch as II.. B. and C. t he number o f state variable> (i ,e" the nu mber 01 flip -flops) is unspecified and the Slate codes a re unknown , P rocess 1 is the only one o f t he three processes Ihat contain, storage. P rocess 2 des<ribes the next state funct io n. as diu,<;ed earlier. Th e sensi tivit y list in this case contains signals X and s t:a t e , In general. for describing com bin ational logic. a ll inpu ts mu , t a ppear in t he sensiti"ity list. s in ce. wheneve r a n input change . . the process must be executed. P rocess 3 describes the o utput function. The same case statement frame work as in P roc . . s~ 2 wi th , tate a , the expression is used , In ste.d o f assigni ng , late name> to next state. val ues Oa nd 1 a re ass igned to Z. If the va lue a,signed i , t he s ame for both va lues 0 a nd I on x . no i ftben-d S<' is needed. SO an ifthenelse appears only for s t.te D, I f there are multiple input variable .. more c omplex Ifthen...,l", combina. t;ons or a ~_ ota tement. as illu,trated earli er. Can ! x u,.,d to represent the conditioning o f Ih e o utputs on ' he input'- Th i, examp lo is a Mealy , tate machine. in ""hich the output is a fUDclio n o f the ci rcuit input~ I f it weTC a Moore , wte machinc, ",'i th t he output d ependent o nl y o n the ,talC. input X wou ld not appear on t he sen, it i"it), lise and there "''QUId be no ift .... n..., l... structure, in the ""se statement, Ther~ is a c ommon pitfall present whe ne,'cr an ifthenelse o r c _ , ta te me nt is e mployed. During sy nthesis. un o~peeted s torage elements in the form of latche, Or fl ip-flops a ppear, For the simple ift hen e lse used in Figure 6 -31, us ing th is pItfall gives a speci fIc ation Ihat synt hesizes to a Hip.Hop . In addition to the two in put sign"l.. RESET and eLK. t he s ignal CLK' . .v . . n t: is p rod uced by ap plYIng the pTC . defined a n ribute ' event t o the CLK signal , CLK ' . ,vent is TRUE i f the value o f CLK c hange . . All possihlc combinations o f valu es a rc represented in Thble 6-S. W henever RESET is 0 a nd the CLK i , fi . e d at 0 Or I o r h as a negative e dge. no aC lion is specified. In V HDL. it i , ass umed Ihal. for any c om binations o f condition' that h a"e un specified actions in ifthenel. .. OT ~Mse , talcmems. the left-ha nd side o f an .ssignme nt slatement remain, unchanged. This is e q ni vak nt to Q <= Q . caus,ng storage t o occur. Thus.. all con,hinations o f c ondilions mus t have the re,ull_ ing action specifIed when n o slorage is intended. If this is n Ot a natur~ l s ituation. an o ther. can be used in t he ifthen else o r " "se. I f t here a re binary va lue, used in t he <>o se ' ta te ment. just as in Scct ion4 -7, an o th . r . m U also b e u ",d 10 handle St combinations including the seven values o ther t han 0 a nd 1 p e rmitt ed for st d_logic. Together, the th ree processes used for the seq uence rCCOgI1izo r deseribe the state storage. the next ' tate f unction. a nd t he o ut put function for a s equential o T ARL6M 111 ",11.,,,1. . " .. r gene .." ,,," .. f . ..., .ge In VIIOL Input. R ESET. 1 C lK. I Act ion C lK ' _ f ALSE fALSE f ALSE Un<pe<:ihtd PALSE PALSE T~U E Unspecified PALSE T~UE FALSE Un'peciikd FALSE TRUE T RU E Q <= I) T RUE circuil. Since Ihese a re all o f the compo" cm, o f a SC'luc nli., circuil al l he . Ia lc d iagram level. the d esc,iplion is c omple te, The use o f t hree dislincl proces ..... ' is only one mClhodology for s e'lucnlia l circuit description, P airs o f p rocesses o r all l hree processes c an I:>c c o",bined for more c lega"l d cscriplions N e"(,lhciess the th ree process descriplion is Ihe easiest for n e .... u sers o f V H D L a nd a lso works well wilh . ),"thesis l ools To synlhesile the circuil inlo aClual logic. a stale assignmenl i , occded. in addilion 10 a lechnology library. Many synthesi, lools will m ake Ihe " "te assign menl independently o r based o n " directive from Ihe usc,. I t is al""l)O';sible for I h~ user t o ,pccify exp li citly Ihe ""IC . ... igomen!. T hi, Can I:>c d one in V HDL by . .. ing a n e numeration Iype, 'The encoding for the state machine ;n Ftgures 6-32 and 6 -JJ Can be specified b y addi ng Ihe following . fler tl><" t yp41 s tll te~t~ declaration: a tt ribut . I Ittributa t~ h enum~" ncodin\l ' "nu~eneoding ' 00. 0 1. 1 0, ~crin\l' of 8tllce~ type : 11 ' , This is nol a 51andard V HDL c onstruct. b ut i1 is recognized by m any . ynthesis t(K A nother o plion is not 10 use a Iype d ed aration for t he Sla tes. but t o d eclare lls.. the slate variables as Signals and use Ihe act ual codes for lhc ~ 1"l es. 10 ' his Case. i f n ales a ppear in I he simulalion o ulput, Ihey will a p pear as Ihe encoded Slale ~ aTu cs. 6~8 H DL R EPRESENTATION F OR S EQUENTIAL C IRCUITS - VERILOG In a apler 4 , Veri log " 'a, used 10 descrilx combinnl;onal circuils. Li hwi$C, Vcr ilog c an d escribe ' torage e lements a nd s equential circuits. In this . .., ion. descrip lion, o f a posi\ive edgetriggered 0 Hip .flop and a S<XJuence recognizer circuil iIIuslrate such uscs o f Verilog. These <lC5cript;on, ,,;11 involve new Vcrilog concepls the mnsl imporlant o f " hich a re Ihe process and the r egi'ter Iype for nels. Th us far, conlinuo . .. as.<ignmenl SI.lementS have been used t o d escribe c om binations o f conditions a nd actions in Vcrilog. A c ont;nuons assignment statemonl 2 92 0 C HAPTER 6 I S EQUEN'TlAl C IRCUITS is li mited in what can be described, howe"er. A proceJS can b e viewed a , a replacement for a continuous assignment Statement that pormits considerably greater dcscripli ". powe r, Multiple p r""",sse, may e xecute concurrentl y a nd a process m ay executc C(l ncurrently wit h continuo us assignmem statements. Wit hi n n p rocess. p roced ural assignment stateme nt $. w hich are not con li nuous assignm ent" ore used , Beca use o f Ihis. Ihe assigned values ne ed t o b e retained o "er lime. This retention of information can b e ac ~; eved by us ing l he register t ypo rather lhan the wire t ypo for ne t" T he keyword for the register t ype i , r a g . Note that just beca use a n N is o f t ype r e ll dOC$ n ot m ean lhal a n actual register is associated wi th its implementation . T here arc additional conditio ns that need t o be present to causc an actu al regisler 10 exist. There are t wo basic Iypes o f processes. th e i nitia l pn:w;ess and Ihe a lwa y. p~ The i n i t i al process execute, o n ly once, be gin ning at t _ O. T he a lwa y . process also executes a t t J ). b ut executes repeatedly thereafler, To prevent " 'mpa nt. uncontro ll ed CXecutiOll, some timing control i , needed in the form of d e lay or event_ based wai ting. The ' operalor followed by an integer can be used to specify delay. The o opera lor can be viewed as -wai t (or e "en t" @ is 10110,,-00 by a n expression that describes lhe event o r events the occurrence o( wh ich wi ll ca U the process to execute. 5e T he t.ody o f a p r""", ss i$ like a se qu ential program, T he process begins wi th the keyword b eg i n and e nd, wilh the keyword a nd, There a re procedural assign . ment statements thaI make up lhe t.od)' of the p roce . .. These assignment Slate ments are classi fi ed as b locking o r non block in g, Blocking assignm ents use as t he assignment operalor and nonblocking assignment. use ~= a , t he o porator. B lock ing = 'g"m.lUs are executed s equent ia ll y. much li ke a program in a pro<:ed ural la n guag~ such as C. N onb/ock ing assignments e \'aluate the ri ght -hand si d e, b ut d o not make the assignment until a ll right_ha nd sides h a", been evaluat ed , Blocking assignment. can b e il lu st rated by the following process bod y. in which A. B, a nd C are o f type r eg' g b a g in B = 1 \; C ~ B; .~ The first statement t ra n sf~rs the conlents of 1\ in lo B. '(he second statement then transfers t he new conten ts o f B into C.At process compiction . C contains the original contents o f 11. SU PfX'I'C l hat Ihe same process body u ses non blocking assignme nt s: b agin B < = 1\ ; C <~ B, .~ Th e [;,,;t stateme nt tramfers the or igi nal contents of A into B and the seoo<1d statemenl lransfers the original contents of B in10 C. A l p "'""" completion. C contains the origi""I contents o f E, not t hose of I \. Effective ly. the t wo statement have exec ut ed concur_ rent ly instead of m seqUCTlU! . Non blocking assignmenl5. exce pt in Ihe cases in wh ich we want registe rs ( of type r eg) to be "\'al ti ated sequentially. " i ll be used . t :XAM I'I. E 6-7 V~ri l og fur l'o l iti "".Edg~ . T rigge",d 0 F lip . ~lop . .i th R es~ 1 T he. e new ooncept. Can nOw b e applied 1 0 Ihe Verilog descriplion o f a positive e dge triggered D nip ~op g i.en in F lgure 6-34. T he m odule and its i npms a nd o utputs a re d eclared. 0 is d edared a . o f t ype r a w s ince;t w ilillore i nformation. The p rocess begins " 'ith the keY"'ord a lway . Foliowing is . ( po.Kg_ C L K o r p o.KWa RE S ET) This is Ihe ~>' ~m c om,o/ Slalement f or the pH>ce SS t hat ini. tiates process e xecution if a n e vent (i.e .. a sp<:cified c hange in a 'p<:cified l ignal occurs). For the D flip-flop. if e ither C LK o r R ES ET c hanges t o 1, t hen the process is e xecuted . I t i . i mport a nI t o nOle that the event c onlrol s talemenl is n ol a p ara m eter IiI! oontaini"8 all input$. For e umple , D d oes n ot a ppear, since a c hange in ilS value c annot i niliale a ~ible c hange in Ih e value o f O. Following Ih e event oontrol <lalement a t I he beginning o f I he p rocess is the ke}'word b eg-in . and a t Ihe e nd o f Ihe process Ihe k ey"-ord a nd a ppear . . Wilhin Ihe body o f Ihe process.l hcrc a re addilional Verilog oondil ional structures I h.t can a ppear. N otable in the Figure 6-34 e x.m ple is ifelse. T he g ene,al structure o f an if-else in Veri log i , i f ( condition) b ewin p rocedur a l 8 tatements aDd ( . 1 i f ( condition) b eg-i" p rocedur al s taterne"t. a nd ) ( .1 b ewin p r o cedur al s tatements a nd) If Incre i , a single prO<:<!duc'l <la tcment, then the b egin and a nd a re unnecessarY' i f (I'. a al) o < a K; a l.a i f (II a . . 0 ) o <a Y; <a Z; a l .a o N ote that a d ouble e quals . isal i . used in oond;lion .. I f A i , 1. then Hip _Hop 0 is Ioad<:d ""ilh Ihc o o",.nts o f x. If A i. 0 and B is O. t hen Hip-flop 0 is loaded wilh thc c omenls of Y. OthcTVI-i. ., 0 ;' loade<.! " 'ith I he c on'enlS o f z . T he e nd re. ult for t "" four oombinalion of values o n A and B is 0 O. O. , , 0 0 Q <> Q <- , , , a p.-oceS$ is similar in .ffeel to the oonditional operalor in a T he ir...,l se wilhin L L 0 Q <0 Q <- o ominuous assignment , talemenl introduced earlier. 11le conditional o perator can be used ,,-ilhin a process. b Uilhe if-else c annot be used in a o ominuous a . . ignmenl " alem<:nl. 294 " " 0 Cl-l"'I"T~R. ~ I S EQ UENT I "' ~ C IR. CUITS _ iUYII-EI:t,;,oo-Trlwered 0 F lip-FlOp w ith R eset, v .rllOll I 'I'OCeM D MCrlpdcn _ 1 . d fLv(CU>. J U:SrI'. D. 0 1, i ...... ~ C U<. RRSKT. 0 , ou~P"t Q; r..;o Q , a l_y ( po . ..." . CU< o r 1 '0"411. RI'.S!:l') ! >e"in It ( RESET) Q <_ 0; al Q <_ 0 ; o ing t l G U RE 6-.w v..;"" I"roo:e>o I b<:rip''''"' o r " """"",-Edp-Tn"""", FI.... t l"p , ," R.,... More complex colldi tiona l eXlIlion o f ' 1 8tcmcn l$ con be For u ample . ....'c might ha" c acbie~ by nCS t Ir~1,;o, ~ru(1ur cs. " " .-" " 0 " .1 01 W, .- " "" 01 .1.. " 0 ."is associ.led ,,'ilh the clo!;al In t h;' l)'pe o f $ltU<tllrc. a n 0 .1 0 .- el. . i f p rccedinl ll Ihat d oes nO. a lready ",",.., a n . 1 . l ltc e nd resu ll for l he e ight combill8lions o f values o nA.B_an dC is O O.. o.. , 0 O O. , 0 ,, o.. , ,. , , , , O.. , 0 O , , , ',.. , , 0 '. .. , , 0 <. 0 <. 0 .0 .w 0 Q Q 0 .. .- '." , , , , w Rel uming 10 Ih e ir d . .. ,n th~ posilive-edge-triggereJ 0 nip-ft<>p I ho ..... n in Fi gure 6--:14 . 8S1iuming l hat a pos i li~e e d le has o a: urred o n e ilher eLK Or RESET. if RESET ;' I . the ftip-tlop OU lput 0 is resel lO O. O1.Mr ..... ise. t M ~al .. e o n D is 110rcd in l he ftip.tIop SO Ih al 0 e<j uals D. D ue 10 the SIru(1ure o f the i r. ....... RESET <:u3 110 I d ominates the clocked to.:hnior o f tlte f ) O op ('ll \L$ing the output Q to 80 to 0, ip.O Similar simple descriptions c an Ite u .ed t o r epresent o ther Oip-nop ty~s a rid Irig. gering approaches. E XAMPL E 6-8 Verilog for the M ilU e nte KctOK ntur A nIOfe complc~ example in Fo g"", 6-35 repreioenlll t he sequeooe real8nir.cr 1Iale d ,a. gram in Figure 6-U(d). ' llle arehitocture in t his dc:5<:riptioo consi5I. o f Ihroe d''IIInct " M that c an t lC<"IJte oimultJUleOl&ly a nd ,nl tract via sllarcd !iI,"~1 values. New c oncepti included a . e 51ale e ncoding a nd CDC ~ Iat~""'n ~ for handling r ondlhoM I '"' In Fi gure 6-35, lhe module a fK,Lre<:_y a nd , "put a nd o utput ~.ri3 b k:l C LK, are d edared for a tat. a nd n e x t_atate. Note th ai . i nce n ext _st a te n eed ,,<.>1 t>e stored. It C<luld also b e dedared a. .. wire. bUI .s ince il is a ss igned wilhin nn a l..-aya . il m u SI be dccla red a s a r eg . BOlh , egiS lers a rc two bits. with Ih e n "'51 significanl bit ( MS II ) numl>cred I and Ihe leasl sIgn ifi ca nt bil ( LSR) numl>cred O. NexI, a name is gi" e n to e lOC h o f Ihe Slal es laken o n Il)' a tate and n ext_.t . . e e. nd b inaf}' c odes a re assigned to them. T h il. c an to.: d one " ''"II a p arameter sta lemen l o r a c ompiler d i.ecl ive o S.UI1II . We ... 'ill usc the para mete r $I.lemenl.li~ t he "-,mpole. di.-ective <tulres a ..ome",'hal inconvenient to.:fore e ach Slale Ihrou&hOut t he d eKript ion. F. om the diagram in Figurc 6-24(d). the statc:s a .e A. n. C, a nd D. In addItion . the parameter S1lllemc n l! givc the . ta te co,k'!l assigned to " "" h of these sta les.. The " Ota llOn u sed 10 deline the " nte coJe:oi is 2 ' b followed by Ih e bin ar y c ode. T h e 2 d~nOl c, In nl Ihere a rc Iwo bilS in the c ode a nd Ih e ' b d enotel thaI the h a $(> of Ih e cOOt given i. bi n,,,),. The ir...,l"" (",ilhout us ing the e l"" If) mak C$ a I...o-way dcci>ion based on ",h elher 8 condilion il T R UE o r F ALSE . t o ronm' ~I, lhe 1;11"" Stalemenl can make a multiway decision b ased o n "'hich one o f a number o f s talemenls II T R UE. A simplified f orm for I he generic < tie 51.te"",nl'$ e e e xpre l on t ca a xpe a lon : s tatement,) RESET. x, Dn d Z a rc d eclared. Ne xt , regi,;le" . nde in which Ihc lor . ..... I ) represent one Of more ouch entries.. T he c a ae e x pr euio n must hove " .luc l lh "t can be laken o n by ign,, ] of the I)'I>C u >c d in . apr e a aio n. l ypic lI y. Ih ~re a rc s equences of ",ullipl e . . a te ments- In Ih e c nm plc In Figure 6-35. the nose . t. lemenl for the next $Iat c function mak es. " '''''''''ay dec;";on basal o n the currenl slate o f lbe circuit. A., B. C, o r Do For each o f t he c a . .. expressions. conditio,,"l St.l~mc n l5 o f various t)'JII'$ a re....,d t o m ake a bInary deci$;on b asro o n .... h ethe. ,"pul X i . I o r O. Nonbloo;king _ i", men. s.alem entS a re t hen uocd to assign the nexl " ate b ased on t he eight p ossible combinations o f s tale "8Iu~ a nd input value. For e xample. consi<Ie. the uptC$Sion B. If X ~qual. L. Ih cn ' he next " ate w,] 11>c C: if X e qual. O he n the next Mate wiLl . b e I \. "[lo is c orrespond. 10 tile Iwo I rans i " o n ~ OUt o f " ,a te B i~ Figur~ 6-24(d ). With this brief introd uction 10 Ih e " '!"' , Inlement, the " ,'crall ""q ~ encer rerug ni zcr can now be undc~t"od. Each of Ih e Ihree procc!>SC' h as. di<1inCI fu nclion, but 2 96 a C HAPTER 6 I S EQUENTIAL C IRCU ITS I I _ n e g ~i2~r, Ve ril .,.. Proc~~~ D e$CripHan I I ( See F i.".,u 6 _241dl f or . tat. . d i"'ijrarnl _ u h " ~ _"(CLX. R ES'"", x , Z I; i nput C LI( , R ESEI'. X ; o utput Z , r . g [ 1,01 . tat@ , next~tate ; p a r _ t u A _ " 'bOO, B _ " ' bOlo C _ Z 'blO , 0 _ " 'bll: r e" Z , lltc>l-,~. poo; iti ~ e d\Ie - tri!N=ed / 1 . ta t e . tor.".., w ith asynclY<anooo. n _t . / I s tate r ""i O< eI ' a lway ("" . . 4 " . e LK o r " " . _ . IU!.5ETI " ""'in i f ( RE= __ 11 , tat e <_ ' " .h t at" < _ n ext...:!Ute , o~ I I ~~ a ~a~g f unction, imp 1 ~t 8 f f o f X a nd . taU n ext . t . t f unction a l . .. y (X 0:< ~ tau) boI"l1> c a . . ( at~l " ~--" " " _. ~~U ", " " . nde . .a H _ ~ O .1 . . . taU <- .- (X) nexC ~ t.o.U H (X) n=t~ tate U ( X) tl.e>:t~tate "' "-- --- C;d " "",--"u te < _ A ; C ;du """~_~ taU < _ 0 ; B , d . . ~t_~ UU < _ A : o~ I I o utput f unctiC<l' i '1:>h.,.>n' . o utput!lS t unc tiC<l I I o f X a nd s u te a lway ( x o r s t a t el .,,, -- b oIgin < 0 " l oUt"l , 0, 0, <- 0 , " " , , ,,, <<- 0, . nd<: . . . o~ . '-"'Ie o t ' IG U RE fi..35 V<riloj: Proc"s> Dcscripli<Mt o f. Seq""""" R ecOin;,,, 6-S I HlJL Rep'. ..." '''''''' for Seque"tial Cir<ui'o-V"dJ.,., 0 2 97 the processes interact 1 0 provide the o wra ll sequ .. ~c e recognizer. The first l " ocL'" describo. . the slate register for , loring the sequen"" recognizer , ta te. NOle t hat Ihe . description resembles t hat of the positi"e-edge -triggered Hip -fl op. There arc two differences, howe,er. F im . there arc 1 "'0 bilS in I he slate register. Second. Ihe slatc that r.,,;ull. from appl)'ing R ESET is Slate A rather tha n stfile 0 , T he first process is Ihe only one o f the three processe<l that has ' torage associated with il. T he second p ,oce. . d escribe. t he next s tate f unction", discussed earlier. T he e yent cont rol " alement contains signals x and s t<tte . In genera l. lor describing combinational logic. all inp ut ' m us t a pp"ar in the e ,'ent control slate me nt. since. , ,'henevcr a n input changes, t he proce. . must b e e xecuted. The fi nal proce", describes I he oUlput function and uses t he . . m e <a . .. <lale menl f ramc"'ork as in the next s tate fu nct ion process. Instead o f . ssign in g slate names. ,'alu e, 0 and 1 arc assigned t o Z. If Ihe value assigned is the s.1me for b ot h valu . .. 0 and 1 On x. n o condition al s latement i , n eeded, so a condilional s tatement a pp"ars o nl y for stale D . I f there are mult ip le input ,ari.bles. m ore c o mplcx if-else com bi notio ns, as ill us trated earlier. can be used t o r eprescol t he conditioning o f t he o utput, o n the in puts, This e. . mple is a Mealy stote m .chine in which the Out p ut is a function o f t hc circuil input s, If it were a Moore , late mac hi ne. with the outpul d ependent o nly on the state. inpul X would not appear On t he .." c nt c onlrol S1alem~ n\ a nd Ihere would be n o c onditional siructures wilhin the c ase SI.lement. T here is a commOn pilfa l! p resent ,,'hene,"er an I rel", o r ca . .. s tatement is employed. D uri ng ,ymhcsis, une xpected storage clemems in the form o f lal<hcs o r Hip-Hops a ppear. F or the "cry ' i mple ifcl . .. used in Figure 6-34. Ihis pitfall is e mp loyed 10 &i,'e a specification thai , ymhcs izes t o" fli p. fl op. In addition 1 0 t he two inpul s ignals. R ESET a nd C LK. events p o C LK a nd p o . .,. ". R ESET a re p rod uced. which a re T RUE if t he value o f the rcspeclive signa l change, fro", 0 1 0 l . S<;:leCled c omb in at,on, o f " alues f or R ESET a nd the t wo e vents a re s hown in Table 6 -9. W hene"er RESET h"" nO posilive <XIge . o r RESET is 0 a nd e LK is fixed al 0 o r 1 o r has a negative edge, no aClion is specihcd . In Ycrilog. t he assumplion is d". o T AStE 69 1 II"' I .... ' ;o n o r ge neration of . tonge in Ve ri I,,!; Input l A ction posed~ R~SET , 00 RESET . ' p osedge e LK FALSE FALSE Unspecifie d FAt.5 E T RU E Q <_ D T RU E FALSE T RUE T RUE 2 98 0 CHAPTIJI.. ~ I S CQUlNT l Al CIK C\.I ITS Ihal. for a ny c ombma"oo o f c ond,t,ons ",ilh unspecifi~d octions in i r.flse o r ClO se I t fl .han d SIde o r.n _ ,,,,me nl slatemem . . ill re"...,n unchanged. This is ,,",!ui'alen' 1 00 < _ 0 c a . . ~in! ~\Orage 10 <><:<: u r. ThUs. all comb'nalion~ o r r ondilion, m u. . I~ resuillng IOC lion specified ...hen n o >!orage is ,nl~nded . To p revem undesi rable l~tchCI a nd nip-nop> fr om OCC"urring. for If..,..., tlrUClures, care mll,1 be l aken to i"elude . 1 in all c a sc:5 if stor3ge ;, no. dClorcd. In a t l"" . Intcme m. a der~"h a .cmen. wh ic h defines Wh31 h 'pp"ns for all c hok." nol ' p"ci ficd , hould b e a dded. Wilhin Ih ", defMUIi s takment. a 'peciflc " c~, l .a lC can t>c ~ p"dfied. which in ' h e e ' '''''pl e is . tate A. Together. Ihe Ihree proc ell6CI used fur Ihe SC<l"e nce recogni~cr d cscr il>e t he slate . tUTOgC. the nex. " ate fUncli,,,,. and t he o utput function for Ih e so:q uenlial cir_ cui!. Since Ihese a re . 11 o f the component. o r a se quen.i al circuil 81 the ~I"tc dia gram level. ,he ~iptioo ;s complete. Th e,"" o f Ihr.,., di'tinct pr~ is OIlly o ne melhodology for s equent ia l circui. de>cription. For e um ple. the DCXI , tale and ou tput p ~ could be ea>i ly comb,ned. ~evcf1heless.the three-proceM descripliOl\ is t ~ e asiest for n e . . U SCB o f Vcri"", a nd al!iO works ...d l ...i lh ~yo.hesas louis. ~atemenl$. th~ Ita,.., 6 -9 C HAPTER. SUMMARY Seque nlial circuils a re t~ foundallon upon ... hi~h m06' digital design . . baso..... R ip-Hops a rc Ihe basi<' ~ t o r age e lements for synchron OWl s equen tial circuil" I' hpH op:s a rc conslroctcd o f more fundamental eleme nt s called lalChes. By .hemscl,c.. lalch es are ' ransparc "l and. as a conSC'lu" n" c. arc ~cry difflcul! 10 u"" ill ~y nchr() nO a, ...-quco.i.1 circuil' u,i"S n si "Sic clock. When latches a rc cORl i)in cd to fo,m nip nops. non tr.n sp ",c nl slorage cleme nts ,uy " ", venien. for usc in , uel , circuils arc formed. n,.re arc . wo lriggcdnS mc.hods u>ed for nip no ps: ",a$ler~ ln'e au d e dge trigg~r;ng. In . ddi.ion. Ihcre a re a n umber of Hip-H"" typeli. incl uding D. SII . J /(.and T. Sequenlial circu il' are formed us.ing Ihese ftip.n"!",, a nd <"<>m bin "tionallogic.. Sequential circu,IS can be analYl.ed t o fin d Male lables a nd S1 a.e di"&f1'1IMS . hal rep....,.,nt the beha>lor or.~ circuil" Also. a nalysis can be p erformed by uSln, logic ' ;mula.io n. 1l!e5C same . ta le d,agrams and s 'a le .ables ~a n be formulated from ~e rba l specifieali()!U o r digilal CIrcuits. U y a!lignina binary c odes to.he I .ales a nd finding n,p-"op input ""'!UD liOfll" " ,quenlia] circuilll can b e d esiancd. The d esi", p rocca a lso includes issues s uch.1 find ing logic for t he circuit OUlPUI., r esell;na.he Sl8'e a t power-up. a nd controllong the behavior of Ihe circui . ...hen i. Cn tc,", " ates unused in the original specioca.ion. Finally. logic . imula .ion pla)'s an imporlant role in veri fy ing .h3t the eircuil de.igned meelS the original specifica'ion. As a n . liernati,c.o th e uSC of logic diagmm., stalc diagram .,. "", s.at e ta ble s. sequcnlial c ireuil' cnn be defined in V HDL o r Ve, il og descriplion s. n"!,",, descrip ti ons. Iypica ll y a l . h" bo!havior~ 1 le'cl. p ro,id e a powerful. nexible a PI" (),IIch 10 scquenlial circu,l <pc<: ir"'alion fO I OOih , im ulation and aUIOffi l l i<' cireui. I)"n lhesi . . These rcpresenlations in""l v~ p roces"", Ihal PJ",idc added descrip1ive p o""r b eyond t~ coocu rr~nl aSSJ"'n1~m s.al emcnlS of V HDL and.~ conlinuous . ..." '. mcn l Slate"", nl o f V~rilog. l lw;: p rot"'W"S ... hich permil p rogramhke coding and use "'oI>Ie"" 0 2 99 i f.then-else and case condilional stateme nt s. can also b e ust."<I to efficient ly describe combi nalionallogic. R EFERENCES I. M ,,~o. M. M, Digital Design. 3rd cd, Englewood Oiffs. NJ ' Prentice H a ll. 2002. 2. R onl. C. H . F",u!amenmis a f L ogic Design. 4th c d , SI. Pa ul: West. 1992. 3. W"KERLY. J. F. V ig i"'l D"-<ign : Principles ami Practices. 3rd c d , U pper S addle Ri.-er. NJ : P rentice Hall. 2000. 4. IEEE S/am/aF(/ V I1DL u IIIguage R efem,ce M amwl , ( ANS1/t666 Std 10761993: revision o f 1 6 6E Std 10761937). New Yor \; : T he Inst it ute o f E lectrical and E lectronics Engineers. 1994, S. PELLE RI ,.. D. A)oP D. T "YU)R. V JlDL M ade Easy! U ppcr S addle R iver. NJ: Prent ice Hall PTR. 1997. 6. SrHAN. S. A~D L LI~OIl , V lIVLfor IJe" iX,,ers. u mdon: P rentice Hall Europe. 1 m. 7 . I EEE Stamlim! Descriptio" L ""g"age B asf(' o n tl,~ Vui/uX(1"M) iI'","mT~ Descripfjan u mg.wge ( IE EE $ td 1364-1995). New York: T he Institute of E lectrical a nd Electronics Engineers. 1995. 8. PAU<ITKAR. $, Veri/og H DL: A G uide t o Digiwl Desig~ 01'" S)'lIIhesis. U ppcr Saddle Ri,'cT. NJ: SunSoft Press ( A Prontice Hall Titte), 19% , 9. Ctll;TI1. M __ Ma.leling, S),lIIlIesi.. and Rapid PTotl)lyping willi t"~ Veri/og HOI... U ppcr S addle Ri,cr. NJ : P rentice H all.lm . 10. n IOMAS. D . E ., ANn P. R. M oo R. lV. The Veri/og l-Ia"J "' QTe Oe"'cTiption La~g"age 4th cd, Boo ton : KluweT Academic Publishers, 1998. P RO BLEMS 6 T he p lu, (+) indicate, a more advanced proble m a nd the asterisk ( .) i ndicate, a ~ solution is a ,'ailable o n t he Compamon Website for the text. 6-- 1. P erform a manual M computer-based logic simulation similar to t hat given in Figure 6-5 for thc SR latch , hown in Figure 6 -6. C onstruct t he inp ut s equence. keeping in mind that changes in state for this type o f latch o ccur in response to 0 ral hor Ih on 1. 6--2. Perform a m anual o r computer-based logic , im ulation similar to that gi"en in Figure 6-5 for the S R lotch with control input C in Figure 67 , In paTt ic ular. examine (he bchavior 01 the ciTCuit when S a nd R a re changed while C h a, t he . al ue 1. 6--3. A p opulor a lt ernative design fOT a positiveedge.tTiggere<i 0 fli p- fl op i , s hown in Figure 636. Manually o r a u toma tic.lly , imulate t he circuit to d ctenni ne whethor its f unctional behavior is identical t o that o f t he circuit in F igure6 13. 3 00 0 C H Af'TE1I. 6 I SEQ UENTIAL C IRCUITS Q , Q o 6-4. F IGUR"; 6-J6 Circuit for !'roblen' 6-3 A Sl'1 o f w avef"rm s a pp lied 10 S II ~nd 0 Ilip. llops is s how n in Fi gure 6 37 T hese w aveforms a re a pp lied t o the flip flops , hown a long " 'ith t he " alue, o f Ih eir tim ing p "ramclers. (M ) I nd icate Ih e k:>(:a(ion$ " n t he w av efo rms al which t he re a re i n pul c ombination o r t iming paramc tcr " iolalio", in signal S I f or flip- fl op 1. ( b) Ind ioate l he IOC~lions t h e w ,,,..,rNm s. 1 wh ich lh ere a rc in pul c ombination o r t iming p arameter violations in signal R I f or flip-flop 1. "n S l .l>2 n R l.Dl I " ' ,I ~_ ,I I" 12 ,I 16 I ,I" 20 24 ,I l iI I )2 ~n.) ~~~i ~ ~:=bJ ~:-Q ... _ .o"' t , _ 0,0 n, ~ - L(l". to - O.'! ' " 1, - 1.0", ' . _ ( l .h . o n GURE 6037 W .,cform. a nd Flip-H<>p> 10< Problem 6-4 Problem, 0 J OI (e) List the t im es at which there are timing parameter vio lations in s ignal 0 2 for Oi p -O op 2_ (d) List the l imes at which there are timing parameter " iolations in signal O J for Oip -Hop 3. Violations should be indicated e ,'en if the stale o f t he Hip_Hop is such that the violations will not affect the nexl stal c, 6 -S_ A seq uential circuit with two D fli p-flop' A and B. two inputs X a nd y, a nd o ne o u tput Z is <pedfied hy t he following inp ut equations, D.. _ XA+ XY D B=XA+XB Z =XB (a) D raw the logic diagram of the circuit, (b) D erive the state table. (e) Derive the state diagram. . ... " A sequential circu it h as t hree D flip .flops A , B. a nd C. a nd o ne inp ut X T he circuit is deseribed by t he following input equations: D .. ( BC+BC) X + (IJC+HqX D, A Dc - B (a) Derive the sta te table for the cir cu it. ( b)O raw two s tatc diagram<;..one for X = 0 a nd the o ther for X = l . 6 -7. A sequential circuit has one flip -flop Q, t wo inp ut ' X a nd Y. and one o utput S. Th e circuit consists o f a 0 fli p_ fl op with S as it. o utp ut ,md logic imp le menting the function D _ X WYWS with D a , the input to the D flip-flop, D erive the statc table and , tate diagram of the sequential circuit. 6 -3. Starting from state 00 in the state diagram of Figure 6-19(3). d etermine the state transitions and output seq uence that wi ll be generated when an input s equence o f 100110111 to i, appl ied. 6 -9. D raw tho state diagram o f the s eque nt iat in Table 6- 10. ~in;u i t . pccified by t~ e . ta te table 6 -10. A " 'que n!ial circu it has two S R flip flops. o nc input X . a nd o ne o utput Y Th e logic diagram o f t he circu it is s hown in Figure 6-:J.8 . O~ ri"e t he state table and state diagram of the d rcu it . 3 02 CHAPTER 6 I S EQUfNrtAL C lRCUr rS 0 o T ARLE 6-10 S ta te T .M. ror U rru; t of Problem 6-9 t nputtnput P. ... nt S tate , , , , , " " , " , ,, ,, ,, , "" " , , "" ,, ,, , 0 0 N extS t_ , , ,, " " o o 0 " " 0 0 0 , 0 0 , , OUtput , 0 , , 0 0 ," " " , o , " , " , 6 - 11 . A sequential ciTCuit is given in Figure 6-38. The timing p orametcn fo r the gates and lIip-~ops a rc a s follows, I n"crler I"" ~ 0.5 nS X OR G al e: ~ 2.0 ns F1i p.hop:lpO _ 2.0 nSot, _ 1,0 ns and t, _ 0.25 ns (a) Find the longest p ath delay from an external circu it input passing l hrough gates onl~ 10 an eXlernal circuit o ulp"l. r"" I, C " V , " C " , ./ o FI GURE 6-38 C ;",." f or P robkm ()-IO. ()-11. a nd ()-12 Probl."" 0 J OJ (bl Find Ihe lo ngesl palh delay in Ihe circ ui t from an exte rn .1 input to p ositi,'e d oc k edge. (e) Find t he lo ngc. t path delay from positi,'e clock edge 10 o utp ut. (d) Find t he longesl p alh dela)' from positive d ock e dge to posilive cl ock edge. (~l D ek rm; ne Ihe ma.< im um frequency o f o l"'r" t io n o f t he ci rcuit in mega hen z ( MH z). 6 - 12. R epeal p roblem 6 11 a "u ming thai the circu ;1 cons is ls o f Iwo c o pies of t he ci rcuit in Figure 6-3R wit h in pul X o f the second circu it copy d ri,'cn by input Y o ft he fi rst circuit copy. 6 - 13. A seq uential circ ui t is gi "en in Figure 6-17. Ca) A dd Ihe nCC~8sary logic a nd/or connect ion. t o the ci r~u it asynchronous r = t to , tate A ~ fl. B I for signal Re:se t (b) Add the necessary logic a nd/or connections t o the circu it synchrono us re:set to state A O B 0 for signal Re set _ . & & & & to provide an 1. 10 pro, ide a O. 6 -14. ' D esign a sequ ential ci rcuit wi lh t W0 IJ H Hops A and B and o ne input X. ip. When X = O the sta to o f the circuit re mains t he s ame. When X - l. Ih e . circu it goes through t he s tale t ran si tions from 00 10 10 to II 10 0 1. back to 00. and then rel"'als. 6 - 15. A :seria l lwo's c omplemelller is to be designed . A binary inleger o f a rbitra ry length is prese nted 10 Ihe :se r ia l Iwo's complo ment or . least signi fi ca nt b it first. on in pu t X , When a given bit is presented 0 1\ inp ut X, the corre~pond i ng o ut p ut bit is 10 a ppear during the s ame d oc k t yde on output Z, To indicato tha t a :sequence is c om pkt e and t hat the circuit is t o be ini tia li zed to r ccei,c a nother seq uenc e, in put Y I>eromes I for one clock cycle. O lherwise. Y i , O. ( d Fi nd Ihe ' t ;t le diasr"m for t he s erial ( wos complementcr, ( b) Find the Slate table l or the serial two's complemen ter. 6 - 16. A Universal Serial Bus ( USB) com mun ication link r equire, a circuit thaI produce, the :se quence 00000001. You a re t o design a synchronous seque nt ial circuit thal starts producing this sequence for input E _ I . Once t he s eque nce slarls, it completes. If E I . d uring the l a,1 o utput in the sequence. the sequence repeats. O t herwise. if E = 0, the o u tput remai ns constant a t 1. (a) D raw the Moore slatc d iagram fo r I ht circ ui l (b) Find t h~ , tale table and make a sWte " ", ignme nt . (e) D e,ign the circu it u sing D f!i p ft ops and logic ga tes. A reset shou ld b e included to place t he circu it in the a ppropriate initial s tate at " 'hich E i$ t xam in ed 10 dcle rm i n ~ if the sequencc o r c on,ta m I ' s is t o be p roduced , & 6-17. Repeat Problem 6-16 for the se qu ence 0 11111 10 that i , used in a d ifferent comm ~ nicatio " n etwork p rotocol. 6-IH. +The seq uence in P rob le m 6-17 is a Hag u,",d in a comm unication netwo rk Ihal represents the ooginning o f a me",ag c. T hi. Hag mu st be unique, As a co nsequence, a l m",,1 fiv e l ' s in seq ue nce may a ppe ar a nywhere el se in the lO ~ 0 CHAPTI:R ~ I SEQUI:NTI"1. C IRCUITS message.. Since this is un. ealwic l or n ormal message contenl. a trick called " hidt can contain ! lrings o f , '1 zero.inserrion ; , used. T he oormal Ionge. than 5. e nters i nput X o f a 5e<JuemiaJ z e . o-in"" n iQn circun. l ltc circuit has t ...o o utpull Z a n d S. W hen a fi fth I in . .. quencc a ppears o n X, a 0 is in . .. n ed in t he I rrum Of OUl pUU a ppearing o n Z a nd the o utpul S .. 1 ind icating to t he circuit l upp lying rhe zero- in sertion ci rcu it wir h inpurs t hat il mu<l . . all a nd not a pply a !l eW in pur for one cl oc k cycle. T his is neccs~ . y s ince Ihe in sertion o f O's in I he ou tput se qu ence causes it ro be longer tho" the in p ut s equence wilhout t he stall. Z ero -inserli "" is iIl u llra ted by t he following exa mple seq" cnCC1: _ ge. S equence on XwilhOUt a ny $Ialls: Sequence o n X wilh $laIl1; S equence o n Z: Sequence o n S: 01111100111 111100001011110101 0111111001111111100001011110101 01111 HXXllllll011oooo1011110101 1XXXXXl 1!XXlOOOO1000000000000000 ( a) Find t he s tale d iavam l or rhe circuit (to) Find t he s ta.e t able l or t he cirnait a nd make a Slate _ ""menl . ( e, Find an impLementation o f tlle cin;uit using D H ip-flops a nd logic: " lea. 6 - 19. In m any c ommunic31ion and nerwor king ' y"le m'l, t he oigna ll ransmine d On l he communication lone uses a n onrel u mto-zero ( NR Z) fo rmal. usa ~ a specific version r eferred 10 a ! non rel urn-.o-zcro in verted (N RZ I). A d reui. th ar c on ve rt S a ny message sequence 0 10 ', a nd I's to a 5e<J uence in t he N R ZI fo rm at is 10 be designed, T h e mapping for ou ch a d n;uit is ~$ folloWS: (a) I f lhe message bit is a O. I hen Ihe N RZI fo rm at m """'ge r ontalns"n i mmedi e c hange from I t o 0 o r chan ge from 0 to I . d epend ing on l he c urrenl N RZI vallie. ( h) If lhe MCS$8ge b il is a I . ' h(n t he N R ZI lor mal message rem .ins fixed a l o or I , dependin, o n I he CUrren t NRZ I , -.Iut. This transfonnalioo is illustnoted by t he follov.ing exampLe " 'hieh aSSllm I Mllhe inilial vat . .. of t he NRZ I mCWIge is I: Message: N RZ I Mcs.age: ( a) 10001110011010 10100001000101 Find . he M ealy m odelll a le d iagram for I he circu it. ( Il) Fi nd t he . rale t able for the circu it a nd m ake a Slate a ss ignmenl. (e) Find a n impleme nt ation o f Ihe circuil using D Aip . nops and logic ga les. 6-Zi). + Repea l p rob lem 6. 19, d e,igning a s eque ntial circuit thar tr.nslorm$ a n N RZI mcs ... ge imo a n ormal message. The ma pp ing for i uch I circ ui t is a. follows: l a) I f a change from 0 to I o . from I 1 00 o ccurs between adjlOlX nt bilS in t"" N R ZI m essagc.lhen t he me$$8ge b it is a O. (I I f no m ange o ccurs bet""Ccn adjacent bilS in t he N RZ I message hen the message bil . .. I . l 'robk,m , 0 3 05 L ----' L ' --------------- - o F IGUR E 6-39 S ign. l, fO T Problem 6-21 6--21 . A pair o f s ign als Request (R) and Acknowledge(A) is used to c omdinate t ransaction, belween a C PU a nd i ls I/O !)'stem. T he interaclion of t he,e signal' is often referred to a , a " hand,hake. T he,e signals a re synchronou$ with Ihe clock a nd, for a transaction, a re t o a lway, ha,'e t heir transitions appear in the o rder , hown in Figure 6-39 , A h andshake c hecker is to b e designed that will verify t he t ransilion o rder. Th e checker has input s, R and A . asynchrono us r eset signal, R ESET, and has o utput. E rror(). I f the Iran,il ion, in a h andshake a re in o rd.r. E .. O. If t he I ra",itions a re o ut o f order. t hen E II<:comes I a nd r emains a t 1 u ntillhe an asyn chronous reset , igna l ( R ESET = I) is a pp li ed 10 Ihe C Pu. ( a) Find the . ta te diagram for the h andshake checker, (h) Find the stale table for Ihe handshake checker, M 6--22. A serial leading ]" d etector is to II<: designed. A bi nary integer of arbilrary lenglh is p re"'nted 10 the serial l.ading ] ', d electm, most significant bit first, on input X. Whe n a given bit is p resented on input X . t he c orre'pondi ng OUlput bit is t o a ppear during the , arne Clock c yde o n OUlput Z. As long as the bits applied to X a re O. Z . . O. W hen the fiTht I is a pp li ed 10 X. Z . 1, For all bi t values applied 10 X a fter Ihe first I is applied. Z = O. T o indicate that a sequence is c omplete a nd Ihat the circuit is 10 b e initialized 10 receive a nother , equence. in pUl Y b ecome, I for one clock cy cl e. O lherw;se. Y is O. ( _) Find the state d iagram for the serial loading I's deteclor. (b) Find t he Siale table for t he serial leading l 's d etector. 1i-13. *A , .quent;al circuit has two fl ip-Oops A a nd S , o ne inpul X and one outpul Y. The stale diagram is , hown in Figure 6--40 , Design Ihe circuit wilb D Hip_flops. l i-U A set_dominant masteroslave fl ip-flop h as , .1 a nd r esel inputs. I t differs lrom a convenlional maSler_slave S R Hip -Hop in tbat. when b otb S and R are equal to 1, t he fl ip-Hop i , scI. ( . ) O btain the characteristic table 01 the sci_dominant H _flop. ip (b) Find the Siale d iagram for the set-dominant fl ip-flop. (c) Design the set-dom inant flip-Aop by u$ ing a n S R flip-flop and logic g ates (including inverters). 3 06 0 C HAI'TER ' I S EQUENTIAL C IRCUIT'> o n cUlu: 6-0141 Sto,,, [ )iapam for Prtlbkm 6 -23 6--25. Find l he logic: d iavam l or I he circuil havillg t he ~Iale l ahle &i>'en in l l1ble 6-5_ Use D ftip.1Iops. 6--Ui. +T he Uale lable f or" Iwisled ring c ounler is gi"en in Tab le 6- 11 . T h is circuit has no inpUl s. a nd it5 () ulpUlS a re t he u nc<>mplcment ed o utpull o f t he flip. flo ps. Since it hns n o input s. il , im ply g oes f rom s late t o , Wle wh enever a clock pulse OCI::ur!o'. ( a, I ksign t he circuit u si ng D f1ip.nop" and a "uming I hat Ihe ullSpedfled n ul " .Ic! arC d on 'I-care COfldilion .. ( b) A dd I h. n ttt$Sll.ry Iogie to Ihe . ircull 10 inilialize i llO . Iale 0 00 on p ower-up m a,ler resel. (~) In Ih. subsection "[lc,signmg " 'jlh Unused Slales"" 0 ( S ection 6-S . I I"e e techniques for d uling " -IIh silu31ions in ",hieh a circUlI accidentally e nleB a n u nused . ,ate a re dlscu..wd. l llhe c irruil you d esiylcd in p am ( a) a nd ( h);' used i n. c hild, loy. whieh o f t he I hree techniques &i"en would you a pply? Jusllfy y our decWon. o T ABU: . . t l State Ta.,.. rur P robkm 6-26 .., .., "00 '" ',n " '0"0' '00 P . ..... I St.te N I $ 1&'" n. ,n .n 00' "" Prohl<m. 0 307 (d) Based o n your decision in p art (e). redesign the circu il il necessary, (e) Repeal pari (0) for Ihe caS<! in wh ich Ihe circu il is u sed 10 conlrol engi nes o n a c(""mer cial airliner. Juslify your decision , ( f) R epeal part (d) based On yo ur de.;i,ion in p art (e) . 6 -2 7. D o a manual verification of Ihe rolution (eith er yours o r Ihe o ne posted on Ihe lexl websile) 10 Problem 6---24. C onsider all Irans il io n, wh ere S and R c hange wilh Ihe d ock e q ual 10 0 6-211 . Do an automal ic logic si mulalionba",d verificalion of your design in Problem 6---25. T he inp ul " "quence used in Ihe . i mulalion should i ndud e a ll 1<an,ilion, in Table 6-6. The si mulation outpul s hould indude ihe inp ul X and the SI "ie ~ariab l .-.; A . B, a nd output Z. 6-29. Ge nera le a "er ifi calion sequence for Ihe circuii described by Ih e ' Iate table in Table 6---10. T o reduce Ihe length o f the simulalion "" quence. assume Ihat the . imul;l lor can h .nd le X inpul. a nd use X', whenc vcr possible. Assume Ihal a R esel input is available 10 inil ia hze Ihe slalc toA ~ O. B ~ 0 and Ihat .11 transition, in t hc , tate diagram must t>e e~er<:ised . 6 -30. D esign the circuit specified by Table 6---10 " nd U $C the seq uence from Problem 6---29 (either yours or the one p osled on the lext web s ile) to p erform a n automatic logic simulation_based verifica lion o f your design. 6 -3 1. Ob tain a t iming d iagram similar 10 Fi gure 6 11 fOT a positive-cdge-tri gge red J K Hip_Hop du ring four d ock p u l",$. Show Ihe liming signals f or C. J, K . y, and Q. Ass u m~ thaI inilia ll y Ihe O\1 tp ut Q is e q ual to I . wit h J _ 0 and K _ I for Ihe firsl p ulse. T hen. for successi"e pulse$. J goes to 1. followed by K going 10 0 and then J going back to O. Assume t h.1 each inpul changes n ear Ih e negalive e dge o f the pu lse, . . A lIlil es r eferred to in the T ema in in gp robkm< a rt a.;ailahle in ASCII form for sim_ ~ ulation and ediling on Ihe C ompa ni on \>" cbsite for the lext. A V HDL or Vcrilog w mpilerisirnulator is ne.;essary f or Ihe probl em, o r p ortio ns o f problem, requesling sim ulalion. Descriptions con \ till b e wrillen. howe .. e r. for m an y o f Ihe proble ms witho ul using compilalion or simulation , 6-32. ' Write a V HDL d e",r ipl ion for Ihe mu lt iplexer in Figure 4-14 by using a process containing a case stateme nt ratheT Ihan Ihe contin uous assignmenl stateme nls as shown in Seclion 4-7. 6 -33. Repeal Problem 632 b)' usin g a VH DL prOttS< containing if-Ihen-else , Iate me nt<6-34. + Wrile a V HDL descriplion for the s equent ial circuit wilh the slate d iagram giv en by Figure 6-25( d), Ind ud e an asynchTonous It ESET . ignal 10 inilialize Ihe circuil t o s tale I ni t . C ompile your description. apply an in put $Cque nce 10 p a ss Ihrough e very arc o{ Ihe slale diagram .1 least once. a n d verify the c o rrectness o{ the sl alC and outpul " 'q uence by c omparing the m to Ihe s lale d iagram , 3 08 0 C HAPTER ~ I SEQUENTIAL C IRCUITS 6 -35. W rite a V HDLde$crip lion ( or t he circuit s peci6ed in P roblem 6-IS. 6 -J6. W rite a VHDLde~ption ( or t be circuit s peci6ed in P roblem 6-1\). 6-37. Write a V HD L de$criplion for a J X n egative-edgetriuercd flip-flop "';th clock c Lle C ompile a nd simulate your description. Apply a , .,qu cl1C"e t hat c"",",," all eight combinations o f i nput. J a nd K a nd . tored value Q 10 b e a pplied in some clock cycle. 6 - 38. W rite a Verilog d eKr iption for the multiplexer in Figure 4_14 by llii", a process containing " caSol S tatement r ather t han t he c onlinuo us assignment stalemenlS as shown i n Se<:tion 48. 6 -3 9. Repea t Problem 6-38 by using a VeriJog p roce. . c ontoining if...,l"" statem..nU. ' -40. + Write a VeriJos de$CriptlOn ro< t he sequential circuil a i"en b )' tile Sla te diagram in F ljure 6-2S(d). I nclude a n M)"DChronous R ESET signal 10 initialize tile cirruil 10 $ late 1 nl t . C ompile y our d exription. I pply I n i npul seqnel1C"e 10 pall throua.h e~ery a rc o f t he . ... t e dialVam at leasl once nd ~erify t he (Ofrectnc:ss o f t he S I.le a nd o utput s equence by c omparin, t hem 10 the S I.te dialVlm. 6-41 . W rite a v~riloJ description for Ihe ~irruit specified in P roblem 6- IS. 6 -4l. W rite a Verilog description for I he d rcuit specified in P roblem 6-]\). 6-4J. Write a Verilog description for a J X n egative-edge_triggered flip-flop with clock e L K. C ompile a nd s imulate your description. Apply a s equence Ihal causes all .i&ht combinations o f inputs J a nd K a nd n ored v8lu~ Q to be a pplied in s ome clock cycle. R EGISTERS A ND R EGISTER T RANSF ERS n C haplers 4 and 5 , W i! s tudioo combinabonal l l,ll'lCt ional b locks. In C haple, 6, we " xam i r>ed sequootka l "'<cuits. In this c hapter. we tHing I he two Kloos togelhe< at'l<l p resent sequent la l l<.>rdional bIod<s, ~""ra l ly ref. . " .-d 10 a . r egisters arid c ou nters. In C hap ter 6 , 111& e irellits 1 M! were "r>aiyzed o r <le6igned did r>Ol haVO:> a ny p atticu lar $lrucrurn. and 100 n umber 01 nip-flOpS w as q uite sma~_ In c ontra.t, t he cit'(:uilS we consider h e", ha1/9 more Sln.octure. with multiple sta~s o r ce~. t hat a re i dentical o r d ose t o iOOn t k:a1. A I$O, b eca uw o j !hIs st'llCIure, ~ i s e asy to acld more sla~. to ~ circuits w ith maR)' " ""e fl ;p. lk>p6 than ttw circu it s in C~t er 6. R egistors are particularly useful 10, stOfing information during !lie proces.sing o f d ata a nd countars a s,""! in s eq .... r.ci"ll t he processing I In a d iQiIaJ.ystem. a dalapath Ur>;! a control " "it a re Ir9Quenl!y Pfesent at the top 0 / t he cIe'ign hiemrct1y. A d 8lapalh oor>sisl$ o f process;ng log'" a nd a coIl9CliO<1 of r<>gistars that parlor"'" da ta ~e$$ir>Q . A control u nifis made up o j k lgc that d etermines IhfI s equence 01 d ata'processi"ll opera ti O<"l$ per'lormOO b y too datapath. R 09is!e, tra nsle, nota b"" d escribes ek>menta ry d ,'tap,<)CeS$O~ " " tOons referred t o as micrr:>op(1rafioru . Register transfefs m ow ;,,1o<m8t"'" 0 0 _ ~st a"" b etw""n regist o", a nd memory. and l hrough p rocessing lOgic . D edicated l ra~s"', oorc!ware U$ i ~g m u lti ple,a", a nd s hared t ra nster oo,,;tware CA ll ed b uMS Im~ t !tlese " """"",enl$ 01 data ~s In the gIO""ri(; c omp uter at tr.e b9g0 nnng 01 C hapter 1. r eglst e", are u sed .....t "" . .""1)' 10< t empo<a ry storage ot data in areas aside trom m emo ry_ Registers 01 t his kind " r e oftel1large. wi1t1 a t " 'asl 3 2 bits. S pecial registerS c a lled shit! m giSle", a ra u&ed less 1 '8Q"""tly, a ppeari,,!! p'Omarily In t he fnput---<>UIpU t p arts 01 Ir.e system_ C ou nt erS am u5ed in t he varkius pa rIS 01 t he compute r t o con1f~ o r keep 01 the sequence 01 actiV<t ios . CM>ra ll , sequential hJncbooal bk>cI<s are used _ y in tr.e generic compute r. In pa'lictJlar, t he C PU a m F PU parIS o f t hfl processor e ach c ontain l arge rMJ mbers o f registers t hat are involved In regl516' ( ra"""rs a nd e><e<:ution 01 mIC'oope<alions. 1 is i n t he C PU a nd !tie F PU t hat <la ta lransle rs, a dditions, \ sub1factions. a nd othe r mlcrooparalions take >"ace, Finall)', (r.e c onooctions sI>own between va rious e leelfOOK: parts 01 t he c ompute, a re r uses, w hich we <!;scuss fo< t na f l"'t t ime tn this chaptar If""" o JO'J 3 10 0 C HAPTER 7 f R EGtSTERS A ND R EGtSTER l RANSFERS 7 -t R EGISTERS A ND L oAD E NABLE A register i nclude. a se t o f flip _ flops.. Since each flip-flop i. c apable of storing o ne b it of information , an n -bit register. composed o f n flip-flops. i, capable o f s toring n bit, o f binary in formation. B}' t he broadest de fmition. a " giS/a consists of a s et o f fli p-flops. t ogether wit h gat es t hat implement t heir . la te trans it ions.. This b road definil ion includes Ihe "arious sequen tial circuils considered in C hapter 6. More commonly. the term regjsler is applied t o sel o f fli p-flo ps.. possibly wilh a dd ed c ombinalional gales. Ihal perform d al a _p rocessing tasks. T he flip-Oops hold d ata. and t he gat es d etermine the new o r t ra nsformed d ma t o be 1ran.terred int o Ine Hip- fl ops. A co ",,,,, is a register t hat goes through a predetermined s eque nce o f stales upon the application of clock pulses. Th e gatc. in the counter arC c onnected in a way tho t produces the prescribed sequence o f bi na ry s tates.. Although counters are a special type o f registe rs. it is common to differentiale them from regislers. Regis1ers a nd c ounters a re . eq uent ial fun clional blocks thai are u ,ed extensively in t he d e,ign o f d igital systems in general a nd in d igital compuler! in particular. Registe . . a re u .eful for stori~g a nd manipulatin g informatio n: coun ters a re e mployed in circuits t hat . ., qu ence and c ontro l o pera tions in a digi tal s)'Slem. Tne simplest register is a register t hat consists of only flip-fl op" without c~ter n al gates. Figure 7-I (a) shows such a register conslructed from four D _type Hipfl opo;. T he commOn C lack in pUI triggers all Hip _Hop' on the ris ing e dge o f e .ch pulse. a nd t he bi nary i nformation available a t the four D input' is t ran,ferred inlO t he 4-bit register. The four Q o utput, can be sampled to o~ain Ihe bi nary information s tored in the register. T he Clear inpu t goes to the R inpu t' of . n four flip_ fl ops a nd is used t o d car the r egi'ter t o a ll O's p rior to its cklC~ed o peration. This inpul i . labeled C lear r ather than Clear. since a 0 must b e app li ed t o resel the Hip Hops asynchronously. Activation o f the asynchronow; R input' 10 ll ip_ llops d ur ing normal d ocked o pera lion can le ad t o cir cui t designs t hat are highl)' delay dependent a nd that can. therefore. easily n,"[function. T hu s. we maint ain Clear a t logic 1 d uring normal d ocked operation . a ll owing jt t o b e logic 0 onl)' when a s}" t~m reset is desire<l. We note that the abili1y 10 clear a register l O.n 0 ', i , o ption al: whether a d ear o peration is pTo"idcd d epends upon the use o f t he register in t he syslem , The transfer of new in format ion into a register is referred 10 as i ""dil1fi the regisler. I f a ll lhe bits o f the regiSler are loaded simullaneously wi th a common d ock pulse. "'e say t hat Ihe loading i , d o ne in parallel , A positi"e clock lransition app li e<lto the Clock input o f the regisler of Fig ure 7-1(8) loads all four D inpuls into the flip Oop' in parallel , Figure 7 -1(b) , hows. symbol for the regi'ler in Figure 7_I(a) . This sym bo l p ermil' lhe use o f Inc regiSler in a design h ierarchy, T he symbol has an inpuls 10 the logic circuit on its left and all o u t pu1S from the circuil o n Ihe right. T he input' i ndude the clock input with the dynamic indicator to represent positi"e-edge trig_ gering of the flip-Hopo;. We n ote that the name Cleor a ppears inside the symbol, with a b ubble in lhe , ignal line o n the o utside o f t he symbol, T hi' notation indi_ c ates t hai application o f. logic 0 10 the signal line activa te s the d ca r o peration on 7 _1 I R og;'l<n."d l ""d & ubi< 0 3 11 "c :Y0. 0. O c 0. " 0. "c 0, ( b)Symboi " ", I.oo<l 0, ", M ~ C iop""l,l"d i op"" " '-L / oIfi,p-tlops) -( el l<>Od " ",,,01 ioput " ( a) L ope d i'vam o t 'lGUM t: H 4 Bi, Regi'[er ( he fl ip-flops in t he register. If t he signal li ne were labeled outside {he symbo l, (he l abe l w ould be C lear _ R egister w ith Parallel L oad Most dig it al systems have a m aster clock generalOr t ha t suppl ies a c o ntinuous tra in o f clock p ll lse, pul,e< a re a pp li ed t o al l flip-flops and registers in t he '11", h~""l l hal s upplies 8 c on sta nt b eal t o all p ans o f 1h c system . For t he d esign in F igure 7-1 (a). t he d oc k mil", b e p revented from reaching (he doc~ inp ul t o the d rcuit i f 1hc o ontents of the register a re ( 0 be l eft un changed. Tllu \., a s e parat e con trol signal ;s u sed t o c onlrol t he s ys tem . In e f f ect, t he m aster c lock a en l ike a 3 12 0 C H AI"fER 7 I RJ;(;1 S'Tt;R$ A N D R EGISTER 1RANS F ~ cloc k cycles during ,..hich clock pulses a re 10 h. ..e a n effect o n I he rcgisler.1 ... c d ock p um a re p revcnl ed from rcaching Ihc rcgi:sler "h~n i t. r onlenl is n ~ t o be c honged . This approach can be i mplemenled wilh a l oad c o nl rol inpul LOdIf c ombined wilh Ih c clock . .. shown in Figurc 7 -1). T he oulPUI of Ih e O R 1 "le is a ppli ed 10 the C inpUIS o f the regi'ler n i p_ ~o p<. T he equ3lion for Ihe logic , hown is C ;"1"'" - Loall + C loc! When Ihe J.,..a" signal i , 1, C lop"'. _ Clod<. s o Ih~ r egister;5 clocked normally. a nd n n, information is t ron.ferred inlo the register on t he po<;ti.e t ransilion. o f lhe clock. Whc n lhe 1 ..0<1'/ ,ignnl I t O. C i"pUlS _ L ....r, lh Ih;, oonstanl i npul applied. Ihere a re no J>06>I ...e lransilions on C i npuu. so l he c onlenl. o f lbe register remain unchantcd.l"hc c ffca o f l he l..o<Id .&ignal o n Ihe signal C u rpuu i llho"-n in Figu", 7-1(d )_ Note Ih311he d oc k p ulsa Ihal a ppear o n C "'PillS are pulses , o O. which e nd " 'Ih lhe ~illvc e dgc Iha, I rigeB lhe ft ip-ftops.1ltesc pulses and..dges appear ..-hen L oad i . I a nd arc replaced by a oonSla nl I when ' -""II is 0. In orller for Ihi' circuit 10 work oorreclly.l..o",/ mu' l be oonSiant a t the o orr1 value. ei,her o o r 1. throughout the in terval" hen C/QC! is O. O ne .&itualion in ,,'hkh I h" OCCUB i . if 1..0<111 OO mCS from a Hip. llop that " triggered on a po<itivc edge or Ct,,,,!. a normal circu ms tana: if a ll H ip.Hops in Ihe .ys lem arc pos i ti>'e~dge n iggcrcd. Since the cI<xk is turn ed on " "d off nl t hc r egi"er C inputs by the u SC o f a logic satc. the l ed",iquc i , referred 10 as c lf"'! 8111j"g. In serting g al'" in Ihe d oc k pulse pal h produtt~ differenl propagolion delays belween Clod: a nd the inputs o f n ,pnops wilh a nd withoul clock " 'ling. If Ihe clock signais arrive a l differenl flip.fIop" o r registe. . a l differen l tinlCt-, c/o.:! . ke... ; , , 'lid 10 exiS-!. B U 10 ha .., a lruly s)nch r""""" S)"Slem. " "C II\U>l e n, ure lhat ~1I I c lod pulses am>.., M lI\ullft_ly I hroughoull he s)'Stem $ 0 thaI , n Hlp-flops Ing. gcr a l lhc same lime. For I h;, rell$On. in roulinc < ksignl. control o f tbe opcmtlOfl o f lhe regisler ""Ihoul using clock p l10g is -.dvlsable. O lhe .... ise. delays be conlro1led 10 d ri,e Ihe clock skew . . d "", t o n ro as poosible. ThIS is applocablc in aggreui>'e low """'-c. o r h igh s peed d cMgnl. A 4 -bit register ",ith " oontrol input L oad t hat is dir l ed Ihrough l "le$ iOlo Ihe D i nput. o f I he nip.flops. ,n5lead 01 throogh Ihe C in pu ts, i . s ho"n In I ~gure 7-2(c). This r eiister is b ased On 3 bit cell shown in Figure 7 .2(a) c o n.isting of a 2-to l multiplexcr a nd a / ) fllpnop. The . igna l E N selects b etween the dot~ b il D c ntuiog th e cell a nd Ihe v~lue Q a l Ihe o utpul o f the cell . For E N . I . D i. selecled a nd t he cell is l oaded. For E N _ O. Q i . se lected and the OU lpot i. loaded back i nto I he fli p.Hop. preser~ing ils c urrenl . tale. T he f udhack eO M ,lio " from o utput 10 i npul of Ih e flip nop is n ece.sary because the D Hip . fl op. u nlike o lher flip-Hop l yl'd d oe s nO l h ."e a " no change i nput condil ion: Wilh each clock p olse.l he D , nput d ete rmines t he nexl slale o f tbe OUlput . To l ea.c the o u lpUl u nchanged. it is ne<"CS$Ary 10 m ike Ihe D i nput e qual 10 , he p rescnt valuc o f t he o utput . T he logic in R ,urc 7-2(1) can b e vl",,-cd as a " " .... I f!'" o f D f lip-nop.. D PIP -Pop ...ilh e""bl~. having the s ymbols"",,n in F igu", 7_2( b). 11\"" - - -- -'co--"' =--=--=--=;-- , - --=-- - E~ : e ', 0 y -,j ....>-rr> flop-l'Iop ... ;,~ . ... b!< o , ----------------------,., ' ----- '" - 0 "e - 0, "lOS -"'0) 0, o. 0 101< e 0, "N E e o n GUKE 7_ Z 4 _B it R egi"cr ,"';Ih 1'. ... n.1 Lood The regiSleT is i mplemented 1:' placing four 0 flip.~ops with e Mbles in paral lei and coonce!ing the LOdd inpm 10 the E N input .. Wh en LOllli is L the d ata o n (he four in puts is t ransferrod into ' he register with the n Ut positive cl<x ~ e dge. When LOll" is O. the curre nt value r ema in . in t he r egiSler.' the next posit ;'-. cl ock edge. Note that (h e d ock pul. .. a re a p plied cont in uously to Ihe C input>. L oad determ in e, w bclhn the n e.! pul.., a =pts new information Or leaves lh ~ in form. _ tion in the regisler intact. T he transfer of 1oforn,a!;on from lopulS 10 regisler is dOlle simullaneousl)' for all four bit< d uring a single posit;," p ul'" t ramition. This m ethod of transfer ill traditionally preferred o ver c lod gating. since it ~ ,'oids clock ~ k ew a nd t he potential for malfunction s of t he circuit. 7 -2 R EGISTER T RANSFERS A digita l '~'ste m i , a sequential circu it made up o f in terconnected Hip-Hop. and gates. In C hapter 6. ,,'e learn ed thaI s<:q uenlial CIrc uits can he srxcified by m ean' o f s tate table s. T o specify a large digital system wi th . . a te ta ble, ilvery difficult. if not impossible, because the number of . tales is prohibitively large. To " ,'ercome t hi' d iffIC ult y. digital ' ystcms a re designed using a m odular. h;"rarchical appr<)ach . The .)'Stem is p a rtiti one d into . ubs)'S tems o r modules. e ach of which performs s ome 3 14 0 C HAPTER 7 ! REGtSTERS AND R EGISTER l RANSFER5 fun ction al task . T he modules are constructed hierarchically from functional b loch s uch as registers. COUnters. decoders. multi plexers. buses. a r ithmetic e lements, flip Hops. a nd primitive gates, T he various su bs ys tems communicate with d ata a nd con trol signals t o form a digital s}stem. In most digit al system design >. we paTtition tbe '}'stcm into two tn>es of mod ule s; a dalapalh. which performs d ata -processing operations. a nd a cOll/rol urlit. which d ete rmines the sequence of Ihose o peral ions. Figure 73 ' hows the general relalionship between a datapalh and a control unit. C o"'rol $ignals are binary sig nals t hat aClivate (he varioUll data-processing o perat ions. To activate a se<Juence o f such operations, the c ontrol unit sends t he proper seq uence o f contTol ~ i gnals t o the datapath. The c ontrol unit. in turn. receives status bit s from the datnpath. These status b it s describe aspects o f the slate o f the da tapath . The Stalus bits arc used by thc control un it in defining the specific sequence of the operalions t o be performed. Note Ihat the d atapath and control unit m ay a lso in teract with other p an , o f a digital system. such as memory a nd inp ut-outp ut logic, through the pathS labele<! d ata inputs, d ata outputs. control inputs, and control outputs. Datapat hs are defmed by their registers and the operations performed on bin a ')' d ata stored in the registers. u amples o f register operations are load. d ear. shift, and mum. 'The registers are assume<! to be basi<: componem, o f thc digi tal .ystem. T he movement of the d ata stored in registers and the processing [l<'rforme d on the data are referred to as rtgiilec rrwlSfec opemtiOl", The register (ran,fer operation. of digi tal sy"terns arc specified by the follo"'ing three basic compo""ms: I . Ibe w t o f registers in the s}'stem. 2. the o perat io ns t hat are p erformed on the data stored in the registers. a nd 3. the c ontrolth.t supervise. the sequence o f operations in the system. A register h as (he capability t o perform o ne o r more elementary operarions such as load. count. a dd . subtract, a nd shift. Por c .amp le. a righl-llhift register is. register that can ' hift d ata to the right. A counter is a register t hai increments a n umber by o ne, A single flip.flop is a I-bit regisler that can b e""t o r clcared. In fact. by l hi' definition. the flip-Ho!," and closely associated gates o f any sequential circuit can bt: ca ll ed registers. A n elementary o peration p erformed o n d ata s tored in registers is called a m icroopumion. E ' amples 01 m icrooperations a rc loading tlie c ontents o f o ne Ctoft"ol eon"," _ _ eon"or '"p'''' ~!".t . s,",", , ip.h "n;t D'''J'Oth fJ. ,,r Co , ,of Dot. o utput< ;npu to o FIGURE: ' 3 tnteract ion between D .tapath,nd O :mt!o l Un it DOl. 'K"P"'" register in to another. adding the contems Of two registers. a nd increment in, the c ontent. o f a regil;ter. A m icrooperation is ~sually. b ut not always.. p erformed in parallel on a , 'ector o f bllO during o ne el<xk cycle. T he r esult o f the m icroopera lion may repla~ the previous binary dOln in the register, Alternati.'ely. t he result may be tran sferr~ t o a nother registcr.le~vin, the previous data u nchan,ed. T he Stquential functional bl<xks introduced in this chap ter are r e,isters Htat implement o ne Of m ore microoperations. Th e OOfmol unit p ro.ides signals tha t SoeqOKncc the m icroopention, in a prescrihed manner_ -1 l 'QuJu 01 a c urrent mkroopt"ration may determine ~II the M 5C<juence o f c ontrol SIgna'" a nd the oequcnce o f f uture microopentions t o be u ecuted. Note that the: t erm " mkrooperation." 11:1 u sed here. does not r efer to I ny p ar. ticular way of producing the control .i8."al,; s pifica lly. it d oe, not im ply lhat the control ,i8."31 are gene rated by a c ontrol unit bMed O Il a technique called micro. programmin. . T hi. c hapter i ntroduce. r egi.ters.t heir implementation, and register tran,f"rs u sing" simple register t ransfer language (RTL) t o r epresent " l"te l'i and specify the operations o n their contents. l be register transfer language U!IC$ a Soet o f e xpression. a nd 5tatemenl$ that ~mblc stalemenl$ u>Cd in HDI..I; and p rogramming langl.Lll.gt'S. This notation c an ooncisely 5peCify p an Of aU o Ia r omplu d'gltal system . uch as I r ompu!.r. T he specification then Steves ' " ba$is fOf mOfC d etaiIM dcsi8." o fthc system. 7-3 R EGISTER T RANSFER O PERATIONS We d enot e th ~ rcgi$ters in a digital . ys tem by u ppercase letter< ( wmctim,,! fol_ lowed by numerals) that indicate Ihe funct ion o f t he r egister. For example. a register that h old, a n a ddress for the memory uni! is usually ca ll ed a n a ddress register a nd c an b e designa!<'<I b\' ! he n ame A R. O 'h.r designations for regi.len a rc P C f or pros. .m c ounter. I R rOf i nllrucllon regis!er. a nd R2 for r e,is!er 2_ T he individual fl ip-Ik>ps in a n . . _bit r egister a re ! \l'lcally numbered in 5C<juence from 0 t o . . -1 . t aning wilh 0 in the le "'t .ignificanl ( often the rightm"'t) ]XI"ition a nd increasing toward Ihe III",t significan t ]XI"it ion. Since t he 0 bil is on the righl. I hi. o rder c an he: r eferred to a.IiIlI~_~",lillJl . in I he sume monncr a . for bytes in C hapler I . T he reve rse o rder. wit h bit 0 On the left. is r eferred t o as bill_c",liull. Figure 7-4 shows r cpresentations o f registers in block diagram form, T he most common way t o r epresent. register is by a rectangular box with the n "mc o f I he register in.ide. a . in port ( a) o f t he figure_ '!be indi"id_ uII bitl c an b e Identified a . in p an (b). T he numbering of !);ts repre~nted by JUS! t he leftmost a nd n ghtmost ""Iuell a t the t op o f a r egister bo~ i. illultrot<'<l by a t6-b.t register R2 in ~rt (0). A l 6-bit progn.m oounter. p c, is partitioned into l wo s ections ,n part ( d) o f t he figure. In this casc_ b it. 0 I hrough 1 are assigned t he symbol L ( for 10w-ortler byte). and bits 8 through 15 a rc o. . ig.ned t he symbol I I ( for high-ord~r b yle) T h e label P C(L). which may also b e written PC(7:0). r eren t o t he low-order byte of t he register. a nd P C(I/) o r 1'C(IS:8) ref~rs t o t he high_or~cr byte. 3 16 0 C HAPTER 7 f REGISTERS A ND R EGISTER 1lI.ANSFEII.S 176l ~ 3 2101 (b) lodi,)d u.l Nt> 0 / 8-t>o, re zi>l<' (. ) Re v.'er R \"'------------------------j" "1''---------'"-1'' ----------;" I (e) L --Z~~~,,~~~~I LI~K~(~")==~~K~()~~ ) ",v."" ",v.'<r " ' umbe ,i" 1 0 / 16-toi, o (d) Two _ p." 16- biI F IGURE 7-1 Bloc k Diagram, o f RegISters Da1a tra~sfer from one register to a nother is designated in symbolic form by means of t he replacement o perator (<---) . T h= the S1atement R2 +- Hl d enotes a transfer o f the c ontent' of r~gister RI in to register R2. In o t h or words. the slatement dc~ignales the copying o f the con1ClH, of Rl into H2. T he register RI is referred 10 as t he w urce of the transfer and 1he register H2 as the des/ina/ion. B)' defin ition. 1he CO "t entS of the source register d o not c hange", a resuh o f the transfer: o nly the contents o f the destination register. R2. change. A statement that s pecifies a register transfer imp ii e. t~a! do t .path circuits arc available from t he o ut puts o f t he w urce r egi.ter 10 the inputs of the destination register and that t he d~ s tination regISter h as a parallel load capability. Normally. we want a given trans fe r to occur not for every d ock pulse. b ut only for ' pecif,c va lu ,," o f the control , ign.l . . This can be specified by a cOIu1i1ionul ./alement. symbolized by the if,lre" form if(K , - 1)then(R2+-Rl) where K, is a control signal generated in t hc control unit . 10 fac1. K, can b<: any Boolean function that evaluat os t o 0 o r I . A m ore conci,e I"ay of writing the ifth on form i . This c ontrol condition. terminated I'"lth a colon. symbolize. 1hc r~q u iremcnt that the transfer operation b<: executed by the hardwore only i f K , _ I . E "ery Mat ement wrilten in register tran sfer n o tation presuppooes a hardware construcl for implementing the t ransfer. Figure 7-5 s hows a block diagram that depicts t he transfer from RI t o H2. Th~ " o utputs o f register R I are conn ec1ed t o t he" inputs o f register H2_ T he l ener" is used t o ind icate the nu mber o f bits in the register transfer p ath from R l to R2. When t he width o f the path i. h Ol'n. n i . replac ed by an ac tual numbeL Register R 2 has a load control input that is acti_ vated by the control signal K ,. I t is " ,"umed t hat the sign al is S)'nchlOnized with the same d ock a . the o ne applied to the register. The fli p-flops are "ssum~d to be ]>OSi ti,eedge triggered by this dock. A , s hown in 1he timing diagram . K , is set to I on 7 l I R<gi>l n T..,..{uOpontioo>. " T"nol" " ""''' ~fO ~ 3 17 I 1 " 0 IH " A A I I o , . _~I~'--\_ _ F IGURE 75 Tran,fer from R l to K2 ""hen K, _ I Ihe rising edge o f a d ock pulse a t l ime I. T he n nt posilive transilion o f Ihe clock al lime I + I finds X, - I, and the inputs o f R2 a re loaded ;nlO Ihe regiSiu in p arallel In Ihis case. X t TelUrn, to 0 o n Ih e posili"e clock IrallSilion al lime I + l . s o Ihat only a ,ingle transfer from R I t o R2 occurs. Note that the clock is n Ot inC luded as a variable in Ih e register transfer SlalemenU. I t is assumed l hat all transfers occur in response t o a d ock transition. Even though the c ontrol c ondition X , boeoomes aClive a llime I, t he &ctual t ran,/er d oes nOl OCCUr until the register i . I riuered by the next po!>itive , ,,, . .. ition o f the clock, a ttimel+ I . T he bas;" s)'mbol, we use in regisler transfer nOlalKm a re li sled in l able 7 \. Regi<ters are denOled by a n uJIPCrcase leiter, po!>sibly foll"""ed by o ne o r mo,.., uppercast: leltcrs and numeral$. l 'arenthe se, a re used ro d enole a part o f a register by specifying Ih e range o f b in in the regiSler o r by giving a symbolic name 10 a por rion of the regiSler, T he left-poinling arrow d enores a t ransfer of d al. a nd Ih e direcliQll o f t ran,fe r" A COmma is used t o t eparale twO Or more register transfers thaI a re eJtecuted at lhe . .. me time, Fo r example, the Slatement X l 'R2 .... R I.Rl .... R2 d enoles an operation that exchanges the c onlcnts o f tWO ,..,gisters simuhaneousl)' for a posilive clock e dge a t which XJ - I. Such an n change is possible with regi ste . . m ade o f Hip -Hops. b ut presents a difficult timing problem with registers m ade o T A8LE 71 8~ >i<: 5 ),,,,,,,1> ror M"1I"" " T ra nsl"cn ' ...... Denotes 0 gl< , e. A ll, R2, DR, III ~ DenOleo 0 p art o f 0 ' .gisl.r Den",. . ' . . n ,l.r o f <1>. . ScPO"'I" .im"ltan..,,,, tron,r. .. Soqu e b rackets Specifi<-> on a dd,. .. fQr m emory R 2(I), 112(7:O),A H (L) R I<-1l2 111_112,112<- 111 D H+-M1ARI Lett . .. (ond nwn<ntls) J>anlh . .... A,~ 3 18 0 C HAPTER 7 I REGISTER.<; A ND R EGISTER'IRANSFER.<; ~ Texlbook RTL, VIII>L, and Verllog Symbols ror Rq;isler Tran,fe.. lUHl T. ., A lL VHDL Vorllog < _ ("'!KuTTenl) < _ (concurrcnt) ass ign _ (non blocking) <_ (nonblock ing) , O ponmon '""' ' , ."" " Combin. . ion.l Aignmenl _ Reg i"er Tran<fer Addttion SuNrtI<tion , BiIWi;c AND BiIW;'" O R BilW i"" XOR Bitw i"" NOT Shift left (logic.1) Shih rigbt (Iogital) A(3 ;O) Veclo""Rcg;.le", Conoalon. . ion " " '"' ., A(3doWJltoO) A [3;Q[ 1. 1 o f latches. S quare brac~et. a re used in conjunction with a m emory transfer. T he letter M d c, ignates a memory word. and the register enclosed inside the square brac~ets p ro,ides t he addr,,",s o f the word in m emory. This i , u pla ined in m ore detail in O lap ter 10. 7 -4 A N OTE F OR V HDL A ND V ERILOG U SERS O NLY A lthough t here a re ,orne sim il ari ties.. the register transfer language us.cd h ere differs from both V HDL a nd Verilog. In particular. there is d ifferent n otalion u""d in each o f the t hree languages. Table 7-2 compares the notation for m any identical o r ' imilar register tra ~sfe r o perations in t~e I hree languages. As )ou study t his c hapter and o thers t o follow_this table will assist you in relating descriptions in the text RTL t o the corresponding de.cription, in V HDL o r Verilog. 7 -5 M ICROOPERATIONS A m icrooperation i , an e lementary operation performed o n d ata s tored in registers o r in memory. The mi crooperation, most often e ncountered in d igital systems a re o f fo ur typ"s: o~e r egi".r to a nolhcr. 2. A rilhmeTic microoperations. wh ich p erform ar it hmetic o~ d ata in regi"ers. 3. L ogic microoperalions, which p"rform bit man ip ul ation o n d ata in registers. 4. S hifl microoperations. which ,~ i ft d ata in r egi"crs. 1. T tamfer microoperations. which t ransfer binary dala from A given m i croopera t io~ may b e o f more than o ne t)p"- Por example. a Is complement o pera t io n is both an arithmetic microoperation a nd a logic microoperation . 7_S I M~...oon. 0 3 19 Transfer microoperations were int rod uced in t he previous s en ion, T his type o f m icroopcration d ocs not c hange the bi nary data b in a s they m o.'e from the s ource register t o t he destinat io n register. The o ther ' hr ee types o f m icrooperat ions Can p roduce ne w binary dat a and. hence, n ew information. In digital systems. basic sets o f o perations a te u sed t o f onn s equence. t hat implement m ore c omp liCllted o perations. In this s ection. we d efine a basic set o f microoperntions. symbolic nOlation for t hese microoperations. a nd d eser;pt;ons o f the digital h ordware t hat impleme nt, t hem. A rithmetIc Ml crooperatlons V.'e define the b ask a rithme tic m icrooperations as a dd. s ubtrnck i ncrement. de<;remen!. a nd c omp lement. The s tatement R1l <----R l + R2 speci fi es an add o pera tion. I t Sla tes tha t Ih c CO nlent, o f register R2 a re 10 b e added t he con lenls o f r egisler R I a nd t he sum t ransferred t o r egister RO. To im pl ement this s tatement with h ard,,are. we need t hree registers a nd a c ombinational component thm performs the add it ion. such a. a parallel a dde r. T he o the r basic arithmetic o perations a re l i"ed in Table 7-3. S uhtract;on is most often implememed t hrough c omplementation a nd addition , I nstead o f using t he minu, operator. we c an specify 2 '. comple me nt , ubtr action by the s tatement 10 RO ..... R I - ~ R 2+1 - ..' here R 2'pcc i/i c> t he I ', c omplement o f R 2.Adding I to R 2 gives the 2 's comple_ m ent o f H2. Finally. adding the 2's complement o f R2 to t he rontcnt~ o f RI is e quivalent to R I - H2. T he i ncrement a n d decre ment microoperations a rc ,ymbuli~"d b )' a plus-()ne and mi nus_,," e o petatio n. respectively. T hese o perations a re i mplemented by using o T ARLt: 7-3 Arithmetk MIrroofoe"'tion, RO .... R t R2 H2 .... R2 R2 .... R2 -1 HO .... Ht + R2 + t R I .... H I + 1 R t<-RI - ! Con tcnt> o f R I p lu. R2 t"''''/cITed to RO Com ple ment of the conton" of HZ ( I', com plement) 2 ', complement 0 ( ti>c content, of R l R I p lu, 2 ', r omplcmcnt of R2 " .n,r.rred '{) RO ( ,uh"o<tion) 1l"lCrcmentl1>c COOtent, o f R I (count up) Deere,""nt ti>c rontents of RI (COIlnt do..'o) 3 20 0 C HAI"TER 7 I R EGISTERS A ND R EGISTER'IRANSFERS aS~iJ ooJJ,oJ corJ. aJL~ullJor. or a uJ6wn Munr n Ie L Mry with parallel load , Multiplication and division are not li lled in Table 73. Multiplication can be r eprel':nted by the s ymbol. a nd division by I. These 1"'0 operations a re not included in t he basic s et of a rithme tic microoperations Ix<:ause t hey are assumed t o b e implemented by sequences of basic microoperations. [n contrast. mu[tip[ica ' tion can be considered as a microoperation i f implemented by a combinational d r cuit as iJl u Sl rated in Section 5-4. [n such a case, Ihe result is t ransferred into a destination register a t the d ock e dge alter all s ignals have propagaled thro ugh the entire comb in ational circui !. T here is a direct relat io nship between the s tatements written in register trans fer notalion and the regis l e~ and d igital functions required for t heir imp[ementa tion . To illustrate. co ns ider the following two stateme nt s: X K] :Rl <---R I + R2 X K , :RI <---RI + R2 + 1 COnlrol ,'ariable K , activates an operation t o add or subtract. [f, a t t he . . me time. c ontrol variable X is e q u al to 0, Ihen X K , = I . a nd the contents of R2 a re a dded t o the c ontents o f R I.If X is e qua l t o 1. then X K , _ 1. a nd the content s of R2 a re subtracted from the c ontents o f R l. Note that the two control conditions are Bool_ ean functions a nd reduce t o 0 when K, _ 0, a condition Ihat inh ibits the execution of both operations si multaneously, " " c ., -( , Ad<i<,Su l>t ,," tO' S eIea(S) C. , C o " ~ f lGURt: 7-6 tmp leme"tat ion of Add . nd Subtract Mkrooperation. " A b lock diagram showing the implementation o f the preceding two . tate m enu i . given in f igure 7.fJ. A n , ,bit adlkr-"Sllbtra<:tor. similar to the one shown in f i gure 5..8 . receiv.s its input d ala from r.gisl . ... R l and R l. The sum o r difference i'l app li ed 10 I he inpub o f Rl . Th e Scle<:t input S o f the adder~ubt ractor selecl> t b. o peration in the circuit. When S ,. O.the two in puts a re a dded. aod when S g I. R2 i . sublracte<l from R I. Applying t M c ontrol variable X 10 the S i nput activates the required operatio n. T he outp~t o f the adder~ubtrnctor is loaded inlO R l On any positive clock e<lge a t which X K , . . 1 o r X K , , . L We c an simplify this to j ust K ,. " mce Thus., the c ontrol variable X sele<:1S the operation. a nd the control variable K , loads the resu lt i nto R L B ased on the discussion o f over fl ow in Section 5-3. the over flo w o utpu t i . t ransferred to /lip-flop V. a nd Ihe o utput carry from I he mo<l significant hi t of the adder-5ubtractor is t ransferred t o flip-llop C. as sbown in f igur e 7.fJ. These transfe", occur when K , . . 1 and a re n ot ",pr~nted in Ihe register transfer stateme n ts; if d esi",d. ,,'e could show th em as additional sim ulta neou. t ran.fe .... l ogic M icrooperalions Logic microoperations are useful in manipulaling the bits < loud in a regi<ter. These ope rations consider each bit in the register separately a nd treal it as a binary vari a b le. T he sy mbols for Ih e four basic logic o peratio ns a re shown in Thble 7-4. T he NOT microoperalion. represented hy a b ar o\"er the l Ourtt register name. comptements aU bits and th us is the s ame as Ihe I 's complement. l be s)mbol " is u5e<i t o d enote the A ND miCl"OClP"ration and the s )mbol ", to <knote the O R microopera. lio n. By using Ihese special . ym bols, it i5 possible 10 d istinguish hetween Ihe add micrOOfJ"'ralion r ep",sent ed by a ... and Ihe O R micrOOfJ"'ratioo . Atthoug.llthe ... s )mbol has two meanings. OOe c.~ n distinguish between Ihem by noting where the symbol occun;. I f t "" ... occurs in a microoperatiOll. it d enotes addilion. I f 1M + " "'urs in a control or Boolean function. il der>Ole< OR. T he O R microopera,ion " ill alway. use the v symbol. R> r example. in the statement ( K, o + K ,): Rl <---- R2 + R3. R4 <---- RS", R6 T A8L E 7..4 '-<>ii< Mk-r oopenllioft. /OO .... Ki RO .... R t"R2 R1l . .. R I",R2 R1l . .. RI EJ) R2 J.oeical " ;".ise NOT ( I', "')f"plemeotj l..ogkaJ bi'wise A N D (<*.rs .,; . . j Logic.oJ bi!wioe 0 11. ( ..,,, b iuj Logica l bi'wise XOR (com pteru en" b iuj m~ I~lLv~ r+. ~!J LU ll O~ ;~I!IIM lL." I~ "JI. '" .~IJ b elw'een R2 a nd R 3 s peci fies a n a dd mlC1"ooperalion. T he O R microopcrnlion i . designat e<! by the lymbQl v b el",e"n regi,t e,s H5 and 1 (6. The logic mitrooperalions Can b e easily i mplemented with a groyP o f gates. o ne for e ach hU p<)5ilion. T he N OT o f a rcgi~l"r b it. is o btained ... i th II N OT g ate. in p;l.allel. The AN D mi<:.ooperalion Is o btained lISing a g roup 0 (" A ND gates. each o f w hirh receive$ a p air o f c orrcspon<linl input'! f rom t he l wo ""UfCC r epsten. l bc o ut p un o f the A ND g ales a re aJlPloed t o the COITesponding i nputs o f lhoe d~lina lion rcgioller.lbc O R and e~chh 'c-OK mocrooperatiorul "''lUI", a similar a rrangemell! o f gales. 111" IQgic mkrooperation~ con c hange b it v alue . . c lear a " ",,up o f bits. o r i osen new b il valu . . into a register, The following u amplC'S show how Ihe b ib SlNCd i n Ihe 16.b'l reg;,ter N l carl be se le<:(ively changed by using ~ logic microop' era!ion and M logic o pera nd slOred in t il e 16 bi! regi't "r 8 2 . The A ND m icroopcralion c~n be used for d~aring Olle more b i" i n" r eg. ister to 0.1 lM: Boolean e quations X O . 0 and X l - X dictate Ihal, , ,'hen A NDed wilh 0 ,. binary variable X p roduces. 0, but ,,-h en A N I>W " ',th I, the VlInabk remaln$ uncMng..d. A given bit 01 group o f bits in r e,"ler can b e cleared t o 0 i ( A NDed " i(h 0, ConSKler Ih e ( ol"",';n, u ample : c ondItion. The "f" <" (010110110101011 < XOJOO:l) 11 I 11 I II < JOOXOX) 10 1 01011 T he 16 bil l o,ic o perand in R2 h u 0 ', in the highorder byte a nd 1 '. in the low o rder byte, By A NDing the c omenlS o f R2 "'ilh Ihe conlcnlS o f HI , il is possible 10 c lear lhe h "h'order byte o f H I and I<:. ..e I he bi!! in the ] oworder b)'te unchang..d, ThU s. the A ND o pcratioo call be used to . .,leclively clear b iu o f a r e,'.IU. ThIS o peration is s ometimes called m . .s king (N" Ihe bots. b ecause it m uh o r d eletes all I ', in t he data in R I, based o n bit po5ition. thaI a re 0 in the n lluk prOVIded in 82_ The O R mlCrooper3tion i . u~ 10 set One o r more bits in a regiSler_ T he Boolean equations X + 1 _ 1 a nd X + 0 X dictates that. when O Rcd with I . the bi ll ury v " ri~bl c X produ ce. a I. b ut when O Rcd with 0, lh~ varia!>le remain. unchanged. A given bil or g roup o f bits ,n a register can be SCI to t if O Red with I, C01lsidcr tile follov.'ing u anl ille: 10101101 10101011 11111111 <JOOXOX) 1111111110101011 " " ( do'.) (m . ... ) RI +- RI,,'l2 The high-ortlcr bYle o f RI is!<:t t o a ll \'5 by O Ring il with all 1'5 in the 8 2 o perand. '!lIe low-order byte relllains , ,"ch""ged because i1 is O Hcd with O'$. T he XOI{ ( e.d usi,'c-OR) mi<roopcration can be used 10 C()llIplCllIcnl o ne o r more hilS;!I a regi.ler, The Boolean cq~ation~ X $ 1 - X alld X $ O - X diclale t ha!. w hen a b in aT)' varia ble X is XO Red wit h 1. it is complemente d, b ut w hen X O Red wi th 0, the variable re ma in . u nchanged. By XO Ring a bit o r group o f bits in r egi.ter R I wit h I's in " , I<:cted positions in R2, it is possible t o c omplement the bits in the se lected positions in R I. C onsider the following e xample: 10101 10\ 10101011 l lllllll OOOOOJOO 0 10 10010 10101011 (data) " " ( mw) R l..-Rl $ R2 T he high.order hyte in H I is c omplemented a fter the X O R operation with I n, a nd the Io,,'-{) . der b yte is unchanged, S hift M lcrooperatlons S hift m ierooperat ions arC u ",d for lateral m o,'ement o f dat a, T he contents of a ~urce register c .n b e shifted either right or left. A I '/I.hifi;s t o,,'ard the most s;g nificant bi t, and a , ig/'I,'hi{l is toward the least significant bit. Shift microoperations a re used in the se ri al tro nsfer o f d ata . They ore .1$0 u ",d for manipulating the c on tents o f registers in a ri thmetic. logical. a nd control operations. The de.tination r eg ister for a shift m icrooperation may be the s ame . s o r d ifferent from the s ource register, W e u~ slrings o f J elten 10 r epresent the ~hift m icrooperalions defined in ' Iable 75. r e nmple. -or RO <- Sr NO, R I <- sl R 2 a re two m ierooperations t hat re;(pectivel)' specify a I-bit shift t o t he righl o f the o f register NO and a t rande r o f the contents o f R2 shifted one bit t o the I dt into regioter H I.The c ontents o f H2 a re not changed by these shifts. For a leftshih microoperation, we call tt>c rightmost hit o f t he ocstination regisler the i ncoming I>il, For a right-shift m icrooper.t ion, we define Ihe leftll106t bit o f the destination register as t he incoming bit, The incoming bit m .y h ",'e d ifferent v" lues. depending upon the t)'llC o f ~ h ift " ,ictOOp"ration. H ere we ,"", ume t hat, for <r And sl. the in coming bit is 0 ,"' shown in the exam ples in Table 75 , The Oil/going b i' is the leftmost hit of th~ $ OUtre regist er for the leftshifl operation and the rightmost bit o f the $ Ou r ce register for the rightshift o per.tion, For the lefl and right shifts shown, t he outgoing bit value is s imply d;oc8rded, In chapter I I. we will content~ o T AHt E75 EUD, pIn . .f Shift, EIg ht-bit omp'" , -" A n ", " "'": D M tI . ... " '" ' " ~""tlo.' . hil, l eft . hill righl R I<'- .I R 2 R J..-srR2 1 0011110 11100101 OOllltOO 0 1110010 3 24 0 C HAPTER 7 f R EGISTERS A ND R EGISTER T ItANSFEIlS 7-6 M 1CROOPliRA T IO N S O N A S INGLE R EGISTER T h i, section co"eTll the implementation of one o r m ore m krooperat;on$ with a s in . gle register a< the destinalion of .11 pTimaTY T eI;UIt . . Thc , i ngle Tegister may a lso ocrve as a s ource o f a n o perand for binary Bnd u nary operalions. Du~ 10 the d ose ties t>clweeTI a single set o f .tOTOgO elements and the m icroope,ations, the combi national logic implementing l~e m icrooperalious is assumed to be a p art o f the Tcgi.tcr a nd is called dedicated logic o f lhe regisler. This is in c onlrasl 10 logic which is s hared by mu lt ipl~ d estination regisleTS. In th is c a.e. the combina1ional logic implementing the microoperations is called sl",,~d logic for Ihe sel o f dc>tina. tion rcgiSlers. T he c ombinalional logic implementing thc microopcrations deserit>cd in l he pre.iow; seclion Can use One o r mOTC function al blocks from c hapter. 4 a nd 5 o r can be d c. igned specifically for the register. Inilia ll y. f unclional blocks w illbc used in COTI\binal ion with D [lip-Hops o r DHipHops wi th enable. A simple technique using mu lt iplexers for se lection i< introd~oed 10 all"w m Ull iple mitTooperat i< ," s " n a sin gle register. Next, single and mul1iplc function registcTll that perform shifting and counting a re designed. Multip lexer-Based Transfers l hcre a re <:>eeas ions when a register receives d ata from two or more different SO urce. a l d ifferent times. C onsider the fo ll owing conditional Slateme n, having an if' ''nl d$~ f "nn if(K, " l)then(R(I .... H l) else i f(K~ " 1) then (RO .... R2) The . alue in register R I is transfer,..,d to register HO when control signa l K , equals I. When K, _ 0, the value in register R2 is transferred t o RO when Kl equals l . O ther wise, the contents o f RO remains uno hanged. ' lhe conditional Slatement may be broken into tWO parts uSing the following control c onditions: T h is specifies hardware connections from Iwo registers. R I and R2, to o ne common d e stination register RO. In addition, making a selection between t wo source regis ters must b e based on . alues o f th~ control variab les K , and K 2 . Thc hlock diagram for a circuit wi1h 4-bil registors t hat implements the c ondi tional register transfer s tatements using a multiplex~r is shown in Figure 7.7(8 ). The q uad 2-to-l multiplexe, sele<;1S between the two source registers. For K , . . I, R l is loaded inlo RO, irrespcctiv~ o f t he ,'alue o f K , . For K, . . 0 a nd K , . . 1. R2 is loaded inlo RO. W hen both K, a nd Kl are e qua l to 0, the multiplexer selects R 2"s the input t o RO, b ut. l>ec,use the control function. K , + K " co n n~cted t o thc L O,\D input of RO e quals 0, the c ontents o f RO remain unchanged. " , " L" ,,\I!)X ru .r "' I ~ '" ( 0) IIlo<k d "V. m " - " " R EG I ITER W.O 1 '" = 1 ''"" = 0, 1- Q, Q, Q, "' REGISTE;1l W '" 0 = ='" ,. , ! -to-l MUX 0 Do 0, 0 '. " " " '" 0, 0, 0, ~ '" = = Q, 0, 0, " " " " " " eo R EGISTER W .O Q, Q (b) 0< . ., 100. o FIG U RE: ' 1 U ", o f Mullipk; n t o S ekd b<;,,.'n T"'Q R ep"e . . T he d etailed logic d iagram fo r the h ardware impleme~l"tion is ~ hown in Figu re 7_7(1J) . Th~ d iagram uses func ti onal block symbols IJ.""d upon detailed logic for the registers in Figure 7-2 a n d f or" q uad 2-\0-1 mu lt iple-c, from C hapler 4 . NOle t hai since t hi$ d iagram rep resent' j ust a I"" t o f a system. I here a r e inputs a nd QUIPU IS th at a re n m yel r onnec led. Also, the clock i , nOI s hown in lh . b lock diagram. but i . s hown in t he d etailed diagram. II is i mponanl 10 rel al e Ih e i nfom,alion g i.en in a block d iagram s ueh a . Figure 7_7(0) wi th Ihe d etailed wiring c onnections in the oor<esponding logic diagram in Fi gu re 77(b )_ In o rder 3 26 0 C HAI'Tl'R 7 I flEGISTERS AND flEGISTEIt 'JR.,<.NSFERS - , , , , , , , , , , , , , ~ '. D e.l;':,,1 "'" " >.::r """ , ., D<docatod R< ~; "'" o , , )- J , -, ... "L 0 . , 0,<1 loti;.:, , . . ,------- , ~~------------, 0<. , M UX H ~ , '" , - F IGURE 7-8 Generalization o f Mu l"pk'Cf SeIe< liOf1 for ~ Source; 10 savc space. we o ften omit t he d etaikd logic diagrams in designs. H owever. it is possible t o ob t ~in a logic diagram wil h d elailed wiring from the corresponding block diagram a nd a li brary o f functiona l block s. In fact, , uch a p roccdure is pcrform~d by c omputer p rogram. u sed for a ut omaled logic synthesi . . The preceding cxampl~ can be generalized by allowing Ihe multiplexer to h ave" SOurce, a n d t hese sources to be register o utp uts o r c ombinational logic implementing microoperalions. T hi' generalization res ~ hs in the block diagram shown in Figure 7-8, The diagram assumes that e ach source is e ither the OUlputs o f a register o r o f combinat io n al logic implement in g o ne o r more microinstruction .. In those cases in wh ich the microopcrations a re d ed icaled 10 t he register, the corresponding dcdic~t~d logic is included as a part o f the registe r, In Figure 7 -".lhe first k sources a re d edicated logic a nd t he 1",1 n - k sources a re e ither registers o r shared logic. T he control signals that sele.ol a given SO urce a re either a single con trol variable o r the O R o f all control signals corresponding to the microopcrations associated with t he source, To force RO to load for a m kroopcra tio n. these control signals a re O Red t ogether to form the L ou,i signal. Since it is assu me d that o n ly One o f the c omrol signal. is I a t any ti me . these signals must be e ncoded to p rovide t he selection codes for t he mu ltiplexer. Two modifications to the given . tructure a re ]>O'S ible. The control , ign.l. could b e applied directly t o a 2 )( n A ND -OR circuit (i. e .. a mu lt iplexer with the decoder deleted). Alternatively. the control s ignals could already b e e ncoded. om itting lhe use o f the all-zero code. so that the O R gate sti ll f orm. the Load signal correctly. Shift Registers A register c apable o f . hift ing its stored b it. latera ll y in o ne o r both d irect ion, is called a _,-hiji T<gisra. T he logical conftguration o f a shift register consists o f " ,-6 I Micloopt ",. .... on. Siooel< R.o&i.... 0 p. e 0 0 p. e >C " >e 0 3Z7 - (b) S ,..,.,. o n CUM.: 79 4 811 Shll. Re. ... e . c hain o f nip-flops. ",ilh . he o u.put o f o ne n ,p'Hop c onnecled t o t he input o f t he nc ~ . nip-Hop. AU Hip-H""" ha ve. c ommon d ock pul'lt: i npul that lCIivat l!S t he .... ift. Th e simplesl possible shift rcgis.e r U K' o nly Oip-Oops. a . s hown in Fi gure 1 9(a ). Th e o utpul o f a , i "c n flip nop Is c onnecle d t o the D i nput o f Ihe fl ip nop al i " right. T he c lock is comOlon t o nil n 'p nops. T he . ulal j "pm 5 1 is th e inpul 10 the lefl mos l fli p. Hop. 11'e seria l aiilpUl 5 0 is l aken from Ihe o utp ut o f the righ tmosl (lipHop. A . ymbol for Ihe Shift , egi"e. is giv en in Fi gure 7 9(b). Sometimes it i , necessary 10 oontrOl llle register SO I hal it shif. . on ly on K lcc I posil;,'" clock edges. R lr t he . hift register i n ~,g u, e 79, t he ' h ift c an be COtItro li ed by c onnecting the clod Ihrough lhe log;c ShlJ"ll in Fi gu..., 71 (c), . .i t h Shil' r eplac inl L uad. Again. d ue.o clock s ke w. t hlt I t usually n ot the " """. ~"'blc a pproac h. T hus.""e l um lat . .. I halthe s hifl o pention a n b e c ontrolled through the f ) i nputs o f t he nip-flops llItller t han ' ''rough the clod: in)JUts C S ..,. REOISTII wmo P .uw.UL LQ.o o If all nip-flop o utput . o f . ....,ft ...,gister ..., aa:es.oible. Hlen i nformalion emered serially by shifllng can be l aken o ul in p aralld from the Hip-flop O1It)JUt <. If a p ara llel l oad c apab ilily is also a ddtd t o. ' hi ft regisler, then d ala e ntered in parallel ClI n be , hifted out ""iaUy. ThU s, s hih r egilt.r wilh accessible Hip- Hop outpulS a nd parallcl Io3d Ca n b e uscd for e onvetting in.coming parallel data to o utgoing ocri.1 data " nd . icc ,cl"S.a. T h e logic diagram f M a 4 1>;1 ~ h i ft rcg ;.lcr w;lh parallel load and the sy ", bol for Ihis regi"~r a re , hol' iIl in Fi gure 7 . 10. lh cre a re two conlrol inpuls, o ne for Ihe s hif. a nd l he o lher for the l oad. E ac h " age o f Ihe r egi'ler COIlsislS o f a D Hip . nOf', an O R gate, a nd t hr"" A ND gat M. n.e fi rsl A ND gale e nables II>e shift u pc , atiQn. The second A N D g ate e nables t he input d ala . The I hird A ND g ale res tores Ihe w n lcn l' Qf Ihe " 'g"te, . . hen n o QPCntion is " "Iui...,d. 3 28 0 C HAI'TER 7 I R EGISTERS A N U "'EGIST~R l RANS FEItS , , , , r Q 'n , ,J ~, />, ~ ~, 0 , , S ilK 4 Shot, ~, ~ " ~ Q J -j , oL)-r Fr> , r;;- , , Q, ~ r;;~, Q, Q, Q, 00 Q, Q, Q, (b)Sy m",~ .- Q, ~ , o FI GU RE 7-10 Shih Rogister wi th Por.lkl Lood The o?<,ralion o f this register is specified in Table 7-6 a nd is a lso given by the register transfen;: S hi/I : Q <-s IQ S hi/f" Load: Q +-D The " No C h"nge' operation is implicit if ne itber o f t be conditio "" fo r t ransfen; is sat is fie d. When both t h ~ s hih and load control inputs a re O. the t hird A ND g ate in e acn stage is e na bled. a nd t he o ut put o f e ach fl ip_ fl op is applied to it s own 0 in pu t. A positive t ran si tion 01 the cloc~ r estores the conte n1, t o the register. a nd the o utput is uncha ngod. W hen the , /li ft inp ut isO and the load in put is I. lhe second A ND gale in e ach slage i . e nabled. and the in put 0 , is app li ed to the D inpm o f the oorrespon di ng flip-flop. The next p<>&itivc d ock transition transfers 1he parallel input d ata int o t he register. When t he , nift inp ut is e qual to I. the first A ND g ate in eac h 7 _6 I Mi<roop<t"""'u O il. Sing!. R egi"" a 3 29 a T ABLE 7.6 .-un <!io n T~b l e f ot I h. Kegi. . o f H g ure 7 10 S hill O peration " " N o oh"n~c l oad parallel d a l> Shill down lrom Qo to QJ ' lage is cn~b l ed a nd the o ther two are di sabled_Sin ce Ihe Load inp ut is disabk-J by the Shift inpUI on Ihe second A ND g ale. we mark it wilh a d on'l-eare condition in t he Shift row of Ihe table. When a positi ve e dge occurs On ' he d oc . the shift oper" t io n causes Ihe d ata from t he serial input S f 10 be lransferred t o Hip-flop Qo. Ihe output o f Q" 10 be transferred ' 0 fli p.flop Q,. ,md .., on down Ihe li ne, N "le t hat b..,eause o f I be way Ihe circu it is d rawn . thc shift occurs in Ihe downward direction, If we r otate Ihe p ose a 'Iu"rt~r l urn c"un1Cr<loc kwi se. t he t egisler sh ift . from left 10 right. Sh ih tegislers " e often used t o interf","" d igit"1 S)'stcms Il ,at arC d i"nnt from each o ther. For example. ,uppose il i, ne<:essary 10 IranSmil an II-bil 'Iuanlit)' belween IWO point s- If t he di$tancc is far. it wi ll be e xpen,ive t o us e" Hnes 10 I ran, mi t Ihe n b il' in paralleL It may b e more economic"IIO u se" si n gle line and Imns mi t I he inlormation serially. one hil a l " lime. Tho Iransmincr load, the ,,-bil dala in p '"" II c1 inlO a s hill tegister and Ihen transmits Ihe d ata S<'ria ll y a long the c om mon line. T he receiver accepts the d ala seriall)' imo a ' hih regiSle,. When " II" hit< a te ac<: umulntcd. they c an"'" t aken in parallel from the o utputs o f Ihe registor. ThUs. Iho transmiller p erform, a p arallellooSeti,,1 <" ",'c rs i"n 01 d ala. a nd thc tc<:eiv~r d()l."s a -;erial.to-para llellX}nvcrsion, BIOIRECl1OtIM. SHIFT REGIS,",R A register c apable o f 'hifting in only o ne dire'C,io n is e;,lkd " , ,,,i(/irff'iollal .l-hif' register_ A r ogi'ler t hal can ' hilt in both directio ns i , called a bidi,ectionalshif! '~iljjter. I, is ]lOS' ible t o m odily Ihe citc ui t 01 Fig !! te 7. 10. hy a dd in g a fourlh A ND g ale in each Slage. l or s hi f.ing the d ala ;n the upward direClion, A n i nv",hgation Ollh~ tCsullant circu it will rel'cal Ihat Ihc lo ur A ND gates. logelher with Ihe O R gate in each 'Iage. c on,h"'le a multiplexer with Ihe selechon inpUlS ,."ro ll ing l he o peralion o f I he register. O ne siage o f a bidireCl ional sh ih regiSlet with p '".lId h~,d i< sh",,'Ti in Figure 711(a)_ Each s tag~ c on,isls 0 1. I ) flip -H op and a 4-lo-l-li ne mu hiple,er. T he '11'0 selcClion inputs 5 , a nd So selcct onC of the m ultiple,er inpulS 10 a pply to Ihe I ) fl ip. llop_ 'l l1e selection line, col\trol Ihe mode 01 o pera tion o f the regiSler ,!Cco rding to Ihe f unction ' ab le " n :ahlc 77 and Ihe regi'ter traml,'rs: 5 , -5 0: Q<----sIQ s, -so: Q <---- srQ S , -S,,: Q<----I) llO C HAI'TER 7 I II..f.GI$TCRS AND REGISTER l RAN5fOlS 0 " ~, fL 0" MUX " ~. " , Moxi< 5, ""_So " - - " ~, " , fL 0- 0, ~, , , Let, ",riol '"I""' 0, 0, 0, ~. (.J D >p: d' qT '''' o l " .... 'ypo<lll . .... o FI GU IU; HI DKlireclion.1 Shift Rcy.t<r ... ith Por ollo . Load o T A III.F.' 7 _ eonlrGl " ~ . 'a n('liott T. .. fo< , Ite Kept,.,. o f F '!:u .... ' 7 , ", " " -* ",..~ N o cllallj/C Shift 1I0I<0'0 S hih up p. .. lI el load T he " No G a nge" <>perotion is implicit if n onc o f the conditions for Ira n ~fers is s at, isfled, When t he m ode oontrol S, ~ 00, i nput 0 o f (he mu lt iplexer is sclec\ed, Th is forms a path from Ih e OUl p UI o f clOtll ~ ip , tl op into its o "'n input. T he next elock Iransilion IraDsfen ~he c urrent stor<:d ,'.I<le back into ,,,.e ll l\ip-O and 1>0 c han", op. o f s tale O ttun. When S,So " 01, Ihe lerminal marked I o n t he mul"plcxe r hM a p ath 10 l he D i npul o f e ac h n,p-nop. T hcx p alm cause a " 'un .oov,'n oporalioll, T he s enal,npul is lransferred inlO t he fiTS! 51a~ a nd the c ontenl o f e ach S late Q, I 'is 7 _6 I Mi<roop<,,,;on, on Singlo Regl"., 0 JJ 1 transferred inlo s lage Q,. When S,So = 10. sh ih -up o pe ra lion resu llS in a sec<.>nd s er ial in put Ihal enten; the last stage. In a dd'l ion. the val ue in each slage Qi ~ I i , Iransferred into stage Q,. Finally. when S,So - II . l he binary info!lllalion on each parallel input li ne is Iransferred into Ihe corresponding Hip-Hop. resulting in a pM' allel load. Figure 7- 11 (b) show symbol for the bidir""tiona' shift regisler from Fig ure 7-1 1(.) , NOle thaI b ol h a lell serial in put ( L SI) a nd a right serial in put ( RS/) are provided , I f serial o utputs are dosired. Q3 is used fo r left shift and Q", for right shift, Ripple Counter A regiSler Ihal goes Ihrou gh a prescribed sequence o f distinct stat es upon t he applicalion of a sequence of inp ut pulscs is ca ll ed a c owUer. T he input pulses may be d oc k pulses or m ay o riginate from some o lher source. a nd they may <.><:Cur a t regular or irregu13r interva l, o f lime. In o ur discussion of counters. we assume clock pulses. b ut o ther signals ca n be 'Ubsliluted for Ihe d ock , T he se qu ence of sIa l", may follow the binary n u mber seq uence o r a ny o lher prescribed sequence of ,Iales. A counler t hat follow, lhe binary number sequence is c alled" b inary co" mer, A n n bit binary counler consisls o f n Hip -Hops a nd can count in binary front 0 Ihrough 2" - 1. C o unlers are available in two calegorics: ripple cou nt ers and s}'nchm nous c o unters. I n a ripple counter. tbe H ip.Hop output Iransilions serve as t he sources for Iriggering the changes in o lher fl ip -fl ops. In other word s. Ihe C inpuls o{ some o f Ihe fl ip-flops are triggered nOI by Ihe common clock pulse . but r alher b y the I ran"l ions thaI occur on o lher Hip-Hop o utpu t"- In " sy nchronous counler. Ihe C inputs o f all flip. Hops r eed". Ih. common clock pulse. and t he change of , tate i , d eler mi ned from the present st OI c of the counter. Synchronous counte rs are d iscussed in Ihe nexI IWO subscel io n .. H ere we p resent lhe binary ri pple c ounter and e ' plain its oporation , T he log,c diagram of a 4-bil binary ripple cOunlCr i< shown in FIgure 7-12. The counter is c onstrucled from D Hi p- Hops connecled such tnat Ihe application of a positi,'e edge 10 Ihe C inpul of each fl ip. nop ca uses Ihe fl ip-flop 1 0 complement il s , ta te The complemented output o f each fl ip -fl op i , connected to Ihe C inp ut of Ihe nexI moot s ignificant Hip.flop. The Hip . Hop holding the leasl sign ifi cant bi t receives Ihe incoming clock p ulse .. Positiveedge triggering makes each flip-flop complement il s value when Ihe signal on ils C input goes I hrough. positiw transi. t ,o n. T he pos il ive n ansil ion occun; when the c omplemenled o utput of t he previous fl ip-Hop. 1 0 which C is c onnecled.goes from 0 to 1. A I-levet ' ig nat On R eut driving t he R in puts d ears t he register 10 all zerOS asynch ronously, To understand Ihe operation of a binary ri pple counter. let US examine t he upward counti ng sequence given in the lell hall of Tahle 7-8. The count slarts or binary o and incremenls by one wilh c .c h counl p ut"", A fta lhe counl o{ IS. lhe co<m ter goes back 10 0 10 " 'peal Ihe count. The leasl significan!..bil (Qo) i , complemented by each count pul se , Every time thaI Qo goes from I 10 O. Qo goes from 0 10 I. complementing Q" Every li me Ihal Q, goes from 1 1 00, it complemen ts Q, . Every li m. Iha t Q, goes 3 32 0 C HAPTER' I REGISTER.S A ND R EGISTER "TRANSFERS 0 ." c " IL l 0 c "l L IC ", " l 0 C R. "" " o F le U RE H 2 4 Bil Ripple C O""IOT o T ABLE 7 4 C ounlin. S eq uen ce . . r Rin.ry C ou nle r Upw_'" Counllng Seq .... . ..,. 0, 0, 0. 0, """" "0"" " 0 0, 0, 0 "0 " "" 0 " , """ 0 , 0 """ ," ," " 0 Oo wnw.'" Counting Sequ. n.,. 0, 0. , 0, " " , " " 0 " " 0 " " " " " " " , " , " " " " , " , 0 " " 0. " , " 0 " , " 0 , , " " from I t o 0, it complements Q" and SO on for any higher order bits in the ripple counter. f ur example. consider the transition from count 00 11 to 0100. Q<l is complemented " " th the count pulse positi"e edge. Since Qo goes from I to O. it trigger,; 0 , and complements it. As a result, 0 ,. goes from I to O. which complements 0" changing it from 0 to L ~ does IlOl trigger Q" because Q, pNXIuccs a negative transition, and t he flip-ftops res]lO<ld only 10 posih" e transitions. nlU~ the count from 001 I t o 0100 is achievcd by changing the bits one al a time. The counter goes from 001] to 00 10 ( 00 from 1 to 0). then t o C O)) (Q, from ] to 0). and finally 10 (Q, 0100 from 0 t o I ). The Hip-Ilops chango one at a time in quick succession as the signal propagates t hrough the counter in a ripple fashion from one stage 10 the nexl. A ripple count er t hat counts downward giv es the sequence in the right half o f Table 7g , Downward counting can b e accomplished by conneCling the true o utput or each flip.flop t o the C input of t he next flip -flop, T he advantage o f ripple co unters is Iheir simple hardware. Unfortunately. they are asynchronous circuits and. with a dded log ic. ca n become circuits w"th detay dependence and unreliable operation, This is particularty t rue for logic thM provides feedback paths from counter o utputs back to count er inputs. A lso, d ue t o the te ngth of time req ui red for the ripple t o finish. large ripp le c o un ters can be slow circuit s. As a consequence, synchronous binar), counters are favored in all but low.power desig,ns wheT<: ripple coulllers ha"e an advantage. (See P roblem 7] 1-) Synchronous Binary Counters Synchronous counters. in c ontrast to ripple counters. have Iho clock applied to the C i npu", of ali flip-flops. ThUs. t he c ommon clock pulse triggers a ll ni p. flop' simultaneously r ath er t han o ne a t a time. as in a ripple counte r, A synchronous binary coun ter t hat c ounts u p by I can b e c onstructed from the i ncrementcr in Figure 5-12 a nd 0 flip-flops as shown in Figure 7.13(a). T he c arry oU'put C O i , a dded by not placing an x value on Ihe C, o m put before the contraction o f a n a dder to the incrementer in Figure 5- 12. O utput C O is u sed to e xlend the c ounter t o more stages. Note t hat Ih e AipHops trigger o n t ho positi"c--edge transition o f the clock T he polarity or the clock is not essential here. like it ",as for the ripple counter. The synchronous counter can be triggered wi,h e ither the positive or the negati"e clock transition. SER .... L ANn PARALLEL C OUNT ERS We will use the synchronous counter in Figure 7 -13 t o d emonstrate Iwo alternative designs for binary coumers. In Figure 7_ \ 3(a). a chain o f 2 input A ND g ate, is used to provide information to each stage about the state of the prior stages in the counter. This is analogous t o t he carry logic in the ripple carry adder. A coun ter thaI uses such logic is said t o ha" e serial g illing a nd is referred t o as a serial col<mer. The analogy to the ripple carry adder sug ge, ts t hat there might b e co unte r tog ic a natogou, t o ' he carry l ookahead adder, Such logic can be derived by c ontracling a c arry lookahead adder, with the result shown in Figure 7-\3(b). This logic can simply replace that in the b lue box in Figure 7-\3(a) to produce a count er with parallel galing. c a ll ed a parallel co,mler. 3 34 0 CHAPTI'.R 7 I H.EGISTER5 AND REGISTEIi. lRANSFElL'l ~-- ~ ( """' o bI< EN ;;;-f-l , '--- i-'l!: ", r Q, ' --- , 0 ' --- ", r-~ 0 , ' --~ ,,~ ----- ""'P"' CO (.J !.uP< I NI"m-$<: . ..1G ... ." ) Symbol o ~lGUKE 713 4 Bi, Syr.chronou$ Binary Coon'.r The a dvanlage o f parallel galing logic i . Ih . . , in going from . Iale 1 111to . tale 0000, only On e A NO g ale delay occurs insoead o f Ihe four A NI) gat. delays Ihal occur for Ihe ""rial counter. Th . . re<luctiOfl in delay allo"", Ihe c ounter 1 0 o perale much faster. I f we e onne", h ,'O 4 bit parallel counters l ogether by connecting Ihe C O oUl p ut o f o ne 1 0 the E N input o f the other. I he result is an g bil ""rial parallel C<"I unler. This counler h i Iwo 4bit p ara ll el parts conncelcd in ""ries with each Ol hcr. The idea can be eX lende<l 1 0 c ounle ... o f a ny lcnglh. Again. employing the analogy t o carry l ookahead a d de rs. a dditi"".1 le~el. o f galing logic can be inlroduced to replace the ""rial c onnections b etween the 4 bil ""gmenu. T he adde<l r eduction in delay Ihal resuits is u""lul for c o nslruning large. fast counters. T he symbol for t he 4 bil counter us ing posilive-edge lriggering is shown in Figure 7.13(e) UP- Do WN BIN AII Y C OUNTE R A synchronous cou nt-<lown binary counter goes through the hinary stales in reverse o rder from 11 11 100000 a nd back 10 1111 to repeal t he count. The logic diagra m of a sy nchronous count -<lown hi nary counler is similar 10 t he circuit for the binary up-counter. except that a d ecrement"r is used in'lead o f an increme nter. T he t wo operalion~ can be c ombined 10 f om) a c ounter that can count bot h up and down. wh ich is referrL><l to as an up-<lown binary c ounter. Such a counler can be de> ;gned by contracting the adder-1l ubtractor in Figure S-8 into an incrcmcntcr-<iecremcnter and adding the D Hip_flops. The cou nt er cou nlS u p for S ~ 0 a nd down for S ~ I . Alternati,'ely. a n up-down co unter with ENABLE can b e designed directly from co unter b eh",'ior. 11 needs a mode inp ut 10 seicct between Ihe t wo o peration s. We deS ignate t hi s mode . .,lecl inpul by S. with S - 0 for up.count ing and S _ I for down.,;:ounting_ Let variable E N b e a oount cn"ble inpul, wi th E N - 1 for normal up o r down-coun ti ng and E N - 0 for d isabling both counts. A 4_bil up-<lOW Tl binary c ounler ca n be described by the fo ll o",ing Aip A op input e qu"tions; D~o - QoffJEN O~. - Q , EElQo':5.;.QoS)EN) D~ , - Q,ffJQo' Q"S,;, Qo ' Q. 5 ) ' E N) D~ J - Q)ffJQo -Q, - Q, S +Qo - Q, - Q"S)'EN) T he logic diagram of Ihe circ ui t can b e easily oblained fmm l he in pUI e ' lumion . . bUI i~ n ot included here. II s hould b e n oted that the e qua tion . . as " r inen. provide parallel gating using distinct carry logic for ~ p,c" u "li ll g and d<> wn _cou nting. I ( is a lso poo;.s iblc 10 uSC Iwo d iSt inct s crial gal ing chains a , well. In contrast. the counter derived using Ihe incrememer--decrem enter uses o n ly a si n gle carry t ha in_ O vera ll , the logic o"st is s imilaT B tNAR Y C OUNTER WITH PA RALLE L LOAD Cou nl ers cmplo)'ed in digital syslems q u ite often require a parallelload capability for transferring an initial binary !l umber in to the count er p rior 10 the co unt " ""ralion . T hi' fu nc tion can h e implemenled by an incTemen teT with an E NABLE,,, E NABLE . . a nd" 2-inpul O R gates a , shown in f igure 7_14. T he" E NABLEs a re u ,ed to enable a n d disab le the p ara ll el load o f input d ala. D, u$ing t he s igna l Lo.d_ Note lhal ENABLE on the incremcnter i , used t o e nable o r d i,able cou nti ng using Counl Load , """lth the Load and C o unt inputs both a l 0, the o utp uts d o not change. evCn ,,'hen pulscs arc applied 10 the C inputs. I f the load input is maintained at logic 0, l he Count input controls l he o pera l io n o f the counter. and the outputs chan ge to the nexl bi nary count for e a ch positive Iran _ .ilion o f Ihe d ock. The d ala app li ed to the D inp ut . is loaded into the Aip-Hops when Load equals I. Iegardless of the value o f C o unt beca use L oad is A NDed wit h Count. Counlers with para ll el load are ,'ery useful in the design o f digital com put. erS. In subse4 ~"nl chapler,,- we will " dcr to them as rogi'lers wit h load and incre men t opcra t ion~ J J6 0 C II AvrER 7 f R .EGIsn;p.S A ND I UCISTFR'IRANSFERS -- --- ----, ~., jD , D , - Q, o n CURE 7_14 4_Bit Bin.'Y Count ...-ith Para llel Load T he binary counter with parallel load can be c onverted i nto a ~yn< b ronoU$ K e D c ounter (without load i nput) by connecting an external A ND g ate t o it. as shown in Figure 7-15. T he c ounter s tans with an all-zero o utput. and the c ounl in pUI i. ah"3)'$ aClive. A s long a~ t he OUtp Ut o f the A N D g ate i ~ O. e ach positive clock edge increments tbe counter by o ne. When the OIltpUt reacbes the coum o f 1001. bulh Qo Bnd QJ b ecome I . making t he o utp ut of t he Al-': D gate equal t o I This c ondition makes L.:>Dd acti ve: SO on Ih e next clock transition. t h e counter d oe, nOI c ounl. b ut is loaded from it s (our inputs. Since all four inpul$ a re c onnected 10 logic O. 0000 is loaded inlo the c ounter following t be c ount o f IOCIi. ThUs. the eircuit c ounts from 0000 through 1001. follOwed by 0000. as r equired for a B CD counler. r-~=c=>~o-~<:,,~_{> CTK' ~ 1- Coun' ~ r-"- 0, o Q, 0, 0, (LopoO ~ g o. 0, 0, Q, 0, QJ 001- FIGURE 7 15 B CD Cou",er O ther C ounlolll C ounlers can be designed t o g enerate an}' (lc~iTCd num ber o f ,1ale. in s equence. A dil-ide-by-'" co''''',,' (a loo k nown as a mOlI,,/o-N co~"'er) is a c ounler thaI g oc' [ h",ugh a r epealed sequ ence of N .late<- The s equence may follow t he b ina,y c ounl o r may l>e a ny o ther a rbitrary sequence. In e ilher case. the design o f {he c ounler follow> the pr<xcdure p rescnted in C hapter 6 for t h. design o f , ynchm _ no,,~ s equent ial circuits. To d emon,lralc t his p rocedure. we will p resent (he d esign o f t wo c ounlers : " RCI) c ounler a nd a c ounter wilh an ",b j'r ~ry s equence o f S lale s. BCD CoUNTER A s shown in t he previous sect io n. a t lCD c ou nt er can b e o blaincd f rom" b inary c ounter wilh p a rallel load . 11 i . a lso I"'-"I ibk tn design a UC D c ounter directly using individual Hip _nop', a nd gate. . Assuming D-'yp<: flip-flof'S for the o ounter. we lis, t he present SlMe. and e<)rre'J>On<ling next states in Table 7-9. A n o ut put Y is included in t he t ab le. This o u tput is cqu.,l ' 0 1 when the present , late i . 1001. In this way. Y can e ""hle t he co unt o f the next d ecade wh ile i h o ,,'n decade switches from 1001 t o ( 0)) . The fl ip-flop input <qu , ion, for D a re o btained from the nextstale val ue. listed in t he t able a nd can b e simpli fi ed by meanS o f " . map<. The unused s tMe. for minterms 1010 throu gh 1111 a rc u ,ed as d on't",a,. conditions. T he si mplified input cqu~tiuns f nt t he B CD c ounter a re D , W' Q , D1= Q l EeQ , 'Q. D. ~ D. ~ y~ Q.@Q ,Q, Q ,e (Q ,Q, Q,Q. + Q,Q,Q.) 3 38 0 C HAPTER 7 I R EG ISTERS A ND R EGISTER " TRANSFERS o . T ARLE 7' S late TobIe and F lip-flop Inpu!> f<>r BCD C ounler P ..-nt S ta te O NexI S tale 0000 , .- .- .- ."""" " "",, " " " "" " " " " " 0, 0, o . (t I a , It"1 Oz(t+ 'l 0 ,(1+ 11 """" """" ",, "", ", ","" " ,", , " , ",," " 0 , ,"" " """ """" "" o OUtput 0 " , " " " " " " T ABLE 7 10 StA Table a nd F1ip.Fl<>p Inputs for Counter te Prelent S t.t. , Next S t.t. , , " """ , " "" 0 0 0 0 O A_OS_DC. Alt.1 ) 81(' I l e(t. I I 0 0 0 " " "" , " , " " " S ynrnronou. B CD counter< can be cascaded to form cou nt er~ for decimal nu mbeTll of any longth. T he cascading i. d one by replacing D , wi.h D, = Q , eo Y " 'here Y is from the ne xt lower BCD counter. Also. Y n eeds to be A NDed ,,'itb Ihe p roduct terms t o the right o f each of . he X OR sy mbo l in each o f the equat ions for D , Ihrou gh D ,. ARBITRARV COUNT SEOUENCE Suppose We " ' ish 10 d es ign a c ounler Ihal has a repeat ed sequence of s ix states, as listed in Table 7- 10. In this s equence. Hip-Ho ps B and C repeal the bin ary coun t 00. 01.10. "'hile ni p Oop A a itemales between 0 a nd I every t hree count~ Thus. Ih e count sequence for the c o unte r is n ot straight bina ry. and IWO s lates, 0 11 a nd I ll . a re not incl uded in the count . T he D flip llop 7 _7 I R <g;',." I Coil D.,;g. 0 '"' '" 3 39 ow I JI >0 I >0 I ~ I --1 "-I'-] / 'o(~ ) ,OO~( <0, ,., o F IGURE ' 16 C oon,e. with Arbitrary Co"", input e quations can be simplified us ing minlerm, 3 and 7 as d on "t.eare conditions, T he simp li fied f unetion. are DA~AeB DB - C Dc B e T he logic diagram of the c ounter is , how" in Figure 7-1 6( a ), Since there are two un uSt:d , tate. . we analyze the <ircuit \ 0 d eterm ine their e lfect The s tate dia gram o btained is d rawn in Figure 7 -l6(b J. T hi' diagram indica le, l hat i f the circuit ever goe< t o one of Ihe unm:ed states, t he next count pulse transfers i t!O one of the valid states, and the c;",nil t hen contin ues 10 c o un t oorrectly. 7 -7 R EGISTER C ELL D ESIGN In Section $ 1. we discussed it erative c ombinational circuits. In Ihis c hapter. we con nect , uc h circuit' 10 fl i ~fiops to l onn " ,q uentinl circuits. A , ing le bit cell of au iterative c ombinational circuit connected to a fl ip-flop that provides the output forms a tw<)-State s equential circu it called a r t!g;51a ".11. We can design an n _bi t register wit h o ne o r m ore associated microoperation, by designing a register cell and making n copies o f it, D epending o n whether the o u tput o f the fl ip_ flop is an input to the iter_ a liw circuit cell. the register cell may have its next " a te dependent o n its present 3 40 0 CHAPTER. 7 I REGISTERS ANO Rf.GISTER TIVlNSFER5 de~ndenty I ~en stale and inputs Q1" on its inputs only_ If Ihe is only on Inputs. ce!! design for the iterative combination.1 circuit and attachment o f the iteralive circuit 10 Hip -flops is a ppropriale_ If. however. lhe wile of lhe nip.. ll op is fe d back t o the inputs o f the iterative circuit cell. s.equential design melhods can . Iso be applied. The next e umple illustrales simple reg;>!er c ell de>ign in such a cas.e. E XAMPLE 1_1 Hegist~r Cell De";gn A r egiller A is 10 implement Ihe following regiller transfers: A ND:Af-A"B E XOR :A f- AeB O R:Af-A"B UnleSll'pe<:itied olhe",ise. we assume Ihal I . O nly one o f AND. E XOR. a nd O R is equal 10 I . and 2_ For all o f A ND. E XOR. a nd O R e qua l to 0_ t he c ontent of A remains unchanged. , \ . imple de.ign a pproach for a register cell with conditions 1 and 2 uses a register wilh parallel load constructed from D flip-flops with E nable ( Enable .. L oad) from Fi gure 7-2. R>r this a pproach. the expreSllion for L oad is t he O R of all oonlrol signals that caus.e a transfer to occUr. 1". e xpression fo r Di consists o f a n O R o f the A ND of each oontrol signal with the o perat ion On Ihe right _ hand side o f the oorresponding t ran,ilion For t hi' example. the resulting e quations for L OAD a nd D ,arc L OAD _ A ND . . EX OR + O R D, ~ A (I+I), _ A NDA o' H,+ E XOR,(A;ii, + A ,8,) + O R(A , + B,) l be C<]uation for Do' h as an implementation si milar to that u se d for the s.el""tion p an of a multiplexer in which a s.et o f E NABLE blocks drive a n O R gate. AND. E XOR. and O R are e nab ling signals. and the remaining p .rt of the respective t e rm, ill D,consists o f t he function enabled, Using D ftip..flops for the regist er ' torage a nd DO clock galin8> a multiplexer must also b e implemented in each cell; D ( FF - LOADD, + L OA D -A , This e qualion is g iwn to show the hidden COSt inside of the basic parallclload regi'!_ l er cell. A more r o mplex approacb is 10 d e. ;gn direclly for 0 flip-flops us ing a s equent ial circuit d""ign approach rather than the ad hoc approach based on parallel load flip..Oops. We can fonn ulatc a coded state table with A a'! the s tate variable a nd o utput. and AND. E XOR. O R. and B as inputs. as sh",,"'n in Table 7- 11. By formu13ting the flip _ flop input equalion for D , ~ A (I + 1),. D , ~ A (l+l)o' = A NDA r B, + E XOR(A , H , + A ,H,) + O R(A , + H,) + AN D EXOR OR,A, 7_1 I R<gi. ... O il D ait;n o 0 34 ' TA .BLE 7_11 S t.Jr T. . . a nd FUp-fIop I np.t. rOf C. ... t. .. N ell S tate,t,(l + I ) ( AHD.O) (E:tDlbO) ( DR.'I ( OR. I I ( UO R . 'I ( EXDR.'I (AND . 'I (AND . I I (DR:(II (B ..o1 (B. ' I (B.o1 (Bo ' l (B ..o1 ( 8"1 o " " " " " " D ue t o the relationship to.lw~cn Ih~ O R op"ratQr and Ihe A N D and E XOR o p"r .IOrs e nd o ther a lgebraic . eductiom.. th i, can to. simplifie<l 10 A(H I), E ( O R + AN O lA ,- B,. ( OR .. E XO R) (A ,8 , + A ,B,) + A ND . . E XO R A , I"" T he l enm O R .. AN D, O R .. E XOR. and A NI) + E XOR d o n o! d tpcnd on ~a l ,," A ; a oo B , associ.tlled wilh a ny o f t he cell . . T he loVe for l hese tennl can to. . hared by all of Ihe " ' gister cells. Using ~ and C, ,,,, intermediate vari.ab.., . . t he follow ;ng..,t o f e qu al ioo, results: C, . C, ~ O R+A ND C, . OR . E XO R C, . AND+EXOR D, _ A(I+I), ,. C ,A ,il ,+ C, (A,ti, .. AJ Il,).- C,A, An implement.t ion fo r regi,jer ce llA , and the logic . hared by all of the cell. ;, gi'-en in Fig ure 7 17. wilh the impkm~n t ltion for logic ' hred b y , h~ regi~ler cellt in A . lI efore comparing t hese rc:sulll with those from the . i mple approach, ,,'e can apply . im ilar simplification and IogiI; ! haring 10 t he ,"""ult. o f the . ;mple a pproach : C, . OR .- AND C, . OR+EXOR D,. A (,..'),. CtA,H,+ C ,(A,S ; + I i ,8 ,) L OAD. C , + C, D u F - LOA !)-!), .. L OAD A; I f these e q u alion. a re used direcUy Ihe COSt o lth" , imp'" apj>TOaCh is s omewhal higher. Howe,"" . i f Iheoe equalions arc plm'ided a minimization 1001 ins lead o f being u o;e d di"'C1ly. t he ..... me equal i on' as the moTe c omplex nt~lhod wilt resutt. Thu s, the case of using Ihe . im p l<:$1 approach d oe. nol n~eessllrily cnuse any inefeasc in hardware c<>sI , '0 In t he pr ~ce d i n g examp le. there I rc no late ral c onneclion' betw e<:n a djacenl cell .. A mong Ih~ opc "" io'" requiring IUler ai conn~C1 i on. are ,hifts, arit hmet ic oper at ion s. and COfllpari<Onl>. O ne npprOllClt t o t he des;gn o f Ihe.o;e $lruclUres" 10 c omb"", combinational de;ilJlS " "ell I n C hapter 5 with selection logic . nd nipfIors. A " , ncn., approach for mullif.. nelional registers u.ing n ip-H. " 'il h parallel Io.ad i . oo"'n ill Fi gure 7-11. Tlri. s;m pl e aj1flfOaCh b)'p;t.SS<'$ " 'gislcr c ell design . bu, 3 42 a C HAPTER 7 f R EG!STERS A ND R EG!STER ' IRANSfEi<.S ~--- ------- ----- EXOR -L'::j::;:1C:;>---i-c. l'::D--+C. A ND+- ------- Cell i a FIGURE 717 Logic D ias"m Regist Cel! D e'ign Example 7 j if directly implemented. can r e, ult in e .cessi.e logic and too many lateral COnneCtions. l b e alternative is t o d o a custom regisler cell design . In such designs, a criti cat factor is t he definition o f the lateral conneotion{i) needed. Also, d ifferent operations can be defined by W nt rolling inpullO the least . ignificant cell of the ce ll cascade. T he custom design approach i, illustrated in the next e xample by the design of a multifunctional register cell. E XAMPLE 72 Register C~JJ D~I~n A register A is 1 0 implement t he follow in g register transfers: S HLA .... ' III E XOR:II .... A $B A DD:A < -II + B Unless 'pecified o therw is e, we aSSume t hat I . O nly o ne o f SHL. E XOR. and A DO is equ~llo I , ond 2. For all o f S HL E XOR. and A DO equal t o (), the w ntent o f II r emain, u nch.nged. A , im ple approach t o designing a registcr ce ll wit h condition< and 2 is t o us.c a rcgister with parallel load con trolled by LOAD. For this approach, the expression for L OAD i . the O R o f all c ontrol s ignal' that cause a tran<fcr (0 occur. 7_7 I ~ CoU D eoip 0 J "J T he I mplement,tion for D , oonsisH o f an A ND OR , " ith each AN D havin S' control signal a nd the l<>sic for the operation ( In t he righthand s ide"" i n input " For Ih is u ample, the resulting e qua tions for L OAD and Diare 1.. 0AI) . SH I.. ..- EXOR ... A OD 0 ,,, 1'1(1)1), - SH l Ai--'''- EXO R (1'1 ,$ Bi ) ... A DD A, $ 8 ,) e C,) C o.,. ( A; $ B;) C; ..-A;8 ; Thcsc equations c an be used without modillcation o r can be o ptimiud Now. suppose. inslead, that . . e do a custom de$ign assumillJl that all <lill>e ""gistcr ""lis a rc identical. This means that the IeUl a nd m ost _iJr! il\cant cells wi ll be t he same as . h O$oe internal the ce ll chain. l!ccausc o f thi . . the value <Ii Co mUSt b e .pecified a nd the use. if an y, o f C . mUSI b e de.ermined for n c h o f the t hree operations. For Ihe left shift, a z ero fi ll o f the vacated right . .." " t bit i$ assumed, gi" ing Co _ 0 , Since Co is not in"olved in Ihe E XOR o peration, it can be assumed t o b e a don 't ure. ~Inally. (or the addition, Co cit her can be assumed to be 0 o r can be left as a variable to permit a c arry f rom. previous addition 10 be injected. We assume t hat C. e q uab 0 for addition , since nO additional ClIrry -in is speciftcd by ,I: register troMfer slate ment. O ur fi ri t fom,ul.tion goal is t o min,mize lateral oonn.-ction. bet"'t'Cn cells. Two o f the ' h""e OJI('ralioom, I dt $hifl and addition, require a Lateral C Qllneclion t o t he left (i.e., toward the m o.t oignilicanl end o f t he cell d la in ). O ur goal is t o usc o ne signal for both operations. $,lly. C~ I t already e ";'t' for the IKIdnion but must b e redefine<llo handle b oth the addition ond l he left . hift. Also in o ur c u,tom d~.ign, the p arollelload Hip . Hop will be replaced by a D flip-flop, We can nOw formulate the sta lc tabl ~ fQT Ihe r~gister cell . hown in Thble 712: '0 D ;_ A(l-t I),. SiT[. E XOR ADD A ,.. S Ill ~C,.. E XOR (A ,$BJ+ADD(A,eR,ElIC,) C.. , ~ S H J...A, . . A D D(-( A ; Ql B;)C,..- A ,B,) l lte . erm A ,$B, a ppcoatlO in both Ihe E XOIt a nd A DD terms. In (lOCI , if C ,. 0 during the E XOR OJI(' ution, . hen the func1 ions for , be ,U rn in A DD , nd for E XOR can b e i<1ent~t In the C .. , e quation, . ." "" S i ll.. and A D D a re both O ,,'hen E XO R is I , C, is 0 for a ll cello in t he ClS<'ade u cep11h e lea<l significant one. r..., r t he l east -, _ . o T A8LE 7-n State Toble.Itd Hip . l op lopu to fo< He ,l l ter e e l. Design in E. . mpl e 71 51.1" . .... ",-. , EXOR . O A OO.O " .. , .. .1 5 t.,. : ,, ,,,, ,, C , .O s tll . 1 .X 00 l lX ( I{! 0 0 1,(1 010 111) 0/1 III W ill I .. ... . AJ.!. l )/Outpul c,., EX~ . 1 ,, ! l'X I IX llX WX A DO. 1 , ,,,, ,,,, 010 1,(1 !lO ( I{! 11\) M 0/1 111 3 44 0 C I-< AI'TER 7 I REGISTERS AND 1lG1~'TER 1 lU.NSFERS ~---------------, "" E'XOR_f~~~~~~~]:~ " S ilL I : S ha ..:! l op: " ' , , ----- ----------_. ". c S ill - ------- -- --- -----_. -- -I '- , - A DD -j--- ---------------. ~" J)- ./ c,;- , , " , , , , , , , )- -- - --- ~. - -- --- ~, -- hi,, , , , .1 .: o n G U RE 7 18 l og'" D i' Vam. Re v.le, Cell De>;!" E um ple 72 ~ i gnificant cell. the specification . tates lhat 4 K O. Thus. input v3lue. C, Me 0 f OT all c e lls in regiMer A . S o we can combine the A D D and E XO Mo perat ions a ll fo ll ow<: D , A(I+I), S HL, E XOR , AD D A,.. S HL C,+ ( EXOR + A D D ),((A ,EB,)eC,) The c xpreuion5 S HL E XO It ADO . nJ E XOR . . ADO. thai a re i ndepe ndenl o f A " Bi a n d C" can be s hared by all ceJJs. l bc resulting e qua t;OIl5 a re E , ~ E XOR + A DD E E E,_ 121 +S~ I L D ; a E, 'A,-+- SI-ILC,+ E ,'A,EB ,)EIlC,) C.-I ~ S HL A , + A DD A ; i ii B,)C, .. A ,B,) T he , es ulling regisler ce ll a ppears in Fogure 718. Comparing l hi s res uh wi th the register cell for the simple design. we nOle t he following two diffe""nces: ), O n ly o nc lateral c o nnection between cells u ists in stead of 'wo. 2. L ogic bas been ve ry efficiently s bared by t he a dd;l;o ll a nd l he EX OR o peration. T he custom cell design has produce<l connection . "d logic " "ings n ot p resent ;n the h l(lC k l e,'c ] design ,,'ilb ( )r wilhout oplimi1.alion. 7 -8 M UL11PLEXER A ND B us-BASED T RANSFERS F OR M ULTIPLE R EGISTERS A typical digitnl syslem has many registers.l'ath, must b e pro"id~d 10 t ransfer data from o ne register t o a nother. The amount of lugic a nd the n umbcr o f httcrcunncc tio ns may b e excessive if each regi. ler has il s own d edicated set o f multiplcocrs. A m ore cffic>e nt .elM, me for t ranMening d ala bet'. ..~n regislers is a 5yS I ~m that uses a !oharw t ",nsfe r palh c a lled a bus_ A bus is c h aract erized by a set o f c ommon Ii ".,., .... ith " ""h line d rhl'n b y selection logic. C ontrol a;gn.aJs for the Iot;ioc select a single " ""fCC a nd o ne o r m ore dcstinatiOM o n a ny c lod cycle for '" hieh a ( ",,,,fer occurs. [ n Seclion 1-4. , ,'c " ",W Ihal m ultipleurJ aJtd f"'ralle1 load . eal. leR can b e used t o implcnlenl d edicatw \ randel'S from multiple A block diag,am f o. such tran,fers bclween Ihree regi.lers is s hown in Figure 7]9(8). T here a re three n_bit 2to. [ multiplexers. each with its own select ,ig" al. Each regisler has ils " wn Iu; .d signal. T he l a me . y.le m b ased un a blls Can b e implem ented by u!li ng a . i ngle n-bit 3 -t".] multiplexer and parallel load .cgilters. I f a set o f m ultiplu er u utputs is . hared a1 a c ommon path. ,hese o utput lines ar e a b us Such a sySle m ,"'i lh a . i ngle """.ees. r , 2 ,.,.1 MUX " l...,-t , ""' r " " '0 "" Ii' " L- , r " , , , ) .'0-1 M L' X , C- " " 2 _10-1 ""' - " , " ( M s ;"p, B . . Cl f lG UIU: ' 1.9 SinSie B u, .'crsu. I).eJ ic.,cd M ultiple . ." ,- LOll L2 3 46 0 CHAPTER 7 I REGISTERS AND R F.(;ISTER lRANSFERS Example, o r Re~i ,te'T. . n, rc . . U,/ ng Ihe S ingle 8w s in . iK"'. " 19(b) R egit.Ie' T,,,,, .fer " 1/0 . .. 1/2 RO . .. R l. R2 . .. R I RO . .. R LRI+-RO - ~ 0 0 ~ U "" "" " Impossible bus fo, Iransfers between Ih ree regislefli is shown in Figure 7 I9(b). The control input pair, Select. d e termines the contents o f the s in gJe S<j urcc register thai will a ppear On t he multiple.er o utputs (i.e.. o n t he bus). The load inputs detemlinc the destination register o r registers t o b e l oaded wil h the b u. d ata. In T"ble )13, tran,fers uSing the singlebus implementation of Figure 7.I9(b) a re illustrated. The first t ransfer is from H2 10 RO. Scle<:t e qual. 1O,selecting input H2 t o the multiple.er. Load , ignal LO for , egister RO i'! I. with all other I<~,ds " t 0, cauSing the (x:mten t$ o f HZ o n the bus t o be loaded int o RO on the next positive d ock transition. The seeond transfer in the table il lustrates the load in g of the conlcnU o f HI in to both RO ,md H2 , The source R I is sele<:ted because Se lect is e qual to 01. In this case. L 2 and LO "re both 1. c au,ing the contentS o f HI on the bus to be loaded in to regiS ters RO and H2. The third transfer. an exchange between RO and R I. is impossible in a single d ock cyde, lince it requir es two si mul1,neOU\ sources, RO and H l. On the single bus. ThUs. th is transfer requires at least two buses or a bus oom bined with a dedicated path fro", One o f the registers to the o(her. N ote that such a transfer Can b e e . ecuted on the dedica(ed multiplexers in Figure ) . !9(a)_So. for a single.bus system, si n,ullaneous transfers with diff.rent SOurces in a single d ock cycle a re impossible, whereas for t he dedicated multiplexers, any combination of transfers is possible_Hence. 1he reduction in h ardware l hat occurs for a si ngJe bus in place o f dedicated multiplexers results in lim it at ion,! o n si mult.neou s lransfers. If we a SS ume that only singJesource transfers are needed, then we can use Figure 719 10 c ompare the complex it y o f the hardware in d ed icated versus b",, b~d syste ms, First o f all. assume a m ultiplexer design, as in Figure 416_In I ~gu re 7 I9(a). there are i n A ND g ate, and " O ~ ga(es p er multiplexer ( not c ounting inver(ers). for a t01al o f 9 " gates. In c ontrast, in Fi gure ) .19(b) . the bus mult ip lexer requires o nl y 3" A ND g ates a nd" OR ga tes, f or" tot al o f 4 n gates. AI,o, the data input connections to the nlultip iexers a re r ed uc ed f m m 61, to 3,, _Th Us. the cos( o f the selcction h ard",.,. is red uced by a bout half, T hree-Slate B us A b u, ca n be constructed with the three state buffers in troduced in Section 2-8 in stead o f " ,u hiplexers. Thill has the p olemial for additional red uctions in t he n um ber of connection .. But why use three-state buffers instead o f a m ultiplexer. p anic ularly for im plement in g buses? The reason is t hat ntany t hreestate buffer o utputs c an b e connected t<>cether t o form a bit li~ o f. bY$. a nd Ibis b u. is i mplemented using only o ne Ie'-el o f logic gate!.. O n the m her hand. in a multiplexer.'UI'h a la ra<' n umber of sourccs meanS a high fan in O R. which requires multiple levels o f O R gate s, i nuodu cing m or e logic a nd in crealing delay. In c ontrast. threestRle buffer> provide a practical way 1 0 construCl fast b uses with many s o urces,so Ihey are o ften p rdcrrcd in suc h CUe .. M ore important . howe>' cr. i lt he fac1 that ' ;gnal, can trave l in two directi<;ln$ on a t hree-'itate bus. Thu s. the t hreestate b us can uSC t he ""me interoonnectioo 10 c arry . ignals illlo a nd o u t o f. logic circuit. T his f eature. wh ich is I II(J6I i mportant "'hen cr05Sing chip boundaries, i . il lustrated i n f'ogure 7 -lO(a).1be 6gurc . hov.'S l egister w ith" Ii . .... t hat se .....e "" b oth i nputs a nd o u t puu I)'ing across tIM: b oundary o f the shaded . "'a. I f the t hreestale b uffers.", e nabled, then t he line, a re o utputs; if tile three-state b ulfen a rc disabled. t hen tIM: lines can b e inputs. The symbol l or lhi, structure il also given in t he figure. N ote th nt t he bidirection.1 buS lin es a re represent ed b y a tw ohcadcd a rrow. Al so. a smali inverted lriangle d enotes t he t hree -state OU l putl o f Ihe regi.ler. Fi gure 7-2O(b) ~ nd Figure 72O(c) s how a multipl exer-implement ed buS a nd " t hr ee-'itate bus. r npeetive ly. fo r c omparison . T he symbol from Figure 720(1) fo r . " '!Bte r with bidirectional input-<>utput I~ i$ used in Figure 7.20(,). In COnltast t o tIM: l ituation in Fi gure 719. " 'he,,, dedicated multiplexers were replaced b y. !>u s. t hese two implcmenlations a re idenlical in terms o f t heir r e!Bter tram.fer ~ UJ t.l U 0 I ~ 0 ~D , -! -" " ~ t.2 L l 1.(1 ' -, OO V ...;..!1" o .~ ,I " ~ '0 .. . \lUX J~ ,,, I 0 'V ~ ", V " 0 En 0 0 I~ ~V ~ 0 ~ ( .) ! I<P*' ""~ bo<Jire<lionol . ." ",_,,,,,, Ii . .. _ ~ ( ,)"" . ....... b w...". . ." "en W>tb bioli,..,;o.w . )",boI Ii . .. o F lG U K t': 7- 2(1 T hru.s"to Hus~ . .... M ul'iple>er B u. 3 48 0 C IIAPTER 7 I RE:GISTERS AN I) REGISTER 11t.ANSFOlS capabnlly.IJOIe tbat. ~ t be tbruooS t8!c a rc J ala ronncd;';""s t o Ihe set o f register block. for cach bit o llbe bus. The muhiplcxcr_impicmenled bus has six d at a " "nn""tions per bi. 10 the SCI o f r cgisler block .. This reduction in the n <l mber of d ata connection. by hull. along wit h t he ab ility to eaSIly ""nSlruel a bus .... ilh many ilQUTCCI>. make. the three-sl~le bus an attracli,c allernalive. The u"" o f such bidireclional inpul-<>ulpullinC\l i . p anic ularly effective belwecn logic cir cuits in d lffe'enl ph )""Sica1 p achges. bus. Ibm 7 -9 only Ibr S ERIAL T RANSFER A ND M ICROQPERATIONS A d igilalsystem;, s.roid 10 o perate In I serial mode ,,hen informltion in t he ')'Siem i . I ran.ferred o r mani pu lated o ne btl 81 a lime. lnformalion is transferred o nc bil a t a lime by shifl ing Ihe b il. o ul of One register and iUIO a &eCOnd reg;';lc,. Th . . tronsler melhod is in c ontrast to p ara lt eltransfcr. in ,..hich all Ih e b il. o f Ihe regi... l er arc I,ansferred at t he IIIme time. The ""rial Ir~ n sfer o f information from . egisle. A 10 regisler IJ i . d one with . hih r egi.I" ..... a . sho"n in the block d tagr.m of Figure 721 (a). n.c . erial OUlpul o f regi.let II ;1 CO<Inecled 10 Ihe serial inpul o f.egiste , B. The ..,rial inf)UI 0 ( register A . ccchcs 0$ ..hlle il! d ata arc t nmferred 10 re&i~lcr B. I t is a lw possible fo< register A 10 r<""',, olhocr binary information. o r if ".., walll to m a,nlal" Ihe <tala in r egilter A . ".., c an connect i n . .. rial OUlpU I to ils serial inpm $ 0 , hal the infonna. lion is circulated l nck into lhe regille . T he initial CO<Ilent of r e,isle r IJ is s hilled o ullhrough il> ~rial o utpul and ;sI011. "n!e1oS il is transferred back inlo regisler A . to 3 I h,rd shift regiue or to o ther sioragc. T he shift control inpul S hift dclcrmi nes when Rnd how n "",y times the ' egislcrs nrc shifte d. T he r eg"tcrs using SMft are con trolled by mean. o f thc logic fWIII H g"'" 7.2. which a ll owllhc d ock p ul"". 10 pass 10 lho: shifl regiSler d ock i npull only when S hifl has t he ~a l"e logic I. T, (b)T-"I~ o t I GUKE 72 1 5 <". 1'r'a",ror T, In H gure 721. each shift regisler h as four 'Iages. "lllc lo gic Ihal supervises Ihe Iransfer mU l l be d e signed t o e nable Ibe sh ifl registers. through the S hift s ignal. for a fixe d time of four clock pulses. Shill register e nabling is shown in the timing d ia gram for the clock ga!ing logic in Fi gure 721(bj . Four pulses find Shi/! in t M active sta tc. SO thai Ihe o utput of the logic connected t o Ih e d ock inputs o f Ihe registe,.. p rod"""s four pulses: T , . T,. T, . a n d T . Each posil i.e t ",n ,i lion o f these: pulses causes a shifl in b oth registers. A fle, Ihe fourth p u lse. Shi/! c hanges hack 1 00 and the Sh ift regislers a re di>abled. We n ote again Ihal. for positi" c-e<ige triggering. the pulses on the clock in pu ts are O. and the in active 1e ,' .1 when no pul"'", are present i s. 1 r alher t h.n a O. Now suppose Ihal Ihe binary c ontcn! of regist er A before the ,hifl is 101 L Ihat o f register B is 0010. a nd t he S I o f r egi,ter A is logic O.l11e n Ihe s eriallr.ns fer f romA 10 B occur.; in four sleps. as shown in Table 71 4. With the fir.;t p ulse T,. Ihe rightmost bit o f A is shi fted inlo Ihe leftmost bit o f H .lhe Id lmast bil of A receives a 0 from lhe serial input. a nd a lthe >ame t ime. all o lher bilS o f A and B are s hifled o ne position t o the rig.h t. The n Ul Ihr ee pulses p"rform identic~1 operations. , hifl ing Ihe bil> o f A into B o n e at a t ime while transferring O's to A . A fter the fo urth s hift, the logic sUp"rvising the transfer c hanges the S h if' signa l t o 0 a nd the Sh ifts stop. Regi<ler 8 c ontains l Oll. which is the prcviou. value o f A . R egiste r A c on t ain. all 0 ' . . T he difference between serial a n d pa ra Uel modC5 o f operalion should b e a pparem fTOm this example. In lhe p arallel Dtode. informaliOl' is available from all b ils of a regiSler. and all bits can b e I randerred simultaneously d uring o ne d oc k pulse. In the serial mode. t he register.; have a si ngl e . .,r ial i nput and a single serial output, a nd in formation is transferred o ne bit at a time. Serial A ddition O p"rations in digital c ompute,.. a re u ,ually d o ne in p a rallel because o f t he fa<let s p""d a lla ;nable. S etial operations are slower. buI h,,,,, Ihe advantage o f r "quir' ing less hardware. T o d emonSlrate the serial mode o f o p"r ation. " ' e will show the o petation o f a serial a d der . Also. w" c ompare the se rial a dder 10 th e parallel ,unlCrp"T1 presen!ed ;n Section ~ 2 10 ilius ITa te the tim .-s pace [racie'off in design . o TA8U:1 1~ E>an.ple (If s ., ri al T . .... fcr TI ming ~' M Inilial . . l "e Afte< T , A fter T, A fter T, A fter T, Shm ~i.te rA S h ift R<>g i. t.< B ,,,, ,, , ,,," , "" " " 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T he 1"'0 binary n umbers to be a dded s enally ar<' s tored in 1"'0 shift ,"giners. Bil. a re a dded. one pair at a t im e. Ih rough a .ingle fulladder ( FA) ciTeuit. a. shown in Figure 7-22. T he c arry ou t o f Ih e full a dder i. Iransferred i nto a D fl ip flup. T he o ut put of thi< c arry lIip.flop is th en used a, the c arry input for the ne~1 pair of Significant bilS.. The , urn bit o n the S QUtput o f t he fu ll a dder c ould be transterred in to a third shifl regi$lcr, bUI we h ave cbosen t o t ranster t he sum bits i nlo f Cpter A the c ontents o t t he . egisler a re m ifted o ut. The se rial i nput o f . egister 8 can r<:i'e ...,'" binary number its contents ani: shifted Oul d uring t he a ddition. l be o peration o f 11. .... ri al adOer is as foLlows: Regisler A hQld, Ihe augend. r<'giSie r 8 holds Ihe addend. a nd lhe carry flip-Rop bas been r uet 10 O. T he serial out pUIS o t A and 8 provide a pair o f significanl b il. for t he full " dder at X a nd Y. The o utpUt of the carry fl ip.flop prOVides the carry input a l Z . Wh en Sioifi is SC I 10 1. the O R g ale e nab le, Ih e d ock 10. b oth rcgi'ters and the fli p fl op. Each d oc k pulse shifts bolh regillers " nee 10 the rig ht . I nI",fe ... the sum bil from S into Ihe ldlm061 lIip-nQf) o f A . a nd I ran,fers the carry " ut pul into the c arry nip-nop. Shifl controL logic enables l he " 'gislen for . . m any c loc k p ulst'l.' t here arc bils in the r<'gQ; len (four p ulltl i n Ihis eI.tlmple). For C D pul . .. a""'" sum bit is t nlruferred t o A . ncW c arry is t ransferred to t he Rip1Iop. and both re&iSlen a re .... iftcd o nce 10 lhe right. This process conlinues unliL lhe shift c ontrol logic d langes Shift 10 O. T hu... lhe addition is a<:romplishcd by passing each p air o f b ill a nd lhe previou c a rry t hrough. single full_adder circu it " nd t rBnsferring the ' UnI. One bil ft( a lime. b ack into r es;"c r A . ~ I" '1' I" ull ,,<1<1., ( A,"re S-4) I- ~. ~ D n GU M[ 722 Sc,;.1 Addnion 1-10 I III)L ~,.oo.. ro. Shifi Il<P'n and e o.-....... VIlOI. 0 3S 1 Initially. ...'e c an r net regiSler A . r egilte. 8 . a nd the Corry nip-Hop t o O. T hen we s hih t he first n umber i nto 8 . N e~t. t he first n umber from 8 is a dded t o t he 0 i n A . While H i l being sh ifted t hrough I he full adder. we c an transfer a second num ber 10 il t hrough its serial inp ut. T he SC>"o nd numoor can b e a dded 10 lli e contents o f r egiiler A a t the $ "n e time t hat a third n umber is t ransferred serially i nto registe, B. S e,ial a ddition m a y b e r epeated t o form the additi()fl o f t .... o, Ihree, o r m ore n umbers. ...ith t heir s um accumulated in rep ter A . A c omparison 0 ( t he " ,rial a dtkr with t he p arallel a dder deC'fibcd in Se<:1i<M1 5-2 pr<Wide$ a n e umple o f s pace.time trade-off. T he p arallel a dtler has " fu ll a dtkn for n_bot o perand . . ,..hereas the llerial a dtler r equires o nl y OM full adtler. Excluding t he , e'"ters from b oth. t he p a, m a dde r is a c ombinational cirntit. l"'l ,..Mreas t he ",, 'ial a dde, is a se<ju ent ial circuit b ecau"" ;1 include$ t he ca rry HipHop . Th e . .,rial circuit also lak e." d ock cycles t o r omplete an addition. Idemical ciTCuiu. such u t he n full a dders in the p~rul l e l a dder. c onnuted t ogether in a chain c onstitule a n e ump le o f an ituaTiv~ I"gic array, I f t he values on t he carries b etween l he full a dtlen a re re8ar<le<i M I tnte variables. then the I t ltes from the l ea. . s lgnilkant c nd t o t he most significant e nd I re t he s ame IS the s tattl a ppelring in s e quence' ( )fI t M nip-l'Iop o utput in t hc s erial adder_ Notc that in t hc i terative ~ a rray the . . a tes a ppear i n s pace. but in t he s equential c irntlt t he I t ~tes appe~r in time. Hy COf\\'e rllng from o ne o f these implemenlations t o t he o ther. OM c an make a !pA<'C-time trade-off. T he paralLel Midc: r in spac:e i s" t imes la. gcr t han the s e.ial a dtkr ( ignoring the a rea o f t he carry nip .nop). bUl it . . n times fa'te" Tile serial adder. althol/llh it is n t imes .Iowcr. " n t imel . maller in SP.lc:e. 'Ill,s J ive. the d c.igner a s ign,H cant Choice in cmpllasi~ing s peed o r a rea. where m ore a rea t ranslatcs into more CO'lt. 7 -10 H DL R EpRESENTATION F OR S l-HFT R EGISTERS A ND C OUNTERS-VHDL E umple. o f s hih r egi'te. a nd a b ina.y c ounter illustrate t he U'iC o f V IIDt. In " 'prese nting regISters a nd OVC.--ations o n r egiltc. c onlcn!. E XAM""': 7-3 V llOt for _ 4 -llit Shif'! He~l<ter T he Y HDt. r ode in FI gure 7-23 d es.::ribcs a 4 -bitlefl . hift r eg is ter at t he b ehavioral Ie,ct. A R ESin' i nput is p resent t hat d irectly r uet, t he register c onlc nti t o zero. l bc shift r eplcr c ootai", Rip _flops a nd SO h lOl process deC'fipli()fl resembling that o f a D nip-llop. l bc f our nip-flops a rc rep<cscnted by t he l i",al a hHt. o f Iype s td..10lilic_vector o(.~ fou . 0 c annot be ~ t o r eprnentlbe nip-ftops since' it is a n OU tput a nd lhe Ili p-liop o utp ut . must b e ~ internally. T he Ielt ob ifl is a chieved by apply in g t he ooncatenali<MI o perator" t o Ihe right three bits o f s hi f t a nd t o s hift ' nput S 1 . T hi. q uantity is t ransferred to s lli f t moving the 00<1lents o ne bit 10 t he lefl a n d loading th e vnlue o f S l i nto l he rightmost bit. f ollo wing the pr<lCC'S' tllat p erfom" t he shift a re two s tale ments. o ne which Msill'lS t he 3 52 0 CHAI'TEFl. 7 I R.ECIST [R S A ND R EGISTER l RANSFERS - - 4 -bi t Shi ft ~i .t e r w ith Reo et i _, l ibrary u 1_ . ~ td. .y >g ic _ 1l64 a ll ; . "tity o r, LLr i . ""r~ (CLK, RESET . S l i n o tQJ. og i c ; Q ' ou~ 5 tcLlogi c_vec to r( 3 d ownt" 0 ); 00 , ....:I. ou~ s t cLlogi c ) ; ~rg.3_r; u cbiueture beh<ovi orAl o f e LV..-'_r h ....'" .... d """ l . m itt . " cL logi c_vecto rl) d ownto 0 11 p roe. . . (RES l':l" , CLIO it ( RE:5lIT ~ ' 1') t h e n s h it t < _ 000 0 " ; . l.if {C LK . v . n~ a n4 ICLK ~ ~ hitt < _ " hif t {:l ~own~o 0 ) a nd i f , ' 1'11 t b.n ~ S I; e "" p roc. .. , o <~ oh ift ; SO < " . h ilt ( )I ; . n<! b ehaviora l; o n GUilE 7 23 Beh",'ioral V HDL Desc ri p ti on o f 4-bil L eft Shift Regis'er wi,h D irec' R""" \'alue in s hift to output Q and the o t h or which defines the shift Oul signal S O as the contents o f the I dunost bit o f s hift. E XAMI'U: 1_4 V HOl for a 4-011 COlln . er The V HDl c ode in Fig ure 7_24 de>erib<:s a 4_bit c ount er at the behavioral leveL A R ESET i nput is p resent that directly r esets t he c ounlor contents 1 0 ZerO. T he c ounter cont .ins fl ipflops and. t herefore. has a process description resembling that o f a D Hip .flop. T he four flip-Hops a re r~presen l ed by Ihe signal c oun t, o f Iypc st<1..1 og i c_vec t o r " nd o f size four. Q c a nno. b e used to represent the fl ip-flops since it is an o utput and the flip. flo p o utput, n l USI b e used intern ally. C ount ing up is achieved by adding 1 in t he form o f - 0001 to c ou n t. Since a d di tion is nOI a n orm "1 o pe r 'l ion On type s t <1..1 09 ic_ve c t or , it is necessary 1 0 use an additional package from the i ee '" library. s t <1.. 1 ogic_ un a i gn ed. al L which defines unsigned n umo.r o perations on lype s t <1..1 og ic. Following t he process that perfonns reset a nd c ount in g a re two Slalcment s,on e which assigns Ihe value in c o un t 1 0 o utput Q a nd the o lhor which defines Ihe count out sig n al CO . A . .hen_ el,.. stateme nt is used in which c o is set to I o n ly for Ihe max im um count with EN equal to 1. 7_1\ I H UL R """,,,,",,,"" Ibr Shift R<gi><<<, ."J C ounu,n-Il<tilog 0 3 53 i _, l ibrary u i ..- . st,'- logi c _1164_all, " i _ . " <!Jogi",-wuolgned a ll , a ntit y count_4~ i . p ort (CLr; . R I;SlIT, r n , i n . ~log1c, Q , o ut a tdJogic_V<!CtorO 4 ownto 0 ) , CO , o ut . td_loqic), . ".". coun t_Lr; a rcbitactur. b ehavioral o f c oun"-' _ r i . :ignal c ount , . td_lWic_v.etorll _ t o 0 1, b ag-in " roc. . . ( RI;SET, CUo;) ..... i f ( RI;SlIT _ ' 1' 1 . han c ount <_ 0000 , . lair 1 CLr;'event a nd I CLK. ' 1'1 . n4 lEN . COlliIt < _ c ount 0001-, ' I'll t ban . .... H , . nd p roc. . . , Q < - =~, CO < _ ' 1' w hen c ount. 1111 - and EN _ ' 1 ' a l ' 0', . nd b<>havloral, o n GU RE 7 _U Il-ehavionol y tlDl . Desaiplioo o f 4--bit Bina'l' Count"' "'-;th Di=:t ReKt 7 -11 H DL R EpRESENTATION F OR S HIFT R EGISTERS A ND C OUNTERS-VERILOG Examples o f s hift regisler a nd binary counter illustrate the u. . o f Verilog in representing registers and o perations o n register co ll tenL E XAMPLE 7_5 Verilo!: C ode f or a Shift ReKi,je< T he Verilog d~iption in R gure 7-25 describes a left shifl register a t t he behav_ ioral leve l. A RESI>"T inp \! 1 is p 'ese nl thai directly ' C . .l ! the regisler contents 10 zero. The shift register c onl.ins flip-flops. s o h as a process description beginning .... ith a lwaya re . . mhling l ha, o f. D nip-flop_ T he four n ip_ nops are represented by Ihe ve<;lor Q, o f type r -u wilb bil. n umbered 3 down 10 O. T he left s hift is achieved by applying ( I 10 concatonale t he righl three bils o f Q and shift input S I. This q uanlily is IransfeHcd to Q . moving the contento o ne bit t o the lefl " nd lo.ding Ihe value o f S l inlO Ihe righlmosl bil. JUSI prior t o Ih e p,ocess Ihat performs the ' hifl J S4 0 C HAPTER 7 I REG[STER.S A ND R EG[STER TI1..ANSFER5 - . . 1 . & l'}_ 4..r_v (CLK, RESET. S I, Q ,50); l DPUt CLK, R ESEr, S I; o utput [ 3,0) Q ; o utput: 5 0; . ... g [ 3;01 a ssign 90 ...'" Q; ~ 0 13J; a lway " ( po udg. CLK o r . .... . <1".. R ES"") it ( RESer) Q < . 4 ' biJOOO; d- O o <~ ( QI"OI. S I); Ji l GU KE 7_25 1 1<0""""[ "".ix'll Dcs<riplioo o f 4 _t>il L dl Sh ih K 'i i",,, with Pi...,.,l R"""l is a c ontinuou, . "ign ment statcmc nll h.1l a ss igns lhe CO nt ent, of the leftmost bit o f Q to the s hi fl OUlput SigMt so , E XAJI.!I'LE 1 -6 V'rit,,)!: Code for _ C ount er Thc Veri log d,,,,,rip,i on in Figure 7-26 describe, a 4_bit binary c ountcr ~l l he b<;;ha"ioral level. A RESET input i, present that diTCCl ly Tescts t he r egi'ter c on. t cnt, to zero. Th~ ~ounleT c ontains Hip-flop, a nd, therefore. lhe description "Ontain! a process resembling that for a f ) fli p-flop. T he four fli p-Hops are represcnted by the signa l 0 o f lype r eg a nd s ize four, C ou nt ing u p is achieved by a dd ing I 10 Q. P rior t o the process that p"rforms r eset a nd cou nting is a c onditional c ontin u_ Oui ai~ignmenl s talement t hat defines the counl o ut sign.1 CO , c o is set t o I only for l hc maximum counl a nd EN cqual to 1. Note that logica [ A ND i , d enolcd by&&, 7 -12 _ C HAPTER S UMMARY R egi.ters a re s et. of flip _ ops, o r inleTco nn ected se t, of fl ip-flops, a nd combin a fl tional logic, T he . im ple.t r egiiters a re Hip.flop. lhat a re l oaded with new c o ntent. from t heir inpll 1S o n e,'cry clock cycle. M ore comple x a re r eg;'ters in which Ibe flip-Hops c an b e loade d with new c ontent! u nder t he c o nt rol of a . ig nal on only s elected clock cycles, R egi'ter t ransfers a re a m can. o f r epresenting a nd ~pccify in g e leme nt ary p rocessing o p"rat ionl;. R egisler tran .fers c a n b<;; r elmed t o c orre'ponding d igilal system h ardware. b o th a t th e block d iagram 1 _111 Cb>p<.o< Swnnouy / I 4 -bit B inary C cwlur w ith 0 3SS _t _ d _ c ounLU_V I(:LI<. R ESFI', ! lI, 0 , COl, i lVlt c Lle RESET, U l; o utput ( J,O) Q , o utput 0 0; ..... a . . l g" 0 0. l count ~~ t 'bllli n 1 )1 l 'bl) ? I , D, . 1_,," (po. .4 q. . cue. o r p O_"""", u snl H IRS!'l'1 ~. ' 'I>0000; _h_ Q i f 11lI) o ~. __ .~ 0 " WOOl; "h o FI GURE ' ,U; 1 ktIo"icnI Veri..,. Desai",. .. ot H .., 8 ,...,. Coomer wi'" 1 ),,,,,, M.... . level a nd al Ille delailed logic leveL i\herooperalions a rc " emenl ary o per al ions p erformed o n dAta i lore d in register . . Arithme t ic m icrooperations ,nelude oddi li on a nd ' Ublraclion, which a re d e..;rib;:d as regiSler t ran,fe,. a nd are imple. m ent ed with c o rre spo nding h ardware, l .ogic m icrooper.lion s- that is. Ihe bi tw;.., " pplie a1i on o f logic primilive. ~ueh as AND. O R , and X OR , c ombined wit h . binary ,,'or d-provide ma!O king and . ., Ieclive com pl e men ting o n o ther b inary words. Left. a "d r ighl-s hifl m icrooperalions m ove d ata laterally o ne o r m ore bil p osnions a t a . ime. Shih rc",ters IKid a n ew dimension . 0 d ata l ransfer, s;""" . hey I re d es'gned ' 0 " """0 in folYl\ll.ion Ia.erally o ne o r m ore bot p osilion. a. a lime. When combined " ;lh t he a b ili .y 10 be loaded wilh data, a ~ h ,ft rcgi5lcr can b e ....,d 10 convert <\;o t. pr~nted in p arallel inlO d ala p re..,n ted lIe .i a ll y. lihw~, Il lhe o utputl o f the regis, er arc accessi bl e. a . hift r egiS'.r can be " sed 10 c o",e . . d ala pre se nlcd seri. ally into dn1a prCfC m ed in parallel, Th i,lu ternl movement of dma Can also be use d in h ardware struct u, e. lha, perform ..,ria l a r it hmel ic 0p"ration~ C ounters a re use d 10 p rovide a seq..cnce o f value .. often in h,nary counling <:or<k . The simpies' o f r ounte" h a. n o inputs OIher ' han a n . oynch. oooU$ ' .:$et for ini'iaJiz.ation 10 u . o. This ); iDd o f r oun ler simply oouoto clock pulses. More r om p lu ve",ions can also be loaded " 'itll data aDd h.,.., onpulsignah ,h.1 c nable th em 10 o ount . M uhipluers ~Iec . a mong mul1iple . rsnsf.r p ath. eDiering a .-eg'!it.r. Buses a .e ohared . egisler tran.fe . p a'h. for muhiplc , eg;'lers and o lfer r educed hardware in trade for li mi tA ion. on I """ib le . im uh aneous Ir.nsfers. In a ddition 10 multi pl ext ers. t hree . , "t e bulle", e n hance I h. imp icmcn tnt io n of b u"", by providing b;dir",, , io nal transfer pat h! and reduced """nections. 3 56 0 C HAPTE R 7 I 1 liG1STEIt.S A ND REGl~TER T RANSFERS R EFERENCES I. M"NO. M. M. Digilal Desisn. 3rd e d . e nSkwood G ilf. . NJ: Prem ice H a ll . 2002. 2. WAKERLY. J. F Digiml Desig".- Prine'ples a nd T'raCliu\ 3rd e d. UppeT Saddle River. NJ: P rent ic e Hall. 2000 . J . I EEE Standard V IIDL Langaog" R fjf"'''Y Ma""al. (ANS I/I EEE Std 1076. 1'193: Tcvi , ion o f I EEE Std 1076-1987) . New Vork : The In ,tit ut e o f E lectrical and Electronics Engineers. 19'14. 4. I EEE SUmdu,,1 De"CTip 'ion Long""g~ B ased o n I h. Verilog(TM) lliml w"r~ De,wipl"'" u",g "a g~ ( IE EE Std 13641995). New York: T he Instilute o f Electrical a nd EIeClronics Engineers. 1995. S. T um"A'. D. E.. ANn P. R. MOORBY , The Veri/og H ardwure D~.,cril"i" n L~"g""g,' 4 th cd. Boston: Kluwer A cademic Pubtishers. \ 998. P R08UlMS ,~, 11,c p lus, (+) indie"t", a more advanced problem and t he asterisk (0) indicate, a ~ solunon " avaIlable o n lhe Comp; ln ion WebSl t" for the tex!. 7_1. Use manual o r co m pulcr b~sed sim ulmion 10 d emonstr ate that the eI""k gati ng f un ction in Figure 7-I(c) works properly Wil h Ih c Tcgi ste r in Fi gure 7 1(a) , U se a posili,e.cdge.lriggcTcd nip fl op wilh Clock as its d ock in pul If> g ellu" tc Load. Be sure t o u se nonzero g ate And Hip.ftop delays. 7- 2. +Changc lhe O R gale in Figure 7-I(c) int o an A NI) gate. and rem Ow t he in"erter on Load. C~) Perform !he sa me sim ulmion as in P roblem 7_1 t o demf> nSlrale Ihal t he new d ock gating circ uilry dOCi nOI work correctly. E xplain what gocs wrong. (b) Will the ci reui, work r onectly if the fl ip- fl op g enerati ng L Ot/d i. lrigge red by Ihe negative rather than thc positive edge o f Clock? 7 -3 . Assume thM Tegisters R I a nd K2 in Figure , 6 h01' 1 1"'0 unsigned nu mbers. When selcct inp ut X i , eq u al 10 I. the adder---'S ubtractor ci rcuit p erforms Ihe arilhmClic opcrmion " R1 + 2 's co mplement o f R2.--This s um a nd the o utput carry C . a re lransferred in to HI and C when X , _ I a nd a positive edge oce urs on the clock. ( a) Show that if C _ 1. then lhe valu" uansfcrred to R1 is equal to HI ~ m. hUl if C ~ O. t he value trans/erred to HI is the 2's comple ment o f R2 - Rt ( b) In dicate how 1he val ue in 1he C hit can b e used 10 de1ect a b orrow after tho s ubtraction o f two unsigned numbers. 7--4. ' P erform the bitwise logic A ND , O R. a nd X OR o f the t "'o 8-bit o perands IOOIlOOlalld I lfXrtlll . _.n" 0 J S7 7- S. 16-bil operand COXIll l l 10101010. whal o peralion must b e p erformed and what operand mus t b e u ",d ( 0 ) 10 c lear all e "cn bil p ositions t o O? ( A>sumc bit p osilion. a re 15 through o from I dl lo righl.) (b) to sel the leftmost 4 bits 10 I ? (.0) 10 r omplemenl t he c enter S b its? 7-(;. ' Sla n ing from Ihe $obil o per and 01010011. s how the u th shift m icrooperation given in Table 75. 7 -7. ' Modify the register of Figure ' 11 SO Ihat il will o perale according t o Ihe following funclion table using mode selection inpuls 5 , a nd So. Giv~n Ih~ " " " ~ o btained after Regllt ... aperlUon " ~alue$ No ehonge Clear " '3i't.r to 0 Shift d o . .'o Load poraJkl da,. " 7--8. A ring c ounler is shifl register. .. in Figure 7.9. wilh the serial o utput conne<:ted 10 the serial input. tM ) S tarting from an initial stalc o f IOOO.lisllhe sequence o f s tales o f t he four flip.flops afler e ach shift, ( h) Beginning in State 10 . .. 0 . how many Slate. a re , here in the COunt s eque nc e o f a n n-bil ring r ounter? 7- 9. A sw;tch-tail ring c ounter (Johnson c ounler) useS Ihe complement of Ihe serial OUlpUI o f a right shift regisler ... its serial input. (a) Starling from a n inilial state o f COXI. lisl Ihe 5<:quence o f S181e$ a lter e ach . hift unti1111e regisler relu,IIS 10 COXI. ( h) Ilcginning in , tate 00 . __ 0 . how many Slates are Ihere in Ihe c ounl ICquence o f a a ,,bit .witch-tail counle, ? 7- 10. How ma ny flip. Hop values a re c omplemented in an 8bil binary ripple c ounler to reach Ih~ n e"t c ount " alue aft~r (a) 1 I1O[11[? ( b) Ol1ll1l1? 7- 11 . + For t he C MOS logic family. III<: p o"'er r onsumplion is p roportional t o Ihe , um o f the changes f,om I-to-O and 0-10-1 on all gate inputs and o utput. in the circuil. When designing r ounters in very low p ower circuits. ripple r oun lers a re p refer red over regular . ynchronou. binary r ou nl ers. C arefu ll y c ount Ihe numbers o f changing inpulS a nd OUlpUI,. i ndu ding those related to the clock for a c omplele C)'cle o f values in a 4-bil ripple counter "ersu~ a regular synchronou, counler o f Ihe <arne length. I la",d on Ihi' examin al ion. explain why the ripple counter is $uperior in t erm, o f p ower c on,ump.i'm . 7_ 12. C onslruct a 16-bh "'rial-parallel rounter. using four 4-bil parallel counters. Supf'OS" a ll a dded logic is A ND gal'-'$ and serial conn~"Ction< a re employed l SI 0 C IIAPTEIl 7 I RF.GtSTIIlS AND IlEGt~ "Il!.AN SFOlS ~Iw!!, Il, [00' ~" I 'B lliU" 1 m"~"m ""mk, Jl~n pl~ ' ". (, c h"in thai a , ignal m u" p ropagate through in ! be 16bil r ounter? 7_ 1J. t A 64 _bil syn chronou, p ara ll el COunler is I n be designed. 1M) ] )raw the logic diagram o f a 64-bil parallel c ounter. u, ing Sbi! parallel routt!er b lock. a nd two lev el. o f parallel gating r onnedion s between the blocks. In lhese b loch. CO is nOi d ri"en by EN. ( bl WIIa! OS t he ralio o f Ihe m uimum fr~""'ncy o f ~"tion o flh . . r ounte r 10 tlla! o f a 64 -bil...,ri.aI .parallel r oumer? A5Sume that tile D fI,p'tIop p ropaga!J()Illime" ,,,itt t he delay o f a n AI'\"D g ate a n d thal lhe niJ>"t\op ilCtUP time i , e qua l to the d elay o f l tD A ND gale. 7- 14. U unl the sync hronou, binal}' roUn ler o f Fi gure 7 13 a nd an A ND gale. c o n, truct II. c ounler that c ounl. from 0000 I hrough 1010. R epe al for a c oum from 0CUl to 11 10. M in imize Ihe n umbe r o f in pu ts 10 l he A ND l ate. 7-1 5. Uling two b inary counte. . o f t he type shown in Figure 713 a nd logic ga!e5, conSllucl II. b inary COUntC' that cou nlJ f rom decimal 9 !hroug" de<:imal 129. A dd I tn a ddilional input 10!he C<,}Ilnler I hal initializes il lync hronOU!l ly t o 9 " hen Ihe siltlal lN IT" I . 7- 16. Veri fy t he flip-Hop i npu l e quations o f t he synchro tlOU"! B CD r ounle. specified in Table 7--,). D raw l he logic: diagram o f l he S O> CO unter "';Ih a COUn t e nable inpUI. 7- 17. ' Use I ) nip_Hops a nd gal eS to d esign a b inary c ounter " 'i llt e ach of the fo ll owing , epea led b inary sequences: (_) 0.1.2 (b) O.I.2.3.4.S 7- 18.. Use I ).type Hipflop< a nd , ale, 10 design a c ounler ""ith t he following , epealed binal}' seq"",n",,, O. 1 .3.2.4. 6. 7 -19. U se o nly 0 '1)1'" flip-flops 10 design a COUnle, " ;ll1lh e follo\O;ng repeated binary seq"",n",,: O. 1 .2.4.87-ZO. D raw!he logic diagram o f a 4 bil rcgi<le. " 'lh m ode s eleclion inputs S, a nd So. T he , elister is 10 b e o perate d accordina 10 tile following function lable: '. " " , " " 7-21. Show 111. d iagram of the , ,,.tenlenl Regi lier Oper~ll on S o than ge Clear reJi>tcr t o 0 C ompIr . ... n' " "'put Load par.llel doll IInfdwar~ l h.t implements th e re8i. ter transfer !'robIcm. 0 3 59 7- 22. T he o u l pUIS o f registers 110. R I. f a. a nd R J a rc conne<1ed through 4, . .. 1 multiple~ers to t ~ i nputs o f 8 f ounh regiSter R4. E ach r egister is 8 bIts long. T h e r equired translers. as dicta ted by f our c ontrol variables. a re C~ : H4 .... RO C,: H4 .... R I Ct : R4 .... f a C): R4 .... R l T he c ontrol v anables a re m utually u cluSive ( i.e" o nly o ne v ariable c an be e q ual to I a l Bny ti me) while l he o ther t hree a re e qual ' 0 O. A I..,. n o t ra n,fer i nto R 4 is to occur for a ll control v anable, e qual to O. ( a) Usi ng r egiller, a nd a m ultiplexer. d raw a d~tailcd logic d iagram o f t he h nrd w.re t ha t i mplemcnll a sing le bit o f t hese register . . ansfers. ( b) l )raw a logic d iagram o f t he l im ple logic thai maps t he c ontrol variablCli as i nputs t o o utputs t hat a u t he t wo se lect n riab l for the m ultiplu"", 1 OUtp UI . 0 t hat a re I h. l oad signals f or r egi,ten. 7_11 ' Uling t wo 4-b,t r<:gI'te", Rl a nd H2. a nd Ao'l D gates. O R p td. a nd in>"erters. d raw o ne bit s litt o f I~ logic di.agnlm l ha, i mplemcnu a ll o f t he following $latements: Co : R 2t-O C ea r f a synchronously wit h t he clock C ,: H2 .... H2 C om plement R2 TraMf.r H lto H2 l be c ontrol v ariables are mUlually u clusi..., (i.e.. only o ne v ariable n n b e e qual 10 I a l a ny l ime) " 'hile 11M: o tlter tWO a re e qual 10 O. i \1so, no t ",nsfer i nto f a is t o O tto, for all ront rot variables " 'luBlto O. 7_24. A register <;ell is 10 be d esigned for t n 8 .bil r egister A Ihat has Ihe follOwing rcaister t mnsfer functions: Co:A .... A,,11 C ,:A ...... A v'B Find o ptimum l or: using A ND. O R. a nd N OT ~ale5 f or t he 0 ' npul 10 t he o flip-fIop'n the c ell 7- 25.. A r cps.er cell is t o b e d igned for I n S .bit regislcr RO that hItS t he follow' n& r cgistcr monsfer functions: S,S,,:RO ...... O S, ' So:HO .... HOv R l 3 60 0 C HAPTER 7 I R EGISTERS A N]) R EGtSTER l RANSFERS J,tMJJUI S ,'So:RO<---ROARI Find optimum logic using AND, O R. and N OT gates for the D input to the D fli p-flop in t he cell. 7- Z6. A Tegister cell is t o be designed for register B, which has the following registeT t ransfers: S ,:B +- 8 + ,1 S",B<---B + I S hare the combi nat io nal logic between t he two t rans fe rs as much as lK>Ssi hlc imp k m~nltra n ,fcrs ;!mon g lhree Tegi.lers. NO. R I . a nd R2. is to be implemented. U se the c ontrol variable a s.u mpt io n, gi"en in Probl em 7_2. The register tran sfers ;! rc", fol lo"'-,: 1 _27. Logic t o C A: R I+- RO C B: RO ..... R 1.R2+-RO Cc : RI ..... R2.RO ..... R 2 Us in g rcgisle r,; and d ed icat ed m ultiple' er$, d r "w a d etai ted logic diagram u f the hardv.-arc lhat impleme nls a single bil of th es.c register transfers. Draw a logic di agram o f . imp te lugit that e o m'erts the c o ntrol vari able~ ( .\. C. . and Cc as inp uts to o utputs thnt a re the SIOLEcr in puts for Ihe mu lt iplexers a nd L OAD signa ls for the registers. 7- 28. "Two register t ramfer , talcm e"ts are gi" en ( otherwi,e. ]{ I is unchanged) C,: R I+- Rl + R2 A ddR2l0RI C ,C l : R I ..... HI + I In crement HI (a) U,ing a 4bit co unter with p ara ll e ll o.d a , in !-.gure 7_13 a n d a 4 hit a dder as in FiguTe 55. draw the logic diagram that implements t hese register transfers. (b) R epeat part (a) using a 4 -bit adde r as in Figure 5-5 plus externa l gates as n ee ded . Compare with the impleme ntation in I"'rt ( a) , 1-29. R epea t Prohlem 7- 27 using one mu ll iplcxcrbaw d bus and one direct connection from o ne re giste r to a nother ins tead o f d ed icated multip le xers. 7_ ~ . D raw a logic d iag"' m o f a bu, s)'stem similar t o the o ne , ho"'n in Figure 7.7. b ut usc three -s ta te buffers and a d ecoder instead o f the mu ll iplcx cTS- 7-31. " A , ),.Ie m is 10 have t he followi ng sct o f register transfers, im pleme nted usin g h u,es: l'robI<nu 0 3 61 C,' RO f- RI C b, R 3f-RI. R I f - R4. R 4f- RO C ,' R 2f-R3 . RO<-R2 C o'R2<-R4.R4 <- R2 (~) For "aeh d e.t in.tion register. li,t a ll o f t he sou ""," r egi.tem ( b) For eac h sou ""," register. li st a ll o f t he d estination r~gi.teffi (~) Wi th cons id eration for wh ich o f the transfers must occur simultaneously. w hat is the minimum number o f buses that can b e used to impicment the set o f transfers? A ssume that each register will h.we I I s ingle bus as its mput. (d) O raw a b lock diagram of the system . showing t he rcg.istcrs a nd buses and the conn ccti<>nS between them. 7 - 32, T he following register transfers a re t o be executed in, " t most. two clock cydes: RO <- RI R2<- RI R 4<-R 2 R6 <- R3 R 8<-R3 R Y<-R4 RIO <- R4 R I I<-RI (a) What i . the minim um number " f ~usc s r equir ed? A ssume thaI o n ly o ne b,,~ c .n be a uached 10 a reg.ister input a nd I h"t any n et conn e<;led 10 . register input is counted 0 $" ~US(h) Draw a b lock diagram conn e<: li ng register.< ~nd mu lt ipic x" .... 10 implemen t the tra nsfem 7-33. What is t he minimum number o f d ock cycl e, requi red to perform the following s et of register 1ra nsfers usi ng two buses? RO <- Ri R7 .... R I R2 .... R3 R 5 <-R6 A ssume th.t o n ly one bus can be a ttached to a register input and that any nel c onnected t o a register input is counted a . a bus. 7- 3-1 . ' The con tcnt o f a 4-b;t register is in iti"Hy (lOOO , T he register is sh ifted eight time. t o the right. with the s equence 10 11 (0)1 a , the serial in put. ' li te IcftmO'it bit o f Ihe SC<Juence is applied fn',,- What i< t he co nt ent of the regi<ler a fle r each . hift? 7 - .\5 T he serial adder o f Figure 7 22 uses two 4-bit regi<tcrs. Register A h olds the bina ry n um ber 0111 a nd register B hold, 0101 The carry nip .nop is initially 3 62 0 C HAI'TER 7 I R EGISTERS A ND R EGISTER ' JRANSFERS r eset t o O. List the binary values in register A and the c arry Mip .Mop a fter each o f four shifts. , All files referred t o in the remaining problems a rc a_ailable in ASCI t lorm lor si mu lation a nd e d iting on the C ompanion Website for the text. A V HDL or VeTl log compiler/simulator i . "ece.,;ary for the problems o r p ortions of problems requesting simulation. Descriptions can still be written, however. for many p rob l em. without us ing compilation o r . ;mul,,;o o. 7- 36. ' W rite a beha"ioral V HDL description fo r the 4 bit register in Figure 7_ 1 ( a) . Compile and . imulate your descript io n t o d emonstrate correctness. 7 -37. Repeat problem 7-36 for the 4 bit register with parallel load in Figure 7 2. 7- 38. Write a V HDL description for the 4 bit binary oounter in Figure 7- 13 using a register fo r the 0 6ip-60ps and Soolean e q uations for the logic. Compile a nd sim ulate your description to demonstrate oorrectness. 7- 39. Write a b ehavior Verilog description for the 4-bit register in Figure Compile and s im ulate your description to demonstrate c orrectn ess. 7' ( a) . 7-40. Repeat problem 5 39 for the 4b it register wi th p arallclload in Figure 7 2. 7-41. Write a Vcr ilog description for the 4-b it bi nary counler in Figure 7- 13 using a register for the 0 Hip Hop' a nd S oolean e q u"tions for the logic. Compile a nd simulate your description t o d emonstrate oorrectness. ,0, " -ii'S.&-~ ~ ~;~!i,Q " ' . i ;n~O~ , - ".".' - , a ,[~~., , . "~ilg.~:1 ,~ ~ ~ ~ 'j , .,,' "'." <> ::"' ~c!!" CO~!~ 3 :,,3 ~Ol;;-~s. ~~,~;r .. i .. to <II <3 'i,~ " Q!J..@lS'g a -!.!i[;~t:> ~p, ~-g '", ~~ ~ C " , ,,, I 5 '~ii''I'~,"L ;[iih~ ~ i:"i~,' =-S-~S!.~l":3' 2 l . = 1O~~i5. ~ 'C:-< ~" ~g,"I' ;' '''i'S2.''' ~ ~_. i ~ <Ii ' " 1\" g ;,. iii is. = ?I ~ \l. ~,.. ~ ~":E ;'C~ 3 3, <> 3 1< ., " ;/O c z 3 '" g-g~~l~ ii ~ .H ~i[~ g ~.H]~~~i !h~~.i~-8. [~i~ ;~i'"'" _ ~3g g i .. - sil";<>, ,,,,,, !II " ~- R~].2 ~! c ~ t ;ld ~~,~ ~ ~ ~ ~~~[hi~~ar ~;'l'" 5 3 ~ ~i" ~~ ~ &~.! 2,liI" -"i>: c~ " i 'ln '5"5"',.." -f h' " ,.!.,'.! Qi(-~ii;i' : P" g!l"' :;! .2 H,-, 0I-~!. _ . . 3 [ . . ~ ~2: s- ,.. - ~ ~. ii",3"i'>_'~iIi ., -ii'~'g. 3 11'0 1> " ai.@i.,,,, _ - l ;;;?g:I: 3 ::ro; "' i! :S ' ~~j' ,:!.i!.s "' '' ''' 12" 5" 0" I l. ,.. $~-~~fo'!i!:~Cl~ " '_.-" ... ;i ;;'!!,~ ., "'- ,..-{I):> ~ ~- .3 !<l~P ; ';li;oi!!.ii'" ~~I<>"'5!:Siil'll. 3 "" 3 8s-odl. 3 .8 q: ~; - -" co ~_ " ,;",,,3 i 3.!:!Q ~!il" 3 "'3" 11: &"' ~"~ 11~,,"t:T ~I-~" 5" i!1 ' ~~H_ ~ ~~1i5 ~~ g:hrh: ~ i~:il~~"'~~~ r~i~~ig~~~~a ' ii l[.~ ~ . " g ". ~ ~" :Ii ~ ~ ,,~~ ',--g. .. ; ! ~ 9 ' ~ <:l i" . "h.i:"i o 'H' '~_~;'\. ~Q. =~i".~ " '''' ~ >" 3 ! ,!I "!. &.~ ~ ."Ii ".. co &. <; h.5~ g 3? S!. .I Ie. @ 2.'" g~2."',~",' ::> S ., ~ . . <i'i c. * ~ii ~~ li!"g~~~ ' i - qi fl~ ' l'ji% , ,,-g. O -l => 9 '" " , " c. ~VJ t im D n~ On z Z >-l _ ?=I Z 00 t'""" C HAPTER 8 I S~QUENCING A NI) C ONTROL 3 64 0 8 -1 T HE C ONTROL U NIT T he bina ry informalion ' Iored in a digilal c omputer can be classified as e ilher d al a o r c<K1!rol i nfonn. lion. As "'e " ,w in Ihe p reviou. c haplcr. dala is manipulal~d in a d alapalh by using m~ralions i mplemenled wilh r egi.ler Iransfers. These operations a re implemented " i tb a dder- sublracto . .... hifle .... registers. multip tucrs. a nd buses. T he c onlrol unil p rovides signals Ihal activate Ihe various microopcralions wilhin Ihe d a lapalh 10 p erform I h. specified processing lasks. T h. c ontrol unil also d elcrm in r:s t he seq uence in which t he ,arious aClions a re p erformed. B ecause Ihe logic design o f a dir,ilal syslem is o flen lTealed in Iwo dislinCl p an" Ihe r .gisler a nd r egi,ler I ransfer design for d atapalhs was o ov.rcd in e napler 7 a nd the design o f Ihe c onl'oJ unil is o overed in Ihis c haple . G .nerally. Ihe liming o f all regisl . ... io a s ynchronous digilal syslem is c on Irolled by a m aster clock gencralOr. The clock pulses are applied 10 all Hip_Hops a nd r egi'te ... in Ihe syslem. including I hose in Ihe conlrol unit. T o p revent clock pulses fro m ch~ n ging t he ' I,n. o f a ll registers On every cl ock cycle. SOme regislers haye a load c onnol signal Ihal e nab l. .. an d d isable. Ihe loading o f n ew d ala i nlo t he reg ler. T he binary variables t hai r onl'ol Ihe selection inpulS o f m ultipluers. buses, a nd pr<><:tSSing logic a nd Ihe load control i nputs o f r egislers a r e genera l ed by t he c omrol uni!. T he c onl'oJ unil Ihat g enerale. l he signals for >C<juencing Ihe m icrooperalion' is a s equential circuil .... ilh s lales Ihal dictale I he c omrol signals for the s)"Slcm. AI any give n time. the s tate o f t he sequential circuit activates a p'ese,it>cd sel o f mic roopera tions. U sing slalU, c on di lions and c ontrol inputs. Ihe " ,que ntia l c omro l unit d elermin cs Ihe next s lale. The digil.l circuil Ihal aclS a. Ibe c onlrol unil provides a s cquen"" o f signals for aClivaling Ihe m ic,ooperations a nd a lso d elermines its Own nexi siale. Based on Ihe a .crall s y.lem design. t here a re 1.... 0 dislinci t ypes o f conlroJ u nils used in digilal syslems. one fo r a r-rogrammable ')"Slem a nd t he Dlher fOT a n onprogrammable sySlem. In a p'ogrammabl~ s )srem. a p orlion o f I he input 10 Ihe p rocessor consist. o f a s equence o f j n"",c,jOn$. E ach in\lruction specif,es Ihe ol)Cralion th at Ihe sySlem is t o p erform ..... hich o perands 10 use. where 10 p ia"" Ihe result, o f I he o peralion . and. in s ome cases. which instruction to e xecute next. F<)T p rogrammable S)'llems. Ihe inSlruClion$ a re usually siored in memory. e ;th., in R AM o r in RD.\{. T o e xe cUle l he i nstructions in oequence. il is necessary t o p rovide t h. m emory address o f Ihe inst'UClion to be e xecuted . This a ddress comes from a . egisler c alled Ihe pro gram collmer (PC). A s Ihe name implies. the P C has logic I hal permits i llo c ounl. In a ddition. in order t o c hange Ihe seq uence o f o pcral ions using decisions based on st alUs infonna tion from Ihe d atapal h. Ihe P C n eeds p arallel l oad capabi li ty. So. in t he c ase o f a p rogramm.ble system. t he r on"o l unil r onlains a P C a n d associal ed decision logic. as well as Ihe necessary logic 10 i merprel Ihe i n'lrucli on . E xum;"g a n i nstruclion m ean. a clh:uing the necessary s equen"" o f m icrooperalions i n t he d alapalh r equired 10 p erform the o peralion specified by Ihe ins1n>C1ion. F or a m mprogrommable s prem. t he comrol unil is nol r esponsible for o b,ain. ing instructions f rom memory. n or is il responsible for s equencing Ihe eXe<;mion o f those instruction s. T here is n o P C o r si milar r egi.ter in such a system. Instead . t he control un it d etennines t he o pe rations t o b e p erform"d and t he s equence o f t hose opera l ion" b ased o n il s inputs and the SlatllS b il' from Ihe d atapalh , Th is c h.pler focuses o n non programmable system d esign , I t ill uslrates t he use o f a lgori thmic st ate m achines ( ASMs) f or c o ntrol unit design plus special ized techniques for ASM implemenlalion. Programmable ,),stcms a re c overed in Chaplc,.,; 10 a nd 12. 8 -2 A L GO RJTHMI C S T AT E l \1ACHI NES A processing I. . k ca n b e defmed by register t ra ns fer mi crooperations c ontrolled by a sequencing mechani,m. Such a task can b e specified as a hardware algorilhm that consists of a finite number o f proce dural s leps thai perform the p rocessing t as k. The most challenging and c reat ive part of dig it al design i . the formulalion of hardware algorilhms Ihal nchie," the r equired o bjecti,es. A h ardware algorithm can be u sed as a b a, is for bolh the data path and the control unit of a system, A flowc hart is a conve ni ent way t o specify a sequence o f p rocedural sleps and decision p aths fo r a n a lgorithm. A flowcl'" rt for a h ardware algorithm mu st have speci.1 ch.rnCleristi", Ihat tic it closely 10 Ihe hardware implementation of Ihe algorithm, As a consequence. we use a spe ci al flo weharl called an a/gor;I"mic Slalr m achine ( ASM) chart to d e li ne digital hardware algorith ms. A .Ulle ",achille is j ust a nolher t erm for a s equent ial cireuit. T he AS M c hart resem ble,. conventional Howchart. b ut is interpreted somewhal differently. A conventional Howchart describes p rocedural slep' a nd deci,ion palhs wilhout a ny concern for thcir relatio nship 10 time. B y contr""l. thc AS"] chart provides not only a sequence o f events, b ut is distinguished by the faci lhal it describes Ihe li ming relalionship t>clween l hc Siaies o f the c ontrol unit and Ihe datap .lh aClions that o ccur in t he stales in response t o clock pulses, T he ASM C hart T he ASM chart contains three basic d eme nt s: the state box. t he scalar decision box. a nd Ihe conditional o utput b o x, as illu strated in Figure 81. For con,enience. a f ounh d eme nt. t ~ e >"ector d cci, ion bo~, h ;ts been a d ded. This a ddiliona l component s impli fi es r epresentalion 01 mulliway decisions and eSlablishes a corresponde nce belween H D L r epresenlalions . nd ASM Charls. A state in Ihe control sequence is indic.ted by a stale box. as shown in Figure 8-1 ( al . Th e . Ulle b ox is r""t .ngle conlaining register Iransfcr o pera lions Or o u tpu t signals that are acti" aled wh il e the c o nt rol unil is in the state. Implicit ly, activalion o{ an outp ut signal means . ssigning a value o f I 10 ' he SIg naL T he symbolic name lor t he s tate is p laced a t the upper left c omer o f the box. and the binar), c ode for the Sla t e, if assigned, is p lace<! a t Ihe upper right c orner o f the box. Figure 8-1(b) sho ws a specific e xam p le o f a slate b o x. T he stale has t hc $ )' m Ix) li c name IDL E. and the bi nary c ode assigned 10 it i. COl. Inside Ihe box is Ihe register Iransler R <---- 0 a nd the output RUN. The regisler transfer indicales t hai Ihe 3 66 C H"'PTER 8 I S EQUENCING " 'ND COr-ITRO~ 0 En'l)' I ~" En'l)' B,ool)' c_ IDLE Rosi<'" "1"""';"" <>r ""tPII' I l ,., e o, ~ I E." 1:: , ;1 ( .) S t.,e b o. ( b) E. .mp!< 01 . .... box R' ~" '<t "1"""';"" <>r ov' p ut . ,." 0 f u" 1 ! E:.i, ( e) c ..na;t""'" ( e) Sc.l>. <Ie<:isioo b ox "'i, 2" - I ""'PII' bo> o H G U REII-I ASM o.ar! E lcmen" regi$te< R is 1 0 be r esel 1 0 0 o n any d oc k pul >e Ihal QC<;urs w hile I he c ontrol is in s tate I DL E . R UN i ndicate. t haI t he o utput signal R UN i. 1 0 b e 1 d uring I he l ime I ha, Ihe coniroi i . in Siale I DLE . R UN is 1 f or any Slate box in whi<:h il a ppears a nd i .O f or a ny Slate box in which il d oes n01 a pp"a r. n 'e sc~/nT ,/~cisio" b tu dcsc<ibes the effect o f an inpUI o n I he <xmlroL II is a d iamond - shaped b ox wilh lwo exit palhs, a s s hown in Figure 8-1(c). T he i"pUi COn dilion i . " s;ngle b inary input vari~ble o r a s ingle Boolean expression d ependenl o nly u pon inpUls, O ne exil p alh i . l aken i f t he i nput c ondition i . l rue ( I). a nd t he othe< i .ta ken if lhe i nput c ondition is false (0). T he t hird e lentent. Ihe condilio"tI/ ompul b tu, is u nique t o t he A SM c han. T he oval s hape o f t he box i , . hown in Figure g l(d). T he r ounded COme ... differellliale i t from the 5Iale box . T he c nlry p ath IQ a r ondil,onal OUipUi box f rom a $ tate box musl pass Ihrough o ne o r m ore decision boxes. If Ihe c onditions "pecified o n l he p alh t hr ough t he decision box es leading f rom l he " t ~te box 1 0 a c onditional OUlpUi box a re satisfied, Ihe register Ira"sfe~ o r OU tputs listed inside the r ond itional o u,put box a re a cti,.te d. TIle _ tk<-i.tion b tu """,",'n in Figure 8.]{e) describes I he e ffert o f a v ector funCliQn Qf i nput. o n t he r ontrol. I t i . a h exagon-.haped bo~ with u p 1 0 2" e~ it p aths f or an n -element b inary , ector. T he i npul c ondition is a v ectm o f " , . I bina!)' input variables m Hoolean e>pressions d ependcnt uport only I he i npuls A n e xit p ath is t aken if I he veclor v alue m atch "" t he label r o r rcspond ing to the e~ ;1 p at h. 8-2 I Algori"",,;" S<ate M, chin. . IDLE r""ry 0 3 67 ASM BLOCK A VAil 1 I ;. i, " START , ' -0 ( ) f 00 01 ~ """'/0 1 M ULO J. IlJEX;" M OW M Ull M OW o F IGURES! AS),,! Bloc k A n AS!>! M od consist, o f one s late box and all o f the d eci,ion a nd c ondi tional o utput boxes c onnected between the . tate box exit a nd e nt ry p aths to lhe same o r o t her s tate boxes. A n example o f a n ASM hlock is shown in Figure 8 2, T he block represcms decisions and o u tput aCl ions that c .n t ake place in Ihe state, A ny o u tputs f or which condilions a re satisfied within the ASM block are aClivated in Ihe bloc k. Any register t ran,fers for wh ich condilions a re satisfied wit h in Ihe ASM block will be execUied when Ihe clock evcm occurs. This s ame clock evenl will a lso I ransfu c onlrol lo the next s tate as specified by decisions wilhin the AS.\{ bl oc k. For the block in R gure 8-2, t he , talc is I DLE. While in the s iale I DLE . Ihe OUlpUi A VAIL is equal 10 L If S TART is O. then t he next state is I DLE. If S TART is I . Ihen at Ihe clock e vem.A is c leared 10 all 0',. and, depending on Ihe value o f the " eclor Q( I: O), t he nexl slale is MULO. MU Ll . M ULl. o r M ULl , In Ihe figure. Ihe enlry path and the five exit p aths for the AS)"1 block are labeled . t the boundaries o f the ASM block , T he AS M c hart is really a form o f s tate diagram for I he sequcnlial circuit p art o f the c ontrol unit. Each state box is equivalcnt to a n ode in the s tate diagram. The d eci,ion boxes a re C<jui"a lent t o input values On I he li n e, thaI c onne ct nod"'! in the diagram, T he register I, ansfers and o utput, in lhe s tate boxc~ a nd the conditional o utput boxes correspond t o the outputs o f the s equtntial circu it , OUlput, in " state 3 68 0 C HAI'T ER 8 I S EQUENCING A NO C OrvTROL box a rc IhOC Ihal ",ould be specified 0 0 a s lale n ode in Ihe slale diagram wilh a M oore model dependency. OUlputs in a condiliOllal o utpul b ox correspond 1 0 Ihe input valu .,,; o n the lines conne.:ling stales in I he stale diagram. Since theS<! d epend OIl the inputs. a Mealy model d ependency is p re"'''l. If all d ependencies in an ASM are M """, model dependencies (i.e.. . th~re a re no conditional OUlput bo~es). the ASM is a Moore modeL. [ f l here a re o ne o r more condi lion al bo~es " ;lh Mealy dependency. t he ASM i~ a M uiy model. T im[ng C onsIderations In o rder 10 clarify l he timing c on.ide"" i",,, for the ASM. ".., uSC tile sample ASM block in Fi gure 8-2. n ", timing o f the events related to s tale IDLE is illustrated in Figure 8-3 . In considering the ti ming o f th e", e\"ents. re.:ali lhal only positive-<:dge- Ir;,ggered Rip-ftO!J$ a re used. During clock cycle [. the control unit is in present stale [O LE. OUlpul A VAIL i~ I . and inpul S TARTis O. Based on the ASM b lock. w ""n a positi," ~Iock e dge 0 ttUr$. the stale r"mains at rOLE. a nd A VAIL remains at I . Also, the comem. o f register A remain unchanged. In c lod: cycLe 2. STA RT becomes I . S o when the ne~1 positive clock edge occurs. register A is cleared t o O. With S TART a t L Q(I:O) is e xamined and found 10 he 01. For this value. wh~n the clock edge 0 ttUr$. t h" n Ut . ute b coomcs M ULL l be n ew . tate M Ull and the n ew value o f A botb a pp"ar at the beginning o f ~lock cycl~ 3. l be value o f A VAIL h eromes D.since A VAIL d ocs nol a ppear in llle Slate box for Slate MU Ll . NOIe l hat the o utput A VAIL _ 1 a ppears oonrurrcntly , ,;\h I h" pres<:nt stale l D t E. b ut the result o f the register transfer for A a ppears concurrently wilh the next s tate MU tl . This is b crouse OUlputS ooxur as)"JICbronou~ly in response to $tal~ and inpul ,alues. " "t regist er !ransfen a nd . tate changes both wait until tile next positive c lod edge. I C lod <),<"1<2 I O<:><k < )'<Ie J I ~-===~"-=====~"~======I S TART _ SlOl< XMULt l DLE o F lG U HF.1I-3 A SM Timin , Bcbavioo- 6-1 I ASM 0 .." Ex. mp l., 10111 3 69 Muitipl"",," 10011 0 M uitip"", - _.. 10111 10111 10111 110110101 o ~'IGURE 8-4 Hand M"lhplioa'ion &amplo 8 -3 A SM CHART E XAMPLES A binary multiplier is used to iUUSlralC ASM c han f ormulalion, The mu ltiplier multiplies two ,,-bit unsigned integers t o produce a m _bit integer result. Binary Multiplier In lhis example. we i ntroduce a hardware algorithm for binary multiplication. propose a , imple d alapath a nd c ontrol unit for its implementation. and then describe its register trans{crs a nd c ontrol b)' use o f an ASM. The s)'stem used for illustration multiplie. two unsigned binary n umber .. In Section 5-5. a hardware algor it hm to e ,ecute this m ul tiplication without using srorage c lement. r esuhed in a c ombinational multiplier with m any a dders a nd A ND gate .. In contrast. the hardware algo. rithm d eveloped here results in a sequenti.1 mUltiplier that useS o~ly o ~ e a dder a nd a long shift register. T he . Igorithm is ill ustrated, the register transfer structure p roposed. a nd the ASM c hart formulated. M ULTIPLICATION A LGORfTMM T he multiplication o f two unsigned b inary n umbers is done with paper and pencil by succcssi,'c Shifts o f c opies o f the mul .i plicand (0 Ihe left and a n addition. The process is best illustrated with a n aClual exa mp le . Let uS m~ltiply t he two binary n umbers 10111 and 10011. as <ho".., in Fig ure 8-4. To carry o ut the multiplication. we look . t s ucce"ive b il:\ o f the mul1 iplier. least signi ficant bit first. If the multiplier bit is I, the multiplicand is copied down for ~se in (he addition 10 fo ll ow. 0 1herwise O's a re copied dow n. T he nu m be~ oopied in succe"ive lines a re shifted o ne position t o the left from the pre>'ious ~umber c opied, (0 a lign Ihem with (he respective mU lt iplier b it being prottS$ed. Finally, the num bers a re addcd and their sum fOnTIS t he product. NOle t hat the product oblained b)' multipl)'ing two ,,bit binary n umbers can h a,'c up to i l, b it' for n :1: 2. W hen the muhiplication procedure is i mplemented wit h d igi(al h ardware. it is useful to cbange the process ,lightly. First. instead o f ha" ing a digital circuit that a dds n binary numbers ,imultancously, it i, less cxpensive to provide a circuit t h.t a dds just Iwo numbe~ Each (imo l he m uhiplicand o r O's a re copied. the)' a re immediately added to aparTial product. T he p artial product is stored in a register in 3 70 a C HAPTER B I S EQUENCING A NI) C Ol'ITRO L pr~par'l;oo tor I he $h:lt aetlon 10 'oll ow_ ! koood. ;nslead o f sl..:fI; og Ihc cop,es o f t he multiplicand to th~ 1~lt. th~ p ania l product is shifte<l to th~ right. This le.~es Ih~ p an ial p roducl a nd t he copy o f Ihe muhip~cand in Ihe same relali~e p osilion as Ih~ I dt s hill 01 the multiplicand did. But. more importanl. instead o f a 2 " -bil adder. only a n ,,bit a dder is n eeded.1be addition aJ"-a},> t akes pla ce in Ihe " "me" pos;tions. in stead o f mo";n8 10 I he lefl ooe bit position each l imc.'hird. wh en the corresponding bit in tile multiplier is O. t here is n o n eed to add all O's t o Ihe p ani.l p roduct. since Ihis d oes n ot alter ito resulting value. T he mulliplication example is relICated in B gurc 85 with t hese chang"" N ote I halth c initial partial product is O. Each time the multiplier bit being prOC<!>oSCd is I. a n additioo o f the multiplicand. follo"'cd by a right shift. is p erfonncd. Each lime I he multiplier bil is a O. only a right shift is performed. O ne o f Ihese Iwo actions i . ])erfonned for u ch bit o f Ihe mulliplier. $ 0 in this case. five such a ctions occur. A n unsigned overflow occurring d uring a n addition is indicaled in blue. This overflow is n ot a p roblem. however. si nce the right Sh ift Ihat i mmediately follows brings the exira partial p roduct bil into Ihe regular most significant bit position. M ULTlPUER B LOCK D lAGRAII The block diagram for the binary multiplier is . ho"" in Figure~. The multiplier datapath is first COIlSlructcd from componcnlS covered in previOU$ chapters. All bUI counl er P a rc u pandcd 10 n bilS: c ounle, P " 'quires flog:" l bits for counling the processing o f I he" bits o f the multiplier. ( r xl d cnot . . I he &m all e$t i nteger g realer than o r e q ual to .t_) W e use the parallel adder from B gure 5.5. a parallel.load "'gister B si milar to I~ gu re 7.2. and parallel.load shift rcgiSl e<s A and Q $imilar to Figur. 710, C ounter P is a '-c<sion o f the parallelload ". . Mul1;pb<ond Mul1ip1i<r 1 01\1 P.",,]pO<Joct 0 10 11 1 Pat".t ",O<Joct . ft ,M, I~t \I lOOlt ",,;,.! 1""'" t p rod"'" A dd " ,wb{>ta..!.';"'" 1 !!!!! A dd ! Q!!L tOOOIOI . ~ mut';pti<r t>it ; . 1 _ .0<1 b or"", ,M, mu"ipl ><>"" .';D mu '"p1 ier to. ;. 1 p . .... t proooct . fter " "" . "" boforo: . . a t' P ''"'t ~ o~", ""if! ' 1000'01 P o"do[ prod<><1 . ~'" 01000101 .M, 001000101 P."", ",odoct or"r .!Jill! A dd 1101 to ' O I OIlOtlOtOI P ." . . I rr"'-'oct ofter 000;1 . ..1 mu ],jpl><>"" . .. """ mulliplier ton ;. , P rod"", o f"r r....t . , l <ote .11.0, o " "if] .M, ""'on: "';1\ "".rn- "n>p>rori/y """"r1<><l, F l GU KE8-5 H.t<J . ... re Mulliplic.aliott E xample 8 -3 I A SM C har, E x.mpk. 0 3 11 c ounter in Figure 7- 14 t hat c ounts down instead of up, a nd C is a flip-flop that can be either synchronously cleared t o 0 Or l oaded from C"",. T hese d .t.p.th com~ ncnts a re c onnected a , s ho"''' in Figure 8-6 . T he multiplicand is loaded into register B f rom IN. t he m u lt iplier is loaded i nto register Q from IN. a nd t he partial product is f onned in r egister A a nd stored in registers A a nd Q. Th is d ual use o f Q is possible because we Use a rig.hl shifl of the multiplier in Q t o e xam in e each suecessi'-e mult ip lier b it t hat a ppears in Q". T he right shift vacates the m06t signi6cant bit in regisler Q. T his.pace accepts t he least significant bit of the partial product from A as it is s hifted. T he n bit binary a dder i , used f or a dd in g B t oA. T he C flip-flop s tores t he c arry C """ whether 0 o r 1. from the addi1ion and i . reset 10 0 d u ri ng the right ohifl. In o rder to count t he Du mber o f addshift o r s hifl actions that a rc to oc<:u r. counter P is prov i d~d_ I t is initially s et to n - I a nd counted down af1er the formation o f e a ch partial product. T he value in P is chec k ~d j ust bcfo r~ it is decremented. S o" o perations oc<:u r, o ne operation for each value in /" n - I d own t hrou gh O. E ach o peration is either an . add and shift o r j ust a shifL When P c ontains O the final product is in the d ouble r egister A a nd Q. a nd p roces,ing 'lOp'The c ontrol unit s t ay< in a n initial state until t he Go signal G b ecomes L T hen t he . ystem s lans the multiplication . T he sum o f A a nd B f onns the N most significant bits o f the partial product. w hkh is t ransferred back to A . C_ from t he add i tio~ is t ran5fcrred t o C B oth th~ p artial prod uct a nd t he m ultiplier in A a nd Q a re shi fted to the right. The c arry from C . hi fts i nto t he most signifiCll nt bit o f A . "' j Muh;plioc.ond R, ~ " Coun"" P r " ",0 r 1 B " Z ero d e t ed "- ( Go) ~,~ , 0 O. un ;' , Pm l.,loddo, 0- , " Multiplier ShLI, ",,,,1<r A Sh,ft ",,,,1<' 0 -m o~ C"", ,,,l ~Y'.t. o H G U RE3-6 Btock P '.gram lor B;"ory Mu ltiptier J 72 CHAP'T'ER 8 I S EQUENCING AND CO,,""T'RQL 0 the le8$t significa nt bit o f A shifts into t he m ost signlfK:ant bit o f Q. a nd I he leasl . ignificant bil o f Q is d iscarded. A fter this right_shift o ""ralion. o ne ( additional) bil o f Ihe pMtial p roduct has lransferred i nto Q. a nd the multip~er b its haye s hifted OIlC position t o t he right. In this m anner. t he te ast significant bit o f Q. Qo. always hoLds t he bil o f t he m ultiplier I hat Ihe COIllrol unil e xamines n ex\. T he c ontrol u nit ~decides" w helher t o add. basd o n I he value o f I h is b it I t a lso c be<:b s ignal Z. which is 1 for P equal 10 z ero a nd 0 for P n onzero, to d etermine w hether t he multi_ plicalion is finished . Q oand Z a re I he Status input> for the oonlrol unit. wilh i np ul G as I he o n ly eXlernal c ontrol i nput. T h e c ontrol signals from the o ontrol u nit to the d alapal h activalc t he re quired m icroo pe r3l ions. MUL...-uER ASM C.......,. A n A SM chan giving t he o equence o f o ""r ations in l be b inary m ultiplier", s hown in Fi g""" 8-7 . I nitially.lhe multiplicand is in 8 a nd l he m ulliplier in Q. T he l oading o f t hese Iwo ""&isters is !lOt h andled e~plicitly by t he m ultiplier c on t rOl unil. A s long as . he A SM", in s la.e I D LE. a nd G is O. DO " " lions occur. a nd . he A SM remains in I DLE. T he m u ltiplication process Slatts when G b oome, J. A s Ihe A SM mOves f rom Slale I D LE 10 Slale MULO. regislen; C a nd A a re c leared to O. a nd the co unt er P is l oaded with the constant n _ L I n Slale M UUJ. a decision is m ade based u poo Q o.the l east significant bit o f Q .lf Qo is I . the c ontents o f 8 a re a dded t v t hose o f A . wilh t he r esult Iransf~rred t o A a nd the c arry l ransferred 10 C. If Qo is O. reg;,;ter A a nd bit C are lef. u nchanged. In b olh cas.eo.. t he next s tate;s M ULl . In s ta. e M ULl. a rigllt s hift is p erform ed o n the c ombined c on.ents o f C .A. a nd Q . T his shift c an be e xpre...,d by the som~ w hal m e.sy liSl o f h e simult aneo", register transfers: C <--- O. A {n _ I ) <--- C.A <--- Sf A . Q{n _ I ) <--- A{O). Q <--- <r Q T o simplify r epresentation o f th;s o peration. we add bit o f nOl ~hon. using II to define a composj,~ ugjSl~r m ade u p o f o ther r egisters o r pieces o f O lher registers. T his <>peml>On. lI. is c alled c oncalmaljOll. For exam ple. C II A II Q r epresents a si ngle register o b tained by c ombi ni ng registers C. A a nd Q from the mOSI significanl e nd t o Ihe least signific.nt e nd. We c .n use . his c omposite regiSler ' 0 r epresent t he riglll <hift C IIA II Q <--- I f C IIA II Q a s s hown i n f igure !!--7. R ecalllh.t we a re assuming . h.t Ihe leftmost b i. o f Ihe result for a right sh ift l akes v n t he val ue 0 unless other",ise spoc ifi ed. so C becomes O. This is r epresent ed e xplicitly, h owever. in the A SM char._ since C is sel t o 0 i n a nother s late as well . T he e xp licit listing a llow, C <--- 0 10 b e p erfor med by using a single c on rrol signal for b o.h st at e. . C ounler P is d ecremented in M U Ll . T he value i n P i . c hecked in s lale M ULl b efore l 'is d ecremented. T his i llustrates a y ery i n'portant t in,ing d iffere"", b etween. Sl a ndard flowchart a nd an A SM c han. T he d ecision o n Z , which represent. l ' O. follows t he register transfer . t ate ment t hat u pdalt< P in the A S)'l K S-J J ASM C h.o" E.OrrIpl 0 3 73 I OLE --l " , , I C<-O.A<-O P "' n-! M ew " J" , I A .... A + B, , - 'MULl C <-O.CIIA UQ <-"C I A I Q, P <-P-l " o --l , , F IGURE H7 ASM Chart for Bin.ry Mult iplier chart. Since the decision on P is [ "'rformed asynchronously and the regisler trans fer s tatement is . ynchrono us " ilh the next positive clock edge. the de<;i\ion o n P precede< the u pdate of P. A l the next d ock edge. when P i , u pdated, the result o f this decision is ava il able to delermine the next stato. The I i.,;t" - 1 times t hat P is c hecked, its content is nonzero. 00 Sialus bil Z remains 0. and the loop, consisling o f sta te, M UUl and M ULl, is executed aga in . The n ih time P is Checked . the con tent o f P is zero. SO s tat u, bit Z is I, This indicates that t he multiplication is com plete. causing t he ASM 10 re!Urn t o . tale I DLE. T he final producl is a ,'a il able in A II Q. with A holding the n most significant bilS and Q t he" least significant bits o f 3 74 0 C HAI'1UI. 8 I Sf.QUI:NONG Ar<U C ONTROL , I r-1j ~~, " - I I , R....... ll I ~\ Z<ro < kl e<1 j (Go) P .,. lk l ' - r \ " Ri JII ' Shift ~,~ -, " 'I u-: I f.... M~~;pti R<&o""r A --I S II;f\_rQ ~ 'j ',J I OUi I " I --'-- , 0 C _O, A O-O P . .. . - l M l'l r \ ~ I Q'-"~ U (A . O) I O 1 00 / "' ,-, , I Q.- .. ~ . tA.O) I ~ .....l, "'-- '" """/ ' " I ~ II O"'''~ I IAI H) I ~ I EI O"' ''~II( A HI) ' ,0> o n <:UMt.: II-lI A I ma~>'C: Brr. . ry M IIl.iplier 8_~ I H.rdwired C ootroi 0 37S t he product. I t i . w orthwhile t o r ee.amine t he h ardware m ultiplication e ,ample f or " - 5 in Figure 8 5. this t ime c onsidering the r elationship to the d atapath a nd the How o f t he A SM c hart. "The type o f regi<;tcrs se\cetcd for the d atapath correspond to the m ierooperalions listed in the ASM chart. R cgi<;tcr A is a shift regi<1er with parallel load that accepts the sum from t~ adder. I t also needs a synchronous clear l o,..,..,t the register to O. Regis ter Q is a shift register. T he C flip-Hop needs t o accept t he inpul c arry and also needs a synchronous clear. Registers B and Q a bo need parallclload in order to load t he mulliplicand . 'nd the multiplier prior 10 the $tart o f l he m ultiplication process. Figure 8-8 sho ....~ an al ternali,c multiplier design that uses Ihe .-ector decision box in its A SM chart. In p art (a) o f the rtgure. Shift Regist er A has been replaced by a combinalional rigl,1 shifter that , hilts I bit to the right. similar t o Figure 5 13). a nd a register with load e nable as shown in Figure 1-2. Thi. combines the a dder with a combinational right shift. n,i s p enn its t he number o f states used in Ihe ASM c han in Figure 8~ to b e reduced t o j ust OllC. In o rder to r eprcscnl t he c hange in the multiplier ,iHtapath. it is necessary to write a regisler transfer s tatement that combines the addition with the shift. Also. the dmapath c hange permits Ihe Aip-Hop C 10 b e deleted. A..suming t halllt e combined delay o f the a dder a nd right shift (which consists only o f wires) is nO more t han the "dder. t he r<."duction in s lates in the multiply l oop substantially speeds up the multiplication o peration. To i llu,I,"le Ihe ,cctor decisiol, box . ...e have used concatenation 10 c ombine Z and Qo into the .-ector (Z. Qo) wh ich is d enoled as Z II Q.,. T he decision based o n this vCl1or;5 s ho wn in the c enter o f t~ A SM chart in Ftgure 8-8(b). There a re f om o utput combination~ r or ' he c omltin"ions in which Z i$ 1. t he next Slate is I DLE. For the combinations in ...hich Z " O.the next s tate is MUL. For Ihe (X)rnbinalions in which QD " 1. t he output i~ an add.righl 'hi!1 wilh input o perand, A a nd B .and [or the c ombina tions in which Q~ . . o. the o utput is an add-right shi'l wilh i nput o perands A a nd O. T hese a re r epresentcd hy t he combined add and shift transfers in conditional output boxes l or the [our output c ombinalion5 , '" Z II Qo- 8-4 H ARDWIRED C ONTROL I n i mplemenling a c ontrol unit. t ...o d istinct a spects must b e c onsidered: t he c on t ro l o f t he n ticrooperations a nd t he " ,quencing o f t he control u nit a nd m ieroopcrations. Very simply pUI. t he first h a, t o d o ... ith the part o f t he control t hat gener~ t es the c ontro l signals. a nd the second has to d o with the part o f t he e ontro l that d eter m ine> w hal h appen, next. [ [ere. we s eparate t hese t wo a spects by dividing t he o rig. inal A SM specification into t ...O p.rlS: a t able Ihat M fines the c ontrol . ignals in t erms o f Slates a nd inputs. a nd a . implified A SM c hart t hat r epresents o nly transi t ion. from s tate t o s tate A lthough ...e a re s eparating these two aspects for d esign purposes. t hey can s hare logic. The control signals a re b ased o n t he ASM c hart. T he control signals n eeded for t he m ultiplier d atapath a re listed in Table 8-1. where we have chosen t o e xam i ne t he d ata path r egisters and tabulate Ihe microop<:rations for each r egister. l Iased o n t he tabulated m icrooperations. the c ontrol signals a re d efined. A c ontrol 3 76 [) [ ) T A .BLE _. C H APT!;IlS ' SEQUENCING A ND C OI'ITRO L _. -- 8-. Co nn... S iplh ,. .. K ....,. M uldplkf alocl<~m Iol",,,, , ,*.clon R< ~ i'l.r A : Signal Ha. ... "., . Inilialize A .... A C I AIIQ .... " CI AII Q R<~'lot B: Flip. Flop c : ! I_IN C., a .... I N CMAIQ~ C oonlet r: I'_N _' 1' .... MUI.o Q Shil, <Ie<: M ULl """ , "",,_0 " "" C lea,-C C~C_ R cl"l"' Q: I Dt E, G ~. . . C IA I Q I.OADB I DLE G . M ULl I .l)ADQ Shirl <lee Initialize S hifl_dec 1'-. " gn al c an be used for aClivalin. m ic .oopcroliom in more Ihan o ne regi5ler. This is .ealiOnabie. in Ih . . casco ~1I('e Ihe d al~palh is d<:dicaled 10 only one Operalion . mulliplication. ThUs, lhe r om.ol s i&nals d o nol need 10 be s cparaled I'l provid<: Ih e generalily required for implemcnling addilional, potentially u nkno wn operalions, FinaUy. Ihe Boolean exp. ession fo. eac h conlrol si gnal is deri.'ed from Ihe local ion o . l oc.lions of Ihe microope'alion in I~C ASM c hart , For e xampl e. for register A . t here a re t h.ee microopcraiions Ihown in Table &-1: d ear. add and load, and right shift, Since the elcar Operation always occurs al Ihe . ame time a s Ih e c~ar for nipflop C a nd Ihe loading 01 c ounler P. aU o f lhese microopcrations Can b e ac livaled by t he s ameronlrol " ",a l. nam ed [n il ioli= Because C i sdeared in Siale MU Ll as ...'eU. h owe,er. we cl>oou: I'l separale r ontrol ligna!. S o Initialize is u sed for d earing A and lo3ding P. In t he IasI column fOf Initia[ize. lhe Boolean expression fOf . .l lich In;lia"ze is 10 be act;,c. as delermined from lbe ASM chart. is l iven in c~rms o f the s late I DLE and ;npul G. Since lnicialize is Co b e I " 'hen G is I in stace I DLE . I DLE a nd G are A NI)ed . .... c this point. Ihe name fOf lhe , lai C is trea ted I . I Boolean ""riabl e. D ependin8 on the implementation, Ih.erc may be luch a I i"",[ . epresenting Ihe Slai C. or lhe Sia le may need I'l b e e xpressed a function o f tbe Slate variables. The ligna[ f or c~aring C. C1ea . _C, is t o be a.cIive in I iale I DLE for G equal to l . as well as in Siale MULL, ThUs, G is A NDed wil h IDLE. Dnd Ihe resu lt is O Red wilh M ULl. T he ' llher IWO internal multiplier c onlro l signals. Load and Shi ft _Dec. are <k~ned in a similar manner. The final Iwo signa[s. Lo"d_U and Lood_Q. load Ihe m ultiplicand and multiplier from oUlside Ihe m ult ip li er syste m. These signals will nol be consi d er~d exp[ icilly in Ihe r emainder of the design , With t he i nlonnalion o n microoperations removed. we can redraw Ihe ASM chat! so Ihal only Ihe informs lion On sequencing i . r epresenled, 111is modified ASM chart for the binary mult iplM:. a ppeul in Ftgure 89. NOIe Ihal all ' l f t he conditional OUlpul bo~. . hove been removed. [n addition. any d ecition box nOl . I (ttI ing tbe ""~I Slate is rCIDO\'ed. In ~rticular. in Figure &-7. lhe decision box Q. '1$ m 00 1. , G ., " ew MlJ U o '" , , F lG UNE H9 Seq""l>tin~ Part o f AS),! O ar! for (be I li".ry Multipher a ffected only a conditional o utpu t OOx_ One:<: 1hat renditional o utput box is removed. Ihe 1wo exil p alh, from decisiOll box Qo clearly g o 10 the " "me stale. S o I hi. decision box has no d f"", (>n the next , Iale and is remove<!. From th i' modified AS M cha n . we can design tne sequencing p an o f the w ntrol unit (i ,e., Ihe p arI Ihat represents Ihe next ,tale b ehavior). T he d ivision o f oonl rol i nl0 nexl-Slale b e hav ior in Ihe fo,m o f lhe modified ASM c han a nd o ut p ut b ehavior in t he f orm of t he c onlrol s ignallable , ho". . h ow the ASM oorres p onds 10 Ihc nex(-$l a le and o utput parts o f a ,""quen!i.1 circuit. Fi gure 8-9 c orre'ponds 1 0 t he OI al e diagram o f a s equential circuit wilhoul lhe o ulpulS specified, u ce pl (hal Ihe r epusen! a lion' "od in t he d iagram for s tales a n d I ra",ilions a re different. Because o f Ihis c orrespo ndence. we c an I rCRllhe ASM c hari a s a s lale d iagram a nd form a slale l able f or Ihe sequencing p art o f Ihe cont rol unil. T hen t he c om rot u nit c a n b e d esigned by Ihe s eq uenlial logic design proce d ure. a s oUllined in C hapter 4. H owe~e r . in man y case s.lhis me lhod is d iffIcult to c arry o u' because o f t he large n umber o f s tates for a typical c ontro l unil. As a c onsequence. we u se s peciatiud m ethods for c ontrot unit design I hat are ~aria l io", o f I he classical sequential logic methods. We next present a nd i llustrale t wo such d es ign met hods. 3 78 C C t IAI"nR 8 1 S EQUENCING AN I) C ONTROL S eq uence Register a nd D ecoder T he se q ~ence r egisl.r a nd d ecoder m~lhod. as Ihe n ame implies. U$CS a s equence regiSler fur Ihe c o ntrol Slates a nd a d oxoder 10 provide a n OUIPUI signal COrre s pon di ng 10 each o f the sial. .. A r~8iS I ~ r wi l h" Hip-Hops e a n have up 10 2 " sl al e, a nd a n " ,10-2" d ecoder has up 10 2 " OUlpulS. o ne for eac h o f Ihe . Ialet. A n , , bil " "Iucnce rcJiSler is e _ nt ;ally" ~ ip-flops. ">gel h er wilh Ihe Msocialed g aits I hal d fW Iheir $lale lransilions. A d diliOllllllogoc .....y be r equired 10 p roduce Ihe nec c sury c onlrol signal OUlpul . . TIle s equencing p an o flhe A SM c han for l he binary mulliplier I w I hrec . ules and I...... inpuLS. T o implem<cnl Ihe ASM chat! " 'Ih a $ njucnce register a nd ~T. " 'e need I...... /lip-flops f or l he regislcr and a 2'10-4-~ne d ecoder. S,nce lhere ore Ihree $lates. only I hree o f t he four deoodc:r OIllpulS a re used. A llhough Ih;,; is a simple example. t he proce<lure 10 be o u llined " pp lieo 10 m ore comple~ , ilu,'iOllI as well. "Il,e Slale lable for the SI."<Iucncing pari o f the con trol uni t is shown in Table 8-- 2: it is derived directly from Ihe AS.\t chari in Figure 8-9. w~ <ksi8!'l'lC the 110'0 Hi pIIops as M, a nd Mo and lL'lSigIIlhe binary ~al" 00. 0 1. and 10 t o I DLE . MULO. a nd M ULl. rcspecth'ely. NUle Ihallho: .npul oolumr\'i " '''e unspecil\cd c" tries ( x) wilen C"er lUI input ~ari3b1c is n ul used 10 d e.ermine the " "X, . ule. The o u .puts o f the s.eq . ..ncing p art o f 1 M con'roI a re d csipalcd by ' he 5Ia'e names. The binary r ode f or lhe prefCnl Slalc de.crmi . ... Ihe particular o utput ~ariablc that is e<j .... , lo I at a n y gi,-en lime. ' llI l1t. when l he preocnt 5Iale iJ M,M~ ~ 00. " "t pul I D LE e<juals I . ",bile lhe OIber OUtput. e qual O. Since the5e OUlpUlI ~nd on lhe p rncnl 5I~le only, they c;o n b e g<:nenled with Ihe 2-10-4-li"" d eoodu having i nput' M ,and M . a nd OU lp ut, I DLE. MULO. a nd M UL L A s menlion~d e a rlier. t he sequ~ntial circuit c an b e d esi8ned from I he s tate t able by m uns o f t he . .,quen tial log;c d e.ign p rocedure p resente d in C hapter 4, Thill e Umple has a s m all n umber o f t lale. a nd i npul . . " " we eQuid use map" 1 0 s implify llIe a oolean f unction . . In mos. r on trollogi<: application!\, lIowever. the n umber o f t . a'e< i . m uch l ar,er . The a pplicalion 01 tile conventional D ,ethod [ J T A BLE &-2 S tate T. .... r. .. S eq""".. K<'ti>t er . .... D erode r Par. ur M ..ltiplier C " n' roI Unl. -, 1 01 MUU> MULl , , , .. ~ Input. O Ko<Ior O utput. G , ,, , Y, .. I OlE MUlO , , , , , , ,,,, , , , , ,, , ,, ,,, , ,, , , , , , ,, , , , M Ul l H I H . d...m.l Con""" 0 1 79 r~quir~s ~xcessiv~ work t o o btain Ibe simplified inpu t e qual ions for tbe fl ip- floJlS. H ere, tbe de> ign can b e s im plified if w e l ake i nto c onsideration Ih~ fact t hat the de.:oder OUtpull are available for use in the design, Instead o f using flip-flop outp ut!; as th ~ pr~sent s t al e conditions, w~ might as w~1I use Ihe oUlputs o f th~ d ecoder to o btain Ih is i nformation. These o u tputs s upply a single signal r epre senting e ac h o f Ih e poosible present slates o f the circ uit. Moreover. in sle ad of using maps 10 simplify Ihe flip_flop equalions, we can o bt ain t hem di rectly by insp"clion o f t be s tate table. Fo. e ump le. f rom I he nexl -st ale c onditions in I he l able. we find Ihat l he nexl Slate o f Mo i . e qu al t o 1 when I he present state is ID l. E and i nput G is e qua l 10 t o r w hen the p resent <late is M Ull a nd i nput Z is equal 10 O. T hese conditions give D . .. . I Dl.E G + MUll Z for the D i nput o f l he M o nip-nop. Similarly.tbe D i npul o f Ibe M, flip-nop is D,"" ~ M ULO NOle Ihat these equations deri,'ed by ill5 peclion ffOm th e stale l able use tbe s late n ames ra lher Ihan Ihe state variable n ames, sinc.: the de<:<:>d er p roducing Ih e state symbols is present. In some cases, it may be possible t o fin d simpler D nip-flop input equaliOfls by using the s tale variab le:5 directly instead o f the stat C$. We Ca n remove redundancy a nd r edu 005t by writing the Boolean equations for the decoder a nd applying a simp li ficalion program to the set o f control e quation . . T he logic diagrarn for th e c ontrol a ppears in Figure 8 - 10. I t OOnS i!l$ o f a twObit regisler wilh fli p-fl ops M, a nd Mo a nd a 2 t0-4line decoder. T he three o utputs , V ~ - '" a o I ri' J I'" I" , ,, , 0 =-- .. I'IG U R 8-10 Conlrol Uni, foc Binary Mutliplicr U.in, 0 .'ic<jUCTlCC R <~1CC ODd a Decoder l 80 0 C II"PTER 8 I SEQUENCING " ND C OI'ITROL ot (he decoder are used (0 generate the con(rol outputs. wcllll$ inputs to the next_ftate logic. T h e outputs Jnitiali u, CJea,_C, ShifUJec, " nd L oad are <!ete,mined f ,om Table g.1. I nitialize a nd S hift_dec " ,e already available . , ,ignals, s o t hat only lat>e lcd o ut put lines a re ndded. I l owever. as show n in t he figure, we must add logic a ales fo, C lca,_C a nd Load. We c omplete the bi nary multiplier d e.ign by connecting the o utput. o f t he c onlrol u nillO Ihe oonlrol in pun o f the d ala pal h. O ne F lip-Flop per State A nolher po6ilble m ethod o f o ontrollogic d esiJII;' l he " '" o f o ne nip-Mop p er Slate. A nip-ftop is u slgned t o e ach o f Ihe stalC$, a nd al a ny lime. o nly o ne o f t M nipflops OOf1lains 1. with .11 l he rCit conlaining O. " ''hen Ihe I I . in l he fli p-flop a s.igned 10 a p articular 5t a te.lhe s equential circuit is in that "'me s tate . '!be . ingle I p ropagales IrQm o ne flip-nop to a nQllier un der t he oo nt rol o f d eci,ion logic. In , uch a oonRg uralion. e a ch fl ipflop represents a s late t h .t i . p resenl only when t he sing]" 1 is t lored in t he flip-H op. 11 is o b"ious Ihal. s hon o f IQme errOf deteclion m oorreelion techniques. this m elhod uses the maximum n umber o f flip-nop'! I ", Ihe sequential circuit_ F m n amplc. a s equen tial circuit wilh 12 Slales using m inimum >"Iriable encoding n ds f our ftip-ft<>p<. " '''th o ne Hlp -llop p er . tatc. t~ t im."t " 'quires 12 nip-H<>p<. o ne for e ach i late.A t first g lance. il m ay ~m Ihat Ihis m ethod ...-ould ;nc"'ase t~ ooot o f t he ' )"llem. since mOre Hip-Hops a re Il~d. B ut t M m ethod offe~ s ome cost advl nlages I h. 1 may n ot b e a pparent. O ne a d".ntage is Ihe simplicity with which t he logic c an b e d esigned-merely by inspeclion o f t he A SM churl o r . tate dia_ gram. N o s tale o r e xci tation tablet . re n ee ded if D ftip. n o~ a rc ~mployed. T hi. orrers a s~vin(lS in d e.ign e flort. Figure 8 -[[ . hows t he s ymbol replacement rules f m t rans forming an A S M cha n i nlo a ~quenl i a l c ircuit wit h o ne Hip -llap p e r $ta\~. T hese r ules a re " ""I easily applied 10 an A SM c han r epresenting ()fIly o cquencing information . such as t hat o f f igure 8-9. E ach r ule speci~es Ihe r eplacemenl Qf a c omponent ' lfa" A SM c hart Wil h a logic cireuiL As shown in !- gure 8 -1I(a). t he $Iale box is r eplaced by . a D fti p_noplabeled with t he n ame o f Ihe State. The e ntry t o t he Slate box oorresponds t o t he D i nput 10 t he flip-flop. T he u i t o f t he s tate b ox oorre~pond. t o Ihe outpU I o f t he Hip_nop. In Fi8 ure S -l1(b). t he scalar decision b o) is replaced by a 2_way d emu lli plexer. T he signal o orresponding 10 Ihe entry 10 the decision box i$ $Cnt t o o ne Qf two exil line $. d epend ing o n t he v alue o f , i",al x.1f X i . O. t he &ignal i . $ Cmlo I he u il 0 lone : il X i . I. the s i,nal is sent 10 t he exit I line. for example. if the . ingle 1 in t he circuit i . ()fI t be e ntry tQ l he deCIsion box. a n d X ;' O. 11Ie I is pa~ t o t he u il 0 line. T he (\cmultiplexer a el.lik e . ....,Ich t hat d irects t he I Ihroug.h lhe p aths In t he cireuil CQlTcsponding t o p aths on l he ASM cbart. In f igure R-11(c), t he " eclor decision box is replatt<! by an n _ ,.."y d emult iplexer. The lignal corresponding 10 l he cI li ry tQ tile decision box is s em 10 o ne o f t he 1!' - I lin~depending on the " slue o f t he . i",al vOXlor X ' " Xr;. . X ... I If X i . O .lhe ~isna l I. selll to the exit 0 line: if X i t 9, Ihe .ignal is $Cn t 10 Ihe eXil 9 line. So. for e xample. if the si ngle I in the circuit is 011 Ihe cnlry t o the decision box, a nd X is 9. s... ~ 4 I H .rdwired C ootml ~'" ) E otry TIl ( .)S1Ooo. '"~ En.IY ~, ( II) S cala, Doci<ioD B ox E ntry D EMUX " '" C ,-'- '" , e' . r- x..x, .... x. . .~ O. (e) V ectOf Deti!.ioD Box ( d)Juoct;"" o t lGUKE l I-U T ,o",fofn>a'iooJ RnIc: . fOl" O :mt,oI U nit " ith 0 "" F1ip-1'l<>!> pef SlO t. 0 381 3 82 0 CI-lAPTF.R 8 I S EQUENCING AND C ONTROL the I is passed t o the n it 9 line. T he d emuhiplexer acts like a switch that directs t M I through t M pat h. in Ihe circuit corresponding to paths in t M ASM c han. n..: junction in Figure S ll(d) i$ any point a t , ,hich two o r rno..., directed lines in the ASM c hart join together. I f a I is present in the d rcu it o n a ny line corresponding t o one of the e ntry p a t hs. t hen it m ust appear o n the line c orresponding t o the exit path. &i'ing that line the value I. I f none of the li nes c orresponding t o eOl ry p ath. intO the junction have the value I . t hen Ihe exit line muSt have Ihc value O. Thus.. Ihe junction is r eplaced by an O R gate. Wit h thes.e four transformations. t M s.eq ueneing p an o f the ASM c hart can be rep laced by a circuit with Ofle Hipnop p er stale. just b y inspeelion. In o rde r t o handle o utp uts. it is merely a matter o f a tt aching c on!follines t o the p roper locations in the circuit Or a dding OUlput logic. The outpulS a re b ased 00 the origina l ASM c hart o r the cont rol s ign.l lable deri,ed from the c hart . Anaching a con trol line based on a n ASM c han is illustrated b y the conditional outpu t '001 shown in Figure 8-] I (e). T he condilional OUlput 'oox in the ASM c han is just replaced by a co",,",,cti on in Ihe eircuil. B ut to c ause the outpul actions t o h appen. a control line is t apped from Ihe co nnc'Ction and labeled with the output variable. The Ira nsfor mation i . sho"n in blue fo r clarity. We nOW uSC these t ransfonnations t o find the c ontrol unit with o ne nip-nop p er sta te for Ihe binary multiplier. E XAMPLE 8-1 Hina ry Multipli . . T he AS)'! charI in Figure 8-9 will be uS<'d for the sequencing p art o f the design. N<.>te t hai the binary codes &i,e n a re ignored. since t hey we..., for the former design approach. The resulting logic diagram i. shown in Figure 812. First. we. replace e ach o f Ihe t hree s tate 'oo~es by a 0 nip-nop labeled " it h the name of the state. as indicaled by I he circled 15 in the figure. SeCOf'd. each o f the deciSion '001es is replaced by a dem ultiplexer with t he d",,;sion ~a ri able as its selection input. as indicated by the circled 2s in t he figure. T hird. each junction is replaced by a n O R gate. as indicated by the circled n . FInally. the c onnections rep...,s.ented by t he directed lines in the AS M c han a rc added from the outputs 10 the inputs o f lhe c orresponding c ompo"""ts To h .ndle the control Out PUIs.. we can use eithe r Ta ble H ] o r the original ASM c hart in Fig ure 8 7. From the table. we s.ee t hat the Boolean function for Initia li ze is al ready avai lab le in the logic diagram. SO we simply add the o utpul labeled Initialize. Li kewis.e. the output for S hih_ dec c an be a dded. For O ear_C a nd Load. how e ,,,r. logic gates a re added. All o f the o utput connectio"" a nd logic a d ded a rc designaled by tbe circled 4s in Fi gure 8-12. O ne final i. .... in Ihe design o f I he control logic with One /l ip. nor pe r <l ale is initialization 10 the .t.'1e h .,ing a 1 in the ID LE lIip.llop and a 0 in all o f Ihe o ther . . This e,in be d one by u sing an as)nchronous PRES ET input o n the ID LE ni p .nop a nd a n asynchronous C LEAR on the other nip-nops. [f only a n asynchronous C L E AR i . a vailable. r .ther I h.n b oth P RESET a nd C LEAR. a N OT g ate can be placed just before the D input a nd a nother N OT gate jU'it a fter the !I--I I Hardwired c .""roI r'y 383 (]) l OLl: '-" <D (]) D EMU)( "- " G- '" G. i ll I- 0 (]) ~11l In;,;, ,; ,,, Gl <D o, , M UU , <D i ll ~. D EMU X ,- " '" G. O. o n GU R E3.12 Con trol Un;, ,,-ith One Fl ip-Flop per St ot. fo< 1he B;nary MuJ';plier OU1PU1 o f t he I D LE nip-Hop . Then 1he IDLE nip.Hop will actually c ont ai n a 0 ,,-hen in 51ate I D LE and a I a l a n o ther times. T hi. p ermiu the asynchronous C LEAR t o be " ",d 1 0 inilialize all t hree fli p- flops in I he ci r~uil . h should be not~d t hai. o ther than ror r esell;ng l h~ cin;uil. Ihe US<: o r asynchronous Hip- fl op inputs for implementing AS M. o r ocher sequential c in;uilS i . generally p oor design pr a< l ioe . 3 84 0 CHAJ'TER 8 I S EQUENCING AND CONTR-OL Once the basic design o f the c omrol logic with o ne flip-flop per state is completed, it may be ~sirab l e t o refine the design. For example, if there a rc a n umber 0 1 junctions connected together by lines. the O R gates that res~lted from the t ran ... formation may be combined. Atso, demultiplexe ... casca~d ""ith each o ther may b e combined. O th er logic reduction o r a nd lechnology mapping may also b e applied t o Ihe design. 8- 5 H DL R EPRESENTATION O F T HE B INARY M ULTIPLIER- VHDL T he hinary muhiplier jusl Slud;w can be represented during the design process a . a behavioral V IIDL description. Such a d.e$cription for a 4bit .'ersion of Ihe multiplier a ppea" in f i gures So\3 and So14. Th is V H DL code represents the block diagram in f igure S-6 and Ihe ASM chart in f igure So7. Th e V HD L code consists of e n tily b inary--,"ul t ipl i er and an architecture b o!havior_ 4 , The architecture COIlt ains two assignment statemenlS and Ihree processes. The processes arc simit;!r to Ihose used lor the " "quena: .ecognizer in C hapter 6. The primary difference is thaI the outpul function proo::>:U h a. been replaced by a process describing t he d atapath rcgisler \ransler>. Due 10 Ihis c hange.lhe VH DL representalion COI.esponds more closely 10 Ihe description in Table Sol and Ihe ASM ch~rt in f igure 89 Ihan 10 , he ASM c han in Figure So7. In Ihe entity. muttipti er inputs and OUlputs a re defined. A llhe beginning of the a .chilecture, a type declaration defines Ihe three Sla le s Internal signals some of which wil l g enerate registe ... a rc d edared nexl. Among the "" a re s tat . . and n "xL"tat . . for the conlro!. registers A. a . p a~J Q , and Hip-Hop C. Also. interme diale signal Z ;s ~dared lor convenience. Next, an assignment is made which forttS Z 10 be I w henevu P contains value O. FoltQ\>;ng this., Ihe OUlPUl$ o f concatenated regislers A and Q are assigned t o tbe mulliplier OUlput M llLT _ Olrr. This is necessary, r atherlhan making A and Q cir~ u it OUlputs.. to permit A a nd Q t o b e uSC<J wilhin tbe circui t. 111e r emainder o f I he description c<>n~iS1S of Ihe thrc<> processes. T he first process describes the s tate register " nd i ndude . a RESET . s welt as the docking. T he $ Ond prO<:<:$! describes the next slate function from Fi gure So8. Note Ih.l, S;""" clocking a nd RESET are included in the slale regisler, lhey d o nOi a ppea. here. In Ihe sensitivity list, alt signals that can affect the nexl Slale. G. z. a nd I Itate are included. O the rwise. Ihis prO<:<:$! . ,..,mb le , Ihat for I he n e x t _ stat" p 'QCe$$ in the sequence recognizer, T he final process in F igur. 8-14 J e",ribes Ihe datapalh function . Since the cond it ions for performing an operation are defined in t erm, of the s tal", and inputs. this p.ocess also imp licitly d er."e. the oo ntrol . igna ls given in Thble SL The"" ooOlrol .ignals d o not appear explicitl y. howeve r, Since the dalapath function has regislers as all assignment J('$\inalions., a n I rande"ar. oontroll'"<l by eLI<. Since OOments will be loaded imo these regi.ter~ b efo.e the multiply operalion is ever p erformed, it is unnecessary 10 provide a reset for the"" regist",.,. T he first i f . ta tement controls Ihe loading of the multiplicand in registu B and the second i f s talement c onlrot, Ihe toading o f the multiplier ;"10 regiSle r Q . ~ e o ~1 ~ , , . !' " " .. , , . , , , ' i B J -;:1 1 ,H ! : 1' I - I i; ". ~ O~ ~;"", .is ~ " l j ~~ :<: .. .... .. ~ i ~ I~ '. ; ,.. "I I-J!J " .... . ....... i ~ , . .. , 0 ",... ~ .. 0 .~ ... ~ .. ~ ~ ",.,I, i: ~~iH )~ ~~ ~ ~':::''''13'' . . 3"'''...I ~ -~ ~ .~ , ,"" u " ... , . ...... .. ~ ' -<1')12 "' ',',. ... ... :l ..... ... " - ! . !_ , : J 'II~ " "~ o ,-' -! .. . ! ! , ~ J! - ',' '1 i, y _ :... . 5.:. , o 8 '-.0 ' o i ~ i I .v . . , , ,' "... . ~. . d : ... .:;!,! a '" H ,, . . . . ' , , " 0. v ~ ~ I" ! '~W .. ~!t~S t , MJ 3 .8.'8':l!!1 a~ -~'" l'l !_&1l~ " , , '" i "' .. l iivo v .. " ", . .. '~ .!!-'-"J ,. J ., 2"'1" J ~ . . .. ; _, . "._!' " , "" . . 3,3 ' , i ~ . , .. ... .. ' '1 oi ,! -.~\ ~ c - .d '" :l " I" ;: = d a~ ! ~-~ ii~~:' ' j .:.l .... .. .l."'i. . " '1 " . ) '10., ",,1.. ~,S;::;:!m' :1 . zi'''' . e . fc: . .... " 1-::& .. . .. ,... . .. ' " ..~..'", , .. -': '" -~ ..... 00 " 0 '. . . ~ 'iLco.u ~tI .. A ~ . . .... .... ........ 0< "' " t!' " ~ ... , I .. '<! ,i ~0 ! ,8 0 ro: s:: o 38 6 C HAPTER ~ I S EQUF.NCING A N ]) C ONTRO l, 0 _ c an, ...., "roc".; ..,,,. "roe. .. d at_tll,..!w>c, . . ~i &bh 0 . , If 1ClJ<1 n~_logic_vec to rl ' a nd eLK . ' 1' t hen 8 < . K iLT_lN, . . <>4 H , 1ClJ<' ~t U _ e o 0) , ' 1 ' 1 t h .o o ! .(;JI,:e i f I.OM>;l ' 1' U .... Q < . MULT_ rN, .on<! U , c . . . n at . . h _ I DLE _ > H G _ ' 1' th<On C <. ' 0 ' , A < . ' 0000 ' , p~. ' 11", _<>4 I f, " h<00 I<I)LO _> H Q IO) ' 1 ' t hen 0 . , . ( '0' ' ' ' ) ( '0" 8 1, . In o ., C . .. , . <>4 I f, C < . C A.(') , . . < _ CA.(3 dooo>~o 0 1; K iLl . ' ' 0' , ., ""_ ,n -,. ., , ., , W 0 - "Oi", _..... c u., I) , " (0) " Q (1 <100mto 1 ) ; _..... I f, <ODd "roc.... , . . <>4 h oobavior_ 4; o n GU K E3-14 V ltDL o ..rnplioo <Jf. B;fWY M " I,; p",or ( Co.It;nL><d) T he regisler Iransfe ... direclly invol"ed in Ih~ multiplicalion a rt c(m,roIled by a c a <talcmenl dq)('nd~nl ul)On l he conlrol . tate. input G, and i nlernal <ignal. Q(O) and z , These transfers are outlined in Figure 8-7 and Table 8 ' , R ~pTesenla . ti on o f lhe a d dil;on in . Ia te MULO Tcqu ircs SOme d fort. n ",t o f a U, t o p<:rfor m addition OIl Sid_logic veetors. a u 'iateme ~ t a ppears j u.t before l ~ e e mi ly d eda Talion for the p ackage ; e. ... . s td.., l ogic_unsiglled , &ll. . In a ddition iO the 'Urn from the addition_we also need to i ran.fer the carT)' o ut. C _. f rom l he additi on imo C , To achieve this, we perform a j bil addi t; on with O's a ppe nd ed (0 l he left o f A and B and Ihe rt:$u lt assign! to a 5 bit variable CA. . The alternative would be t o wr it e C & A 0 $ t he transfer d estination. but lIS<" o f conca tenation & in d estina tions is not permitte<l in V HDL. Since CA. is a variable. its value is assigned immediately and is available for O$lSignmen1 (0 C and " a ftet the i f s latement. III State MOLl. Ihe shift is p erformed by using c oncatenation. 0 $ was done in the u amp!e in C haptet 5. f ' is decremenle<l by subtracting a 2-bit consta nt with value I . This description can b e simulated to validale il. c orrectness and synthesized t o a utomatically produce the logic if desired. 8 -6 H DL R EP RESE NTA.TIO N O F T H E B INA.RY M U LTlPLtR- VERILO G T he binary multiplier just studicd can b e r epresented d uring the design process as a behavioral Veri l"ll description . Such a deocription for a 4hit version o f Ihe multi plier a ppears in Figures 8 15 and 8 16. This Verilog r ode r eprescn" the block dia gram in Figure 8--6 and the ASM chart in Figure 81. The Veril"ll r ode is c ontained in a module b in''':YJrlultiplier_v. The deocriplion contains two assignment Slatemenls a nd t hree processes. The processes a re similar 10 those used for the seque nce r erosn i,er in C hap ter 4. 1 1,. primary difference is t hat the o u tput func l ion p roccu has bee n replaced by a process deocribing the d atap.'th regisler t r.ns fer. D u e t o I hi. change. the Veril"ll representalion c orresponds more clos.ely to the <k$c-ription in Table 8-1 and lhe ASM c hart in Figure 89 than t o 'h~ AS M c h.rt in Figure 81. A t tbe beginning o f lhe d escription . multiplier inputs and outp uts are " "fined. A p arameter decIMation defin es the Ihr~ stalt:$ a nd t heir b inary codes. Internal signals o f type register a re " "fined. A mong these a re the . . t . . t~ a nd n e"t_.t . . t~ for the contrOl. regislers I\.. B. P a nd Q . a nd Hip-Hop C. B ased o n clocking specifications. mosl o f these will become a Clual positive..,dge-triggered registers. T he notable e~cep t ion is n e >< t _ "t. . t e . AIS(>, i ntermediate signal Z o f type " ire is declared for coovenience. N ut, an assign men. is made wh ich fOTees z to b e I w henever P c onta in, vaJ ue O.ll1is O$lSignment uses the o peration O R (I l as a r~d"crion opemlor. R eduction is t he applic",ion of a n o perator to a wire Or regis t er that c ombine.lhe in dividual bits. In t his case. the applical ion of O R t o P causes all bits o f P t o be O Red together. Since the O R is p receded by a _. that overall operation performed i. a N OR. O lher <>pe r .lors may . Iso be applied as re<luction operators. The second aS$ignment statement assigns the OUlputs o f concatenate<! regiSlers A a nd Q 10 the mull iplier OUlput tillLT_ OUT. This is d one for c.-",vcniene<' to m ake t hat o utput a si ngle structure. The r emainder o f Ihe deocriplion ronsists o f th e t hru proce<SCS. T he flrst p roass deocribes the state register and includes a RESE"I' as well as the clocking. ' llI e second process dcocribes the n ut s ,.te function from Figure 8 -9. N ote that . ince clocking a nd RBSET a rc irn;luJed in Ihe sta te regiSler, t hey d o n ot a ppear here. In the event control statement. all signa ls that can affect the next sta te. G. Z. a nd . t. . t . . a re included. Otherwise. this process resemblt:$ that for the next >late process in the s equence recognizer. a J SS C HAPTER 8 I S EQUENC ING A NI) C OI'ITROL I I B i""IY I Iult1plier w ith n . 4 , V~ri1O\1 D eo.cription I I s.... P il/Ur. . 8 - 6 a nd B -7 f or b loc k d iagr"", a nd A 9t C hart _ . .1 .0 b inuyJOO,>ltipl1ecv ICLK, R ESIrr, G , L WlB, ! .(W)Q, K ILT_ IN, MIJl.T_(X11'); i nput CLK, JlE5E."I', G , L WlB, LCIo\DQ; i nput [ J , OJ K lLT_lN , Q \ltpue [ 7 , 0] K lLT3:<1I'; r -.g [ 1 ,01 ~ t.~., extJtaU, P ; r_ p ar. . . u r IDLE . 2 'bOO, r -.g [ ) . Ol A, B, Q : ~ _ 2 'bOl , K ILl _ 2 'blO, C; w h. Z; a uign Z ~ _ I P ; . . . 1 . ... I fJLT_CQI' _ ( A , O); _. . I I.tate r "'li n"r a lway (po U49_ CLK o r p<> .od~ RES!.T) i f IRESET _ _ \ ) . tate < _ l ot..E ; d o. " t a te < _ n e>ctJtaU; .~ I /"""t Otat . . f WlCtiOfl a l . .. " ( G o r Z o r n ate) -,. c u_ ( nat . ) I DLlI, i f IG _ _ l l -, ~tat~ < . K ILO ; _1 . . r >extJu u < _ I D LE; " ""t Jtat . . < _ MUL l ; K JLl : i f IZ_l) r >@XtJta t . < _ I DLE; _I . . . " ""t....taU < _ ~; . . nd<: . ... ~ I ldo. """"th f WlCtion . . l . .ay" ( _.od~ CLK) a n GUR[ S IS Veriloa Dc:><riplioo o f BInary Mulupll<' -" i t Il.Oo'.C8 11 B KJL1'_ rn, ~. i t IWADO " 11 Q < * I fJLTJN: c . . . ( natel IDLE: " -,..- " , , (G n .- 0, , .-2'bll, 4'bO OOO, O~ ~, " " " '"-" c.* i\._ ( QIO] < 0, -" K ILl: l 'bO, ( C. A {l,ll), 0 . * ( A[OJ. O {),IJ), P . _ P - 2'bO), O~ .1>4<: . ... OM ..-ul. a FI GU k E 8-16 VcriIotI o ...:n"""" o f 8 inuy Multlpher (Coolinued) T he final procc>s d . c,i\>e. t he d atnpath ru"clion. Sin"" the c ondition, for p erfonning an o peration aT<O d efined in lerm5 o f ' he Slates a nd inputS, ' his p ' OttSS a lso implicilly d efines l he c onlrol s ignal. given in Table 8-1. T he. . oon1.01 .ignalll d o nOI o p",," uplicitly. h o wever. S inu the d OI.palh runction I ta. " 'giSle", a . all . "';gnment d. ., inations. all tran .I.", "TC c ontrolled by e LK. Since contentS will b e loaded into t h= regislers l>efore Ihe multiply o peration is e vu performed. il is u nne$Sllry 10 p rovide a reSCI f or I hese rc gi~ l ers. T he first i f s .a tement o onlroh t he l oading o f l he m ultiplicand in10 regis,er B a nd t he s econd i f 5 tatement c ontrols Ih~ l oading o f t he m ultiplier i nto r egister Q . T he r egister transfers directly invol"cd in the muhipli<:~tion a re COnlrolled by a e a.a stat ement d cpendenl u pon t he c ontrol s tate, input G. a n d internal s ignal. Q I 0 ) a nd Z. T hese t ransfers a re OUllined in l ~gu re 8-7 a nd Ta hle 8-1. R epresenta . t ion o f t he addition in s tate HULO us<::sconcatenal;on o f c a nd 1\ t o o btain t he c arry OUl, C _, f or l oading i nlo C. V erilog d oes p ermit t he used o f 1\1..., 4-bit o perands with a ~bil r esult for Ih e addil i<:m. I n 51ale OWL1. lhe s hifl i . p erfonned by using c oncatenation as " '"' d one in t he e xamp le in C hapter 5 . P is d ecrement ed b y subtrocling a 2bit c on,t.nt with value [. l llO 0 CI-I"-P'ffiR 8 I S EQUENCING " -Nil C ONTROL This dCs.:riplion C~n be simulaled 10 validate il! 10 automalically produce t he log ic if desired 8- 7 COrT~ctne", and sy n thesiz~ d M IC R OPROGRAMMED C ONTROL A c onnol unit wi th its binary c omrol ,alues stored as ,,ords in memory is called a corum/. E",, ~ word in the wnITol memory contains a m iemi,, struction Ihat specifies o ne o r more microopo-rations for Ihe system. A sequence o f microinstruclions constitutes a microprogram. T he microprogram is usua ll y fi~ed a t Ihe system design lime and so is stored in R OM. Microprogramming involves p lac ing r epresentation, for c ombinations o f values o f control ,ariables in words o f R OM. T h"'" r epr"",nl ations a re acccss<:d via success,ve read operalions for use by the rest o f Ihe c omrol logic. T he c onlenls o f a word in R OM at a given address sp<:cify t he micrOOp<:rations 10 b e p erformed for both lit( d atapath a nd the c ontrol uni t. A microprogram can a lso be ' Iored in RAM. In I hi' c ase. il is lo aded al system st ar tup from SOme f onn of nonvOI.tile ,Iorage. s uch as a m asnctic d is k. Wit h either ROM o r R A M. the memory in t he c ontrol unil is ca ll ed ro,Hml m~mo,y. If RAM io used. Ihe memory is r eferred t o as "';I~b1. comrol memory. ~ lgure 8 -]7 shows Ihc general c onfiguralion o f a m icroprogrammed o ontrol. The c omrol memory is a ,"umed t o b e a ROM ,,ilhin which all c ontrol microprogram! a re p enna nenlly $Iored . T he w nlTal addrt!M "'Kisler ( CAR) specifies Ihe address o f the microinstrlloC lion. The w mml "~M ,~gisr'r ( CDR). which i . o ptional. may hold the microinSlruction <urrcnlly boeing . .e euled hy the d atapath a n d the w nllol unil. O ne fu nn ion o f Ihc con1rol word is 10 d eterm in e the a ddress o f t he ne xt microinslruction to b e e ,cculed. Th is m icroin,t r""lion may b e Ihc nexI o ne in " 'quence. o r it may be located 5OII1ewhere e lse in the w ntrol memory. Therefore. o ne Or more bitS that .pecify the m ethod for d elennining l he addre9$ o f the ne ~ t microinstruClion a re presenl in I he current m;croin . ..uction. T he nexl a ddress may a l", be a function o f s talus and eXlema' control inputs. When a micro;Mtruclioo is . .c euled. Ihe "~x' ad,lr,n K~"~ra/Qr p roduces the next a d dress Thi! a dd r..,; i . t ransferred t o Ihe C AR on Ihe nexl clock p ulse a nd is used 10 r ead the nexl microin struction to be c 'cculed from RO M Th Us. the microin!lTuctions c onta in h it s for aClivaling microoperalioM in the d atapath a nd b it' Ihal specify Ihe sequence o f microinSlrlloClion. executed. T he n extaddress g enerator. in c ombinati"" with Ihe CA R. is s omelimes called a microprogram s~q"'nct'T, , ince il d elennine! Ihe sequence o f i n.tructions r ead from c ontrol memory. T he a ddress o f Ihe next microinstruclion can b e specified in se,eral ,,ays. d epending o n tbe se<[uencer inputs. Typical funClio", o f. m;cropr(lgram s equcncer a r~ increment in g the C A R by , ,!Ie a nd loading the CA R. Possible s o urces for the load operation include an a dd re . . f rom control memory. a n e xter nally provided address, and an initial ~dd r ess 10 ! larl conlrol unit o per ation. The C DR h o lds the p r=nl m icroin'lruclion " hile I he nexl address is c omputed and Ihe next microinstruClion is read from memOl)'. The C DR b ruk. up tlte long c ombinational d da)' p ath' Ihrough Ihe control m emory followed by Ihe d al apath. lis presence allows the system t o usc a higher clock frcquency a nd p r ~ i nformation faster. The inclu<ion o f a C DR in a system. howe,er. romplicales Ihe mi"r(>p"'KTamm~d C"",ruI '"r' j O""_ ~< . . -odJ_ rol><'otor Seq""""" C ""'ruladO,,,. "'~"'<r . - C"",ruI od<Ir<S5 """= 0"" ,.. -~ ( 110M) ~ .. C -1..1.., , Coo,ruI d o . . " P' , , T----T----r --M ( opI"""l) , : C -" . .u .lol. ... a C """" Coolrul<i F1GURF.1I-11 Mi<ro,>rovammW C"",roI Unit Ch-gani. .,;"." sequ encing 01 microinstructions, particularly when decisions a re m ade based on Sla.us bil$. r'Or si mplj.ci.y in o ur brief d i<ru$$ ion. we omi, ' he CD R and t ake th e m icroinstruction. directly lrom the R OM ou tputs, The R OM o peral . .. a . a combinat;onal circui . wi lh th e address as Ihe in llut and tM: c orresponding microin5lruclion a$ Ih e o utput. T he contc ntS 01 Ih e specified word in ROM remain on lh e o u tput line. as long as the address va lu e is appl ied t o . he inputs, N o readlwrite s ignal is n ceded. as it is with RAM. e ach d oc k pu l ~ e~ccu l e. t he mic roopera'ion s specified by the microinSl ruc1 ion and a lSO Iransfers a new a ddress t o the C AR . In this , . se .l he C AR is Ihe only component in the c on.roltll8t receives clock pul.." a nd Slore5 s late inlonnation . T he n .,.t _ addr e$$ g eneralor arid the control memory a re c ombinational ci rcuits. Thus.. t he s tate o f the cODlro! u nit i . given by Ih e COnlenlS o f the CAN. Microprogrammed control has been a very popul ar alternative imple"", nl. _ tion technique for control u ni," for both p rogrammable a nd n ""programmable system s. H o,,c ver. as .y< lems ha,'e becom e more complex a nd " "rformant(: specificahons have increased Ih e n eed for c o""urrent parallel sequences o f acti,'itie .. the loc kstep n ature 0 1 microprogramming h .s becorne less a ttractive for r ont rol unit 3 92 0 C IIAPTf.R 8 I SEQUEN"CING AND C ONTROl imple mentation. Further. a large ROM o r RAM tends t o b e much slower than th e corresponding combinational logic. Finally. HDl.5 and synthesis tools facilitate the design o f a )mplex COI,trQI units without the necd fQr " I ""btep programmable design approach. Overall. micropmgrammed c omml f m the design o f c onnol un;ts. particularly direct d atapath C<)<\trol in CPUs. has d ed ined significantly. HQw<:~"r. a new flavor o f microprogrammed control h"" e merged. for implementing legacy corn p uter archite<:turcs. These arch ite<:t ur C$ h .,'e i nstruct;"" sets that d o not f<)llQw COOl temporary architecture p rinciple . . Ne,'enheless. such architectures m ust b e implcmcnlcd due t o m"ssive inv estment. in software that usc. them. Further. the conlemporary archite<:ture principles mDltlle u<l in the imptementa ti ons t o mect performance goal .. The control for these system, is hierarchical wi th microprogrammed oontrol selectively use-d at the top I nel for complex instruction implemen. tation and hardwired control at the I"",er level for implementing simple instructions a nd Step> uf complex instructions.1 a w ry r apid m te. Ihis fla~or o f microprogram_ ming is cmered for a Complex Instruction Set Computer ( e ISC) in O >apter 12. In formation on the more traditional na,or o f tnicroprogramm ed colllmt. derived from pa.1 edil ion. o f th is lext. is available in a s upplement. M icmprogrammed Control. o n the C ompanion Website for the t~xt. 8 -8 C HAPTER S U MMARY This chapter lias u amillcd t he interaction b etwcen d .t.paths a nd COIItrul uni ts and Ihe difference between programmed and nonprogrammC<l s~stems. 11 \. algorit h_ m;c >late machine (ASM) is a m ean, for r epresenting a n d specifying c ontrol funclions. A binary multiplier was used t o illuSlrate AS).! ch~f\ f onnulalion. Th'n implementation approaches t o ,quential circuit design. s equence ,egister plus d ecoder a nd One flipnop p er state. were p ru,ided. in addition 10 the basic design p rocedure in o >arter 4. VI IDL and Verilog alternatives for d e",ribing c ombin.tiollS o f d at.path a n d c ontrol were a lso iilu,lrated, Fin3l1y. m icroprogrammed r on trol was hri.fly di ",usscd. R EFEREN CES 1. M,,)<o. M. M. ComputeT E"gi""ri,,g: HaTd ..." " D aign: E nglewood a ilfs. NJ: ]>r.ntice 1 011. 19M. 1 2. M A!<O. M. M. Digi.,,1 Design. 3rd E d . Englewood Oiffs.. N J Prenlice Hall. '"" 3. I fiE I i S W",/ard \ I H D L f"''''WlIuge /l.efer~"<'< "'"""ul. ( A NSIIIEEE Std 10761993; revi,ion o f I E EE Std 1076-1987). New Y urk:The Inst;tule o f Electrical a nd EIe<:trQnics E ngi neers. 1994 -'. S'1IT1I. D . J. H DL Chip D aign. Madison.AI..: Doone Publications. 1996. S. I EEE S Ian,/",,/ D~.aiplion l A"g"age B aud o n Ih~ V uifog(TM) fI"Td""r. OacTip'io" fA"g""ge (I E EE Std 13064 1995). New York: T he Inslitute of Electrical and E lectron;cs Engineers. 1995, 6. J>AL.'<""'AR. S. V~rilQg H I )C A. G"id~ to /}igital Duign a nd Syntll~_'is. S unSoft P ress ( A Pr~ntia Halll1t1 c). ]996. 7. ' iHOMAS. D . E.. AND P. R. MOORII Y. Th~ V~rilog l Iardwarr Desoipli()f1 umguag~ 4th ~d. &>Slon, K ]uw ~r AC!ld~mic Publishers. 1998. h ~ P ROBLEMS T he p lu s (.+) i ndicales a marc: advanced problem a nd Ihc aSlerisk ( . ) i ndicates a SOIUl ion is aV8ilabl~ o n t h~ C ompanion Websit~ foo- ll>e l ext 3 - 1. ' A state d iagram o f a s equential circuil is given in Figure 8 -]8. Find Ihe c orre'ponding A SM chart. MinimlU Ihe c hart r omplexily by using b oth Ve<:tor a nd scalar d eci, ion boxe . . The i nput' 10 t he circuil a re X , a nd X ,. a nd Ihe OUlputs are Z I a nd Zz. 3 -:!. ' Find Ihe respon.., for Ihe ASM c hart in Figure 8-19 10 l he following scq~nce o f i llpuls (,"",ume Ih31 l he inilial Slale is S TI): , ,, A, 0 8, C 0 S tale: S TI 0 0 0 0 0 , 0 Z: 8--3. An A SM chart is given in Figur~ 8 19. Find Ihe 51ale table for Ihc oorresponding s equcmia l Circuit. lI-4. Find I he A SM c hart c orresponding 10 I "" following descriplion: Th~re arc: IwO ' Iate l. A a nd R. I f in Slate A and ;npul X is I . Ihen Ihe nexl s lale is A . I f in Slale A a nd inpul X is O. Ih~n Ihe n~x l . I.le is B. I f in O1ale B and i npul Y is O .lhen Ihe n ~ '1 Slale is H. I f in S la'e B a nd i nput Y is 1 .lhcn t he nexl Slale i .A. OUlPUI Z i . "'lUaIIO I while Ihe c i"",il is in Slale B. / '''''' ~I.IO I~.II 00 (--\:j'i':>---""",""'"'----.(~~ " "''' a n GURE lJ.1.8 S I.,e Oi q; ,am lor Problem 8-1 311 4 a C HA!"TE.R' I S EQUENCING A Nn C ONTROL m J- , , ./ m m " /' , , o n G UK IE , , J, 1-,' ASM Ouort for ProI>km 8-2 a nd P robl<m S.3 &-5. Find Ih e A SM for I circuit t h.I d e lects a diffe rcntt in val"", in . n ;Opill signa' X al I. ..., successi,c po5Ili,c clock edge.. I f X hili different valuQI at ,....., .lJCCeSSive POSH;"\! dock e dge.. Iheo OUlpul Z is c qu" ll " I for the next clock cycle. Othcrv.;sc. o utpu t Z is o. 8 -6. +The ASM c hart for a sync hr ono u ~ ci:uil wi,h clock C K for a washing machine i s,o b e d c~eIOped. Th e circuit has th ree external inpUIs, START, F ULL. a nd E MPT Y (w hich are I for al mosl a single clock c yde and a re mutuaJly exclusive). and e xt ernal oU lput<. HOT. C O LD. DRAIN. and T URN. The d atapath for Ihe c ontrol consists o f. down-ooul\tcr. ,,'hleh h al t hree inptl~ R ESET. DEC, and LOAD. ThIS c ounter synchron ou<l y decrcmcnl.! once each m,nute for D EC = l . b ut c an be l oaded or .ynchronously rcsct { )II any cycle o f clock CK. I t has a single o utput , Z ERO. w hkh is t w hene'"r tile c ounter c ontains , .Iue z ero a nd is OOl/>e".,se. i 'robItm, 0 3 95 I n ils o peralio n. Ihe eircuil g ""s I hrough four diSlincl cydes. WAS H. SPIN. RI NSE. a nd S P I N. which a re d elailed as [o li o"'. .: WASH: Assume that t "" circuit is in ils power-up stale I D LE. I f ST ART is I for- a d ock cy.::le, H OT beoomes I a nd remaillS I until F ULL ~ 1. filling l he w asher ",;Ih hOI waler. Nex!. using LOAD, Ille down..;:ounler is l oaded w;lh a val . .. from a panel dial which i ndicales how m any minUles the wash cycle is 1 0 lasl. D EC and T URN t hen b ecome I aad Ihe washer " ""'hes illl contcnill. W hen Z ERO b ecomes I . Ihe wash is c omplCIe,andTURN a nd D EC b ecome O. S PIN : N e.l. D RA IN becomes I . d raining Ihe wash waler. W hen E MPTY b ecomes I . t he d ow ll-counlcr i . l oaded with 7. D EC a nd T U RN Ihen become I a nd t he r emaining w ",h ""aler is w rung h om t he contents. When Z ERO b ecomes I. D RAIN. D EC. a nd T URN r elum t o O. R INSE: Nexi. C OLD bccQmes I a nd r emains I Iml;1 F U LL ~ I . fil ling l he w .sher wilh cold rinse waler. Next. using L OAD. the down-coun1er is l oaded wilh value 10. D EC a nd T URN l hen I",come I a nd the washer rinses i1 s c on _ 1.nlll. When Z ERO l>cromes I . Ihe rinse is c omplele, and T U RN a nd D EC b ecomeO. SPIN: Next, D RA IN beCOl'rlCS L d raining t he rinse waler. W hen E MPTY b ecomes I . t he d own-counler is l oaded with 8. D EC a nd T URN t hen beC()ll,e I a nd Ihe r emaining r in", w ater is w rung from the r onlenl$. W hen Z ERO b ecome. l . D RA I N. D EC. a nd T URN return 10 0 a nd t he c ireui1 returns to s tate I DLE. ( a) Find t he ASM c hari for Ihe washer circuil. ( b l M<.>dify YOlur design in p a r! ( .) a numi ng Ihat Ihere a re 1 "'0 mOre inpulS, PAUSE a nd STOP P AUSE c au"," t he cireuil. i ncluding the counter, 10 h ah and all OlUIPUIll IOl g o 10 O. W hen ST ART is p ushed. the w .sher rCSumCS o pe ra lion "1 l he p oint it p aused. W hen ST OP i-s p ushed. all o utput, a re resct tOl 0 u eepl fOlr D RAIN which is s ci tOl l . Wh~n E MVrY I:>ccomes 1. t he 5tate returll$ 10 I DLE. S--7 . Fi nd a n A SM c hart f or" traffic ligbl controller thaI wor ks as follOlws: A liming signal T is l he i nput 10 l he c onlroller. T defines Ihe yellow light i nlernta. , ,'ell as t he changes o f Ihe red and green lighls. T he o ul p ulol0 l he signals a re d efined b y Ihe foliOlwing table: GN YN RN GE YE RE Gree ... Lig l". Nortll/Soulh SigJ1.1 Yellow Ug/ll. North/Solllh Sig".l R<.I Ugh! . NorllllSouth S ;",. I G ,.en U iI'l, EasllWe Ol Signal Yellow Ug/lt, El5IIWesl Sign.l Red U ghl. E. S1 IWesl Sign al 3 96 0 C HAPTER 8 I S EQUENCING A N ]) C ONTROL Wh ile T - O. the green light is o n for o ne s ignal and the red light for the other. With T = I . the yellow light is o n for the signal that was previously green. a nd the signal that was pre"iously red remain! red. When T becomes O. the . ignal that was previously ~'e ll ow becomes red. a nd t he signa l t hat was previously red becomes green . This p allem o f a llemating change, in c olor continu e"- Assume that the c ontroller is synchronous with a d ock that changes much m ore freq ucnlly than inpul T. 8---3. " Imp lement the ASM chart in Figure 8 19 by u si ng o ne fl ip-flop p er state. 8---9. " Implement the ASM c han in Figure 8 19 by u sing a sequence register a nd d ecode r. 8-10. +Implement t he ASM ch an derived in Problem 8---6(a) by using one flip. Hop p er state. 8 - 1.1. "Multiply the two unsigned binary numbers 100110 (mu lt iplicand) . nd 110101 (multiplier) b y u sing bolh the hand m ethod a nd the hardware method. 8 - 12. Manually simulate the proc<:" o f mulliplying the two unsigned bi nary n umbers 1010 (m ult ip Hc and) a nd 1011 ( multiplier). List the contents of registers A . Q. P. and C and the c ontrol state. using the system in Fig ure 8-6 with n e qual to 4 and with the h ardwired c ontrol in Figure &-12. 8 -13. D etennine the ti me it t akes t o proceso the mU ll iplication o peration in the dig it al sy1;lcm described in Figure 8-6 a nd Figure 8 -9, Asoume t hat the Q register has n bit< a nd the interval for a clock cycle is f nanosecond"8-14. Prove that the multiplication o f two ,.bit numbers gives a producl o f n o m ore than 2n bits. Show t h.t I hi. condition implie. that n o overHow can occur in the final resu lt in the multiplier circuit defined in Fig ure 8 6, 8 - 15. Consider t he block diagram o f the m ultiplier , how n in Figure 8-6. Asoume that the multiplier and m u ltiplicand consist of 16 bi ts each . (a ) How many bits can be expected in the product. and where i. it available? (b) How many bits arc in t he P counter. and what is the binary num ber that must be loaded into it initia ll y? (e) Design the combination .1 circuit t hat ch""ks for zero in t he P coun te r. 8 - 16. ' Design a digital sy1;tem with three 16-bit registers A R. BR. and C R and 16-bit data input IN to perform the following operation. . OISSUming a t wo', complement representation and ignoring O\'erfiow: l a ) n a nsfer two 16-bit signed numbers t oAR and B R on successive d oc k cycl es a fter a go signa l G becomes L (b) I f the n umber i nAR is positive but nonzero. multiply the c ontents of BR by two a nd transfer the result t o register CR. (c) 11 t he number in A R is n egative. multiply the com enls o f A R by Iwo . nd transfer the resull t o register CR. (d) l ithe n umber in A ll is u ro, reset register CR 10 0 , _ m, 0 3 97 8 -17. +Modify I he multiplier design in Figure R-6 a nd Ihe A SM c hari in !'igure 8-7 1 0 p erfonn 2", complement signed n umber m ultiplicalion using B oolh', algorithm. which emplo)'& an a d d er-subtracto r. The decision 1 0 a dd, 1 0 ,ublrOCI. o r 10 d o n othing is m ade On Ihe b a si, o f t he c urrent least significant bil (LSB) in Ihe Q regisler a nd on Ihe previoU$ LSB bit from I "" Q regiSler befon: Q was s hifted right. ThUs. a Hip-Hop m u.t b e pr01lide<l t o s lore the p revious LSB from Ihe Q regiSle,- The initiat " atue o f t he previoU$ l easl .ignifica nt bit is 10 be O. T h e following lable defines thc decisions: LSD o f o o a P f lOY iou . L SD o f , " o a Actlo>n Le . ." p a",.t prodl>C\ unchanged Add mu lliplicand 10 partiat prodl>C\ Subtract muttiphcal><l h om panial prodUCI U a,'. partial prod"", unchanged 8 -18. +Design a digilal syslem Ihat multiplies Iwo unsigned binary n umbers b ylhc r epeated a ddition met hod. f ur example. t o m ultiply 5 by 4, Ihe digilal syslem a dds the multiplicand fOt.Lr timt<: 5 + 5 + 5 + S 20 . i..tl the multiplicand be in register BR. Ihe multiplier in regisler A R. a nd Ihe p roduct in regisler PR. A n a dder circuil a dds I he conlenlS o f DR 1 0 PH. a nd A R is a d owncounte,A l e ro-<le l e<:tion circuit Z e he<: ks when A R b ecomes z ero a ftcr each lime Ihal il is de<:rcmenled. O "" ign I he c onlrol by t he Hip-Hop pcr s tale method. K S-19. Wri le. compile, a nd s imulale a V H OL d escription for t he A SM shown in Figure 8-19. U5(: a s imulalion inpul t hat passes Ihrough all p alhs in Ihe ASM c hart. and include b olh tile otale a nd OUlp ut Z as s imulation o utputs. COITect a nd r esimulale your design if necessary. S-:W. Wrile. c ompile. and simulate a Verilog description for the A SM in Figure 81 9. Use c ode 00 for <tatc S T 1. 01 for s tale S TI. an d 10 f or s late ST3. U se a , im ul at io n input Ihat pas. .. t hrough all p aths in t he AS M chart. and include b olh Ihe s lale a nd Z a s s imulalion o utput . . C orrect a nd , es imulate your desig:o if nc~ry. 8 -2 1. P erform t he d e . ign in P roblem 8 -S using Verilog i nslead o f an A SM c hart . Use Slate n ames SO. S I. S2. -" . . a nd code< t haI a re the hinary c qui . . l ent o f Ihe i nteger in t he . tate name. C ompile a nd s imulale your de.ig:o using a <im ulalion i npu l Ihal I horoughly v alidales the design a nd Ihat provide< bot h s tate a nd Z a s ,im1llation out pUIS. C orrect a nd fes imulate yo ur desig:o if necessa ry, S-22. +Per fonn Ihe de.ig:o in Problem 8-7 using VH DL i nstead o f an ASM chart. Compile a nd s imulale y our desig:o by r unning Ihe traffic light through Iwo full c ydes. Use realistic i nler...a l. for T and a slow d oc k. Adjust the d oc k in teTVal. i f necessary 10 avoid long sim ulation Ii . ..... 3 98 0 C HAPTER 8 I S EQUENCING A N]) C ONTJt.OL C ompile a nd s imulale y our design by running the traffic light t hrough t wo full cycles. U se t he s tate assignment m elhod in P roblem 8-21. Use realistic intcn'als for T a nd" . Iow clock. Adju>! the d ock i ntervals if ncccSS,ITY t o a>'oid long simulation times. M EMORY B ASICS i ll m ajof component o Ia cligllal COfl'l\l'J I. . , ~r<i is present I n. ~rQ& p oopoolioo,OI'" d iyilallysternl . Ra~ " *'>O<Y (RAM) Il10<. . d ata temporarty, alld r ead-only ........:.ry (ROM) s tor.... d ale p ermaoenlly ~ Io\JIC d IM::eII ROM . ..... 101m o Ia . .. rIet)I 010.>0 . .......... _ (PLDo.) tM1 . . . _ i nIonnation 10 define lOgIc dlt:uUII. M etI'IOfy o ..lIIUdy 01 RAM tMogIns t Jylooking 3. ~ in ~r"" 01 a IIICIdIII WIth onputa. OUIpuIS. a nd signllllimOriog . We , ...,. u se equiVBlonl k>gk;aI m odM 10 unde<sIand 'hoI inIor . ... ......n<ingo 01 R AM ~ _ static RAM and <Jynamic R AM 8 '" " ",,_...s, " """,8 l Y1'" 01 (tynamlc RAM used l ot ~n1 01 dllla a 1 h9I1 SI>\HIdf ! >II1_ 11>8 C PU and m omory ~'" s u rveyed. F inally,.,.;o poJ t R AM c hips togelhet 10 b uild s ""pltl RAM sy6!o ms In mat1y o Ilhe previous c hapteu. the ~ presenli1d were bf(>8d , pena~ to mud1 o Ilhe generic ~ a t ! he b eginning 01 ChapI9< , . In 1 M ct\IIJIIet. for ! he l im - . we can b it fI'IOftI pnocise a nd p oinIlO epecffic . . - oIlMr\'IOI'Y e nd <'9Ia1ed ..... ' . ....... 011. wit!> . ... p roOIUOr. ... ir1Iemal c ache is Iargety very I asl R AM. CPU, . ... e xtemaI _ illIrgIIIIy l iS! RAM. T he R AM s ubsystem, ~ i ll - r ......... II type 01 ~. I n . . 110 _ . _ I n:! ~ " *"'l<y 10< SIOfing inIorrnation I IbouIIhe s cr-. on'IIIQO Il'lIIIe vicIeo ~. RAM ~rs in dis!< c ache in l he <hie o ont.-, I<> & peed \.If) c bk IICOI!IOI&. Asi<Iu f fom!he I'IoghIy 0&f'I1taI role 01 the R AM l uboyslem in sl<>ring d ata . "" p rograms, w e fOnd m emory in v arklus n.. 8egoo'."U o.n.m .... Iorms 9 _1 appl~ in most oubsyslems o ilhe g.tne<1c c omputer_ M EMORY D EFINITIONS I n digilal 'l"I~ m s. m~mory is a collection o f 01:11$ c apable o f OIOOIIj b inary ' nformalion. In a ddItion 10 l hex lis. _ mory c ont ams (i<'CIronic c irruiu ( If 8t orin. a nd retrie~in g t he intOl'mal;on. A. indicated In t he d i""",""", 0 ( the genc:ric c omputer. memory . . use d ill many dIffereD! par. . o f. ,nodcfn compute . p.ovidinl temporary o 3 99 4 00 0 CHAPTER 9 f MEA-lORY ElAS1CS o r p ermanenl s lorage for subslanlial amou ntS o f binary information. In o rder fo r this informalion t o be processed, il is sent f rom the m emory to processing hardware consisling of regisler.; and c ombinational logic. The processed in format io n is l hen returned to the same or 10 a d ifferent memory. lnpul and o utput devices also interaC1 with memory. Information from an input device is placed in memory s o l hat it can be used in processing. O utput info rm ation from prt>Ce>sing is placed in memory. and from there it is sen! to a n o utput device, Two types o f m emories a re u sed in v arious p .rt. o f a c omp ut er: random aecess m .mary ( RA M) and read-only memory ( ROM). R AM a ccepts ne,,' information for s torage t o b e a vailable later for usc. T he p roce. . o f s toring new information in m emory i, r eferred t o as a m emor y " "ite o)X',ation . The process of transferring t he s tored information oUl o f m emory i. r eferred t o as a mem ory read o peration . R AM c a n perform b ot h t he wr ik and t ht r ead operations, wh ereas R OM as inTroduced in C hapter 3, p er forms o nly read operation,,RAM sizes may r a nge from hundreds t o b illions of b iu. 9 -2 R ANDOM-AcCESS M EMORY Memo!}' i, a colleC1 ion o f bi nary storage cells togelher wilh associated cirouits n eeded to transfer information into and o ul o f t he cell"- Memory cells can be a cce,sed t o t ransfer informalion to o r from a ny desired location, wit h the a~ss t aking Ihe sa me tim e regardless of l he local ion , hence. lhe name r andom -lleuss memory, In CO nlraSl, ser,"1 m emo'}', such as is exhibited by a magnetic disk o r t ape onil. l ake, d ifferem lenglh, o f ti me to access information, depending o n wh~re l he de' ir ed location is relative t o t he current ph~ical Jl'O' ition o f the d i. k o r tape. Binary information i , stored in m emory in g roups o f bil"- each g roup of which is called a word. A word is a n entily o f bits l ha t moves in a nd o ut o f memory as a u nit- a group o f I ', and O's t hat r epresents a number. an in struc_ tion , o n e o r m ore a lphanumeric c huacters, o r o ther binary-<:oded informalion. A group of eight bits is c a ll ed a b yte, Mosl c o mput er memories use words Ihat a r e multiple, o f eight b it . in lengt h. ThUs, a 16-bit word c o m ains t wo bytes, a nd a 32 -bit word is made u p of four byt~<- The c apacity o f a memOTy unit is us ually sta ted as the tOla l num ber o f b yte. l hat it can store. Communication o c tween a m emory a nd ilS e nvironment is a chie"ed Ihrougb data input a nd OUlput lines, addre", seleclion lines, a nd c omro lli nes thai specify the direction o f transfer o f information. A b loc. di~gram of a memory i . shown in Fi gure 9-1. The n da ta i nput li ne, provide l he information t o b e s tored in memory, and th e" d ata o ut_ put li nes s upply the informa ti on coming o ut o f memory. The k a ddre", lines specify t he particular word chosen a mo ng the m any available, The two control i npun specify l he d irenion of t raosfer desired: the Write iuput causes bin ary d ata t o be t ransferred into memory, a nd the R ead i nput c au se. binary d ala to be transferred out of memory, The memory unit is spec ifi ed by the number of words it c ontain' a nd the number of bit' in each word . The address line. select o ne p articular word. Each word in memory is assigned an identification n umber ca ll ed an addr<!Ss. A ddre,,,,,, n da . . ;nP"1 h ".. [ ] f lG U R E 9-1 Block Diagram o f M.mor~ Tange from 0 t o 2" - I, wheTe k is the number o f addTess lines. l ne selection o f a specific word inside memory is d one by applying the k-b;t binary a ddress t o the a ddress lines. A d ecoder ac.:epl5 tbis ooddress and o pen. the p all. . need<.>d to select t h. word specified. C ompmer m emory varies greatly in Sile. I t is customary t o TdeT to the numbeT o f words ( or b)"tl:1) in memory with oDe o f Ihe lelle~ K ( t ilo), M ( mega), o r G (giga). K i . e qual t o 2 10, M is e qual t o 2 "', a nd G is e qual to 2 "'. lnus.64K _ 2'". 2M _ 2 ",8nd 4G _ 2J1. C onsider. for e xample, a m emory with a c apacity of 1 K words o f 16 b i" e ach . Since I K - 1024 - 2'". a nd 16 bits constitute two bytes. we can say t hat the memory can accommodate 2048. Or 2 K. bytes. FIgure 9 2 show> t he possible COntents of the first three and the last t hree " ,ords o f this size o f memory. Each word contains 16 bil$ that can be d ivided into two bytes. 'Ine words aTe Tecognized by their decimal a ddresse, from 0 t o 1023. A n e q uivalent b inary a dd ress consisls 01 10 bits. T he /irst address is ,pe<:ilied using ten 0'<. a nd the last address i . , pecified with ten I ' . . Thi. is because ] 023 in binary is e qual t o 1111111111. A word in m emory is selecte<l by its binary address.. W hen a word is r ead o r w ritten. the memory o perates on all 1 6 b its as a single unit. \lUlOOOl.W 0 0 C0Dnl1O 2 tOl 10101 OtOlI 100 1010101l '0001(0) OCW l lOIOlOOO110 1111111101 1111111110 I llll] l tll )021 ' 022 1023 10011101000'(10) OCW"OIOOOlllIO 1 101]tl000lO0Ioo [ ] f lG U RE9- 2 ContenlSof a 1024 X 16 Memory 402 0 C HAPTER ~ I MEI>\OR Y IIA5JCS The i II: X 1/; m~1nOI'Y of the Agure has 10 bil$ in t he addreM and 16 bits in e.-ell "'....d .l( iDSlead."'e ha~e I 641< x 1 0memory. it is ~ 10 " ,dude 16 bits in t he addre<&, a nd each . .-oro wi ll consist o f t o bi lS.1be n umber o f a ddress bits needed in m emory i. d ependenl o n t he 10111 n umber o f words lhat can b e stored lhe re a nd i . independ~n l o f I he n umber o f bils in ~ac h wo rd. T he nu mber o f b ill I n the addr~ for a word is d etermined frolll the rcialiomhip 2 ' " " III . w here I n is I he I<JI"I num ber o f ",'Ords a nd k is the min imum number o f a ddress bit:! ""tisfying the reiR ti ons hip. Write and Read Operations 'The l wo . ",., .... liol1$ Ih~\ a random-attC'f6 m~mory c an pe rform a rt " Tile and , ead. A ~ is a t ran,fer o f a ropy o f a Slored w ord \JUI 01 memory. A W ri te ';&'1"1 s p:ciIie5the Imn!S.,...,n o pention,:and a R ead signal ~ the lransfer-out operation_ On ~pl;", ooe o Ithc$e c onlrol signal>, l he i mernal cin:uits inside memory p r....i de t he desired func\ion. T he s te.,..that m ull b e laken f or. wrile a re a s follov."$: w n'/t: i . a lransfu i mo memory 0 1. n ew word to be S lorN. A A pply ! he b inary a dd re5ll o f t he <ksired , m.d 1 0 t he a ddress h ntS. l , A ppl y the dala b its lhal m ust b e s lored in memory 1 0 I he <Jail , npullines. 3, A ctivate the W rite inpul. I, T he m emory u nit will th en I ~ k e t he bil~ f rom the d al. i nput lines a nd Store them in t h. word s pecified b)' th e "ddf<'si lin es. T he step' that must b e l aken for a re ad a re a s follows: 1. A pply the b inary a d dress o f Ihe d e,ired w ord 10 t he add1"('5' lines. A ctiva le t he Read i npul. l, The m emory w illlh en lake t he bits frQm . h e w ord l hal has been ..,I.,,,.ed by lhe addr~ a nd apply th~m 10 I he d a l. OUlput t inn. ~ c onl enls o f t he selected w ord a rc n ot c hanged by rud i", t Mm . Memory is made u p o f R AM ,nte&nlted c iralits ( chi.,..). plus BddOllona l lo&ic d rcui . .. R AM chips usually provide I he two r ontrol ,npu lS for l he relOd a nd ""rile .",.,ralions in a " ""e...hat differe nt eonfigllralion frQm t ha i JUS! d c$ct,bed. Ill$\ead o f having " 'para le R ead a nd Wrice in pu ts 10 r onlToillle '''"0 . ",.,nllion s. m os. i nle' t rnted circuil1 p rovide a t l eu C hip Seleci thaI . .,Ieci.!he c hip 1 0 b e read ( rom or wriu~n 10 a nd. Rc~dlWrile thaI d eterm ,nes lhe p articul.r o penl ti oo . l'lIe m emo ry operations that , esult from thQlO c on.rol inpuLS are , hown in Tahle 9- '. T he O Iip Selecl is u ..,d 10 e nable t he p arlicular R AM c hi p Or chips r onlain' in g the w ord to b e ac<:em:<J. Wh en C h ip Select is inaclive. ' h e m emory c hip o r chips a rc n ol selected. Bnd no o pe ra lion i . p erformed. When Chip Se lecl i$ ICl i> 'e. Ihe R ead / Write inp u. d etermine' t he o peration to b e p erformed. While C h ip Setect acceMe!l chips. a signal ii also provided Ihat accesses the entire m emo ry. We will call lhis $ignaltlle Memory E na bLe. T imi ng W aveforms T he o pe ration o f t he m emory u nit is c onlrollcd by an eXlerlUlI d e,'ice, l uc h as C PU T he C PU i . 5 )nd!ronilMi by its own clock pulses. T he m emory, howe>~r. o T A8LE,.1 Con trul1np~ 1S t o. M. .. ory Oaip C h ~_ " " , , None Write to . . lected " ur<! Reod from ..,Ie,,,ed ,,-ord does not employ t he C PU clock. Inslead. ils r ead "nd wrile operaliOlls arc lime<! by cbange< in val ue. o n t he CQn trol inputs. T he a c(dS rim~ o f. memory read oper ation i, Ihe m uimum time from Ibe app lic ation o f Ibe add,e . . t o the appearance o f tbe data a t I he D ala OUlpUt. Simil.rly. tbe .... ,il~ c ydt rim~ is tbe m uimum t ime from the application o f t he a ddre . . t o the completion of all internal memory o per a lion, required 10 , lore a word. Memory writes may be pe.fonne<l o ne a fler t he o lh er a t the intervals of the C)"Cle lime. The C PU must [,<o'ide the memory control signals in , uch a way as t o synchroni ze its OW" internal d ocked o perat;ons with the r ud a nd write o perat ions of memory_ Tbis m ean, that Ihe acceos time and the wrile cycle l ime o f t he m emory must be related within the C PU 10 a p eriod equal 10 a fixed n umber o f CPU d oc k pulse periods. Assume. a . an c um pie. t hat a CPU o perates wi th a clock frequency of SO MHz. giving a period o f 20 ns ( I " s 10- 9 oj for o ne clock pulse. Sup pos.e now that the CPU c ommun icates with a memory with a n ao:eos time of 6~ ns a nd a write cycle time o f 75 ns. T he n umber of clock p ul ses r equired for a memory r equest is Ihe integ. . value greate, than o r e qual t o the targe r of Ihe ao:eOS lime a nd t he " ',ite cycle t ime. divide<! by the clock peri od . Since tbe p eriod of the C PU clock is 20 n. . and the larger o f the access time and w ,ite cycle time is 75 " .. it will b e neC<$S8ry 10 devote at leasl four clock pulses t o each "",mOly request. T he m emory cycle timing shown in R gure 9 ) is for a CPU with a SO MH~ d oc k a nd memo!), with a 7Sns write C)'cte time and a 6S.ns ac<:ess time. T he wrile cycle in p an <aJ sho"", four pulses T l. T2. T3. a nd T4 w ith. cycle of 20 Ill, For a w ,ite o pe"'t;on. the CPU must provide I be address and input d ata t o I he memory. The addrcos is apptied. a nd Memo!), Enable is set 10 tbe high level a t t he posil ive e dge o f Ihe T I pulse. T he d ala. nuded s omewh.t l ater in Ihe write C)"Cle. is applied a t the positive edge o f The IWO lines Ihat cross each o ther in t he a ddress and data w aveform. d esignate a poosible cbange in value o f the mu~lines. T he shaded area, r epresent unspecified values. A change of the R ead/Write si gn al t o o t o designate the wrile opcraliCKt is also a t the positive e dge of 'no To avoid destroying d ata in o ther " ",mOly words. it i, ; mponant tbat th is c hange occur afler t he signats o n the a ddress lines ha"e beoome fi:<ed at the desired val ues. O ,he,wise. o ne o r m ore o ther words mighl be n' '''''''ntari ly addressed and accidentally wrilten o ver with d iffe ren t data_ T he R ead /Wrile signal must stay at 0 long enough a fler apptication of I he address and Memory E nable to allow the write opera ti on 10 complete. Rna ll ~addreos a nd d ala signals musl remain stable for a . horl lillle a fter tbe R ea d/Write gO<:$ to I. again to a "oid destroying data in o ther memory n_ 4 04 0 C HAI'TEIt. 9 I MEMO It. Y DAS I CS _ l I I .. _ n \ X .- (oJ Wm . ,a. _ lII . . _ n ~w':':"=J~_ ,i,. , .~ ~" W l p.. 1 ___ _________ ' 0' .( b) o x 00,. , x _ \ == ~ " ,'id X ::::n 1 ....,.,.. I 'I (;UKF; J -.) M e..-,. C yck 11m,n, WI>"e fonm word .. A t the C()mp letjon o f , he fourth d ""k pulse, the me mory wri, e opcralion has ended with 5 ns to spare. ~ n d the CPU c .n apply the addre . . and co mr ol $ig' nal, for a nother memory requesl wilh ,he next 71 pulse, The read cycle sho wn in f igure 9.3(b) has an address for Ihe memory thRI is provided by tl\(> C pu. The CPU a p pli es the addtes&. sets lh e Memory Enn bl e to I. and seto Re ad/Wr;te to 1 1(> d e, i",ale. read openl1ion, a ll at the positive edge o f 71. Th e memory p l,.., es the data o f , he " 'ord sele.: ,ed b y l he address o nto , he dal8 OUlput lines wil h in 6.'l ' " from lbe lime lhal lbe add . .... is app~ cd al>ll t be memory e nable;s activated. l ltcn. lbe CPU transfers the da,a imo one of its in ternal r eps. ten d uring the posi""" t r.lt!i tion o f the nexl n pulse. " 'hich can al"" change l be a dd . .... a nd c on,rob for tbe rout memOl)' Tf!quest. ~_J I S MM I .,"g"'"" C ;onll<. 0 4 05 Properties o f Memory Integraled circuil RAM may b e e ither slatic O J dynamic. Slaric R AM ( SRAM) coo .i.ts o f internal latches that Ilore the binary inform3lion. The stored i nfonn.lion remains valid as long as p o wer is applied 10 Ihe RAM. DJ,,~mic RAM ( DRA M) siores the bi nary information in the form of electric charges o n capacilors. The capacit"'"' are accessed inside the chip by n-channel M OS transistors. The slored c harge On the capacitors tends 10 dischar~ ,,-it h time, and Ihe capa.cilOrs mLlSI be periodically recharged by r~fff.hjng t he D R AM. T his;" d one by cyding Ihrough the ",ords e,..,ry lew miUiseCOllds.. r eading a oo re"'TIling them 10 reslore the decaying c hrge. D R AM offers reduced po",er eonsun,pt;';'n a nd larger storage ~apa.city ill a sillgle memory chip. but S RAM is easier t o use and h as s horler read and write c yck... Also. n o refresh i . r equired for S RAM. Memory units t hat lose s tored informal;';'n when po,,'cr is t urned off arc said 10 be " olalik I ntegraled circuit RAM . . both SIa l ic a nd dynamic. are o f this Cate gory. since the binary cells need eXle,nal p owe, t o maintain the Slored informalion. In e ontrasl. a non,o/a.i/e . mmory. s ueh.s m agnelic disk. relains its s l"rcd informa _ lion a fter the removal o f p o",.r. T hi. is because Ihe d ala s tored on magnelic components is represenled by Ihe dir""li'm " f magnelization. whi~h is r elained aftcr po""er is turned o ft A no lher oonvolalile m emory;" ROM. discu ...... in Section 3-9. 9 -3 S RAM I NTEGRATD C IRCUITS As indicated e a rlier. memory ronsisl$ o f RAM ch ips p lu. a dditional logic_We ",ill r onsider Ih e internal structure o f Ihe R AM chip first. Then we will Sludy combinations of RAM chips a nd addil;';'nal logic used 10 r on.truct memory. The internal s tructure of a R AM c hip of m ....o rds wilh n bits p er word coru;isl' o f an array 0 1 mn binary SIQ"'8e cells and associaled cirruitry_The cirruily is m ade up o f decoders 10 select Ihe ""01"d t o be r ead o r ",TIllen. read circuits. "'Tile eircuil . . and OUlPUI logic. Tlte R AM c rll is Ihe basic hinary storage ce ll used in Ihe R AM chip. which is Iypically d esigned"" an d eetron ic circuit r alher Ihan a logic circuit. NC,'Crlhcl.,... il is possible and r on"enient 10 model the RAM chip using a logic model. A Sialic RAM chip s erveS"" Ihe basis f"r o ur discussi"r'- We firsl p =nl R AM cell logic f or ' Ioring a single bil " nd Ihen use the cell in a hierarchy 10 describe Ihe RAM chip. Figure 9--4 shows Ihe logic model o f Ihe R AM cell. T he storage p an o f Ihe cell i . m odeled by an SR latch. T he i npul. 1<> Ihe M ch a re " nabled h)' a Select signal. For SeI""l equal to O. the stored r onlenl i . held. For Selecl e qual to I . Ihc s tored c onlcnl is delermined hy Ihe values o n J j a nd I i . '1Ie o utputs from Ihe lalch a re g aled by Select 10 produce cell OUlputs C a nd C. For Selecl equ~ 10 O. both C and C are O. a n d fOT $elect equal 10 L eis the Slored value and C is its romplement. T " o blain simplified static RAM d iagrams.. .... e i nlerconnect 8 set o f R AM cells and read and wrile cireu i" 10 form a R AM b i lice Ihat conlains all o f Ihe eir cuitry associated wilh a single bil posilion o f a sel o f R AM ,,"Ofds.. T he logic diagram for a RAM bil sl ie e is soo",'n in Figure 9 -5(a). The porlion o f I he model r epre"D1ing each RAM cell i . highlighted in b lue. The l oading o f a cell latch i . 4 06 0 O M P'TER 9 I M EMOli. Y lI ,o\$ICS , , Q , Q o t 'I GU KE9-4 SloliG RAM Ce ll now oonlfo lled by a Wo rd s"lect in pul. I f Ihis is O.then b oth S and R I fC O,and Ihe celllMch OOfIlenu remai n unchanged. I f Ih e WOTd s,,1ect input is I . t hen Ihe val .... t o be loaded i nto Ibc latch is controlled by 1 "0 signals B and B f rom t he Wrile " I..ogic.. In o rder for e ither o f the.., signals t o b e 1 and potentially chance ' he Stored val ..... ReadlW rite muM b e 0 a nd 0 '1 Select mU51. be 1 .1Mn t he D ala In value and il$oomplem.en l are app~ed to B a nd 8 . respectively. 10..,1 o r re&C:I t he latch in t he RAM cell .., lected. I f D at3 In is I lbe 100ch il; ..,110 1, and if Dala In is 0 II><: latch i . resel to O. oompleting the ,..rile o pe ralion. O n ly o nc ,..ord is wr itten a l" t ime. That i<. only onc Word s " lecl line is I . and all o ther Word s.,lect lines arc O. Th us. only o ne RAM cell a ttached 10 B and B is w rinen.l1tc Word Seleci also controls the reading of the R AM ce ll s, using shared Read logic. If Word s"lect is O. t hen lhe lIored value in the S R I itch i . prevented by the A NI) p t" from reaching the pair o f O R g ales in the Read Loaic. But if Word Select i$ I , l be s tored val .... passes thrOtlzh 10 t he O R g ates a nd is c aptured in tl><: Read L.o&ic SR latch. I f Bit s,,\ect i I also I . the capt ured valtoe appears On I hc D ala Oul line o f tbe R AM b il slia:. Note Ihat for ~rticular Read L ogk design. tile read O tturs regardlcso o f Ihe value o f R cadlWrite. T he synlbol for the R AM b ilslice given in Figure 9 S(b) is used 10 r epresent Ihe internnl m ucture o f R AM chips. Each Word s"lect hne c ~t endl beyond the bit slice, SO t hai when Ill ul tiple RAM bil slice, are placed side by side, c orresponding Wo rd Se lect l ine. connect. The o ther ,ig.nal. in the lower Jlortion o f the symbol rna)' be connected in ~ariou. wa ys.depending On the s tructur. o f the RAM chi p.. ll>e symbol_nil blod: di.a8Jll m for a 16 X I R AM chip . re shown in f igure 9-6. B otb ha~e foor add ....... inpulS for the 16 one-bil " OIed in RAM.1"1tere are a bo On. Input. D ata O utput, and ReadIWrito ,,;gnals1M Chip s,,1ect at t he chip level o orruponds t o t be Memory E nable.1 tl><: level of _ R AM ODn!iJSling o f multiple chips 1 M internal 'itructu~ o flbe R AM chip ODn'iim o f a R AM bit sJitt having 16 RAM cells. Since there are 16 Word S elect lines to be DJntroiled sueh that o ne a nd Qnly one has the value logic I a l a give n t im. ., a 4 to- i l;-li ne dc"CQder i . used 10 decode the four addre ss bits into 16 Word Select bits. Th ~ only a dditional logic in the figure is a triangular symbol ,.. ith one n ormal input. o ne normal OUtput. a nd a loeCond input o n the b onom o f Ihe symbol. This symbol is a t hreest ale buffer l bal allows conslruction o f a m ullipkxer ,..itb an ,,_<is 'l..-J I S RAM t o,rg .... 1 C ittu;" , ., w , ~ , , , J )- , .- ., ~ y- Q 0 - O 0 J> , .~ R AM II w , .~ , Q J )- , 0 ~ )- "., .~ II J V, ~ , SJ J Wri ' Ok>P: Wo<d R A. M " ,II )C - . .0 7 0 " ""'" I .,,. ,' , ~, o ReodlWrit. . "'" D u.;. Q D . .. " " , B W' Wril. ! ,l" . .I< Q Q 0 . .. " ", Fl GU RE ~ RAM B" St~ Modoel a rbitrary nu mb<:r o f i nputs T hree-state o u tpu," arc conn""ted together and properly controUed uSi ng the Chip Select inpu ts. Il y u si ng three-state buffers ( )fl t he o utp uts o f R AM chips, t hese o u tpu," can b e c o nnected together to p rovide the word from the chip being r ea d on t he bit l ine. attached t o the RAM o utput s. T he enable s ignals in the p receding discussion correspond to the C hi p Select inpu . . o n ' he RA M chips. T o r ead a word from a p artkular R AM chip. the D rip Set""t value fo.- that c hip must b e t . and for aU o ther chips attached to t he s ame o ut put bit Un ea the O Up Se lec t must b e O. The.., combi nation. containing a single t can b e o btai ned from a d ecoder. .,.,.1 . , , , - ,' ' " ,r, " " , W ""I ",1oct I- """"" R AM cdl1 , , W [lat. I -1 R AM cell , , , H " " " " R AM " ,II R.odIW,ite ( ,)S),," \>01 '" o... ift 0 . . . inpu. D .u",,! ~~ Bi, W rite "0". ",.,.t ,~, R .~ C lIip " ,loa (1)) BlocS. diaVU> o F1 GU KE9-6 16- W",d by J_ Bit RAM O Up C oincident Selection In side a R AM chip. t he d e<:oder with I: i np ulS and 2 ' OUlputs req uires , . AN"D gal e!! wilh k inpulS per gale i f a s traightforward design approach is " ""d. In addi.ion. i f the n umlx' o f words is laIgt' . and all bits for o ne b it Jl'OOition in the word a re cont ained;n a s ingle R AM bit sl ice. the n umber o f RAM cells sharing the read a nd wT ile circu it s is s iS<) large. The electrical properties resulling from b(>lh oC the$<: s ituations c ause the a cress and write cycle t imes o f t he RAM 10 be<:omc long. which i . undesirable. The tOlal n umber o f d ecoder gates. the number o f inpulll per gate. a nd tile n umber of RAM cells p er bit .Iice: can all be reduced by employing two decoders with a co incidml se/'ion schemc. In o ne possib le configuralion. two kl2 -inp ut decoders are used instead o f one k.input decoder. O ne dec<:><kr controls Ihe word ..,Ieet lin.,. a nd the o ther c omrol. th e bit ..,Iect ~nes. The result is a t""o--dimensiOllal matriJt ..,Ieclion scheme. If tl>e R AM chip has m words " ;Ih I bil p er word. then Ihe scheme ..,Ieclll lhe RA M cell at the inte...,Clion o f the Word SeleCl row and the Bit Select column. Since the Word ScI""1 i . n o 1000ger strictly ..,Iecting ".-ord" its n ame is changed 10 Row ~1I.An o utpul from the a dded doooder that s elttU One Or more bit .Iices is referred t o a . a CoIum" S~lul. O:>inci dcn t sclcClion is illustrated for the 1 6)( I RAM chip wi th the structure shown in Figure 9-7. The chip con.i'lll o f four RAM bil slices o f four billl each a nd has a total o f 16 R AM cells in a lwo-dimension~1 arr1ly. The two most significam address inputs go througl1tlle 2-t~4-~ne row decoder t o ..,Iect one o f IIIe four rO"l o f Ihe a rray. ' n ,e IWO least significa JlI a ddress inpUI' g o Ih rougl1 the N tH-line column d ecoder t o ..,lecl o ne o f Ihe four coIumTlll ( RAM bit slices) o f the array. The column d ecoder is enabled with the Chip Scl..,t input. When tile Chip Select isO.aU o utput' o f Ihe d.<:<>der a re 0 and nOne o f the cells is selected. T his p revem. writing imo any RAM ce ll in Ihe array. Wilh Chip Select at I ,a single bi t in Ihe RAM is a cre...,d. For exam pit. for the addTCM 1001. Ih e forsl two address bits aTe decoded 10 ..,Ieel TOW 10 ( 2,.) o fthe R AM ceU array. T he seoood t,,o address bi!] a re d ecoded t o ""lcct column 01 ( I w) o f the array. T he R A M cell accc'SCd. in row 2 and column I o f the array. iscell 9 ( 10., 0 1,) . With a row and column selected. Ihe R ead / Write inpul del ermines Ihe operation. During the read operalion ( R ead / Wrile . . I ), the selected bit o f the ..,Iccte<! row goes t hTOtlgh the O K g ale t o l he three-$late buffer. Note Ihat the gate is d rawn according t o tit<: a rray logic established in Fi gure 3-22. Since the buffer is e nabled by O ip s.,1tt1. 1he valL>C read appears a l the O .la O utp u t. O UTing the write o peration ( ReadfW r il e . . 0). the bil .,ailable OfIthe O ala Input line is t ransferrl into the ..,Iccted RAM ceU . Those RAM ""lis not ..,leCle<! a rc disabled, and thcir pr evious bi nary values remain u "ch'nged . T he s ame R AM cell a rray is used in Figure 9-8 t o p rodu"" a n 8 )( 2 RAM chip (eight words o f two bit< each). The row d..,oding is unchanged from l hat in FlguTe 9-7; Ihe only change> a re in Ihe column and output logic. Since t here are just I hree address b il s. and Iwo arc h andled by Ihe row d ecoder. the col um n d ecoder has o n ly o ne a ddress bit a nd C h ip S tltct . . inpu,s and p roduces j u.t 1"'0 C olumn Select ~ne . . Since 1",'0 billl a l a time are 10 be written o r rea d. the C olumn Se1""1 lines go 10 adi"""n l pairs o f R A M bit <lice . . TWo inpUI lines.. D ala Input 0 a nd D a ta I nput 1. each go 10 a different bi t in a ll o f t he pairs. Fi na ll y. c orresponding hits o f t he pairs share Outpul O R ga les and Ihree_st ale buffers. giving o ulput lines Data O utput 0 and Data O utput I . T he o peration o f this ,truClure can be illustrated by Ihe application o f Ihe address 3 (011,). T he firsl t wo bits o f t he a d dress. 01 . acress row 1 o f Ihe array. The fo n al hit. 1. acce'SCs col umn I. which COn_ sists o f bit slie<..'S 2 ( 10,) a nd 3 ( I 1 ,). So the word to be "Titl en O f read liel! in RAM cells 6 and 7 (011 0 , and 011 1,). which c onlain bits 0 and I. respectively. o f word 3. 41 0 0 CHAPTER 9 I MEMORY BASICS , -"- o t 'l(;UR 97 Oiagram < If. 16 ~ I R AM U sing. 4 ~ 4 K AM ~n A rray We can demo n ~l rai e Ihe sav in gs o f Ihe coi ncidenl selection scheme by COn sidering a more r eali"jc s ialic R AM size. 32 K x 8. This R AM chip cOnl. ins a 10lal o f 256 K bils. T o m ake lhe n umber of roWS a nd c olumn. in Ihe array e qu al. "e lake Ihe square r ool o f 256K. giving 512 . . '1'. S o Ihe firsl nine bill; o f III<: addr~ a re fed 10 t he row decoder a nd Ihe remaining six bits 10 Ihe column d ecoder. Wilhoul coincidenl ... Iec lion . Ihe $i ngle d eeodu would have 15 inpul~ a nd 32.168 OUlpU ts. Wi th coincid ent . .. leCl ;on, t here is o ne 9 -t<>-5 12-line decoder a nd o ne 6-lo -6l -Ji ne d ecoder. ' Ibe num ber o f g ales for a s tra ;ghlforward design o f Ihe single decoder , ,ould b e 32.&Xl. For Ihe Iwo coincid cm d eeoders. Ihe n u mber o f gales is 608, reducing Ihe g au COunl hy a faclor o f m ore Ihan 50. In a d diliOtl. a hhough ;t a ppears Ihal Ihere a re 64 li mes a . many ReadlWrile circuits. Ihe c olumn . .. Iection 9 -4 I A . ... y o f$RAM I e. -" 0 4 tt " --- - o F1G U MI> 9-8 Block Diagrom o f,n 8 ~ 2 RA1>1 U oins' 4 ~ ~ RAM Cell Array can b e d one between the II.AM c db a nd tbe Read/Write circuils, s o Ihat only the original eight c ircuil' are required. Because o f Ihe reduced number " f RAM cell$ a \lathed I " each lI.eaJlWrilc circ ui t at any lime. t he access time o f t he chip is a lso improved. 9 -4 A RRAy OF S RAM y es In tegrated circuit RAM chips are ovailable in a variety o f si .es. If the memory Unil n eeded for a n applicalion i . l arger l han the capacity o f o ne chip. i. is necessary to rombine a n umber o f chips in an array t o form Ihe required size o f memory. The capacity o f the m emory dep<:nds o n two p aramcters, the n umber o f words and tbe 4 12 0 C U"PrER. I MI:.MOR Y II "SU:;S JII t Jw tt orl W{J L r iUmLr p er Increase In n umL req UIres we increase Ihe address lenglh. Every bil a dded to the lenglh o f the addre~$ doubles t he n umber o f words in memory. All in crease in the nu mber o f bit~ p er word r equires Ihnt we increase Ihe n umber o f d ata input a nd out put lines., b ul Ihe addrJ/SS length r enla;n, t he same. To Iltustrate an a rray o f RAM 1 let u . Ii"'t imroduce a RAM chip using Ct. the r oodensed r epresentation for inputs and o utputs S!Knoll in Figure 9-9_ T he C3p11C1ly o f t hi, c hip i . 6-IK words o r8 bits each. l be c hip r e<julre$. [6-bit address and S input a nd OII t l"' l lines. [ n.lead o r 16 lines for lhe address a nd S lines e ach f or data input and d ata OUlpul. each i1 s hown in the block d i'gram by a single line. E ach line has a slash ""rOM il wilh a n umber in dicating Ihe n umber of lines represenled. '!"b e CS ( Chip Select) input s elts the particula r R AM chip. a nd t he R IW ( R cad/Write) input specifICS the rCAd Or wr ite operation wh e n Ihe chi p i , s decled. ' Th e small triangle i hown 81 the o utputs is I he . tandMd graphics symbo l for I h ree~tn l e OIIlpUls. T he C S i nput Of the RAM controls the beha.1or o f the d at a Outpul linea. When C S = O. Ihe c hip is nOl selecled. a nd all its d lla OII II"'IS are in the h l", .impedance state. Wilh CS . 1 .lhe d a", OUlpullines c arry the eiJ.ht bits o f Ihe . .. It'CIed word. Suppose lhat we " "8nl 10 illCfease Ihe n umber o f " 'ortls in I he ~mory by u .ins t,,o o r m o re RAM chips. SinO!: e very bit a dded 1 0 t he .ddr~ d oubles the binary number Ihat can be formed. il is n atu .... l t o increase the number o f words in (actors o f two. F or u ample. Iwo RAM chips will d ouble the num l>Cr o f w ord. and add o ne bit 10 the OOIIIf'O'I ilc address. Fo ur R AM chips mullipl), Ihe number o f words b)' fo ur and a dd two bi . . to the cOlllf'O'lile addrcso. C onsider the possibilily o f c orulrucling a 251i K " 8 R AM wilh four 64 K , ,8 RAM chips. DS . hown in Fi gure 9.10. T he eiJ.h1 d ata input lines , 0 t o a illhe chips. T he Ihre<Htale o utputs c an b e c onnecled l ozelhe r t o fOfm Ihe eIght COIIImon d ata o utpu l li ~ This t~pe o f OUlput conne<tion is possible o nly with thrN:-.;tale outpula.JUSI o ne c hip s elect input "'111 b e aeti,c a t any time . .. h,le Ih e o the r thrN: chips ,"',11 be d isabled.lbe eiShl OUlpu ts o f I he . ., l'"Ctw c hip will c on lain I ', a nd 0 '. . a nd the OIher thrN: "'ill be in a h igh-impedance stale. pr~nting Oflly o pen ciT~uilS t o the binary o utpul . ign. ls o f Ihe ~Iect~d ch ip. Th ~ 25!5 K word m emory r eq lli res an IS-bit addreso. T he 16 least ,igniflcant b il. o f the addre ... a re applied 10 Ihe addre ... Input. o f all fo ur chips. T he two mOSI 6 -IK" 1.,.., ..... ,- " "".~ R udlW,il< ~ RAM v f --"--OUlpul . .... ~" " DRS - ~ o n GU M. E99 SymOOl t ot. M K x 8 R AM CIIip ., , L. . I -,, . , ';~' I" - w rite - I "'""'" ~" ~ ~" ADRS ~ , :- ~" ADRS '--- ~ DATA . oM ~ ~. ., o t l CU ME 9-tO B lock Di.o""m o f. 2S6K X a R AM sign ifiC<lnt bits a rc ~pplied 10 a 2 x 4 decoder. The (Qur o utpu ts of the <k<:o.kr a re a pplied 10 t h e C S i nputs o f t h e f our c hir- Th e IDemOf)' i . d i sab led w ilen [he E N input o f the d ecoder, M emory E nable. i . e<juaJ t o O. All four o mpul. o f t he d ecuder a re t ""n O. a nd none o f t he c hip' is ..,Iocted. v.'ben t he d ecoder is e nabled. addre . . bil5 17 a nd 16 d etermine ( he pal1i<:ular c hip thai i . selected_ If these bilS 4 14 0 C H AI'rER 9 I M EMORY B ASICS 16 i" p"'do" U .. . j, " 60IK X 8 RAM ," M" V 60IK X 8 RAM +, " AO~ D ATA V , ADRS ~ ~ "" ~ - , " 16 """1"" d o" Ii "". o F1GUJU 911 Bloc k D i .~m 0 1. 60IK X 16 RAM a rc equal t o 00, t he first RAM chip i< selected. Th e rema ining 16 a ddress b it. then selcct a word wilhin tne cnip in the range from 0 t o 6 5535. The next 6 5536 WOT<is a rc selected from the second R AM chi p with an tSbit address l hm. t am wilh 01 followed by the 16 b ilS from t he c ommon a ddress lines. T he a dd ress range for each chip is lisled in decimal under its symbol in the figure. t1 is a lso possible 10 c ombine 11"0 chips t o form a composile m emory c on laining t he s ame n umber o f words. but with twice as many bits in e ach word. Figure 9 11 s how, l he imerconnection of 11"0 64K X 8 chips t o form a 64 K x 16 memory. The 16 d a ta inpUI a nd d ata Out pul line. arc split belween the t wo chips. Both receive the same t6-b i! a ddress and the c ommon CS a nd H IW c om rol i nput s. T he two lec hniques just described may b e c ombined 10 assemble a n a rray o f idemical chips i mo a large-eapac; !y memo')". Th e composite memol}' will have a numbeT o f bils per word that i s" muhiplc o f that for one chip, The 100ai n u mber o f wOlds will increase in factors o f 1"'0 times lhe word capacily o f one chip. A n ex!ern al d ecoder is n eeded t o selcc! the individ ual chips ba:d o n the addilional a ddr""s bits o f the composite memory. To reduce l he nu mber o f pins o a the chip p acbge . man}' R AM !C~ provide common t erminals for Ihe d a ta input and d ata o utput. Th e c ommon t erminals a re said to b e b idirlXtional, which meaas that for the read o pe ration they acl as o ut p ut . . and for the write operation l hey act " ' inpm s. Bidirec!ional li nes are c onstructed with three-stale buffers a nd arC diso:us~d f unhcr in Section 2-S, T he u: o f bidircc\ional signals req uire, con!rol o f the !hree-S!ale buffers by both Chip Selecl and Read/Write. ~_5 I DI<.AM I C. 0 41 S 9-5 D RAM I es Because o f its ability t o provide high storage capacity at low cost, d}lIamic R AM d ominales Ihe high-ca pao:ity memory appli~alions, including the p rimary RAM in c.:>mputers,. Logically, D RAM in many ways is ' imilar t o S RAM, I low evcr, because o f t he ele<:tronic circuit used t o implement the ! lorage cell, its electronic design is c.:>nsidernbly more challenging. F urther, as the n ame "dynamic" implies., t he s torage o f i nformation is i nherently only temporary. As a c.:>nS<'([uence, the information must b e p e ri odically - refreshed" t o mimic the behavior o f static storage. This need for refresh is t he primary logical difference in the behavior o f D RAM c ompared t o S RAM . We explore Ihi$ logical diffe.ence by examining the dynamic R AM cell, the logic requ ired to p erform the refresh operation, and the impact o f the n eed for refresh on m emory system o peration. ( D RA~) DRAM Cell T he dynamic RAM cell circuit is s hown in Fi gure 9.12(a). I t c onsim o f a c apacitor C a nd a t ransistor T. T he c apacitor is u scd to s tore electrical charge. I f th ere is s uffi cient charge s tored on the capacitor. it can b e viewed a . s toring a logical l . I f I here is insum<:ient <:harge $tor~d On the ca!>,,<:itor. it c an b e viewed a$ s toring a logical O. T he t ransistor a<:ts much like a switch. in t he s ame m anner as t he t ransmission gate i ntroduced in C hapter 2. When the s .... itch is " open,- the c harge o n t he ca!>"citor r oughly remains fi:<ed, in o ther wo<ds, is sto< ed. B ut wbeD the s .... itch is ' "dosed .'" c harge can flow into and out o f t he c apacitor from t he e xternal B it (B) li n e. This cha rge Oow a ll ows the c e ll 10 b e w ritten .... ith a I Or 0 a nd to b e r ead . In o rder t o u nderstand the r ead and write operations for the cell, we will use a hydraulic analogy with charge replaced by water, the c apacitor by a small storage t anl, and the transistor by a ~alve . Since the bit line has a large capao:itance. it i . r epresented by a large t anl a nd pumps which can fill a nd e mpty this tan k rapidly. This a na logy is giyen in Figures 9-1 2(b) and 9-12(c) with the valve d osed. N ote thai in o ne case the small storage lank i$ full r eprescnting a s tored I and in the o the r case, it is e mpty r epresenting a store<! 0. Suppose that a 1 is t o be wrillen into the c ell T he "al~e is o pened and the pumps fill up the large tank. Water flows through the valve, filling t he small . torage tank as s ho"" in Fi gure 9 -12(d). T hen the v ah'e is <i()1;{:d. leaving the small t ank ful l which rep resents a l .A 0 can be written using the same sort o f o pera t ion" e xcept that the pumps empty the large tan\: as shown in Figure 9.12(e). Now, suppose " 'e want t o rcad a s to",d value and that the ,'alue is a I " ",re s ponding t o a full storage tank. With the large tank at a known intermediate level, the v ah'" is o pened. Since t he small storage tan k is full. water flow< from the small tank t o the large t ank iocrea,ing the le"el o f the water surface in the large tank . li gh tly a . shown in Figure 'J-12(f). n ,i, i nc. ea;c in level is o bserved as the r eading o f 1 from the storage tank . Correspondingly, if the storage t ank is initially emp'Ythere wilt be a slight decrease in t he level in the large t ank in Figure 9-12(g), which is observe<! as the reading o f a 0 from the storage tank. ll!l=:~ lllt:=~ ( d) ,., ( e) ll~~ l llEl~ , ;;; [ ) n CU k E,.. n O y . .. mi< RAM n. hyd,.~1or: w .".Iosr or ""U ope""""'. and occU 1I'IOd<1 ] n t he r cad " ""ration juS! d ncribf,d, Figures 9 .l2(f) and 9 12(g) show that. regardless o f lite initi ' to red value in lhe . ,orage t ank. it nOw r o nla,ns an intermediale value ... hieh will not cause c "uugh o f a change in lhe l ovd o f the u ternsl t ank 10 permit a 0 or I t o b e o bscn'ed. So lhe r ead o peration has destroyed the s tored v 1ue: t his is r eferred t o a s a dcs'",elivc r rull. T o be a ble 10 r cad t he o riginal . to red value in lh e ( mu.e. we mUS t !<SIUr#: ;1 (i.e . relurn t he s to rage l ank 10 i l' original le.'e l). To perfono the 'C$10re (00- a Slored I oo..:,,.d. the large lank i . filled by 11M: p umps a nd t he . .... I1 " k fiJis I hrough t h e o pt . . vllve.. T o p erform t he r estore for a Slored 0 ~ ....-ed. tile l arg. lank is e m plied by the pumps a nd the small tank dralM through lhe: op<:>n ,-. Ive. In the aclual . tonge c ell.the: I re Other paths presem for ( ha rte flow. T hese p ath. a rc aoalogollS to small leaks io lhe Slorage lank . Due 10 Ihese leak . . a full small storage tank will e~e nlually d rain t o a poim al which the inerea$(l in the le~cI o f t he lorge lank 00 a read ca nnol be observed . . a n increase. In fnel, if Ihe .mall tank is le$$ t han half full when rcod . it i$ pOSSible Ihat a Mereas.: in the Ic~e l of t he large tank may be <:>b5;:,,'ed. To e ompeusalc for these leaks. the small itorage tan k . tonna a I must be periodically refilled. 'Thi, i , rcferre<llo a . a refresh o f the cell contents. E~ery s tonge cell mU>l b e refreshed before i t. Ic~cI has declined t o a ",""nt al , ,'hidlthe s tored value cao n o longer be ~rly obsen-cd. T hrou", Ihe hydraulic analOBY. the D RAM o peration has b een explained. J u" 10$ for l he SRAM. We e mrJoy, logic model for the cell. The IIl/XkI ' hown in Fi gure 912(h) i, a D latch. The C input 10 the D latch is Select a nd t he D i nput 10 I he [ ) latch is B. 10 o rder 10 m odtlthe OUlp ut o f the D RAM <0:11, "-c uSC a t hree_ . tale h ufftr with Select as i t. c ontrol input and C as it 5 o utput. In the original cleeIron ic circuit for the D RAM cell in I~gure 9 12(8). 8 a nd C a rc Ihe .,.me signal. but in the JOKieal model they arc ""parate. This is necessary i" the modeling pro''''is t o ",'(lid connecting g ate QUtpulJ t ogether. 9-~ I DIlA."I ICs D "t 7 DRAM Bit Slice Using t he logic m<::>del f or the D RAM c dl, """ can c onstruct the D RAM bi t- slice model shown in Fi gure 9-13. T h . . model . . similar t o t hat for the S RAM bit-slice in Figure 9 -5. I t is a pparent t hat. aside f rom the cell structure. t he two R AM bit slices a re logically . imilar. Howe,er. f rom the s tandpoint o f cOSt p er bit. they are q uite different. The D RAM c dl CQnsi,ts o f c apacitor p illS o ne transistor. The S RAM cell typically c ontains six t ransist""" &i'-ing a cell complexity roughly three t ime. t hat o f the D RAM. T herefore. t he n umber o f S RAM cells in a chip o f a given s itt -, .~ ~ , c oH Q -, C O~ A M W~ cell .~ , ~ DRAM cell W,..d , .~ -~ .~ -, C ,., H Q W~ D ~A"1", D --- - 0 .. . . D ao. " "I R<ad' Wiii< B" x le ( b) SymOOI Writ< 100>< .!. R<od t.,.", D n G URE9-13 D RAM Bit Slice M<><kl D.'. "'" 41 8 0 C H /lI'T ER ~ I M EM ORY ElAS1CS 1 less l an onc-tbl rJ 01 those inIlle DRAM. The DRAM cost I"" bil is less than s 11"3 Ihc S RAM COSI p er bil. which juS1 ifies the use o f D RA M in large m emorie . . Refresh o f I h ~ D R AM c ontents remains t o be discu<Sed. BU I firsl. we n eed 1 0 develop the typical st ruCture used t o h an d le a ddrc"ing in D RA Ms. Si nce many D R AM chips are used in a D RA M. we wanl 10 red uee Ihe physical size o f Ihe DR AM ch ips. Large D RAMs r equire 2{1 o r more addr~"$S bi t. . which would req ui re 2{1 a ddr . ... pins o n e ach DR AM chip. To ",d~e t he number o f pin. . t he D RA M address ill applied ..,rially in 1 "'0 p ans " 'ith Ihe row a ddress firsl a nd l he column address " """"d. This can be d one since the row address.. which p erfonn, the row ..,lection. is actually needed before the column a d dress.. which reads ou t t he data from Ihe rOw selected. In o r der 1 0 hol d Ihe rOw a d dress Ihro ugho ut Ih c rcad o r wrile s lored in a regisler a s sh",",,'", in Figure 9_14. T he c o lu mn I . The load . ignal for the row a ddress and for Ihe column a dd",..." i , CAS thai in addilion 1 0 RAS a n d' :~~"',,~ l~'l;~: ch ip R /W ( R cadlW,ilc). a nd O E ( i Ihal t his design uSC-' signa ls aCl ive a t t he L OW ( 0) level. T he hming for D RA/>I wrile ,md read opcr aliOl ' appe ar , in Fig ure 9.15(a). The row a ddress is applied 1 0 t he a ddress input . . and Ihen R AS cha ng"", f rom 1 t o O. loading Ihe rOw ad<.ln. ... in lo l he r ow addr"" register. This address i , a rr1ied I " . Ihe row a ddress decoder and selccts a row o f D RAM cells. Meanwhile. 1he column I H er"" h coo,rut!.-" I ~,- I """nO<. I - I-- I R Qw ......, "" "'P'" 0 .... I R.,... '",,,n A -- 0 ""' ( ""'",n C olumo _ret> "' ~O<' . DRAM O RA\ ' .~ L -- (QJ U ~""nl 00 .'"' '." D HA " I rrL .. Inp<JtIO\I'r<>ll.oi" . .r- C ol"mn_. 0.." ;n! 0 . . . " '" a FI G U RE 9- 1" Bk<:k Diagnom o f D RAM r ""Iuding Refresh L og" 'J..~ I D RAM I e. n n 0 4 19 n I~-- A~()( oW "" 0 .'1"" on.'*' ,-" ,- A ddrsw \ X == )C -I ; \ I \ W O. o n G U MF. ~15 Timing f ", D RAM W I;!. 000 Re;><l O po ... , ,,,,," I I 4 20. 0 CI-I,o\PTER 9 I MEMORY lIASICS a ddress is applied. a nd t hen CAS e hanges f rom I to 0. loading t he c o lumn a ddr esl i nlo Ihe onlumn addre ... register. Th,s a ddr"", i . a pplied t o t he col umn a ddresl d ~'<'Odcr. which !'01e'Cts a s et o f c o lumn . o f the R AM a rray o f s ile e qual 10 the nUm _ l>c r o f R AM d "la bil . . Th e i nput d a'n wil h Read/Write _ 0. is " pp li ed o ver a l ime int e".1 , imH ar 10 I hat for Ihe co tu mn addrcIS. T he d al. b il. arc a pp li ed t o Ihe SC I o f bit h ne. i elecled by Ihe column a ddr ess d ecoder which. in l um " pp ly the val ue. 1 0 the D R A M cells in Ute s elected TOW. " 'riling Ihe I leW d ala i nto Ihe cells. " ''hen C AS a nd R A S retu rn 10 I. Ihe ,,,i le ')'l'le ill (lOltIpiete a nd t~ D R AM ce ll. s tore Ihe I>CWIy . . n utn data_ N01e , hat the s lo'ed d ata in all o f the o , hc r e e l" in t he addresse.:l row has been reslored. 1llc: rud o pera lion timing oho"'n ,n Fi gure 9-IS(b) i. .. m ilar.lim ing o f t he a ddre"" o perallon. i . t he samc_ H o"'cvcr, n o d ala is a pplied a nd Rudl Write 1$ I i nstead ofD. Data v alue. in l he D RAM C<!II. in ' h e selected ro", arc applied t o the hil hn e, " " d s ensed by the se n... a mplifi c1"$. The I I t he v alue. t o boo! se nt 1o Ihe D ala o utput. which ing Ihc rc ~d QjXralion. a ll v alue. in t he a ddressed r ow a rc To SU llPO n rdresh. a dditionollogic s ho. . o in c olor is p resenl in t he block dia gram in Figure 9-1 4. T here i . a R efresh COUnter a nd a R efresh cOfUTolle r. 1llc: Refresh c ounter i< u .cd 10 proYtUe Ihe add~ o f the row 01 D R AM cells 1 0 be r efreshed . It I t eMo:n1ial for t he ref.~ m0de5 that r equ ire the a dd"'-H 10 h e p m"oded from within t ht D RAM chip< 1llc: refresh <:(lUnler .dval'K:CS o n each n :fresh e yde . Due 10 , he n umher o f bits in th~ c ou nter. , ,-he n it reac h ~ 2" _ \ , w here n is t he n umb;:r o f r o",. ill Ihe D RAM a rrny. il a dvances 10 0 on t he next r dresh. T he s ta nd.rd way$ in " 'h ien a r efresh cy cl e can be triggered and I h~ c o rresponding rdt~sh t ype, uTe as fo llo ws; I . MAS unly r ef_ h. A r ow a ddress is p laced o n Ihe address lill ~ nnd R AS i . c hanged t o D. In this """". the r dresh a ddresses must boo! a pp li ed (, om outside lhe D RAM c hip, ')-pically by I n Ie c a lled a D RAM COfluoILc . 2. C AS bel....., R AS rer....1L The C AS i< c bangcd from I t o 0. fol ......-cd by a change: from I ' 00011 R AS. Addll'OIIal refresh cycles c an be p e rformed by chonging R AS " 'ilhout changJllg CAS. T he refresh addre!6CS for IhlS case come from , he refresh c ounter, " 'hich i . incremented . f,c, ' he refresh for e tch ')'l'1e. 3. I lidd en " ,r",. h. Following a norrll.1 rea d Or wr ite, C AS is left a l 0 and RAS is cycled. e ffecli,'ely performing u C AS b efore R A S , ef,e,h, D uring a h idden r efre,h. t he o U'pu, d ata from t he pri or read rem ai n. valid. Th us,l he refresh i . h idden, Unfortunatel y. t oc time la ken by t he h idden , efr esh ill significant. s o a s ubsequent r ud o r wrile o pera tion ~ d elayed. In all ~ n oIc t hat t he , n'"at'OII o f refresh ill c ont rolled externally by using tl\c R i\S a nd C AS .ignal.. E ac h row o f a D RA M c hip requlTcs refreshing ...;Ihill a specified maximum rdrC$b lime. Iypically rangillg from 16 to & I miUiseconds ( m,) . RcfrcshCi may b e p erformed a l " "enly . paced pointS in the r efre.h lim". a n a pproach called d;"rib~t cd r dre'h. A lternat ively. all r efre,hes may be p erformed o ne a fter the othcr. U a ppr oach called burst r efre.h , F or e xa mple, a ti 4M ,, 4 ! )\{AM has a refre< h ti me o f 64 m . a nd has 4096 rows 10 be , efreshed , T he 4 1 DRAM TJP<' 0 42 1 length o f l ime t o p erfonn a single r dre5h is 60 ns.. a nd the ,..,fresh i nte"al for dis trib~ted refresh is 64 msJ4096 . . 15.6 microsecond5 (J.lS). A total time o ul f or refresh of 0 ,25 ms is used out of the 64 m , refresh interval. FOT t he s.ame D RAM. ~ burst refresh also ta kes 0.25 I llS. The D RAM controller mUSI iniliale a refresh every 15.6 ~ for di$lribuled ref,..,sh and mU$1 i niliale 4.096 refreshes se<juentially every 64 ms for bursl refresh. D uring any r dresh cy<:le. n o D RAM reads OT writes can occur. Since use o f b um refresh would halt computer operalion f or a fairly long period, dislrib uted refresh is m ore commonly used. 9 -6 D RAM TYPES Ch'er the last 1 \<" decades. b oth the capacity a nd s peed of D RAM h a5 illCJeased significanlty. . ~ q uest for s pew has resulted in Ihe evolul;';'n of many Iypes o f D RAM. S everal o f the D RAM types are li5ted with brief descriptions in Ta ble 9 2. O f Ihe m emory Iypes tis led. the f irsllwo have largety been reptaced in tlt e m arkel' place by Ihe more advanced SD R AM and R DRAM approaches.. Since " 'e have chosen to provide a discussion o f error-corrceling code. ( ECC) for memories on Ihe texl websile. o ur discussion o f m emory t yp'" h ere will omit the ECC fealUre and foc-us On synchrono us D RAM. d ouble d ala r ale synchronous D RAM, a nd R amb~ D RAM . Before con5idcring Ihese Ihree types o f D R AM. SOme o f tlte underlying c oncepts are covered briefly. Firsl o f alt, al ll hree of Ih"5e D RAM types work well beeau se o f Ihe parlicu_ lar e ll vi roomenl in wh ich they o perate. In modern high-speed compuler 'y1tems. Ihe processor inleracts with Ihe D RAM wilhin a m emory hierarchy. MO:SI o f Ihe in structions and d ata for Ihe processor a rc felched from two lower level, o f the hierarchy. Ihe L I a nd L2 cache . . These are c omparatively . maller SRAM-based memory Structure. , hat are CO"cred in detail in C hapler 14. For OUr purposes.. the key issue is Ihal mo:sl of 1M