11
Lecture EE114
Lecture 11
Common Drain Stage
(Source Follower)
R. Dutton, B. Murmann
Stanford University
R. Dutton, B. Murmann
EE114 (HO #15)
1
Common Drain Stage
VDD
+
v gs
-
Vo
IB
R. Dutton, B. Murmann
Cgd+Cgb
vi
Vi
RL
CL
Cgs
ro
-gmbvo
vo
RL
EE114 (HO #15)
gm vgs
Csb+CL
2
EE114
Lecture 11
CD Voltage Transfer (1)
'
1
vo % sC Ltot + sC gs +
%
RLtot
&
vi
+
v gs
-
g m + sC gs
vo
=
vi g + sC + sC + 1
m
gs
Ltot
RLtot
gmvgs
Cgs
Cgd+Cgb
vo
CLtot
C Ltot = C L + Csb
$
" ! vi sC gs ! g m (vi ! vo ) = 0
"
#
RLtot
RLtot = RL ||
sC
1 + gs
vo
gm
gm
=
!
s ( gs + C Ltot )
C
vi g + 1
1+
m
1
RLtot
gm +
RLtot
1
|| ro
g mb
R. Dutton, B. Murmann
EE114 (HO #15)
3
Low Frequency Gain
av 0 =
gm
1
gm +
RLtot
RLtot = RL ||
1
|| ro
g mb
Interesting cases
RL, ro, gmb=0
PMOS, source tied to body, ideal current source
VDD
VDD
RL, ro, gmb0
Vo
Vi
Yin
av 0 = 1
Vi
NMOS, ideal current source)
CL
Vo
IB
RLtot=1/gmb
CL
av 0 =
PMOS, source tied to body, load resistor
EE114 (HO #15)
gm
g m + g mb
( ty p ic a lly 0 .8 )
RL
ro, gmb=0, RL finite
R. Dutton, B. Murmann
av 0 =
gm
gm +
1
RL
4
EE114
Lecture 11
High Frequency Gain
s
1!
vo
z
av (s ) = = av 0 "
s
vi
1!
p
z=!
1
RLtot
p=!
C gs + C Ltot
gm +
gm
C gs
Three scenarios
|z|<|p|
|z|>|p|
|a v(s)|
|z|=|p|
|av(s)|
|av(s)|
f
f
f
( in fin ite b a n d w id th !? )
R. Dutton, B. Murmann
EE114 (HO #15)
5
CD Input Impedance
Hint*:
I=Cgs(vi-vo)
By inspection*
vi
Yin
+
v gs
-
Yin = s ( gd + C gb )+ sC gs ( ! av ( s ))
C
1
Cgs
gmvgs
Cgd+Cgb
vo
CLtot
RLtot
P S - - In s ig h t fr o m M ille r T h e o r e m ,
p . 9 H O # 1 0 is c o n s is te n t
*Really, try and be brave.
R. Dutton, B. Murmann
Gain term av(s) is real and close to
unity up to fairly high frequencies
Hence, up to moderate
frequencies, we see a capacitor
looking into the input
A fairly small one, Cgd + Cgb,
plus a fraction of Cgs
T h is is im p o r ta n t to h a v in g in s ig h t a s a d e s ig n e r
EE114 (HO #15)
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EE114
Lecture 11
PMOS Stage with Body-Source Tie
Gate-body capacitance is in
parallel with Cgs
VDD
gmb generator inactive
Low frequency gain very
close to unity
Vo
Vi
Very small input capacitance
CL
Yin
(
Yin = sC gd + s ( gs + C gb )1 " av ( s ))
C
Yin ! sC gd
R. Dutton, B. Murmann
EE114 (HO #15)
7
CD Output Impedance (1)
+
v gs
-
Let's first look at an analytically
simple case
Input driven by ideal voltage
source
Cgs
gmvgs
vo
Cgd+Cgb
Csb
1/gmb
By inspection*
Z out =
Zout
1
1
g m + g mb s ( gs + Csb )
C
Low output impedance
Resistive up to very high
frequencies
*Really, try and be brave.
R. Dutton, B. Murmann
T h is is im p o r ta n t to h a v in g in s ig h t a s a d e s ig n e r
EE114 (HO #15)
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EE114
Lecture 11
CD Output Impedance (2)
Now include finite source resistance
vg
Ri
gm(vg- vo)
Cgs
Zx
Cgd+Cgb
ix
Zx =
vo
ix
Zout
Csb
(
ix = ( o ' v g )g m + sC gs )
v
& vg
= vo $1 '
$v
o
%
R. B. Dutton, Murmann
1/gmb
vg
vo
#
!( m + sC gs )
!g
"
vo
=
Ri
1
+ Ri
sC gs
EE114 (HO #15)
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CD Output Impedance (3)
Zx '
Two interesting cases
1
1 ( + sRi C gs )
sC gs #
gm &
$1 +
!
$
gm !
%
"
Ri < 1/gm
Ri > 1/gm
|Zx(s)|
|Zx(s)|
1/gm
1/gm
f
f
Inductive behavior!
R. Dutton, B. Murmann
EE114 (HO #15)
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EE114
Lecture 11
Equivalent Circuit for Ri > 1/gm
Zx
Zout
R1 || R2 =
R1
R2
Csb
1
gm
R2 = Ri
1/gmb
L
L=
Ri2C gs
g m Ri ! 1
This circuit is prone to ringing!
L forms an LC tank with any capacitance at the output
R. Dutton, B. Murmann
EE114 (HO #15)
11
Inclusion of Parasitic Input Capacitance*
What happens to this result if we dont neglect Ci=Cgd+Cgb?
* H in t: o n p . 1 0
r e p la c e R i w ith :
Ri
Zi =
Ri + sCi Ri
Zx =
)
1
C
1 ( + sRi { gs + Ci }
sC gs #
gm &
$1 +
!( + sRi Ci )
1
$
gm !
%
"
g
1
1
<
<m
Ri { gs + Ci } Ri Ci C gs
C
g
1
1
< m<
Ri { gs + Ci } C gs Ri Ci
C
!
|Zx (s)|
|Zx(s)|
1/gm
1/gm
f
R. Dutton, B. Murmann
f
EE114 (HO #15)
12
EE114
Lecture 11
Application 1: Level Shifter
VDD
Vi
VG S=Vt +Vov ! const.
Vo
IB
Output quiescent point is roughly Vt+Vov lower than input
quiescent point
R. Dutton, B. Murmann
EE114 (HO #15)
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Application 2: Buffer
VDD
Rbig
Vo
Vi
IB
Rsmall
Low frequency voltage gain of the above circuit is ~gmRbig
Would be ~gm(Rsmall||Rbig) without CD buffer stage
R. Dutton, B. Murmann
EE114 (HO #15)
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EE114
Lecture 11
Issues
Several sources of nonlinearity
Vt is a function of Vo (NMOS, without S to B connection)
ID and thus Vov changes with Vo
Gets worse with small RL
Reduced input and output voltage swing
Consider e.g. VDD=1V, Vt=0.3V, VOV=0.2V
CD buffer stage consumes 50% of supply headroom!
In low VDD applications that require large output swing, using
a CD buffer is often not possible
CD buffers are more frequently used when the required
swing is small
E.g. pre-amplifiers or LNAs that turn V into mV at the output
R. Dutton, B. Murmann
EE114 (HO #15)
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Application 3: Load Device
VDD
Advantages compared to resistor load
"Ratiometric"
M2
1/(gm2+gmb2 )
Vo
Vi
M1
Gain depends on ratio of similar
parameters
Reduced process and
temperature variations
First order cancellation of
nonlinearities
Disadvantage
Reduced swing
av 0 =
g m1
g m 2 + g mb 2
R. Dutton, B. Murmann
EE114 (HO #15)
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EE114
Lecture 11
S u m m a r y E le m e n t a r y T r a n s is t o r S t a g e s
Common source
VCCS, makes a good voltage amplifier when terminated with
a high impedance
Common gate
Typically low input impedance, high output impedance
Can be used to improve the intrinsic voltage gain of a
common source stage
"Cascode" stage
Common drain
Typically high input impedance, low output impedance
Great for shifting the DC operating point of signals
Useful as a voltage buffer when swing and nonlinearity are
not an issue
R. Dutton, B. Murmann
EE114 (HO #15)
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