4300 COMP Computer Architecture
Multicycle Implementation
Dr. Xiao Qin
Auburn University
http://www.eng.auburn.edu/~xqin
[e-mail]
Fall, 2010
1
The Problem with Single-Cycle
Processor Implementation: Performance
Performance is limited by the slowest
instruction
Example: suppose we have the following
delays
Memory read/write
ALU and adders
Register File read/write
200ps
100ps
50ps
What is the critical path for each instruction?
2
What is the critical path for lw?
Data
R1 (rt)
P
C
address Inst.
ROM
Instruction
Memory
WriteRegister
R2 (rs)
-100
ReadRegister#2
ALU and adders
100ps
Port#2
REGISTERS
lw
200ps
ALU
ReadRegister#1
16 (Imm)
Memory read/write
Port#1
16
SIGN-EXTEND
Register File read/write 50ps
32
Address
DataOut
DataIn
RAM
lw: 200 + 50 + 100 + 200 + 50 600ps
3
Data Memory
What is the critical path for sw?
sw R1, -100(R2)
Data
P
C
R1
address Inst.
ROM
Instruction
Memory
16
WriteRegister
R2
ReadRegister#1
-100
ReadRegister#2
200ps
ALU and adders
100ps
Register File read/write 50ps
10ps
ALU
Port#2
REGISTERS
sw
Memory read/write
Sign-Extended
Port#1
16
SIGN-EXTEND
32
Address
DataOut
DataIn
RAM
Data Memory
4
What is the critical path for sw?
sw R1, -100(R2)
Data
P
C
R1
address Inst.
ROM
Instruction
Memory
16
WriteRegister
R2
ReadRegister#1
-100
ReadRegister#2
200ps
ALU and adders
100ps
ALU
Port#2
REGISTERS
sw
Memory read/write
16
SIGN-EXTEND
Register File read/write 50ps
sw: 200 + 50 + 100 + 200 550ps
5
Port#1
32
Address
DataOut
DataIn
RAM
Data Memory
What is the critical path for each
instruction?
R-format
Load word
Store word
550ps
Branch
Jump
200 + 50 + 100 + 0 + 50 400ps
200 + 50 + 100 + 200 + 50 600ps
200 + 50 + 100 + 200
200 + 50 + 100
200
What is the implication?
6
350ps
200ps
Alternatives to Single-Cycle
Multicycle Processor Implementation
Shorter clock cycle
Multiple clock cycles per instruction
Some instructions take more cycles then
others
Less hardware required
Pipelined Implementation
Overlap execution of instructions
Try to get short cycle times and low CPI
More hardware required but also more
performance!
7
Our Simple Control Structure
All of the logic is combinational
We wait for everything to settle down, and the
right thing to be done
ALU might not produce right answer right away
We use write signals along with clock to determine
when to write
Cycle time determined by length of the longest
path
State
element
1
Combinational logic
Clock cycle
We are ignoring some details like setup and hold times
8
State
element
2
Single Cycle Implementation
Calculate cycle time assuming negligible delays except:
memory (200ps),
ALU and adders (100ps),
register file access (50ps)
PCSrc
M
u
x
Add
Add
4
ALU
result
Shift
left 2
PC
Read
address
Instruction
Instruction
memory
Read
register 1
ALUSrc
Read
data 1
MemtoReg
Zero
M
u
x
Write
data
ALU ALU
result
Address
Write
data
RegWrite
9
ALU operation
MemWrite
Read
register 2
Registers Read
Write
data 2
register
16
4
Sign
extend
32
MemRead
Read
data
Data
memory
M
u
x
Where we are headed
Single Cycle Problems:
what if we had a more complicated instruction like
floating point?
wasteful of area
One Solution:
use a smaller cycle time
have different instructions take different numbers of
cycles
a multicycle datapath:
PC
Address
Instruction
register
Instruction
or data
Memory
Data
10
Memory
data
register
Data
A
Register #
Registers
Register #
ALU
B
Register #
ALUOut
Multicycle Approach
We will be reusing functional units
ALU used to compute address and to increment PC
Memory used for instruction and data
Our control signals will not be
determined directly by instruction
e.g., what should the ALU do for a subtract
instruction?
Well use a finite state machine for
control
11
Multicycle Approach
Break up the instructions into steps, step
takes each a cycle
balance the amount of work to be done
restrict each cycle to use only one major functional
unit
At the end of a cycle
store values for use in later cycles (easiest thing to
do)
introduce additional internal registers
PC
0
M
u
x
1
Address
Memory
MemData
Write
data
Instruction
[2016]
Instruction
[150]
Instruction
register
Instruction
[150]
Memory
data
register
12
0
M
u
x
1
Read
register 1
Instruction
[2521]
0
M
Instruction u
x
[1511]
1
0
M
u
x
1
16
Read
data 1
Read
register 2
Registers
Write
Read
register
data 2
A
B
4
Write
data
Sign
extend
32
Zero
ALU ALU
result
Shift
left 2
0
1M
u
2x
3
ALUOut
Instructions from ISA perspective
Consider each instruction from perspective of
ISA.
Example:
The add instruction changes a register.
Register specified by bits 15:11 of instruction.
Instruction specified by the PC.
New value is the sum (op) of two registers.
Registers specified by bits 25:21 and 20:16 of the
instruction 5 bits 5 bits 5 bits 6 bits
6 bits
5 bits
Reg[Memory[PC][15:11]] <= Reg[Memory[PC][25:21]] op
R-Format
op
rs
rt
rd shamt funct
Reg[Memory[PC][20:16]]
13 In order to accomplish this we must break up the
instruction.
Breaking Down an Instruction
ISA definition of arithmetic:
Reg[Memory[PC][15:11]] <= Reg[Memory[PC][25:21]]
op
6 bits Reg[Memory[PC][20:16]]
5 bits 5 bits 5 bits 5 bits 6 bits
op
rs
rt
rd shamtfunct
Could break down to:
IR <= Memory[PC]
A <= Reg[IR[25:21]]
B <= Reg[IR[20:16]]
ALUOut <= A op B
Reg[IR[20:16]] <= ALUOut
We forgot an important part of the definition of
14arithmetic!
R-Format
Idea behind multicycle approach
We define each instruction from the ISA perspective
(do this!)
Break it down into steps following our rule that data
flows through at most one major functional unit (e.g.,
balance work across steps)
Introduce new registers as needed (e.g, A, B,
ALUOut, MDR, etc.)
Finally try and pack as much work into each step
(avoid unnecessary cycles)
while also trying to share steps where possible
(minimizes control, helps to simplify solution)
15
Five Execution Steps
Instruction Fetch
Instruction Decode and Register Fetch
Execution, Memory Address Computation,
or Branch Completion
Memory Access or R-type instruction
completion
16
Write-back step
INSTRUCTIONS TAKE FROM 3 - 5
CYCLES!
Step 1: Instruction Fetch
Use PC to get instruction and put it in the
Instruction Register.
Increment the PC by 4 and put the result back in
the PC.
Can be described succinctly using RTL "RegisterTransfer Language"
IR <= Memory[PC];
PC <= PC + 4;
Can we figure out the values of the control
signals?
17
What is the advantage of updating the PC now?
Step 2: Instruction Decode and Register
Fetch
Read registers rs and rt in case we need
them
Compute the branch 5address 5in case the
6 bits
5 bits
bits
5 bits
bits
6 bits
R-Format
instruction is a branch
op
rs
rt
rd shamt funct
RTL:
2);
A <= Reg[IR[25:21]];
B <= Reg[IR[20:16]];
ALUOut <= PC + (sign-extend(IR[15:0]) <<
We aren't setting any control lines based on
(we are busy "decoding" it in our control logic)
the instruction type. Why?
18
Step 3 (instruction dependent)
ALU is performing one of three
functions, based on instruction type
Memory Reference:
ALUOut <= A + sign-extend(IR[15:0]);
R-type:
ALUOut <= A op B;
Branch:
if (A==B) PC <= ALUOut;
19
Step 4 (R-type or memory-access)
Loads and stores access memory
MDR <= Memory[ALUOut];
or
Memory[ALUOut] <= B;
R-type instructions finish
Reg[IR[15:11]] <= ALUOut;
6 bits
5 bits
5 bits
op
rs
rt
5 bits
5 bits
6 bits
rd shamt funct
R-Format
The write actually takes place at the
end of the cycle on the edge
20
Write-back step
Reg[IR[20:16]] <= MDR;
Which instruction needs this?
6 bits
5 bits
16 bits
op
21
5 bits
rs
rt
offset
I-Format
Summary:
22