4300 COMP Computer Architecture
Pipeline: Introduction
Dr. Xiao Qin
Auburn University
http://www.eng.auburn.edu/~xqin
[e-mail]
Fall, 2010
1
Full Multicycle Implementation
Z ero
PCWrite Cond
Control
Unit
PCWrit e
ALUOp
2
ALU
Control
IRWrite
funct
op 6 I[31:26]
I
R
jm paddr
Instruction I
rs
32
IorD
6 I[5:0]
5
rt
5
5
0
MUX
rd
1
I[25:0]
0M
U
1X
RN1
MemWrite
ADDR
Memory
RD
M
D
R
2
U
RD2
MemRead
B
4
RegWrite
2
16
E
X
T
N
D
32
PCSource
ALU
0
1M
U
2X
3
ALUSrcB
<<2
X
3
1X
A
MemtoReg
im m ediate
0
U
RD1
WD
WD
0M
M
1U
ALUSrcA
Operation
WN
Registers
1M
0X
RN2
32
CONCAT
RegDst
5
PC
28
<<2
Z ero
ALU
OUT
What is Pipelining?
A way of speeding up execution of
instructions
Key idea:
overlap execution of multiple instructions
3
The Laundry Analogy
Anna, Brian, Cathy, Dave
each have one load of clothes
to wash, dry, and fold
Washer takes 30 minutes
Dryer takes 30 minutes
Folder takes 30 minutes
Stasher takes 30 minutes
to put clothes into drawers
4
A
B
C
D
If we do laundry sequentially...
6 PM
T
a
s
k
A
O
r
d
e
r
7
8
9
10
11
12
2 AM
30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30
Time
C
B
D
Time Required: 8 hours for 4 loads
5
1
To Pipeline, We Overlap Tasks
6 PM
7
8
9
30 30 30 30 30 30 30
T
a
s
k
11
12
1
Time
A
O
r
d
e
r
10
C
B
D
Time Required: 3.5 Hours for 4 Loads
6
2 AM
To Pipeline, We Overlap Tasks
6 PM
7
8
30 30 30 30 30 30 30
T
a
s
k
A
B
O
r
d
e
r
C
D
10
9
7
11
12
1
2 AM
Time
Does Pipelining help latency of single
task? No
Does Pipelining help throughput of
entire workload?
Yes
Pipeline rate limited by ___?
the slowest pipeline stage
Multiple tasks operating simultaneously
Potential speedup = ? Number pipe stage
Unbalanced lengths of pipe stages will
___ reduces speedup
Time to fill pipeline and time to drain
it reduces speedup
Pipelining a Digital System
1 nanosecond = 10^-9 second
1 picosecond = 10^-12 second
Key idea: break big computation up into pieces
Separate each piece with 1nspipeline register
a
200ps
8
200ps
Pipeline
Register
200ps
200ps
200ps
Pipelining Digital a System
Why do this? Because it's faster for repeated
computations
Non-pipelined:
1 operation finishes
every 1ns
1ns
Pipelined:
1 operation finishes
every 200ps
200ps
9
200ps
200ps
200ps
200ps
Comments about pipelining
Pipelining increases throughput, but not
latency
Answer available every 200ps, BUT
A single computation still takes 1ns
Limitations:
Computations must be divisible into stage
size
? Pipeline registers add overhead
10
Pipelining a Processor
Recall the 5 steps in instruction execution:
1.
2.
2.
3.
4.
Review: Single-Cycle Processor
11
Instruction Fetch (IF)
Instruction Decode and Register Read (ID)
Execution operation or calculate address (EX)
Memory access (MEM)
Write result into register (WB)
All 5 steps done in a single clock cycle
Dedicated hardware required for each step
Review - Single-Cycle Processor
12
What do we need to add to actually split the datapath into stages?
The Basic Pipeline For MIPS
13
DMem
Reg
DMem
Ifetch
Reg
ALU
DMem
Ifetch
Reg
ALU
O
r
d
e
r
Reg
Ifetch
Ifetch
ALU
I
n
s
t
r.
Cycle 6 Cycle 7
ALU
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
Reg
Reg
Reg
DMem
What do we need to add to actually split the datapath into stages?
Reg
Basic Pipelined Processor
14
Pipeline example: lw
IF
15
Pipeline example: lw
ID
16
Pipeline example: lw
EX
17
Pipeline example: lw
MEM
18
Pipeline example: lw
WB
Can you find a problem?
19
Basic Pipelined Processor
(Corrected)
20
Single-Cycle vs. Pipelined Execution
Non-Pipelined
Instruction
Order
0
200
4 00
600
ALU
MEM
Instruction REG
Fetch
RD
lw $1, 100($0)
800
1000
1200
14 00
ALU
MEM
1600
1800
REG
WR
Instruction REG
Fetch
RD
lw $2, 200($0)
800ps
REG
WR
Instruction
Fetch
lw $3, 300($0)
800ps
800ps
Pipelined
Instruction
Order
lw $1, 100($0)
0
200
Instruction
Fetch
lw $2, 200($0)
200ps
4 00
REG
RD
Instruction
Fetch
lw $3, 300($0)
200ps
600
800
ALU
MEM
REG
RD
Instruction
Fetch
ALU
REG
RD
1000
1200
14 00
REG
WR
MEM
ALU
REG
WR
MEM
REG
WR
200ps 200ps 200ps 200ps 200ps
21
1600
T ime
T ime