4300 COMP Computer Architecture
Laboratory Assignment 3:
Pipelined Datapath with Interlocks
and Forwarding
Dr. Xiao Qin
Auburn University
http://www.eng.auburn.edu/~xqin
[e-mail]
Fall, 2010
1
Introduction
From your multi-cycle machine to a
machine with pipelined datapath
Based on the five stage MIPS pipeline
You are allowed to create your own pipeline
2
Introduction (cont.)
Implementation of branch or load delay
slots is NOT required.
Implement each part as described
Answer all related questions
Submit your programs.
You must test (i.e., compile and run) your
simulator on a Linux machine.
3
Your Pipeline
A load-store
GPR-based 3-operand machine
Execute the subset of MIPS instructions
Implement interlocks between pipe stages to
recognize and resolve data hazards:
through forwarding when feasible, including forwarding
through the register file
through NOPs otherwise (interlocks)
4
Hazard Detection Situations
LD R1, 45(R2)
DADD R5, R1, R7
(Requires stall)
5
Comparators detect the use of R1
in the DADD and stall the
DADD (and future instructions)
before the DADD begins EX.
LD R1, 45(R2)
DADD R5, R6, R7
DSUB R8, R1, R7
(Requires
forwarding)
Comparators detect the use of R1
in DSUB and forward result of
load to ALU in time for DSUB to
begin EX.
Hardware interlock
Remaining Stalls
Some data hazards cannot be resolved by
forwarding:
LW
SUB
AND
OR
R1,0(R2)
R4, R1, R5
R6, R1, R7
R8, R1, R9
Hazard detection
causes stall until
hazard is cleared.
Hardware interlock
6
Implement Load Interlocks
Recall that the following code requires a
stall or load interlock to prevent Read
After Write (RAW) hazards
LW
SUB
AND
OR
R1,0(R2)
R4, R1, R5
R6, R1, R7
R8, R1, R9
Hazard can be detected in the ID stage
by comparing rt and rs registers
7
In which State Should Data
Hazards be Checked?
Instruction issue when instruction
transfers from ID stage into EX stage
Data hazards checked in ID stage
* If stall is required, instruction is stalled before it is issued
* If forwarding is needed, controls are set
8
Load Interlock Detection Logic
Opcode field Opcode field of
of ID/EX
IF/ID (IF/ID.IR0..5)
(ID/EX0..5)
Matching Operand
Fields
Load
Register-register
ALU
ID/EX.IR[rt]==IF/ID.IR[rs]
Load
Register-register
ALU
ID/EX.IR[rt]==IF/ID.IR[rt]
Load
Load, store, ALU
ID/EX.IR[rt]==IF/ID.IR[rs]
immediate, or branch
6 bits
5 bits
16 bits
op
rs
rt
offset
6 bits
9
5 bits
5 bits
5 bits
5 bits
op
rs
rt
rd
5 bits
I-Format
6 bits
shamt funct
R-Format
Implementing a Stall after Detection
Change opcode in ID/EX pipeline register
to 00000 (NOP)
Recirculate contents of IF/ID register to
hold stalled instruction
10
Forwarding Logic
Detection is similar to detecting RAW, but
more cases
All forwarding values originate at ALU or
data memory output
Terminate at ALU input, data memory
input or zero detection unit
11
Forwarding Logic
12
Additional
MUX inputs and paths
Building a Pipeline
Simulate concurrent behavior
PCSrc
RegWrite
1
0
W
Control
M
W
E
M
W
ADD
ADD
4
Branch
<<2
RegWrite
PC
ADDR
RD
Instruction
Memory
rs
32
rt
RN1
5
RN2
5
WN
5
WD
RD1
Ze ro
ALUSrc
Register
File RD2
ALU
ADDR
Data
Memory
0
1
immed 16
E
X
T
N
D
13
1
ALU
Control
6
RegDst
0
5
ALUOp
MemRead
1
5
IF/ID
0
WD
32
rt
rd
RD
ID/EX
EX/MEM
MEM/WB
Building a Pipeline
Push Model vs. Pull Model
"push" model: Fetch the next instruction and use
that to push the behavior of all the downstream
pipeline stages.
"pull" model: Complete the instruction in the WB
stage, emptying that stage and pulling the
upstream activities down the pipe.
Which is better?
14
Building a Pipeline
Pipeline must behave as follows
The fetch stage: use the current value in the PC to index
memory, and retrieve the instruction from the memory.
Put it in a buffer (you could call it the IF/ID latch !) where
it will be grabbed by decode in the next clock cycle.
Decode reads zero, one or two values out of the register
file and stores them in a buffer (the ID/EX latch) for use
by the execute stage in the next clock cycle. If you're
using the "pull" model you'll need to delay the change of
PC until then.
Execute: The result could be put in an EX/MEM latch.
The memory stage: If the instruction in MEM is an R-type
instruction, the MEM/WB latch should buffer the result
that was being held in the EX/MEM latch.
Write-back puts the results of an R-type instruction or a
load into the register file. This value should come from
15 the MEM/WB latch.
A Test Case
To instrument your simulator to keep track
of number of clock cycles of execution,
total instruction count, and number of
NOPs executed.
Take nearly the same example program
you used for Lab 2 - but with NOPs
inserted after each load or branch - and
run it on your pipeline.
16