ARITHMETIC
Milo 1
DIGITAL D. Ercegovac and Toms Lang
s
a
Morgan Kaufmann Publishers, an imprint of Elsevier, c 2004
Updated: February 13, 2004
Chapter 2: Solutions to Selected Exercises
with contributions by Elisardo Antelo
Exercise 2.1
Assuming that ci is connected to the XOR input with load factor 1.1 (Fig.
2.5(c)), the average delay of the carry-out is
T1 = tN AN D (1) + tN AN D (2.1) = 0.07 + 0.033 + 0.07 + 0.033 2.1 = 0.242ns
Adding an inverter and changing the XOR into XNOR, we obtain for the
carry delay:
T2 = tN AN D (1) + tN AN D (2) = 0.239ns
This represents a 1.4% reduction in the carry delay. Note that the dierence
is very small because of the XOR input with load factor 1.1. A larger reduction
would result if the XOR input load factors were symmetrical at 2.
Exercise 2.4
TSRA = tsw + (n 1)tp + (n/m)tbuf + ts (Expression (2.27))
tsw = max(tgi , tki , tpi ) + tN AN D2(L=2) = tpi + tN AN D2(L=2) = 0.329 +
0.136 = 0.465ns
where, assuming a switch has one standard load,
tgi = tAN D2 = 0.16 + 0.027 1 = 0.187ns
tki = tN OR2 = 0.07 + 0.046 1 = 0.116ns
tpi = tXOR2 = 0.30 + 0.029 1 = 0.329ns
tp = tN AN D2 = 0.07 + 0.033 2 = 0.136ns (L = 2)
tbuf = 1.5 0.136 = 0.204
ts = 0.46 + 0.03 L = 0.46ns (Table 2.2, delay ci to si with L = 0)
Therefore,
TSRA = 0.465 + 31 0.136 + 8 0.204 + 0.46 6.8ns
From Exercise 2.2, TCRA = 13.8ns so the SRA aproximately halves the
delay. Note that to reduce the load the network for computing the sum bits
uses separately obtained pi signals
Digital Arithmetic - Ercegovac & Lang 2004
Chapter 2: Solutions to Exercises
2
Exercise 2.5
Figure E2.5 shows the carry chains for the given operands.
group 3
X
Y
0
1
1
0
15
c11 c9
c12 c10
c16 c13
c3
c4
c8
c14
c15
group 2
0 01
1 10
1
1
group 1
0 00
1 01
12
1
0
8
group 0
1 10
0 01
1
1
4
10
00
0
position
c1
c2 2
c5
c6 4
c7
s 15 6
carry-skip path
carry-ripple path
t
group size m = 4
Figure E2.5: Carry chains in carry-skip adder (Exercise 2.5).
Exercise 2.10
(a) T = mtc + (s 1)tmux + (p 2)tmux + (s 1)tmux + (m 1)tc + ts .
(b) Let tc = tmux and m = s. T = (4m 3 + n/m2 )tc + ts and mopt =
(n/2)1/3 .
Exercise 2.13
The gi and ai signals are
x
y
gi
ai
0
1
0
1
1
0
0
1
0
0
0
0
1
1
1
1
The expressions and values for the CLG-4 carries are
c0
c1
c2
c3
c4
=1
= g 0 a0 c 0 = 1 1 1 = 1
= g 1 a1 g 0 a1 a0 c 0 = 0 0 1 0 1 1 = 0
= g 2 a2 g 1 a2 a1 g 0 a2 a1 a0 c 0 = 0 1 0 1 0 1 1 0 1 1 1 = 0
= g 3 a3 g 2 a3 a2 g 1 a3 a2 a1 g 0 a3 a2 a1 a0 c 0
= 0 10 110 1101 11011=0
Exercise 2.15
A 64-bit, three-level carry-lookahead adder is shown in Figure E2.15.
Exercise 2.17
n = 128, m = 4, tclg = tAG = 6tag = 3ts
T1CLA = tag + (n/m)tclg + ts = 1 + 32 6 + 2 = 195tag
Digital Arithmetic - Ercegovac & Lang 2004
Chapter 2: Solutions to Exercises
3
c60
c56
c52
c48
c44
c40
c36
c32
c28
c24
c20
c16
c12
c8
c4
c0
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
CLA4
A15
G15
A14
G14
A13
G13
A12 c
48
G12
A11
G11
A10
G10
A9
G9
A8 c
32
G8
A7
G7
A6
G6
A5
G5
A4 c
16
G4
A3
G3
A2
G2
A1
G1
A0 c
0
G0
CLG-4
A15-12
G15-12 c
60
c56
CLG-4
A11-8
G11-8 c
44
c52
CLG-4
c40
A7-4
G7-4
c36
c28
c24
CLG-4
A3-0
G3-0
c20
c12
c8
c4
CLG-4
c48
c64
c32
c16
Figure E2.15: 64-bit three-level carry-lookahead adder.
T2CLA = tag + tAG + (n/m2 )tclg + tclg + ts = 1 + 6 + 8 6 + 6 + 2 = 63tag
T3CLA = tag +2tAG +(n/m3 )tclg +2tclg + ts = 1+12+12+12+2 = 39tag
For the 4-level CLA we use another level with a group size of 2. Because of
the smaller size of this group the delay of this level is smaller, we assume
it to be tclg2 = 2ta,g .
T4CLA = tag + 2tAG4 + tclg2 + 3tclg + ts = 1 + 12 + 2 + 18 + 2 = 35tag
Exercise 2.20
i
xi
yi
gi
ai
pi
8
7
0
1
0
1
1
6
1
1
1
1
0
5
0
1
0
1
1
g(0,1)
g(1,0)
g(2,1)
g(3,2)
g(4,3)
g(5,4)
g(6,5)
g(7,6)
=
=
=
=
=
=
=
=
1 = c1
g 1 a1 g 0
g 2 a2 g 1
g 3 a3 g 2
g 4 a4 g 3
g 5 a5 g 4
g 6 a6 g 5
g 7 a7 g 6
4
1
0
0
1
1
3
0
0
0
0
0
2
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
0
Level 1 outputs:
= 1,
= 1,
= 0,
= 0,
= 0,
= 1,
= 1,
a(1,0)
a(2,1)
a(3,2)
a(4,3)
a(5,4)
a(6,5)
a(7,6)
= a 1 a0
= a 2 a1
= a 3 a2
= a 4 a3
= a 5 a4
= a 6 a5
= a 7 a6
=1
=1
=0
=0
=1
=1
=1
Level 2 outputs:
Digital Arithmetic - Ercegovac & Lang 2004
Chapter 2: Solutions to Exercises
c0
4
g(1,1)
g(2,1)
g(3,0)
g(4,1)
g(5,2)
g(6,3)
g(7,4)
=
=
=
=
=
=
=
g(1,0)
g(2,1)
g(3,2)
g(4,3)
g(5,4)
g(6,5)
g(7,6)
a(1,0) c0 = 1 = c2
a(2,1) g(0,1) = 1 = c3
a(3,2) g(1,0) = 0, a(3,0)
a(4,3) g(2,1) = 0, a(4,1)
a(5,4) g(3,2) = 0, a(5,2)
a(6,5) g(4,3) = 1, a(6,3)
a(7,6) g(5,4) = 1, a(7,4)
= a(3,2) a(1,0)
= a(4,3) a(2,1)
= a(5,4) a(3,1)
= a(6,5) a(4,3)
= a(7,6) a(5,4)
=0
=0
=0
=0
=1
Level 3 outputs:
c4
c5
c6
c7
=
=
=
=
g(3,0)
g(4,1)
g(5,2)
g(6,3)
a(3,0) c0 = 0
a(4,1) g(0,1) = 0
a(5,2) g(1,1) = 0
a(6,3) g(2,0) = 1
Level 4 outputs:
s0
s1
s2
s3
s4
s5
s6
s7
c8
=
=
=
=
=
=
=
=
=
p0 c 0 = 1
p1 c 1 = 1
p2 c 2 = 1
p3 c 3 = 1
p4 c 4 = 1
p5 c 5 = 1
p6 c 6 = 0
p7 c 7 = 0
g(7,0) a(7,0) c0 = 1
Exercise 2.23
A diagram of a 4-bit conditional-adder module is shown in Figure E2.23.
Exercise 2.26
X
Y
01
10
01
10
01
11
11
11
S0
c0
S1
c1
11
0
00
1
11
0
00
1
00
1
01
1
10
1
11
1
S0
c0
S1
c1
11
0
00
1
11
01
1
01
1
10
S0
c0
S1
c1
00
1
00
1
00
11
00
01
10
00
01
11
Digital Arithmetic - Ercegovac & Lang 2004
Chapter 2: Solutions to Exercises
5
x3 y3
x2 y2
x1 y1
x0 y0
FA
FA
FA
HA
HA
HA
HA
NOT
c1
4
s1
3
c0
4
s1
2
s0
3
s1
1
s1
0
s0
2
s0
1
s0
0
Figure E2.23: 4-bit conditional adder for Exercise 2.23.
The result is (c0 , S 0 ) because cin = 0.
Exercise 2.29
a) Type 1 adder:
x
y
c0
i
c1
i
ci
si
1000
0111
11111
00000
00000
01111
100
000
110
001
001
101
111
110
011
100
100
101
The actual delay, assuming critical path in producing F , is
TT ype1 = tXOR + tOR2 + 10 tc + tOR2
where tc is the delay of producing a carry:
tc = tAN D2 + tOR2
Given that tc has the same expression for the carry-ripple adder and that
the actual delay of tc is 15% smaller than its worst-case delay and assuming
the same variation for tXOR and tOR2 , we get:
TT ype1 0.85TCRA
Digital Arithmetic - Ercegovac & Lang 2004
Chapter 2: Solutions to Exercises
6
b) Type 2 adder:
x
y
chains
timing
1000100111
0111000110
jihgfedcba
6543211111
In this example, the longest chain is zero-carry chain efghij of 6 positions.
The actual delay is
TT ype2 = tXOR + tmax + tOR2 + tAN D10
where tmax = 6tc .
Consequently, including the delay of AND-10, for this input pattern the
addition delay is rougly 70% of that of the adder of type I.
Exrecise 2.32
a)
X
Y
W
S
C
Z
S
C
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
1
0
1
1
1
1
1
1
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
111
110
010
010
101
001
100
110
a carry in;
1
0
1
0
0
1
1
1
1
0
0
1
1
1
1
0
00
10
10
00
00
11
11
00
a carry in
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
1
1
1
1
1
0
1
0
1
1
0
0
1
1
0
0
0a
1
1
110000110
001001101
101010101
111101110
010001010
101110000
111111010
100011101
P output of Odd-parity module.
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
0a
1
1
b)
X
Y
W
Z
T
P
S
C
1
1
1
Exercise 2.35
1
101
1
011
001
1
110
1
100
011
1
Digital Arithmetic - Ercegovac & Lang 2004
110
0
111
101
0
011
1
011
111
0
Chapter 2: Solutions to Exercises
7
Exercise 2.39
Method 1:
X
Y
H
Z
Q
T
W
S
1
0
1
0
1
1
0
1
1
1
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
0
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
Method 2:
X
Y
P
T
W
S
1
1
1
1
1
0
0
Exercise 2.43
Radix-2 signed digit addition of one conventional and one signed-digit operand:
X
0
1
1
1
0
1
1
0
Y
+
1
0
1
0
0
0
1
1
Y
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1
W
T
S
+
S
S
Digital Arithmetic - Ercegovac & Lang 2004
Chapter 2: Solutions to Exercises