330 EE Exam 1 Fall 2009
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _
Instructions: Students may bring 1 page of notes (front and back) to this exam. There are 8 questions and 6 problems. The points allocated to each question and each problem are as indicated. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; nCOX=100A/v2 ,pCOX=nCOX/3 ,VTNO=0.5V, VTPO= - 0.5V, COX=2fF/2, = 0, and = 0. If reference to a bipolar process is made, assume this process has key process parameters JS=10-15A/2, =100 and VAF = . If reference to a diode is made, assume the process parameter JS=10-17A/2. If any other process parameters are needed, use the process parameters associated with the process described on the attachment to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters.
1. (2pts) A section of the periodic table that shows most of the key materials used in semiconductor devices is shown. List two materials that can be used for impurities to form an n-type region in single-crystal silicon.
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2. (2pts) When the gate to source voltage of an n-channel MOSFET exceeds the threshold voltage, a special conductive layer is formed in the channel just under the gate oxide. There is a special name for this special conductive layer. What is it? 3. (2pts) The MOSFET was reported somewhat earlier than the BJT. How many years lapsed from the time the MOSFET was first reported to the time the BJT was first reported? 4. (2pts) Why cant deposition/diffusion be used rather than epitaxy to form the lightly-doped n-type region that forms the collector in a standard Bipolar process? 5. (2 pts) Why is metal usually preferred over Polysilicon when making interconnects in a MOS process? 6. (2pts) What is the major advantage of using a shallow trench isolation rather than Local Oxidation (LOCOS) to separate devices in a MOS process? 7. (2pts) Some processes allow stacked vias for interconnecting multiple levels of metal. What is the major advantage, from a designers viewpoint, of the stacked vias?
8. (6pts) Assume that you are using a standard Poly-Poly capacitor of 1pF in the design of a circuit that requires applying a voltage across the capacitor of about 3.5V and that this voltage is causes an electric field in the dielectric that is just below the breakdown of the SiO2 dielectric. Assume a scenario whereby a process engineer comes to you and proposes a modification to the process whereby the SiO2 that is currently used as the dielectric can be removed and replaced with air (this is possible!). What effect would this change in process have on the voltage you could apply to the capacitor and the area required to realize the same 1pF capacitor? (The dielectric constant of SiO2 is 4.5, that of air is 1.0. The dielectric breakdown of SiO2 is about 10MV/cm and that of air is about 20KV/cm.
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Problem 1 (12 pts) A cross-sectional view of a layered capacitor (not to scale) is shown where one terminal of the capacitor is comprised of the A nodes and the other terminal is comprised of the B nodes. Assume the cross-sectional area of each of the plates is 10002.
A B
Meta l2 thick oxide Meta l1 thick oxide Poly 1 thick oxide p+ d iffusio n n -we ll p sub strat e
A B A
a) b)
Determine the capacitance between the nodes A and B under bias. 0V Repeat part a) if the voltage at node A is 5V higher than that at node B
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Problem 2 (12 pts) The stick diagram of a logic circuit is shown. The connection of the source of the right-most p-channel MOSFET to VDD was inadvertently missed thus the circuit will not perform as desired. a) Give the circuit schematic of the circuit that is represented by the stick diagram b) Because of the error in the stick diagram, there will be an ambiguous Boolean state at the output for some combination of the input variables {A,B,C}. For what combinations of the input variables will the output become ambiguous?
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Problem 3 (12 pts) Determine the size of transistor M1 so that the output voltage is 3V.
OUT
1
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Problem 4 (16 pts) Assume the transistor M1 has dimensions W=30 and L=1 and the area of the diode is 4002. a) Determine the current IOUT b) Accurately determine the diode voltage
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Problem 5 (12 pts) Assume the emitter area of Q1 is 2002 but assume that there is considerable variability of the of the transistors in the process. a) b) c) Determine VOUT if of Q1 is 50 Repeat part a) if the emitter area of Q1 is increased to 4002. Repeat part a) if of Q1 is 100
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Problem 6 (16 pts) A driver buffer comprised of large transistors can be used to drive a large load. Assume you have a 64-bit wide data bus and have the need for a driver buffer that can drive all 64 bits. The circuit schematic of one of these buffers is shown. The length of the transistors M1 and M2 in each of these buffers is 1 but the width of the transistors is very wide with M1 having a width of 10,000 and with M2 having a width of 30,000. A driver chip is comprised of 64 of these buffers along with a bonding pad for each input and each output. Because of the large current flow, there will be a need for 10 bonding pads for VDD and 10 bonding pads for VSS as well.
DD
2 k 1 SS Determine the cost per good die if this buffer chip is fabricated in a process with 6 wafers that cost $800. Assume a defect density of 1.8/cm2. Clearly state any assumptions you make relating to how you determine the area of the die when you solve this problem. k
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TRANSISTOR PARAMETERS
MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K' (Uo*Cox/2) Low-field Mobility COMMENTS: XL_AMI_C5F 3.0/0.6
W/L
N-CHANNEL P-CHANNEL UNITS
0.78 -0.93 volts
20.0/0.6 439 0.69 10.0 20.0/0.6 < 2.5 50/50 0.70 11.4 <50.0 0.50 56.9 474.57 -0.95 -11.7 <50.0 0.58 -18.4 153.46 volts volts pA V^0.5 uA/V^2 cm^2/V*s < 2.5 pA/um -238 -0.90 -10.0 uA/um volts volts
FOX TRANSISTORS Vth
GATE Poly
N+ACTIVE >15.0
P+ACTIVE <-15.0
UNITS volts
PROCESS PARAMETERS N+ACTV P+ACTV POLY Sheet Resistance 82.7 103.2 21.7 Contact Resistance 56.2 118.4 14.6 Gate Oxide Thickness 144 PROCESS PARAMETERS Sheet Resistance Contact Resistance MTL3 0.05 0.78 N\PLY 824
PLY2_HR 984
POLY2 39.7 24.0
MTL1 0.09
MTL2 UNITS 0.09 ohms/sq 0.78 ohms angstrom
N_WELL 815
UNITS ohms/sq ohms
COMMENTS: N\POLY is N-well under polysilicon.
CAPACITANCE PARAMETERS N+ACTV P+ACTV Area (substrate) 429 721 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) 311 256 Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active)
POLY 82 2401 2308
POLY2
M1 32 36 61 53
M2 17 16 17 34
M3 10 12 9 13 32 39 28 32 48
N_WELL 40
864
74 53
58 40 55
206 278
UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um
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