330 EE Exam 2 Fall 2011
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _
Instructions: This is a 50-minute exam. Students may bring 2 page of notes (front and back) to this exam. There are 7 questions and 5 problems. The points allocated to each question are as indicated. The problems are all equally weighted and worth 16 points each if solved correctly. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; nCOX=100A/v2 pCOX=nCOX/3 ,VTNO=0.5V, VTPO= - 0.5V, COX=2fF/2, = 0, and If reference to a bipolar process is made, assume this process has key process parameters JS=10-15A/2, =100 and VAF = . The ratio of Boltzmann's constant to the charge of an electron is k/q= 8.61E-5 V/K. If any other process parameters are needed, use the process parameters associated with the process described on the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Also attached to this exam are two tables that have information about large and small signal models of devices and basic amplifier structures. 1. (2pts) The gate of transistors is "self-aligned" in most (probably in all) CMOS processes. What is the major significance of this self-alignment?
2. (2pts) In a standard bipolar process, MOS transistors are not available. Yet, there is a device that is available in a bipolar process that is also a square-law device with nearly 0 input current. What device is this? 3. (2pts) What does the term "unilateral" mean in terms of an amplifier modeled as a two-port network?
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4. (4pts) If a BJT is operating in the Forward Active region and it is observed that the emitter current is 5mA and the base current is 1mA, what is the "" for the transistor?
5. (2 pts) When comparing MOS and Bipolar voltage amplifiers that have the same basic architecture and the same current levels, the voltage gain of the Bipolar circuit is generally quite a bit larger than that of the corresponding MOS circuit. Why is that?
6. (2pts) terminal?
In the common gate amplifier, which terminal of the transistor is the input
7. (2pts) Why is the parasitic SCR that exists in an n-well CMOS processes a dreaded device that must not be used in the design of useful circuits ?
8. (2pts) TRIACs and SCRs often pass very large currents. Why does this large current not cause excessive heating that would destroy the device?
9. (2pts) How much will the threshold voltage of a MOS transistor designed in the ON 0.5 process change if the bulk to source voltage is -4V instead of 0V? (The attachment on this exam includes device model parameters for the ON 0.5 process.)
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Problem 1 Assume CC for the circuit shown is very large. a) Determine the quiescent drain current IDQ b) Draw a small-signal equivalent circuit. c) Determine the small signal output voltage Vout
5V 10K CC W=L=4 VIN=.002sin(2000t) 2.5V 10K VOUT
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Problem 2 For the circuit shown, assume M1 is operating in the saturation region and Q1 is operating in the Forward Active region. a) Determine RB so that the quiescent output voltage is 6V. b) Draw the small-signal equivalent circuit c) Determine the small-signal voltage gain in terms of the small-signal model parameters d) Numerically determine he small-signal voltage gain if VOUTQ=6V.
10V
W=1 RB
10K
VOUT
C L=4
M1 Q1
VIN
AE=1002 =100
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Problem 3 In the circuit shown, VIN is a small-signal input voltage and the temperature of the circuit is 300K. a) What value of VXX is needed so that the quiescent output voltage is 6V b) If VXX is increased by 1% from the value determined in part a), how much change in the quiescent output will occur c) How much change in the quiescent output voltage will occur from the value determined in part a) if the temperature is increased to 400K?
12V 1K VIN
Q1
VOUT
AE=1002 =100
VXX
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Problem 4 Assume the two capacitors are large and the nonlinear 3-terminal device is characterized by the equations
I1=10-4 V1 V -4 I2 = 1 + 0.002 V2 10
a) b) c) d) Determine the small-signal model of the nonlinear three-terminal device in terms of the Q-point I1Q and I2Q If the three-terminal device is modeled as a small-signal amplifier, determine the small-signal amplifier parameters in terms of the Q-point I1Q and I2Q Determine the Q-point currents I1Q and I2Q VOUT Determine the small-signal voltage gain A V = V IN
B
3
12V 833
I2
10K
I1
Vin
V1
Threeterminal Device
Vout
RL 833
V2
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Problem 5 Shown below is the cascade of two two-port networks and the parallel interconnection of two two-port networks. Each of these interconnections forms a twoport network. a) Give the input impedance RIN and the voltage gain AV of the two-port network formed by the cascade configuration in terms of the model parameters of the individual two-port networks. Assume AVRA=AVRB=0. b) Give the input impedance RIN and the voltage gain AV of the two-port network formed by the parallel configuration in terms of the model parameters of the individual two-port networks. Assume AVRA=AVRB=0.
I1 V1 I1A V1A
RINA ROUTA
I2A V2A
I1B V1B
RINB
ROUTB
I2B V2B
I2 V2
AVRAV2A
AVAV1A
Two Port (Thevenin)
AVRBV2B
AVBV1B
Two Port (Thevenin)
Cascade of two two-ports
I1A I1 V1 V1A
RINA
ROUTA
I2A V2A I2B V2B I2 V2
AVRAV2A
AVAV1A
Two Port (Thevenin)
I1B V1B
RINB
ROUTB
AVRBV2B
AVBV1B
Two Port (Thevenin)
Parallel Interconnection of two two-ports
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TRANSISTOR PARAMETERS
MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K' (Uo*Cox/2) Low-field Mobility COMMENTS: XL_AMI_C5F FOX TRANSISTORS Vth GATE Poly 3.0/0.6
W/L
0.78
N-CHANNEL P-CHANNEL UNITS
-0.93 -238 -0.90 -10.0 < 2.5 -0.95 -11.7 <50.0 0.58 -18.4 153.46 volts uA/um volts volts pA/um volts volts pA V^0.5 uA/V^2 cm^2/V*s
20.0/0.6 439 0.69 10.0 20.0/0.6 < 2.5 50/50 0.70 11.4 <50.0 0.50 56.9 474.57
N+ACTIVE >15.0
P+ACTIVE <-15.0
UNITS volts
PROCESS PARAMETERS N+ACTV P+ACTV POLY Sheet Resistance 82.7 103.2 21.7 Contact Resistance 56.2 118.4 14.6 Gate Oxide Thickness 144 PROCESS PARAMETERS Sheet Resistance Contact Resistance MTL3 0.05 0.78 N\PLY 824
PLY2_HR 984
POLY2 39.7 24.0
MTL1 0.09
MTL2 UNITS 0.09 ohms/sq 0.78 ohms angstrom
N_WELL 815
UNITS ohms/sq ohms
COMMENTS: N\POLY is N-well under polysilicon.
CAPACITANCE PARAMETERS N+ACTV P+ACTV Area (substrate) 429 721 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) 311 256 Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active)
POLY 82 2401 2308
POLY2
M1 32 36 61 53 74 53
M2 17 16 17 34 58 40 55
M3 10 12 9 13 32 39 28 32 48
N_WELL 40
864
206 278
UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um
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