330 EE Exam 3 Fall 2010
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _
Instructions: Students may bring 3 page of notes (front and back) to this exam. There are 8 questions and 8 problems. The points allocated to each question are as indicated. The problems are worth 16 points each. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; nCOX=100A/v2 ,pCOX=nCOX/3 ,VTNO=0.5V, VTPO= - 0.5V, COX=2fF/2, = 0, and = 0. If reference to a bipolar process is made, assume this process has key process parameters JS=10-15A/2, =100 and VAF = . If any other process parameters are needed, use the process parameters associated with the process described on the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Also attached to this exam are two tables. One relates to FI and OD for static CMOS logic gates and the other relates to the basic amplifier configurations. 1. (2pts) The cascode configuration is the cascade of two basic amplifier structures. In a bipolar process, what basic amplifier structure is the first stage of the cascode configuration? 2. (2pts) When building high-gain amplifiers, a cascade of individual stages such as the common-emitter configuration or the common-source configuration can provide a very high gain. Op amps are high gain amplifiers. Why are more than two stages seldom used to get a large gain when building op amps? 3. (2pts) Why are resistors seldom used when biasing linear MOS circuits?
4. (4pts) When implementing Boolean functions, a given function can be implemented with dominantly either NOR logic or NAND logic. If implemented in standard static CMOS, one of these is often preferred. Which is it and why? 5. (4pts) For many years, as the feature size and the supply voltages in semiconductor processes changed, the processes invariably had n-channel and p-channel threshold voltages that approximately satisfied the relationship VTn= -VTp=VDD/5 This relationship provided two particularly useful characteristics of logic gates. What were they?
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6. (4 pts) a) b)
Compare the speed (propagation delay) of the following two digital circuits A minimum-sized inverter driving an equal rise/fall inverter (the reference inverter) An equal rise/fall inverter (the reference inverter) driving a minimumsized inverter
7.(2pts) In a CMOS inverter, what are the static operating states (Cutoff, Saturation or Triode) of the MOS transistors?
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Problem 1 Design a voltage amplifier with a dc gain of 20 that can drive a 10K load. You can use any number of resistors, capacitors, and either MOS or bipolar transistors and up to two dc power supplies, both 10V. Your design should include any biasing that is needed.
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Problem 2 Assume you have a process with devices characterized by the model parameters nCOX=100A/v2 ,pCOX=nCOX/3 ,VTNO=2V, VTPO= - 1V, COX=2fF/2, = 0, and = 0. Analytically determine the trip of point a CMOS inverter designed in this process with device sizes Wn=Wp=1u and Ln=Lp=1u if it is biased with a supply voltage of VDD=5V.
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Problem 3 A reference inverter in a process is shown below. a) Give a schematic for and size a 3-input NOR gate for an OD of 5 b) Give a schematic for and size an inverter with ODHL=2, ODLH=1 c) Determine the trip point for the inverter in terms of ODHL and ODLH . Assume all devices are of length LMIN
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Problem 4 An input signal X to reference inverter is to drive one input of a 3-input NAND gate. The NAND gate is sized for equal worst case rise and fall times and has an OD of 300. a) Design a pad driver (shown in the block diagram below) that will drive the NAND gate as fast as possible (or nearly as fast as possible). b) Give device sizes for the devices in your pad driver. c) Determine the worst case propagation delay (tHL+tLH) for the propagation of the signal from X to Y if the process characterized by the reference inverter in Problem 3 is used for the design.
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Problem 5 A segment of a logic block is shown below. Unless specified to the contrary, assume the devices are sized for equal worst-case rise and fall times and that the overdrive factors, if different than 1, are as indicated by the numbers on the logic gates (if two numbers are given, the top one is ODHL and the lower is ODLH, and the letter M indicates devices are all minimum sized). Assume that in the process where these gates are fabricated is characterized by a reference inverter with characteristics 0.5u proc, tREF=20ps, CREF=4fF,RPDREF=2.5K a) As a signal is propagating from B to G, determine tHL at node D b) Determine the propagation delay from B to F
4
C A
M
4
G
F B
2
1/4 2
D
3
4fF
6fF
4
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TRANSISTOR PARAMETERS
MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K' (Uo*Cox/2) Low-field Mobility COMMENTS: XL_AMI_C5F 3.0/0.6
W/L
0.78
N-CHANNEL P-CHANNEL UNITS
-0.93 volts
20.0/0.6 439 0.69 10.0 20.0/0.6 < 2.5 50/50 0.70 11.4 <50.0 0.50 56.9 474.57 -0.95 -11.7 <50.0 0.58 -18.4 153.46 volts volts pA V^0.5 uA/V^2 cm^2/V*s < 2.5 pA/um -238 -0.90 -10.0 uA/um volts volts
FOX TRANSISTORS Vth
GATE Poly
N+ACTIVE >15.0
P+ACTIVE <-15.0
UNITS volts
PROCESS PARAMETERS N+ACTV P+ACTV POLY Sheet Resistance 82.7 103.2 21.7 Contact Resistance 56.2 118.4 14.6 Gate Oxide Thickness 144 PROCESS PARAMETERS Sheet Resistance Contact Resistance MTL3 0.05 0.78 N\PLY 824
PLY2_HR 984
POLY2 39.7 24.0
MTL1 0.09
MTL2 UNITS 0.09 ohms/sq 0.78 ohms angstrom
N_WELL 815
UNITS ohms/sq ohms
COMMENTS: N\POLY is N-well under polysilicon.
CAPACITANCE PARAMETERS N+ACTV P+ACTV Area (substrate) 429 721 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) 311 256 Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active)
POLY 82 2401 2308
POLY2
M1 32 36 61 53
M2 17 16 17 34
M3 10 12 9 13 32 39 28 32 48
N_WELL 40
864
74 53
58 40 55
206 278
UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um
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