330 EE Exam 3 Spring 2011
Name_ _ _ _ _ _ _ _ _ _ _ _ _ _
Instructions: This is a 50 minute exam. Students may bring 3 page of notes (front and back) to this exam. The points for the first eight questions are as indicated. The 5 problems are worth 16 points each. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; nCOX=100A/v2 pCOX=nCOX/3 ,VTNO=0.5V, VTPO= - 0.5V, COX=2fF/2, = 0, and If reference to a bipolar process is made, assume this process has key process parameters JS=10-15A/2, =100 and VAF = . If any other process parameters are needed, use the process parameters associated with the process described on the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Also attached to this exam is a table discussed in class that relates to the basic amplifier configurations.
1. (2pts) What is the major reason that CMOS technology has replaced NMOS or PMOS technology for manufacturing logic circuits?
2. (2pts) When building logic circuits with CMOS NAND and NOR gates, any logic function can be implemented with only NAND gates, with only NOR gates, or with a combination of NAND and NOR gates. There is often an advantage for using only NAND gates. What is this advantage?
3. (3pts) systems?
What are the 3 major hierarchical levels that are used in describing digital
4. (2pts) It was observed that to have equal rise and fall times in a CMOS inverter in the process we have been working with, it is necessary to have the width of the pchannel transistor about 3 times wider than the width of the n-channel transistor. What physical property is responsible for this increase in width requirements for the p-channel devices?
5. (2pts)
What does the term "ratio logic" refer to?
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6. (2 pts) There are many desirable characteristics of a logic family but one is more important than all of the rest. Which one is that?
7.(2pts)
What is a "current sink"?
8.(5pts) Determine the small-signal voltage gain for the following circuit. Assume ,model parameters given at the top of this exam except for and VAF which are , = .01V-1 and VAF=200V. Assume VXX is chosen so that the quiescent output voltage is 2.5V.
5V W=20u L=4u
2.5V
Vout Vin
AE=100u2 VXX
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Problem 1 Design a current source that provides a sinking current of 5mA. The current source is to have ideally an infinite output impedance. You have available one DC voltage source, any number of resistors and capacitors, and any number of either MOS or BJT transistors. The characteristics of the MOS and BJTs are included in the directions section of this exam. Be sure to include device sizes and component values for all devices and label the output current node on your design.
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Problem 2 Assume the bipolar transistors have been biased to operate in the Forward Active region and the MOS transistors have been biased to operate in the Saturation region. Determine the small signal voltage gain in terms of the small-signal model parameters the of devices. Assume the capacitors are large. .
VDD
RB1 C1
M2
RD3 M3
RE4
Vout
Q4 C2 RL
Q1
Vin
RS3
-VSS
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Problem 3 A number of years ago National Semiconductor published an Application Note suggesting that the basic digital CMOS inverter could be used as an operational amplifier in some applications. An application of the CMOS inverter as an operational amplifier is shown below along with the same application using a conventional operational amplifier. Assuming the devices M1 and M2 have model parameters specified at the top of this exam except for the parameter which is .01V-1 for both transistors. Assume that the device dimensions are W1=5u, W2=15u, L1=1u, and L2=1u and the resistors are very large,. Determine the small-signal voltage gain of the two-transistor amplifier based upon the CMOS inverter. (It can be shown that the quiescent values of the input and output voltages, VA and VB, of the two-transistor amplifier in this application are both 0V. You may assume this is true).
R2
Vin
R1
VOUT
R2
2.5V
Vin
R1
VA
M2 VB M1 -2.5V
VOUT
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(continue solution for Problem 3 here if additional space is needed)
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Problem 4
A three-input CMOS NAND gate is shown.
a) Determine the high and low logic levels for this gate b) Assume the length of the all devices is 1u and the widths of the n-channel devices are also 1u. Determine the widths of the p-channel devices so that the gate has equal worst-case rise and fall times. c) What is the input capacitance seen at the A input?
3.5V
C
M6
B
M5
A
M4
F C
M3
B
M2
A
M1
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Problem 5 A static CMOS inverter with Wn=Wp=1000u and Ln=Lp=1u was designed in a 0.5u CMOS process and is driving a 1pF load. Determine tHL and tLH for the output of this inverter. Assume the input rise and fall times to this inverter are arbitrarily fast and that the supply voltage is 5V.
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TRANSISTOR PARAMETERS
MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K' (Uo*Cox/2) Low-field Mobility COMMENTS: XL_AMI_C5F FOX TRANSISTORS Vth GATE Poly 3.0/0.6
W/L
0.78
N-CHANNEL P-CHANNEL UNITS
-0.93 -238 -0.90 -10.0 < 2.5 -0.95 -11.7 <50.0 0.58 -18.4 153.46 volts uA/um volts volts pA/um volts volts pA V^0.5 uA/V^2 cm^2/V*s
20.0/0.6 439 0.69 10.0 20.0/0.6 < 2.5 50/50 0.70 11.4 <50.0 0.50 56.9 474.57
N+ACTIVE >15.0
P+ACTIVE <-15.0
UNITS volts
PROCESS PARAMETERS N+ACTV P+ACTV POLY Sheet Resistance 82.7 103.2 21.7 Contact Resistance 56.2 118.4 14.6 Gate Oxide Thickness 144 PROCESS PARAMETERS Sheet Resistance Contact Resistance MTL3 0.05 0.78 N\PLY 824
PLY2_HR 984
POLY2 39.7 24.0
MTL1 0.09
MTL2 UNITS 0.09 ohms/sq 0.78 ohms angstrom
N_WELL 815
UNITS ohms/sq ohms
COMMENTS: N\POLY is N-well under polysilicon.
CAPACITANCE PARAMETERS N+ACTV P+ACTV Area (substrate) 429 721 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) 311 256 Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active)
POLY 82 2401 2308
POLY2
M1 32 36 61 53 74 53
M2 17 16 17 34 58 40 55
M3 10 12 9 13 32 39 28 32 48
N_WELL 40
864
206 278
UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um
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