# Register now to access 7 million high quality study materials (What's Course Hero?) Course Hero is the premier provider of high quality online educational resources. With millions of study documents, online tutors, digital flashcards and free courseware, Course Hero is helping students learn more efficiently and effectively. Whether you're interested in exploring new subjects or mastering key topics for your next exam, Course Hero has the tools you need to achieve your goals.

11 Pages

### EE 330 Exam 3 Spring 2011

Course: EE 330, Fall 2011
School: Iowa State
Rating:

Word Count: 1070

#### Document Preview

330 EE Exam 3 Spring 2011 Name_ _ _ _ _ _ _ _ _ _ _ _ _ _ Instructions: This is a 50 minute exam. Students may bring 3 page of notes (front and back) to this exam. The points for the first eight questions are as indicated. The 5 problems are worth 16 points each. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If...

Register Now

#### Unformatted Document Excerpt

Coursehero >> Iowa >> Iowa State >> EE 330

Course Hero has millions of student submitted documents similar to the one
below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.

Course Hero has millions of student submitted documents similar to the one below including study guides, practice problems, reference materials, practice exams, textbook help and tutor support.
330 EE Exam 3 Spring 2011 Name_ _ _ _ _ _ _ _ _ _ _ _ _ _ Instructions: This is a 50 minute exam. Students may bring 3 page of notes (front and back) to this exam. The points for the first eight questions are as indicated. The 5 problems are worth 16 points each. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; nCOX=100A/v2 pCOX=nCOX/3 ,VTNO=0.5V, VTPO= - 0.5V, COX=2fF/2, = 0, and If reference to a bipolar process is made, assume this process has key process parameters JS=10-15A/2, =100 and VAF = . If any other process parameters are needed, use the process parameters associated with the process described on the attachments to this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Also attached to this exam is a table discussed in class that relates to the basic amplifier configurations. 1. (2pts) What is the major reason that CMOS technology has replaced NMOS or PMOS technology for manufacturing logic circuits? 2. (2pts) When building logic circuits with CMOS NAND and NOR gates, any logic function can be implemented with only NAND gates, with only NOR gates, or with a combination of NAND and NOR gates. There is often an advantage for using only NAND gates. What is this advantage? 3. (3pts) systems? What are the 3 major hierarchical levels that are used in describing digital 4. (2pts) It was observed that to have equal rise and fall times in a CMOS inverter in the process we have been working with, it is necessary to have the width of the pchannel transistor about 3 times wider than the width of the n-channel transistor. What physical property is responsible for this increase in width requirements for the p-channel devices? 5. (2pts) What does the term "ratio logic" refer to? Page 1 of 11 6. (2 pts) There are many desirable characteristics of a logic family but one is more important than all of the rest. Which one is that? 7.(2pts) What is a "current sink"? 8.(5pts) Determine the small-signal voltage gain for the following circuit. Assume ,model parameters given at the top of this exam except for and VAF which are , = .01V-1 and VAF=200V. Assume VXX is chosen so that the quiescent output voltage is 2.5V. 5V W=20u L=4u 2.5V Vout Vin AE=100u2 VXX Page 2 of 11 Problem 1 Design a current source that provides a sinking current of 5mA. The current source is to have ideally an infinite output impedance. You have available one DC voltage source, any number of resistors and capacitors, and any number of either MOS or BJT transistors. The characteristics of the MOS and BJTs are included in the directions section of this exam. Be sure to include device sizes and component values for all devices and label the output current node on your design. Page 3 of 11 Problem 2 Assume the bipolar transistors have been biased to operate in the Forward Active region and the MOS transistors have been biased to operate in the Saturation region. Determine the small signal voltage gain in terms of the small-signal model parameters the of devices. Assume the capacitors are large. . VDD RB1 C1 M2 RD3 M3 RE4 Vout Q4 C2 RL Q1 Vin RS3 -VSS Page 4 of 11 Problem 3 A number of years ago National Semiconductor published an Application Note suggesting that the basic digital CMOS inverter could be used as an operational amplifier in some applications. An application of the CMOS inverter as an operational amplifier is shown below along with the same application using a conventional operational amplifier. Assuming the devices M1 and M2 have model parameters specified at the top of this exam except for the parameter which is .01V-1 for both transistors. Assume that the device dimensions are W1=5u, W2=15u, L1=1u, and L2=1u and the resistors are very large,. Determine the small-signal voltage gain of the two-transistor amplifier based upon the CMOS inverter. (It can be shown that the quiescent values of the input and output voltages, VA and VB, of the two-transistor amplifier in this application are both 0V. You may assume this is true). R2 Vin R1 VOUT R2 2.5V Vin R1 VA M2 VB M1 -2.5V VOUT Page 5 of 11 (continue solution for Problem 3 here if additional space is needed) Page 6 of 11 Problem 4 A three-input CMOS NAND gate is shown. a) Determine the high and low logic levels for this gate b) Assume the length of the all devices is 1u and the widths of the n-channel devices are also 1u. Determine the widths of the p-channel devices so that the gate has equal worst-case rise and fall times. c) What is the input capacitance seen at the A input? 3.5V C M6 B M5 A M4 F C M3 B M2 A M1 Page 7 of 11 Problem 5 A static CMOS inverter with Wn=Wp=1000u and Ln=Lp=1u was designed in a 0.5u CMOS process and is driving a 1pF load. Determine tHL and tLH for the output of this inverter. Assume the input rise and fall times to this inverter are arbitrarily fast and that the supply voltage is 5V. Page 8 of 11 TRANSISTOR PARAMETERS MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K' (Uo*Cox/2) Low-field Mobility COMMENTS: XL_AMI_C5F FOX TRANSISTORS Vth GATE Poly 3.0/0.6 W/L 0.78 N-CHANNEL P-CHANNEL UNITS -0.93 -238 -0.90 -10.0 < 2.5 -0.95 -11.7 <50.0 0.58 -18.4 153.46 volts uA/um volts volts pA/um volts volts pA V^0.5 uA/V^2 cm^2/V*s 20.0/0.6 439 0.69 10.0 20.0/0.6 < 2.5 50/50 0.70 11.4 <50.0 0.50 56.9 474.57 N+ACTIVE >15.0 P+ACTIVE <-15.0 UNITS volts PROCESS PARAMETERS N+ACTV P+ACTV POLY Sheet Resistance 82.7 103.2 21.7 Contact Resistance 56.2 118.4 14.6 Gate Oxide Thickness 144 PROCESS PARAMETERS Sheet Resistance Contact Resistance MTL3 0.05 0.78 N\PLY 824 PLY2_HR 984 POLY2 39.7 24.0 MTL1 0.09 MTL2 UNITS 0.09 ohms/sq 0.78 ohms angstrom N_WELL 815 UNITS ohms/sq ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV Area (substrate) 429 721 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) 311 256 Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active) POLY 82 2401 2308 POLY2 M1 32 36 61 53 74 53 M2 17 16 17 34 58 40 55 M3 10 12 9 13 32 39 28 32 48 N_WELL 40 864 206 278 UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um Page 9 of 11 Page 10 of 11 Page 11 of 11
Find millions of documents on Course Hero - Study Guides, Lecture Notes, Reference Materials, Practice Exams and more. Course Hero has millions of course specific materials providing students with the best way to expand their education.

Below is a small sample set of documents:

Iowa State - EE - 330
EE 330 Final Exam Fall 2008Name_ _ _ _ _ _ _ _ _ _ _ _ _ _Instructions. Students may bring 2 page of notes (front and back) to this exam. There are 10 questions and 8 problems. There are 2 points allocated to each question and 10 points allocated to eac
Iowa State - EE - 330
EE 330 Final Exam Fall 2009Name_ _ _ _ _ _ _ _ _ _ _ _ _ _Instructions. Students may bring 3 pages of notes (3 front + 3 back) to this exam. There are 8 questions and 8 problems. The points allocated to each question are as indicated. The problems are a
Iowa State - EE - 330
EE 330 Final Exam Fall 2010Name_ _ _ _ _ _ _ _ _ _ _ _ _ _Instructions. Students may bring 3 pages of notes (3 front + 3 back) to this exam. There are 8 questions and 8 problems. The points allocated to each question are as indicated. The problems are a
Iowa State - EE - 330
EE 330 Final Exam Spring 2011Name_ _ _ _ _ _ _ _ _ _ _ _ _ _Instructions. Students may bring 3 pages of notes (3 front + 3 back) to this exam. There are 9 questions and 8 problems. The points allocated to each question are as indicated. The problems are
Iowa State - EE - 330
Jan 17 is a University Holiday No lecture given on this date
Iowa State - EE - 330
HW1Problem 1 Assume a simple circuit requires 10,000 MOS transistors on a die and that all transistors are minimum sized. If the transistors are fabricated in a 32nm CMOS process and the spacing overhead for the transistors is a factor of 10, determine t
Iowa State - EE - 330
EE 330 Homework 1 Spring 2012 Due Friday Jan 13 Problem 1 Assume a simple circuit requires 10,000 MOS transistors on a die and that all transistors are minimum sized. If the transistors are fabricated in a 32nm CMOS process and the spacing overhead for th
Iowa State - EE - 330
HW2 solutionProblem 1. Extrapolating the data from Figure 1.4, predict the transistor count of a microprocessor in 2016. Solution 6 to 12 billion Problem 2. Sketch a transistor-level schematic for CMOS 4-input NOR gate. SolutionABCD YABCDProblem
Iowa State - EE - 330
EE 330 Homework Assignment 3 Spring 2012Problem 1 Problem 1.6 of WH parts b) and c). Modify this problem to design of these functions using both the compound gate approach and the static CMOS gate approach. Compare the number of levels of logic and the t
Iowa State - EE - 330
EE 330 Homework Assignment 4 Spring 2012 (Due Friday Feb 3)Problem 1 Problem 2 Problem 3 Problem 4 Problem 53.1 of Weste and Harris (WH) 3.2 of WH 3.5 of WH 3.7 of WH A first-order RC filter is shown. The 3dB band edge of this filter is given 1 by 3dB .
Iowa State - EE - 330
EE 330 Fall 2010 Lab 1: Cadence Custom IC design tools - Setup, Schematic capture and simulationObjectiveThe objective of this lab is to familiarize you with the basics of the Cadence Custom IC design tool, Virtuoso. You will first set up your account t
Iowa State - EE - 330
EE 330 Spring 2011 Laboratory 2: Basic Boolean CircuitsObjective:The objective of this experiment is to investigate methods for evaluating the performance of Boolean circuits. Emphasis will be placed on the basic CMOS inverter but the concepts are appli
Iowa State - EE - 330
EE 330 Laboratory 3 Layout and LVS (Layout Versus Schematic)Fall 2011 Objective: The objective of this experiment is introduce the concept of layout of circuits. In this context, design rules and CAD tools used for verifying that all design rules are sat
Iowa State - EE - 330
EE 330 Section: _Name: _Pre-Lab for Lab 4: From Boolean Function to Silicon1) Draw the layout for your inverter and the other gate you chose (3-input NAND or NOR) 2) Attach the hand-drawn gate level implementation of the assigned Boolean function that
Iowa State - EE - 330
EE 330 Laboratory 4 From Boolean equation to SiliconFall 2010Objective:The objective of this experiment is to implement a Boolean function description in silicon, given area and pin constraints. A second object is to introduce the concept of parameteri
Iowa State - EE - 330
EE 330 Laboratory 5 Creating bonding padsSpring 2011Objective: The objective of this experiment is investigate the design of a basic bonding pad andsimple ESD protection circuitry.Part 1: Layout of a resistorThe first step of this lab is to learn how
Iowa State - EE - 330
EE 330 Laboratory 6 Models for MOS DevicesSpring 2011Part 1: IntroductionThe mathematical relationship between the terminal currents and voltages for a device is termed the device model. Although the basic operation of the MOS transistor is quite strai
Iowa State - EE - 330
EE 330 Laboraory 7 MOSFET Device Characterization and ApplicationsFall 2010 Objective: The objective of this laboratory experiment is to become more familiar with the operation of the MOS transistor, to develop methods for measuring key parameters of the
Iowa State - EE - 330
EE 330 Laboraory 8 Thyristor Device Characterization and ApplicationsFall 2011Objective: The objective of this laboratory experiment is to become familiar with the operation thyristors, to develop methods for measuring key parameters of thyristors, , an
Iowa State - EE - 330
EE 330 Laboratory 9 Semiconductor Parameter Measurement and Thyristor ApplicationsSpring 2011Objective: The objective of this laboratory experiment is to become familiar with using a semiconductor parameter analyzer for extracting model parameters for d
Iowa State - EE - 330
EE 330 Laboratory 10 Bipolar Devices and ApplicationsFall 2010Objective:The objective of this laboratory is to investigate applications of BJTsDiscussion:Although the major emphasis in this course has been on integrated devices, discrete transistors
Iowa State - EE - 330
EE 330 Laboratory Experiment Number 11 Design, Simulation and Layout of Digital Circuits using Hardware Description LanguagesPurpose: The purpose of this experiment is to develop methods for using HardwareDescription Languages for the design of digital
Iowa State - EE - 330
EE 330 Fall 2011Integrated ElectronicsLecture Instructor: Randy Geiger 2133 Coover rlgeiger@iastate.edu 294-7745Lab Instructors: Rui Bai Yongjie Jiang Curtis Mayberry Srijita Patra Brian Modtland bairui@iastate.edu yjjiang@iastate.edu curtisma@iastate.
Iowa State - EE - 330
EE 330 Fall 2009Integrated ElectronicsLecture Instructor: Randy Geiger 2133 Coover rlgeiger@iastate.edu 294-7745 Sheng-Huang (Alex) Lee and Dan Congreve http:/class.ece.iastate.edu/ee330/ 1012 CooverLab Instructors: Web Site: Lecture: MWF 9:00 Lab: Sec
Iowa State - EE - 330
EE 330 Lecture 2Basic ConceptsReview from Last TimeChallenges Managing increasing device count Short lead time from conception to marketplace Process technology advances Device Performance Degradation Increasing variability Increasing pressure for cos
Iowa State - EE - 330
EE 330 Lecture 2Basic ConceptsQuiz 1The International Technology Roadmap for Semiconductors (ITRS) makes predictions on challenges and trends in the semiconductor industry. What is the ITRS projecting for the supply voltage of digital ICs in 10 years?
Iowa State - EE - 330
EE 330 Lecture 3Basic ConceptsHistorical Background, Feature Sizes and YieldReview from Last Time Sophisticated Integrated CAD Toolsets are extensively used in the industry to design integrated circuits Minimize the chances of an error Real asset to
Iowa State - EE - 330
EE 330 Lecture 3Basic ConceptsHistorical Background, Feature Sizes and YieldQuiz 2How many minimum-sized MOS transistors can be placed on a square die that is 1000 on a side in a 65nm process? (Neglect any bonding pads needed to get the signals to the
Iowa State - EE - 330
EE 330 Lecture 4Statistical ConceptsHistorical Background, Feature Sizes and Yield Digital Systems A previewReview from Last TimeDefects in a WaferDefect Dust particles and other undesirable processes cause defects Defects in manufacturing cause yie
Iowa State - EE - 330
EE 330 Lecture 4Statistical ConceptsHistorical Background, Feature Sizes and Yield Digital Systems A previewQuiz 3The defect density is often considered as proprietary information. Assume, however, that a process engineer had a lapse of thought and di
Iowa State - EE - 330
EE 330 Lecture 5Digital Systems A previewStatic CMOS Gates Other Logic Styles Improved Device ModelsReview from Last TimeStatistics ReviewfN fx N , y N 0,1x y 0 1+x f x dx 1yxy fN y dy 1If the random variable x in Normally distributed wi
Iowa State - EE - 330
EE 330 Lecture 5Digital Systems A previewStatic CMOS Gates Other Logic Styles Improved Device ModelsQuiz 4Determine VH and VL at the C output for the Static CMOS NOR gate shown. Use the switch-level model for the transistors introduced in the last lec
Iowa State - EE - 330
EE 330 Lecture 6Improved Device Models Stick Diagrams Technology FilesReview from Last TimeMOS TransistorQualitative Discussion of n-channel OperationSource Bulk Gate DrainDrainGaten-channel MOSFETSourceEquivalent Circuit for n-channel MOSFETD
Iowa State - EE - 330
EE 330 Lecture 6Improved Device Models Stick Diagrams Technology FilesQuiz 5Design, using the Complex Logic Gates approach, a logic circuit that implements the Boolean function Y=AB+C Assume the input variables available are A, B, and C. How many trans
Iowa State - EE - 330
EE 330 Lecture 7Delay Calculations Stick Diagrams Technology Files - Design RulesReview from Last TimeMOS TransistorQualitative Discussion of n-channel OperationSource Bulk Insulator Gate DrainDrainFor VGS smalln-channel MOSFETGateBulkSourceSo
Iowa State - EE - 330
EE 330 Lecture 7Technology Files - Design RulesQuiz 6Determine the LH propagation time if a minimum-sized CMOS inverter is driving a capacitive load of 200pF. Use typical values for modeling the CMOS inverter but state what values you use.AY 100pfAn
Iowa State - EE - 330
EE 330 Lecture 8IC Fabrication Technology Part 1Review from Last TimeTechnology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules Serve as Interface Between Design Engineer and Process Engine
Iowa State - EE - 330
EE 330 Lecture 8IC Fabrication Technology Part 1Quiz 7The layout of the cascade of two CMOS inverters is shown. It has some layout errors. Identify them.And the number is .183546972And the number is .1749638542Quiz 7 Solution:- B
Iowa State - EE - 330
EE 330 Lecture 9IC Fabrication Technology Part 2Review from Last TimeTechnology Files Design Rules Process Flow (Fabrication Technology) Model Parameters (will discuss in substantially moredetail after device operation and more advanced models are i
Iowa State - EE - 330
EE 330 Lecture 9IC Fabrication Technology Part 2Quiz 8A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this 2m crystal provide? In solving this problem you ma
Iowa State - EE - 330
EE 330 Lecture 10IC Fabrication Technology Part IIIEpitaxy Polysilicon Interconnects Back-end ProcessesReview from Last TimeIC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Implantation Etching Diffusion Oxid
Iowa State - EE - 330
EE 330 Lecture 10IC Fabrication Technology Part III- Interconnects - Back-end ProcessesQuiz 9What is the major reason shallow trench isolation (STI) is used instead of Local Oxidation to create the field oxide in a MOS process?Silicon Nitride Etched
Iowa State - EE - 330
EE 330 Lecture 11IC Fabrication Technology Part IV- Back-end ProcessesDevices in Semiconductor ProcessesReview from Last Time Contacts usually of a fixed size All etches reach bottom at about the same time Multiple contacts widely used Contacts not
Iowa State - EE - 330
EE 330 Lecture 11IC Fabrication Technology Part IV- Back-end ProcessesDevices in Semiconductor ProcessesQuiz 10What is the major reason contacts of metal to poly are not allowed in the gate region of a transistor?AA'Unacceptable ContactAnd the nu
Iowa State - EE - 330
EE 330 Lecture 12Devices in Semiconductor ProcessesReview from Last TimeBack-End Process FlowWafer Probe Wafer Dicing Die AttachWire Attach (bonding)PackageTestShipReview from Last TimeWafer Dicingwww.renishaw.comReview from Last TimeDie Atta
Iowa State - EE - 330
EE 330 Lecture 12Devices in Semiconductor ProcessesQuiz 11A wire obtained with a ball bond is shown sitting on a bonding pad. What is a typical value for the dimension d1 shown?d1=?And the number is .183546972And the number is .174963
Iowa State - EE - 330
EE 330 Lecture 13Devices in Semiconductor ProcessesDiodes Capacitors MOS TransistorsBasic Devices Standard CMOS Process MOS Transistors n-channel p-channel Primary Consideration in This Course Capacitors Resistors Diodes BJT (in some processes) n
Iowa State - EE - 330
EE 330 Lecture 13Devices in Semiconductor ProcessesQuiz 11Consider a p-n junction comprised of uniformly doped p-type and n-type materials where the doping density of the p-type material is 5 times that of the n-type material. If under zero bias the de
Iowa State - EE - 330
EE 330 Lecture 14Devices in Semiconductor ProcessesMOS TransistorsReview from Last Time Lets study the diode equation a little further Vd Vt d S I I e 1 Diode Characteristics10000 100 1 0.01 0.0001 1E-06 1E-08 1E-10 1E-12 0 0.2 0.4 0.6 0.8 1 Vd (v
Iowa State - EE - 330
EE 330 Lecture 14Devices in Semiconductor ProcessesDiodes Capacitors MOS TransistorsReview from Last TimeReview from Last Timehttp:/www.oftc.usyd.edu.au/edweb/devices/semicdev/doping4.htmlReview from Last TimeReview from Last TimeReview from Last
Iowa State - EE - 330
EE 330 Lecture 15Devices in Semiconductor Processesthe MOS TransistorReview from Last Timen-Channel MOSFETGate Source L DrainWLEFFBulkReview from Last Timen-Channel MOSFET Operation and ModelVDS VGS VBSID IGIBApply small VGS (VDS and VBS ass
Iowa State - EE - 330
EE 330 Lecture 15Devices in Semiconductor Processesthe MOS TransistorReview from Last TimeFringe CapacitorsCdA C dA is the area where the two plates are parallelOnly a single layer is needed to make fringe capacitorsReview from Last TimeCapacit
Iowa State - EE - 330
EE 330 Lecture 16MOS Device Modelingp-channel . n-channel comparisons Model consistency and relationshipsCMOS Process FlowReview from Last TimeOperation Regions by Applications300 250 200 150 100 50 0 0 1 2 Vds 3 4 5IDTriode Region Saturation Reg
Iowa State - EE - 330
EE 330 Lecture 16MOS Transistor Models CMOS Process FlowReview from Last TimeGraphical Interpretation of MOS Model 0 V W I C V V V L 2 W V V C 2LDS D OX GS T 2 OX GS TV VGS GSTDSV VTV V VDS GSTV VGSTV V VDS GSTReview from Last TimeMo
Iowa State - EE - 330
EE 330 Lecture 17CMOS Process Flow Characteristics of Finer Feature Size ProcessesBipolar ProcessReview from Last TimeOperation Regions by Applications300250IDTriode Region Saturation RegionAnalog Circuits200Id150 100 50 0 0 1 2Cutoff Region
Iowa State - EE - 330
EE 330 Lecture 18Characteristics of Finer Feature Size Processes Bipolar ProcessHow does the inverter delay compare between a 0.5u process and a 0.13u process?VDDVINVOUTVINVOUTVSSHow does the inverter delay compare between a 0.5u process and a 0.
Iowa State - EE - 330
EE 330 Lecture 19Bipolar Device Modeling Bipolar ProcessReview from Last LectureBasic Devices and Device Models Resistor Diode Capacitor MOSFET BJTReview from Last LectureBipolar Junction TransistorsOperation and ModelingReview from Last LectureB
Iowa State - EE - 330
EE 330 Lecture 19Characteristics of Finer Feature Size Processes Bipolar ProcessBasic Devices and Device Models Resistor Diode Capacitor MOSFET BJTBipolar Junction Transistors Operation ModelingCarriers in Doped Semiconductorsn-typep-typeCarriers
Iowa State - EE - 330
EE 330 Lecture 20Bipolar ProcessesBipolar Devices BJT JFET Thyristors SCR TRIACReview from Last LectureSimple dc modelTypical Output CharacteristicsSaturation300 250 200 150 100 50 0 0 1 2 Vds 3 4 5ICForward ActiveVBE or IBIdVCECutoffForward
Iowa State - EE - 330
EE 330 Lecture 20Bipolar Device Modeling Bipolar ProcessReview from Last LectureBasic Devices and Device Models Resistor Diode Capacitor MOSFET BJTReview from Last LectureBipolar Junction TransistorsOperation and ModelingReview from Last LectureB
Iowa State - EE - 330
EE 330 Lecture 21Bipolar Devices ThyristorsSCRs TriacsReview from Last LectureC B EE C vertical npn B ECB B E A-A' Section C B E lateral pnp ECBCB-B' SectionReview from Last LectureD A-A' Section D S GG Sp-channel JFETB-B' SectionReview f