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### EE 330 Final Exam Spring 2011

Course: EE 330, Fall 2011
School: Iowa State
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Word Count: 1134

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330 EE Final Exam Spring 2011 Name_ _ _ _ _ _ _ _ _ _ _ _ _ _ Instructions. Students may bring 3 pages of notes (3 front + 3 back) to this exam. There are 9 questions and 8 problems. The points allocated to each question are as indicated. The problems are all worth 10 points. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific...

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330 EE Final Exam Spring 2011 Name_ _ _ _ _ _ _ _ _ _ _ _ _ _ Instructions. Students may bring 3 pages of notes (3 front + 3 back) to this exam. There are 9 questions and 8 problems. The points allocated to each question are as indicated. The problems are all worth 10 points. Please solve problems in the space provided on this exam and attach extra sheets only if you run out of space in solving a specific problem. If references semiconductor processes are needed beyond what is given in a specific problem or question, assume a CMOS process is available with the following key process parameters; nCOX=100A/v2 pCOX=nCOX/3 ,VTNO=0.5V, VTPO= - 0.5V, COX=2fF/2, = 0, and If reference to a bipolar process is made, assume this process has key process parameters for an npn transistor are JS=10-15A/2, n=100 and VAFn = and those for a pnp transistor are JS=10-15A/2, p=20 and VAFp = . If any other process parameters are needed, use the process parameters associated with the process described on the last page of this exam. Specify clearly what process parameters you are using in any solution requiring process parameters. Several tables that may be of use are appended at the end of the exam. 1. (2 pts) There are two types of photoresist. What are they? Briefly describe how they differ. 2. (2 pts) In the context of electronic devices, what property does the term "unilateral" characterize? 3. (2 pts) What is the purpose of planarization steps in a semiconductor process? 4. (2pts) Why are design rules typically given in terms of multiples of a parameter () rather than given directly in standard units such as microns? Page 1 of 15 5. (2pts) Explain what changes occur in the depletion region of a pn junction between reverse bias and forward bias. 6. (2pts) Why is the "Six-Sigma" metric not useful for performance standards in the design and fabrication of integrated circuits? 7. (2 pts) Which two of the six basic amplifier configurations are noted for having a large noninverting voltage gain? 8. (2 pts) If static CMOS logic gates are built with all minimum-sized devices, the propagation times can get quite long. But there are actually some significant advantages of using a minimum-sizing strategy as well. One is obviously a reduction in area and a second is convenience of sizing. What is a third major advantage? 9. (4 pts) The gate to source voltage of an n-channel transistor in the ON 0.5u process was measured to be 3V and the small signal transconductance parameter was measured to be .001A/V. Determine the dimensions of the transistor. Page 2 of 15 Problem 1 Determine the output voltage for the following circuit. 5V 50K 10K VO=? M1 W1=2u L1=1u M2 W2=4u L2=1u Page 3 of 15 Problem 2 Consider the following circuit where the capacitor is very large. a) Determine the quiescent output voltage b) Derive the small-signal voltage gain. 21V 20K 0.75K VOUT C AE=100u2 VIN(t) 10K 0.5K Page 4 of 15 Problem 3 A segment of a logic block is shown below. Assume the lengths of all devices are LMIN. Assume all gates are sized for equal worst-case rise and fall times and gates with an overdrive factors that is different than 1 are as indicated by the number on the gate. Assume that the process where these gates are fabricated is characterized by a minimum length reference inverter with tREF=20ps, CREF=4fF, RPDREF=2.5K a) b) Determine the propagation delay from B to F Repeat part a) if the 2-input NAND gate in the path from B to F is minimum sized. A B 2 C D F 4 4fF 10fF 4 Page 5 of 15 Problem 4 Assume a 12" wafer costs \$2500 and has a defect density of 2 1.25/cm .This wafer is used to create circuits with a die area of 0.4cm2. a) Determine the hard yield for these die b) If the soft yield of these die is 60%, determine the manufacturing cost per good die Page 6 of 15 Problem 5 In the following circuit assume the diodes are ideal. Determine the currents I1 and I2. 10K 10K 4V 10K -6V I1=? 10K 10K 4V 10K 10V I2=? Page 7 of 15 Problem 6 Assume all MOS devices in the following circuit are operating in the saturation region and all bipolar devices are operating in the forward active region. a) Draw the small-signal equivalent circuit b) Determine the voltage gain from the input to the output in terms of the smallsignal model parameters and the resistor values in the circuit VDD M1 RC Q3 RB1 RD Vin M2 Vout C M4 2 RL C1 RB2 I1 -VSS Page 8 of 15 Problem 7 A polysilicon region formed on thick oxide in the ON 0.5u CMOS process (description of process attached) is shown below. The width of the polysilicon is 1u. a) b) Determine the resistance between nodes A and B Determine the capacitance from the polysilicon to the substrate. A 2u B 2u 2u 11u 2u 10u Page 9 of 15 Problem 8 port equations A four-terminal device is shown below. It is characterized by the I1 V12V2 2 I2 V1V3 I3 V3 2V1e 2 a) Determine the small-signal model for the device in terms of the quiescent port voltages b) Determine the small-signal model at the operating point defined by V1Q=4V, V2Q=2.5V, and V3Q=1V c) Determine I1Q at the operating point given in part b) d) Determine the small signal current i2 if the small-signal port voltages are v1=1mVRMS, v2=2mVRMS and v3=3mVRMS I1 4-Terminal Device I2 I3 V1 V2 V3 Page 10 of 15 Problem 9 (Extra Credit 10 points) Design a Voltage Amplifier with a small signal gain of +80 that can drive a 1K load. You have any number of MOS transistors, resistors, capacitors, and two dc power supplies of 10V available. Include all biasing circuitry needed for the design. Page 11 of 15 TRANSISTOR PARAMETERS MINIMUM Vth SHORT Idss Vth Vpt WIDE Ids0 LARGE Vth Vjbkd Ijlk Gamma K' (Uo*Cox/2) Low-field Mobility COMMENTS: XL_AMI_C5F FOX TRANSISTORS Vth GATE Poly 3.0/0.6 W/L N-CHANNEL P-CHANNEL UNITS 0.78 -0.93 -238 -0.90 -10.0 < 2.5 -0.95 -11.7 <50.0 0.58 -18.4 153.46 volts uA/um volts volts pA/um volts volts pA V^0.5 uA/V^2 cm^2/V*s 20.0/0.6 439 0.69 10.0 20.0/0.6 < 2.5 50/50 0.70 11.4 <50.0 0.50 56.9 474.57 N+ACTIVE >15.0 P+ACTIVE <-15.0 UNITS volts PROCESS PARAMETERS N+ACTV P+ACTV POLY Sheet Resistance 82.7 103.2 21.7 Contact Resistance 56.2 118.4 14.6 Gate Oxide Thickness 144 PROCESS PARAMETERS Sheet Resistance Contact Resistance MTL3 0.05 0.78 N\PLY 824 PLY2_HR 984 POLY2 39.7 24.0 MTL1 0.09 MTL2 UNITS 0.09 ohms/sq 0.78 ohms angstrom N_WELL 815 UNITS ohms/sq ohms COMMENTS: N\POLY is N-well under polysilicon. CAPACITANCE PARAMETERS N+ACTV P+ACTV Area (substrate) 429 721 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metal1) Area (metal2) Fringe (substrate) 311 256 Fringe (poly) Fringe (metal1) Fringe (metal2) Overlap (N+active) Overlap (P+active) POLY 82 2401 2308 POLY2 M1 32 36 61 53 74 53 M2 17 16 17 34 58 40 55 M3 10 12 9 13 32 39 28 32 48 N_WELL 40 864 206 278 UNITS aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um^2 aF/um aF/um aF/um aF/um aF/um aF/um Page 12 of 15 Page 13 of 15 Page 14 of 15 Page 15 of 15
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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Iowa State - EE - 330
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