330 EE Spring 2011 Laboratory 2: Basic Boolean Circuits
Objective:
The objective of this experiment is to investigate methods for evaluating the performance of Boolean circuits. Emphasis will be placed on the basic CMOS inverter but the concepts are applicable to larger circuits. Time domain behavior of the inverter will be considered. Part 1.1: Introduction A digital inverter with Boolean input A and Boolean output Y is shown in Fig. 1a
Figure1 Digital Inverter a) Gate Representation b) Simple Transistor Implementation c) Transistor Implementation Showing Bulk Connections This gate level representation provides no detail about the underlying circuit used to realize the gate. Fig. 1b shows transistor level detail but does not show how the bulk is connected in the circuit. The representation in Fig. 1c shows all connectivity of the
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inverter. In the latter view, the input and output variables are labeled as voltage variables rather than as Boolean variables. Part 2 Simulation of a CMOS Inverter In this section we will focus on the creation of a schematic of a CMOS inverter and on the simulation of this inverter in Spectre. Part 2.1 Attaching technology information In the last lab, we simulated a simple circuit consisting only resistors and capacitors. In this lab, we will implement an inverter using transistors. Create a new cell named 'inverter' in schematic view. To use the correct models for the transistors, we need to choose which "Technology" we would like to use. By choosing a technology, we decide which semiconductor manufacturer will manufacture our design if we choose to fabricate it as an IC. For the purposes of this course, we will use the 0.5 process from ON Semiconductor. ON Semiconductor is a spin-off from Motorola and purchased a company called AMI who provided this 0.5u process to universities for many years. An occasional reference to AMI may still be made even though the company no longer exists. When the attach process is complete, all the ON 0.5 process information will automatically be used in our designs. The process information includes critical parameters such as the minimum device size, the available layer masks, and the supply voltage level. To attach a library to a specific technology, right click on the desired library name in the Library Manager and choose Attach Tech lib... In the form that pops up, choose the technology library to be AMI .6u C5N and click on ok. Check CIW to see if the technology file was attached successfully. Part 2.2 Creation of a Schematic Consider an implementation of the CMOS inverter of Fig. 1c in the ON 0.5 CMOS process. Use a 5V power supply and size the devices M1 and M2 with the drawn dimensions given in Table 1. Table 1: Device Sizes for Inverter W 1.5u 4.5u L 0.6u 0.6u
M1 M2
Create a schematic view of the inverter in a new cell in your lablib library (for convenience use the name inverter for this cell). For the NMOS and PMOS transistors, use the cells nmos4 and pmos4 from the NCSU_Analog_Parts library, respectively. NOTE: The transistors should have 4 terminals, NOT 3. When editing the transistor properties, the lengths and widths need to be in the fields labeled "Width" and "Length", not in the "Width (grid units)" or "Length (grid
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units)" fields. When entering numbers in the Cadence design and simulation environment, you can use engineering notation such as k (103), M (106), m (10-3), u (106 ), n (10-9), etc. The suffix should be written right next to the number without spaces. For example, 10*10-9 can be entered as 10n or 10e-9 but not as 10 n. The labeled voltages on the schematic of Fig.1c include the voltage VSS which is often set at ground but for generality we have designated it as VSS. These labeled voltages must be designated with pins on the schematic you enter in Cadence. Pins can be of different types depending upon the intended use of the pin. To add pins, go to Add --> pin. The process of adding a pin is the same as adding labels, that is, separate multiple pins by a space and then place them on the schematic. Be sure to wire the pins to the appropriate wires! The voltages VDD and VSS should be bidirectional (inputOutput) pins. The voltage designated as VIN should be in input pin and the voltage designated as VOUT should be designated as an output pin. Also note that the specific pin will be automatically connected to the wire labeled with the same name. Be careful while naming wires and pins. Later labs will require you to reference these, and all references are case sensitive. Pick a labeling style and stick to it! Part 2.3 Symbol Creation To re-use the inverter we just created efficiently, we need to create a symbol for our schematic design. Go to DesignCreate CellviewFrom Cellview. If you think the information automatically filled is correct, press OK. A window with the symbol will be opened. Use the buttons on the left to Change the symbol view to make it look like an inverter. Make sure you keep the pins consistent. This process simply creates a graphic no wiring or electrical connections are used in the lines. The critical electrical parts are the red squares where the exterior circuit will attach to the graphic. Part 2.4: Inverter transient response simulation Now that we have a symbol for our inverter, let us set up the test bench. Create another schematic called test_inverter to test the design. The test bench is shown below.
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Figure 2: Inverter simulation test bench Use the voltage sources from analogLib. For the pulse input source, you can use either the vpulse or the vsource component from the analogLib library. You will need to apply an input square wave of frequency 1MHz with magnitude of 5V and rise and fall times of 1 pico seconds each. To instantiate your own inverter, use the instantiation procedure as you would for any other component from analogLib but choose the inverter cell instead from your own lablib library. Set the dc power supply voltage to 5V and the load capacitor to 1pF. Check and Save your work and correct all errors or warnings. Open the Analog Design Environment and check the Setup parameters first. Click on Setup Simulator Directory Host and check the Project Directory. This is the directory where simulation results are stored. It is recommended that you always store your simulation data on the local hard drive. To ensure this, set your project directory to /local/[username]/cadence/simulation. If you see /home/username then you should be aware that some simulations might run unusually slow and could take your entire ENGR disk quota. You can make this choice the default for all of your future Cadence sessions by creating a new file called .cdsenv in your home directory and adding the following line to it (with your username). asimenv.startup projectDir string "/local/[username]/cadence/simulation " Set up the transient analysis to run long enough for 5 complete input cycles. Select the input and output voltages for plotting and start the simulation. Did you create labels for those nodes of interest (recall how we used the labels vIn, vMid, and vOut in lab1)? and Debugging evaluation of results become easier with labels. Show this analysis to your TA.
Part 2.5: Inverter transfer characteristics simulation Modify the source and simulation environment to obtain the dc transfer characteristics (VOUT vs VIN) of the inverter for inputs voltages between 0V and 5V. At what value if VIN are the input and output equal? What is the maximum value of VIN that can be applied and still keep the output near 0V? What is the minimum value of VIN that can be applied and still keep the output near VDD? Show the transfer characteristics to your TA. Part 2.6: Inverter driving a load Increase the load to 10 pF. What do you notice at the output? What if you have a 100 pF load? Or a 1uF load? Explain what you think happens.
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Increase the width of the transistors of the inverter by a factor of ten (i.e. Wp=45u, and Wn=15u). Revert back to a 10pF load and simulate. What happened, and why did it occur? Show your plots to your TA.
Part 3 The Verilog Inverter
A Verilog representation of a digital system, be it a small or a very large system, is characterized by a set of modules that describe the system. A large system will be comprised of a large number of nested modules whereas a small system may be comprised of only a single module. As such, the main building block in Verilog is the module. The structure of a module includes statements about input/output variable mappings along with a description about how the input and output variables are related. An example of a module named "testcircuit" is shown below
module testcircuit (vout, vdd, vss, vin); output vout; inout vdd; inout vss; input vin; assign vout = ~vin; endmodule
This module has one output, vout, one input, vin, and two bidirectional ports, vdd and vss. The relationship between the input and output for this simple module is defined by the assign statement. The module description is always terminated with an endmodule statement. In Cadence, we can create behavioral modules several ways, two of which will be discussed in this experiment.
Symbol-Based Module Creation
With the Symbol-based method, a symbol view (that may have been created earlier) is used to generate a behavioral view with the input/output pin and direction information. The user must then enter the remainder of the module to fully define the operation of the circuit.
Text-Based Module Creation
The user creates a module by creating a text file that includes the module name, pin names and input/output direction information. This text file defines the behavioral view of the module. The user must then enter the remainder of the module to fully define the operation of the circuit. Modules that represent a digital system are simulated by using a special module in Verilog called a Test Fixture. A Test Fixture has no inputs or outputs but contains instantiations of the modules that need to be tested along with a description of the excitations that will be used to simulate the system. In this laboratory, you will be asked to create behavioral views of an inverter. You will also be asked to simulate the inverter using individual test fixtures.
3.1 The Verilog File
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Create a behavioral view of the Boolean Inverter. The following steps create the skeleton of the module from which you can add the functional description. In the Library Manager, select the inverter that you designed. Click on File New Cell View and in the View Name field, type behavioral. The Tool field should be set to Verilog-Editor. When you click OK, an emacs file editor window with the following contents will open:
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//Verilog HDL for "your_library", "your_inverter" "behavioral"3 module your_inverter (vout, vdd, vss, vin); output vout; inout vdd; inout vss; input vin; (Add your code defining the operation of the inverter here) endmodule
Since you've already designed, checked and saved this gate in the Cadence environment, the Verilog-Editor will have prior knowledge of how your module looks like, and we only have to add the line that describes the output. To save and exit in the emacs editor, click Ctrl-X Ctrl-C, then when prompted if you want to save, click y. What we just did is write a description of the inverter in a behavioral way. In other words, how do the outputs relate to the inputs, without knowledge of how the operation would be implemented with transistors .
3.2 Simulating Behavioral Code
Now we are ready to simulate our file. Right-click on the Behavioral view and select to open it in Read Only. In the window that opens click Tools Verilog-XL. A Setup Environment window will open and will prompt you for the run directory. Always remember to be certain about this because it's where you should go when you need to debug. It will propose your_inverter.run1, hit OK. Now the Verilog Environment for Verilog-XL Integration window will open. Before we can simulate our circuit, we need to setup a test bench.
The test bench is needed to specify the time and value properties of the inputs. Click on StimulusVerilog, an options window should open. The stimulus file that is used in every simulation is called testfixture.verilog by default. After a simulation is done, this file gets set back to its default contents. Hence, we will always write our test fixtures and save them as something other than testfixture.verilog. That way we don't have to rewrite them every time we run a simulation. Select the Copy mode, and in the Copy From / File Name select testfixture.verilog, in the Copy To / File Name select testfixture.new (or a better more descriptive name of your choice) as the destination. Also check the Make Current Test Fixture and Check Verilog Syntax buttons. Hit OK. If the filename never existed it will open a file editor for the new file otherwise you can open the Stimulus Options again and go to Edit. The file should like this by default, and the bolded text has been added.
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// Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus initial begin vin= 1'b0; io_vdd = 1'bz; io_vss = 1'bz; #80 $finish; End always #20 vin = ~ vin;
This will initially set vin at a (1 bit) value of 0, and after every 20 time units, will invert it. The whole process will last 80 time units. As to vdd and vss, they are set to a high impedance value. Now we are ready to simulate. Click on Simulation _ Start Interactive, after a warning hit Simulation Continue.
3.3 Accessing Simulation Results
Now we are ready to view the results. Debug Utilities View Waveform will start SimVision. It is a versatile results browser and plotter; it can be used for both digital and analog waveforms. In the Design Browser section, descend into the top module: the available nets will show up below, select all four of them to plot them. You can collapse the Design Browser window now. After you are done inspecting the waveforms, you can print them using File -> Print Window.
Deliverables:
1. Inverter Transient Plot 2. Inverter Transfer Characteristics 3. Inverter Load Simulation 4. Verilog Simulation Results
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