330 EE Laboratory 4 From Boolean equation to Silicon
Fall 2010
Objective:
The objective of this experiment is to implement a Boolean function description in silicon, given area and pin constraints. A second object is to introduce the concept of parameterized cells (pcells) which are useful for making layouts of widely-used circuits when the basic circuit structure remains fixed but when some characteristics of the circuit, such as the device dimensions or the number of elements in the circuit, may change.
Introduction
A simplified Custom IC design flow is shown in the flow chart. From the flow chart, we can observe that we now have the basic skills to do a complete design of a simple circuit. In this experiment, we will take the system System Description description in the form of a simple Boolean expression and convert it to a layout for fabrication through MOSIS. Before we start the design, a layout technique that can save considerable time on the part of the designer will be Circuit Design introduced.
(schematic)
Part 1: Layout of an inverter using pcells:
From the previous experiment that focused on layout basics, most likely concluded that it takes considerable time to layout even a simple circuit (e.g. a Boolean inverter) and considerable attention must be devoted throughout the layout process to avoid creating either layout errors or even circuit errors. One way to expedite the layout process is to use parameterized cells (pcells). Pcells are "macros" that take have numeric arguments as an input and that generate as an output a layout that is "correct by construction". For example, we will consider as an example a pcell where the length and the width of a transistor serve as numeric input parameters to create the layout of an NMOS transistor (exclusive of a bulk connection!). The available pcells that are available at this time to students in this class for the AMI 0.5u process can be found under the category "layout macros" in the NCSU_TechLib_ami06 library. To practice, backup your inverter cell by copying it to a new cell called inverter_old. Delete the layout view of the inverter and re-create it. In the new layout
Simulation
(verification)
Layout/DRC
Extraction
GDF for Fabrication
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window, click on Create Instance and select NCSU_TechLib_ami06, in the Library entry, and then choose nmos in the Cell entry. If you now click in the layout window you can place an instance of the nmos pcell. Hit Shift-F to view the pcell in its layered form. If you need to modify the properties of this instance, select the instance, bring up the "properties" form, and edit the width and length to desired values, just as you would in schematic view. Note that using pcells will only produce the transistors or contacts; you still have to draw the required interconnects. Don't forget the bulk connections! Complete the inverter layout using pcells and make sure that you pass LVS. Show this circuit to your TA.
PMOS PCell
NMOS PCell
Experiment with the fields "Fingers" and "Multiplier" in the properties of the transistor pcells. Can you use the resulting layouts in making your gate designs more compact?
Part 2-: Layout of a logic function
Part 2.1: 3 - Input NAND/NOR Gate
Using pcells, create either the 3-input NAND or NOR gate. To do so, first build it in a schematic view, then build it in a layout. Make sure it passes LVS. Finally, create a
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symbol for it and build a test bench to show functionality. Show the test and results LVS to your TA.
Part 2.2: Boolean Function
Implement the boolean function given to you at the end of last week's lab. Use the inverter from part 1, your NAND or NOR gate from part 2.1, and your partners NAND or NOR gate. You must go through the full design flow (schematic, layout, LVS, symbol, test bench). When completed, show the results to your TA. Exchanging gates . You will randomly be assigned to layout a 3 input NOR or 3 input NAND gate. Build your gate in schematic view, create a symbol for it, build it in layout views, and then LVS to demonstrate your correct layout. Once the netlists match, you can exchange gates with your colleagues. You may exchange gates using the following steps. These steps are used to "pack" an inverter cell in lablib library in a single file that can then be given to a colleague. - From command line, cd into the lablib directory cd ~/ee330/lablib - Create an archive of the inverter cell tar cvf ~/inverter.tar inverter
The file inverter.tar in the home directory contains all the views required to use the inverter cell. If you receive this file from a colleague, use the following steps to enable the use of inverter in your design. - To keep the external designs separate, create a new library called exchange (or some other name) and attach it to the AMI06 process. - If you have the inverter.tar file in your home directory, move it to the exchange directory mv ~/inverter.tar ~/ee330/exchange - Extract the design cd ~/ee330/exchange tar xvf inverter.tar The inverter cell will now appear in the exchange library. Instantiate the symbol and the layout views from this cell to use the inverter in your own design. To make your design routable, layout of your logic function should follow the scheme of Fig. 1. Use VDD on top, VSS at the bottom, the inputs to the left, and the output to the right. This will make the final routing of all the designs easy since we will have signal and power paths running vertically and horizontally between the designs.
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VDD
INS OUT
VSS
Figure 1: Cell input, output and power directions It is a good idea to fix the height of every gate to be the same. Similarly, fix the widths of the power rails of an individual gate before starting layout. If you and your colleague agree on a set of specifications before starting layout, you could just abut the gates and avoid routing power and ground rails. Once the cell is constructed, you must prove that it solves the assigned equation. Build a test bench in schematic view that shows proper output values for all 8 input combinations of A, B, and C.
Design Constraints
Following is a summary of the constraints you must abide by when doing the layout. - You may only use the NAND, NOR and inverters you previously created. - - The completed cell should have dimensions smaller than 150m150m . - The inputs (A, B, C) for the complete cell must be available at the left boundary of the cell. - The output Y of the completed cell must be available at the right boundary of the cell. - Use a 6 wide metal1 bus at the top of the complete cell for VDD and a 6 wide metal1 bus at the bottom of the complete cell for ground. Use these rails to supply power to your gates. You may use different widths for the power supplies inside individual gates. - Avoid using metal2 inside layout of individual gates. - You may not use metal3 anywhere.
Deliverables:
1. Pcell Inverter 2. NAND/NOR schematic, LVS, and successful test 3. Boolean function schematic, LVS, and successful test
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