330 EE Lecture 2
Basic Concepts
Review from Last Time
Challenges
Managing increasing device count Short lead time from conception to marketplace Process technology advances Device Performance Degradation Increasing variability Increasing pressure for cost reduction Power Dissipation
Review from Last Time
Creation of Integrated Circuits
Most integrated circuits are comprised of transistors along with a small number of passive components and maybe a few diodes
This course will focus on understanding how transistors operate and on how they can be interconnected and possibly combined with a small number of passive components to form useful integrated circuits
Review from Last Time
Semiconductor Industry is One of the Largest Sectors in the World Economy and Growing Rapidly Growing Device Count and Rapidly Shrinking Feature Sizes (Moore's Law?) Designers Must Handle Incredible Complexity Yet Work in Large Teams and Make Almost No Mistakes
Review from Last Time
ITRS Technology Predictions
ITRS 2004 Supply Voltage Predictions
3.5 3 2.5
Volts
2 1.5 1 0.5 0 2000
Analog
Digital
2005
2010
YEAR
2015
2020
Review from Last Time
ITRS Technology Predictions
Minimum ASIC Gate Length
120
Length in nm
100 80 60 40 20 0 2000 2005 2010 YEAR 2015 2020
Selected Semiconductror Company Profiles
Texas Instruments: World's largest producer of analog semiconductors, 2nd in DSP Ranks 3rd in World in semiconductor sales
Number of employees: 28,400 2010 sales: 2010 income: $14.0B $3.2B
Average annual sales/employee: $490K
Average annual earnings/employee: $113K
Selected Semiconductror Company Profiles
Intel: World's largest producer of semiconductors Cofounders: Robert Noyce and Gordon Moore Number of employees: 82,500 2010 sales: 2010 income: $43.6B $11.5B Robert Noyce BA Grinnell 1949
Average annual sales/employee: $528K Average annual earnings/employee: $139K
Selected Semiconductror Company Profiles
Marvell:
Cofounders: Sehat Sutardja (CEO), Welli Dai and Pantas Sutardja
Number of employees: 5890 2010 sales: 2010 income: $3.6B $904M Sehat Sutardja Average annual sales/employee: $611K Average annual earnings/employee: $159K Fabless Semiconductor Company
BSEE IASTATE (approx 1985)
Considerable Cash Flow Inherent in the Semiconductor Industry
Essentially All Activities Driven by Economic Considerations
Many Designs Cost Tens of Millions of Dollars Mask Set and Production of New Circuit Approaching $2 Million New Foundries Costs Approaching $10 Billion (few players in World can compete) Many Companies Now Contract Fabrication (Fabless Semiconductor Companies) Time to Market is Usually Critical Single Design Error Often Causes Months of Delay and Requires New Mask Set Potential Rewards in Semiconductor Industry are Very High
Will emphasize economic considerations throughout this course
Understanding of the Big Picture is Critical
Solving Design Problems can be Challenging Be sure to solve the right problem !
How can complex circuits with a very large number of transistors be efficiently designed with low probability of error?
Many designers often work on a single design Single error in reasoning, in circuit design, or in implementing circuit on silicon generally results in failure Design costs and fabrication costs for test circuits are very high
Design costs for even rather routine circuits often a few million dollars and some much more Masks and processing for state of the art processes often between $1M and $2M
Although much re-use is common on many designs, considerable new circuits that have never been designed or tested are often required Time to market critical missing a deadline by even a week or 2 may kill the market potential
How can complex circuits with a very large number of transistors be efficiently designed with low probability of error?
CAD tools and CAD-tool environment critical for success today Small number of VLSI CAD toolset vendors CAD toolset helps the engineer and it is highly unlikely the CAD tools will replace the design engineer An emphasis in this course is placed on using toolset to support the design process
CAD Environment for Integrated Circuit Design
Typical Tool Flow
(See Chapter 14 of Text)
Laboratory Experiments in Course
VLSI Design Flow Summary
Analog Flow
System Description
Circuit Design (Schematic)
Print Circuit Schematic
SPICE Simulation
Simulation Results
Layout/DRC...
Extraction
DRC Report
LVS
Back-Annotated Extraction Post-Layout Simulation
LVS Output File
Post-Layout Simulation
Fabrication
VLSI Design Flow Summary
Analog Flow
Cadence Virtuoso
System Description
Circuit Design (Schematic)
Schematic Editor
Print Circuit Schematic
SPICE Simulation
Simulation Results Spectre (or HSPICE)
Layout/DRC...
Assura DRC
Extraction
Assura RCX DRC Report
LVS
Assura LVS LVS Output File
Back-Annotated Extraction Post-Layout Simulation
Spectre (or HSPICE)
Post-Layout Simulation
Fabrication
Digital Flow
VLSI Design Flow Summary
System Description Verilog Description Verilog Simulation Synthesis (Synopsys) Simulate (Gate Level)
VHDL Simulation Results and And Comparison with System Specs. Gate-level Simulation
Print Circuit Schematic
Place and Route (SoC Encounter) --- --- or DEF GDS2 File -------DRC
DRC Report
Circuit Schematic (Cadence)
Connectivity Report and Show Routing to TA
LVS
Extraction
Back-Annotated Extraction
Post-Layout Simulation
Post-Layout Simulation
LVS Output File
Fabrication
Digital Flow
VLSI Design Flow Summary
System Description Verilog Description Cadence SoC Encounter
VHDL Simulation Results and And Comparison with System Specs. Gate-level Simulation
Verilog XL Verilog Simulation Synthesis Synopsis Simulate (Gate Level) Place and Route (SoC Encounter) --- --- DEF or GDS2 File -------DRC
DRC Report
Print Circuit Schematic
Verilog XL Circuit Schematic (Cadence)
Connectivity Report and Show Routing to TA
LVS
Extraction
Back-Annotated Extraction
Post-Layout Simulation
Post-Layout Simulation
LVS Output File
Fabrication
Mixed Signal Flow (Digital Part) System Description VHDL Description
VLSI Design Flow Summary
VHDL Simulation Results and And Comparison with System Specs. Gate-level Simulation
VHDL Simulation Synthesis (Synopsys) Simulate (Gate Level) Place and Route (Silicon Ensemble) --- --- DEF or GDS2 File -------DRC
DRC Report
Print Circuit Schematic
Circuit Schematic (Cadence)
Connectivity Report and Show Routing to TA
LVS
Extraction
Back-Annotated Extraction
Post-Layout Simulation
LVS Output File Post-Layout Simulation
A
B
VLSI Design Flow Summary Mixed-Signal Flow (Analog Part) System Description
Circuit Design (Schematic)
Print Circuit Schematic
SPICE Simulation
Simulation Results
Layout/DRC
Extraction Back-Annotated Extraction Post-Layout Simulation
LVS
DRC Report
LVS Output File
Post-Layout Simulation
C
D
VLSI Design Flow Summary
Mixed-Signal Flow (Analog-Digital Merger)
A
C
D
B
Layout Merge
Show Layout to TA
Schematic Merge
Extraction
LVS/DRC Output Files
LVS/DRC
Post-Layout Simulation
Fabrication
Simulation Results
Comments
The Analog Design Flow is often used for small digital blocks or when particular structure or logic styles are used in digital systems Variants of these flows are widely used and often personalized by a given company or for specific classes of circuits
Wafer
6 inches to 12 inches in diameter All complete cells ideally identical flat edge very large number of die if die size is small
die
Feature Size
Feature size is the minimum lateral feature size that can be reliably manufactured
Often given as either feature size or pitch Minimum feature size often identical for different features
What is meant by "reliably"
Yield is acceptable if a very large number of these features are made
If P is the probability that a feature is good n is the number of features on an IC Y is the yield
YP
n
Pe
loge Y n
Example: How reliable must a feature be?
n=5E3 Y=0.9
loge Y n loge 0.9 5E3
Pe
e
=0.999979
But is n=5000 large enough ?
More realistically n=5E9
loge Y n loge 0.9 5E9
Pe
e
=0.999999999979
Extremely high reliability must be achieved in all processing steps to obtain acceptable yields in state of the art processes
Feature Size
Typically minimum length of a transistor Often minimum width or spacing of a metal interconnect (wire) Point of "bragging" by foundries
Drawn length and actual length differ
Often specified in terms of pitch
Pitch approximately equal to twice minimum feature size
Feature Size Evolution
Mid 70's 25
2005
2010 2020
90nm
20nm 10nm
1 103 nm 106 m 104 A
o
MOS Transistor
Active
Poly
MOS Transistor
W
Source
L
Drain
Gate Drawn Length and Width Shown Region of Interest (Channel)
MOS Transistor
W
Source
L
Drain
Gate Actual Drain and Source at Edges of Channel
MOS Transistor
Weff L eff Source Drain
Gate Effective Width and Length Generally Smaller than Drawn Width and Length
Technology Nomenclature
SSI MSI LSI VLSI Small Scale Integration 1-100 Medium Scale Integration 100-103 Large Scale Integration 103-105 Very Large Scale Integration 105-106
Any design in a process capable of incorporating a large number of devices is generally termed a VLSI design
Device and Die Costs
Consider the high-volume incremental costs of manufacturing integrated circuits Example: Assume an 8" wafer in a 0.25 process costs $800
Determine the number of minimum-sized transistors that can be fabricated on this wafer and the cost per transistor. Neglect spacing and interconnect. Solution:
ntrans
Ctrans
Awafer Atrans
Cwafer ntrans
4in 2 5.2 E11 2 0.25
$800 $15.4 E 9 5.2 E11
Note: the device count may be decreased by a factor of 10 or more if Interconnect and spacing is included but even with this decrease, the cost per transistor is still very low!
Device and Die Costs
C per unit area $2.5 / cm 2
Example: If the die area of the 741 op amp is 1.8mm2, determine the cost of the silicon needed to fabricate this op amp
C741 $2.5 / cm 2 1.8mm2 $.05
Actual integrated op amp will be dramatically less if bonding pads are not needed
Size of Atoms and Molecules in Semiconductor Processes
o
Silicon:
Average Atom Spacing Lattice Constant
2.7 A
o
5.4 A
o
SiO2
Average Atom Spacing
3.5 A
5 to 10MV/cm 5 to10mV/ A
0
Breakdown Voltage
Air
20KV/cm
Physical size of atoms and molecules place fundamental limit on conventional scaling approaches
End of Lecture 2