330 EE Lecture 5
Digital Systems A preview
Static CMOS Gates Other Logic Styles Improved Device Models
Review from Last Time
Statistics Review
fN f
x N ,
y N 0,1
x
y 0 1
+
x
f x dx 1
y
x
y
fN y dy 1
If the random variable x in Normally distributed with mean and standard x deviation , then y is also a random variable that is Normally distributed with mean 0 and standard deviation of 1.
Review from Last Time
Statistics Review
f
x N ,
x +
The random part of many parameters of microelectronic circuits is often
assumed to be Normally distributed and experimental observations confirm that this assumption provides close agreement between theoretical and experimental results
The mapping
y
x
is often used simplify the statistical
characterization of the random parameters in microelectronic circuits
Basic Logic Circuits
Basic Logic Circuits
Will present a brief description of logic circuits based upon simple models and qualitative description of processes Will discuss process technology needed to develop better models Will provide more in-depth discussion of logic circuits based upon better device models
Models of Devices
Several models of the electronic devices will be introduced
Complexity Accuracy Insight Application
Will use the simplest model that can provide acceptable results for any given application
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Gate Drain
Drain
Gate
Cross-Sectional View
Source
n-channel MOSFET
n-type n+-type p-type
Top View
Source
Drain
p+-type SiO2 (insulator)
Gate
POLY (conductor)
Designer always works with top view Complete Symmetry in construction between Drain and Source
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Gate Drain
Drain
Gate
VGS
Source
n-channel MOSFET
Behavioral Description of Basic Operation If VGS is large, short circuit exists between drain and source If VGS is small, open circuit exists between drain and source
Boolean/Continuous Notation:
VDD
Voltage Axis
G=1
Boolean Axis
0V
G=0
- Voltage Axis is Continuous between 0V and VDD - Boolean axis is discrete with only two points Most logic circuits characterized by the relationship between the Boolean input/output variables though these correspond to voltage ranges on the continuous voltage axis
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Gate Drain
Drain
Gate
n-channel MOSFET
Source
Equivalent Circuit for n-channel MOSFET
D D
G=0
G=1
Source assumed connected to ground
S
S
This is the first model we have for the n-channel MOSFET !
MOS Transistor MODEL
Drain
ID
Gate
Source
Equivalent Circuit for n-channel MOSFET
D D
G=0
G=1
S
S
Mathematically:
ID =0 VDS =0
if VGS is low if VGS is high
MOS Transistor
Qualitative Discussion of p-channel Operation
Source Bulk Gate Drain
Drain
Gate
Cross-Sectional View
Source
p-channel MOSFET
n-type n+-type p-type
Top View
Source Gate
Drain
p+-type SiO2 (insulator) POLY (conductor)
Complete Symmetry in construction between Drain and Source
MOS Transistor
Qualitative Discussion of p-channel Operation
Source Bulk Gate Drain
Drain
Gate
Source
p-channel MOSFET
Behavioral Description of Basic Operation If VGS is large (negative), short circuit exists between drain and source If VGS is small (near 0), open circuit exists between drain and source
MOS Transistor
Qualitative Discussion of p-channel Operation
Source Bulk Gate Drain
Drain
Gate
Source
p-channel MOSFET
Equivalent Circuit for p-channel MOSFET
D D
G=0
G=1
Source assumed connected to VDD and Boolean G at gate is relative to ground
S
S
This is the first model we have for the p-channel MOSFET !
MOS Transistor MODEL
Drain
ID
Gate
Source
Equivalent Circuit for p-channel MOSFET
D D
G=0
G=1
S
S
Mathematically:
ID =0 VDS =0
if VG is high ( VGSp is small) if VG is low ( VGSp is large)
MOS Transistor
Comparison of Operation
Drain
Drain
Gate
Gate
Source
Source
D
D
D
D
G=0
G=1
G=0
G=1
S
S
S
S
MOS Transistor
Comparison of Operation
Drain
Drain
Gate
Gate
Source
Source
A model for the n-channel and p-channel transistor has been developed
Termed the ideal switch-level model Several other models will be developed later Invariably use simplest model that is justifiable Will introduce better models only when needed
Symbols have been introduced for the two basic transistors
Other symbols will be introduced later
Logic Circuits
VDD
VDD
VDD
A=1
B
=0
A
B
A=0 B
=1
Circuit Behaves as a Boolean Inverter
Logic Circuits
VDD
Truth Table
A B
A 0
B 1
1
Inverter
0
Logic Circuits
VDD
VDD
A B
C
A=0 B=0
C =1
Logic Circuits
VDD
VDD
A B
C
A=1 B=0
C =0
Logic Circuits
VDD
VDD
A B
C
A=0 B=1
C =0
Logic Circuits
VDD
VDD
A B
C
A=1 B=1
C =0
Logic Circuits
VDD
Truth Table
A 0 B 0 C 1
0
1 0 1
0 0 0
A B
NOR Gate
C
1 1
VDD
Logic Circuits
Truth Table
A
C
B
A 0 0 1 1
B 0 1 0 1
C 1 1 1 0
NAND Gate
Other logic circuits
Other methods for designing logic circuits exist Insight will be provided on how other logic circuits evolve Several different types of logic circuits are often used simultaneously in any circuit design
Pull-up and Pull-down Networks
VDD
PUN
VDD
A
B
A
B
PDN
PU network comprised of p-channel device PD network comprised of n-channel device One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks
VDD
VDD
PUN
A B
C
A B
PDN
C
PU network comprised of p-channel devices PD network comprised of n-channel devices One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks
VDD
VDD
A C B
A
PUN
C B
PDN
PU network comprised of p-channel device PD network comprised of n-channel device One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks
In these the circuits, PUN and PDN have the 3 interesting characteristics 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time
VDD
PUN X Y
n
PDN
What are VH and VL? What is the power dissipation? How fast are these logic circuits?
What are VH and VL? What is the power dissipation? How fast are these logic circuits?
Consider the inverter Use switch-level model for MOS devices
VDD
VDD
A
A
B
A
B
What are VH and VL? What is the power dissipation? How fast are these logic circuits?
Consider the inverter Use switch-level model for MOS devices
VDD
VH=VDD VL=0
A B A
ID=0 thus PH=PL=0 tHL=tLH=0
(too good to be true?)
Pull-up and Pull-down Networks
For these circuits, the PUN and PDN have 3 interesting characteristics
Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time
What are VH and VL?
VDD
PUN Y
n
X
VH=VDD, VL=0 (too good to be true?)
What is the power dissipation?
PH=PL=0 (too good to be true?)
How fast are these logic circuits?
PDN
tHL=tLH=0
(too good to be true?)
These 3 properties are inherent in Boolean circuits with these 3 characteristics
Pull-up and Pull-down Networks
Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time
VDD
PUN X Y
n
Three properties of Static CMOS Gates (based upon
simple switch-level model)
PDN
1. VH=VDD, VL=0 (too good to be true?)
2. PH=PL=0 (too good to be true?)
3.
tHL=tLH=0
(too good to be true?)
These 3 properties are inherent in Boolean circuits with these 3 characteristics
Pull-up and Pull-down Networks
Concept can be extended to arbitrary number of inputs n-input NOR gate
VDD X1 X2
n-input NAND gate
VDD X1 X2 Xn X1 Y
Xn Y X1 X2 Xn
X2
Xn
Pull-up and Pull-down Networks
Concept can be extended to arbitrary number of inputs
n-input NOR gate
VDD X1 X2
n-input NAND gate
VDD X1 X2 Xn X1
Y
Xn Y X1 X2 Xn
X2
Xn
1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time
Pull-up and Pull-down Networks
VDD X1 X2
VDD
Xn Y X1 X2 Xn
PUN X Y
n
n-input NOR gate
PDN
VDD X1 X2 Xn X1 X2
Y
1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time VH=VDD, VL=0
PH=PL=0
Xn
n-input NAND gate
tHL=tLH=0
VDD X1
Nomenclature
VDD X1 X2 Xn X1 Y X2
Y
X2
Xn
X1
X2
Xn
Xn
n-input NOR gate
n-input NAND gate
In this class, logic circuits that are implemented by interconnecting multipleinput NAND and NOR gates will be referred to as "Static CMOS Logic" Since the set of NAND gates is complete, any combinational logic function can be realized with the NAND circuit structures considered thus far Since the set NOR gates is complete, any combinational logic function can be realized with the NOR circuit structures considered thus far Many logic functions are realized with "Static CMOS Logic" and this is probably the dominant design style used today!
Example 1: How many transistors are required to realize the function
F A B A C
in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available.
Example 1: How many transistors are required to realize the function
F A B A C in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available.
Solution:
C A F
B
20 transistors and 5 levels of logic
Example 1:
How many transistors are required to realize the function
F A B A C in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available.
Solution (alternative): From basic Boolean Manipulations
F A B A C A B A C F A 1 C B A B
A B
8 transistors and 3 levels of logic
F
Example 1:
How many transistors are required to realize the function
F A B A C in a basic CMOS process if static NAND and NOR gates are used? Assume A, B and C are available.
Solution (alternative):
From basic Boolean Manipulations
F A 1 C B A B
F A B A B
A B
F
6 transistors and 2 levels of logic
Example 2
Y A B C D
Standard Static CMOS Implementation
A B Y C D
3 levels of Logic
16 Transistors if Basic CMOS Gates are Used
Example 3: XOR Function
A B Y
Y=A B
A widely-used 2-input Gate Static CMOS implementation
Y=AB + AB
A Y B
22 transistors
5 levels of logic
Delays unacceptable and device count is too large !
Consider again
Example 2:
A B
Y A B C D
Standard Static CMOS Implementation
Y C D
3 levels of Logic 16 Transistors if Basic CMOS Gates are Used
Can the same Boolean functionality be obtained with less transistors?
Observe:
VDD C A D B Y B A D C
Y A B C D
Significant reduction in transistor count and levels of logic for realizing same Boolean function
Termed a "Complex Logic Gate" implementation Some authors term this a "compound gate"
Complex Logic Gates
VDD
Pull-up Network
C A D B Y B A D C
Pull-down Network
Y A B C D
Complex Gates
VDD C A D B Y B A D C
Pull up and pull down network never both conducting One of the two networks is always conducting
Complex Gates
Nomenclature:
VDD PUN X Y
n
PDN
When the logic gate shown is not a multiple-input NAND or NOR gate but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Gate
Complex Logic Gates also implement static logic functions and some authors would refer to this as Static CMOS Logic as well but we will make the distinction and refer to this as "Complex Logic Gates"
End of Lecture 5