330 EE Lecture 6
Improved Device Models Stick Diagrams Technology Files
Review from Last Time
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Gate Drain
Drain
Gate
n-channel MOSFET
Source
Equivalent Circuit for n-channel MOSFET
D D
G=0
G=1
Source assumed connected to ground
S
S
This is the first model we have for the n-channel MOSFET !
Review from Last Time
MOS Transistor
Qualitative Discussion of p-channel Operation
Source Bulk Gate Drain
Drain
Gate
Source
p-channel MOSFET
Equivalent Circuit for p-channel MOSFET
D D
G=0
G=1
Source assumed connected to VDD and Boolean G at gate is relative to ground
S
S
This is the first model we have for the p-channel MOSFET !
Review from Last Time
MOS Transistor
Comparison of Operation
Drain
Drain
Gate
Gate
Source
Source
D
D
D
D
G=0
G=1
G=0
G=1
S
S
S
S
Review from Last Time
Pull-up and Pull-down Networks
Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices 2. PD network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time
VDD
PUN X Y
n
Three properties of Static CMOS Gates (based upon
simple switch-level model)
PDN
1. VH=VDD, VL=0 (too good to be true?)
2. PH=PL=0 (too good to be true?)
3.
tHL=tLH=0
(too good to be true?)
These 3 properties are inherent in Boolean circuits with these 3 characteristics
Review from Last Time
Example 3: XOR Function
A B Y
Y=A B
A widely-used 2-input Gate Static CMOS implementation
Y=AB + AB
A Y B
22 transistors
5 levels of logic
Delays unacceptable and device count is too large !
Review from Last Time
Complex Gates
Nomenclature:
VDD PUN X Y
n
PDN
When the logic gate shown is not a multiple-input NAND or NOR gate but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Gate
Complex Logic Gates also implement static logic functions and some authors would refer to this as Static CMOS Logic as well but we will make the distinction and refer to this as "Complex Logic Gates"
Complex Gates
VDD PUN X Y
n
PDN
Complex Gate Design Strategy:
1. Implement
Y
in the PDN
2. Implement Y in the PUN (must complement the input variables since pchannel devices are used) (Y and Y expressed as either SOP or POS form)
XOR in Complex Logic Gates
A B Y
Y=A B
Need Y and Y in standard SOP or POS form
XOR in Complex Logic Gates
A B Y
Y=A B
Y=AB + AB
Y= AB + AB
Y=AB AB
Y= A+B A+B
XOR in Complex Logic Gates
A B Y
Y= A+B A+B
PDN PUN
Y=AB + AB
A
B
A
A
A
B
B
B
XOR in Complex Logic Gates
A B
VDD
Y
Y=AB + AB
A B
A B
A
A
Y= A+B A+B
B
B
Y
12 transistors and 2 levels of logic
A
B
Notice a significant reduction in the number of transistors required
A
B
XOR in Complex Logic Gates
A B Y
A B
Y=AB + AB
A B
Y= A+B A+B
Multiple PU and PD networks can be used
Y= A+B A+B A A+B + B A+B AB + AB
A
A
B
B
Complex Logic Gate Summary:
VDD PUN X Y
n
PDN
If PUN and PDN satisfy the characteristics: 1. PU network comprised of p-channel device 2. PD network comprised of n-channel device 3. One and only one of these networks is conducting at the same time Properties of PU/PD logic of this type (with simple switch-level model): Rail to rail logic swings Zero static power dissipation in both Y=1 and Y=0 states Arbitrarily fast (too good to be true? will consider again with better model)
Consider
A B
2 levels of Logic
Y A B
Standard CMOS Implementation
Y
6 Transistors if Basic CMOS Gates are Used Basic noninverting functions generally require more complexity if basic CMOS gates are used for implementation
Pass Transistor Logic
A VDD R B Y
Y A B
Requires only 2 transistors rather than 6 for a standard CMOS gate (and a resistor).
Pass Transistor Logic
B A R Y
Y A B
Even simpler pass transistor logic implementations are possible Requires only 1 transistor (and a resistor).
Pass Transistor Logic
B A A B R Y
Y AB
6 transistors, 1 resistor, two levels of logic
(the 4 transistors in the two inverters are not shown)
Pass Transistor Logic
B A B A R Y
Y AB
B A B A
2 transistors, 1 resistor, one level of logic
Y R
Y AB
Pass Transistor Logic
B A R Y
Y A B
Requires only 1 transistor (and a resistor)
- Pass transistor logic can offer significant reductions in
complexity for some functions (particularly noninverting) - Resistor may require more area than several hundred or even several thousand transistors - Signal levels may not go to VDD or to 0V - Static power dissipation may not be zero - Signals may degrade unacceptably if multiple gates are cascaded -"resistor" often implemented with a transistor to reduce area but signal swing and power dissipation problems still persist - Pass transistor logic is widely used
Logic Design Styles
Several different logic design styles are often used throughout a given design (3 considered thus far)
Static CMOS Complex Logic Gates Pass Transistor Logic
The designer has complete control over what is placed on silicon and governed only by cost and performance New logic design strategies have been proposed recently and others will likely emerge in the future The digital designer needs to be familiar with the benefits and limitations of varying logic styles to come up with a good solution for given system requirements
MOSFET Modeling
Simple model of MOSFET was developed Simple gates designed in CMOS Process were introduced
Some have zero power dissipation Some have or appeared to have rail to rail logic voltage swings All appeared to be Infinitely fast Logic levels of some can not be predicted with simple model Simple model is not sufficiently accurate to provide insight relating to some of these properties
MOSFET modeling strategy
hierarchical model structure will be developed generally simplest use model that can be justified
MOS Transistor Models
1, Switch-Level model
Gate Drain
Drain
Gate
Source
Source
D
D
D
D
G=0
G=1
G=0
G=1
S
S
S
S
Advantages: Simple, does not require understanding of semiconductor properties, does not depend upon process, adequate for understanding basic operation of many digital circuits Limitations: Does not provide timing information (surfaced when looking at static CMOS circuits, and several others that have not yet become apparent from the applications that have been considered) and can not support design of "resistor" used in Pass Transistor Logic
Recall
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Gate Drain
Drain
Gate
n-channel MOSFET
Source
D
D
G=0
G=1
S
S
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Gate Drain
Drain
G
Gate
n-channel MOSFET
Source
D
D
G=0
G=1
S
S
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Insulator Gate Drain
Drain
For VGS small
n-channel MOSFET
Gate
Bulk
Source Bulk
Gate
Drain Insulator
Source
Resistor
n-channel MOSFET
For VGS large
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Insulator Gate Drain
Drain
For VGS small
Source Bulk
n-channel MOSFET
Gate
Gate Drain Insulator
Bulk
Source
n-channel MOSFET
For VGS large
Capacitance from gate to channel region is distributed Lumped capacitance much easier to work with
Improved Switch-Level Model
Drain Gate
Source
G RSW CGS VG
D
Switch closed for VGS="1"
S
Switch-level model including gate capacitance and drain resistance
Still neglect bulk connection and connect the bulk capacitance to the source
Improved Switch-Level Model
Drain
D
D
Gate
G=1
G=0
S
Source
S
Switch-level model
G RSW CGS VGS
D
Switch closed for VGS="1"
S
Switch-level model including gate capacitance and drain resistance
Improved Switch-Level Model
Drain
D
D
G=0
Gate
G =1
Source
S S Switch-level model
G RSW CGS VGS
D
Switch closed for VGS="0"
S
Switch-level model including gate capacitance and drain resistance
Improved Switch-Level Model
Drain Gate
G
Source
D RSW
CGS VGS
Switch closed for VGS="1"
S
Switch-level model including gate capacitance and drain resistance
CGS and RSW dependent upon device sizes and process For minimum-sized devices in a 0.5u process
CGS 1.5fF
R sw
2K n channel 6K p channel
Considerable emphasis will be placed upon device sizing to manage CGS and RSW
Is a capacitor of 1.5fF small enough to be neglected?
1pf 100pf
.01uf
Is a capacitor of 1.5fF small enough to be neglected?
1pf
1fF
100pf
10fF
.01uf
1pf
Drain
Model Summary
1, Switch-Level model
D D G=1 G=0
Gate
Source
S
S
2,
Improved switch-level model
G RSW CGS VG S S D
Switch closed for VGS= large
Switch open for VGS= small
Other models will be developed later
Example
A
What are tHL and tLH?
Assume VDD=5V
VDD
Y 1pf
A Y
With basic switch level model ? With improved switch level model ?
Example
VDD
Inverter with basic switch-level model
G
p-channel Model
D
A
Y
A
A
S G VDD D
n-channel Model
Y
A S
Example
A 1pf
What are tHL and tLH?
G
p-channel Model
D
Y
A
A
S G VDD D
n-channel Model
Y 1pF
A
With basic switch level model
A tHL=tLH=0 Y
S
Example (cont)
With simple switch-level model tHL=tLH=0
VDD
A 1pf
Y
A
Y
Inverter With improved model ?
A 1pf
Y
Example (cont)
Inverter with improved model
VDD
Inverter with Improved Model
G
p-channel Model
D RSWp
A
Y
CGSp A
A
S Y
Inverter
G
VDD D
n-channel Model
RSWn CGSn A S
Example (cont)
With improved model
tHL=?
Y 1pf
A
G
p-channel Model
D RSWp
A
CGSp
A
S G VDD D
n-channel Model
Y 1pF
RSWn CGSn A S A
Y
RSWn=2K CGSp VDD CGSn
1pf 5V
5V
Example (cont)
With improved model
Y
RSWn=2K CGSp VDD CGSn
1pf 5V
tHL=?
5V
Recognize as a first-order RC network Recall: Step response of any first-order network with LHP pole can be written as
t
y(t) F I Fe
where F is the final value, I is the initial value and is the time constant of the circuit
For the circuit above, F=0, I=5 and R C
SWn
L
Example (cont)
With improved model
Y=VOUT
5V
tHL=?
V (t) F I F e
OUT t
RSWn=2K CGSp VDD CGSn
1pf 5V
R C
SWn
L
I
F t tHL=? tHL=?
Example (cont)
With improved model
VOUT
5V
RSWn=2K CGSp VDD CGSn
1pf 5V
tHL=?
I
I=5V, F=0V
F tHL
I/e
R C
SWn
L
t
tHL as defined has proved useful at analytically predicting response time of circuits
V (t) F I F e
OUT
t
1 F I F e e
tHL
Example (cont)
With improved model
I
I=5V, F=0V
F tHL I/e
R C
SWn
L
t
1 F I F e e
1 0 I 0 e e 1 e e
tHL
tHL
tHL
t
HL
t =R C
HL SWn
L
Example (cont)
With improved model
tLH=?
5V
VOUT
RSWp=6K CGSp VDD CGSn
1pf 0V
VDD=5V
y(t) F I Fe
t
For this circuit, F=5, I=0 and R C
SWp
L
Example (cont)
With improved model
VOUT
5V
RSWp=6K CGSp VDD CGSn
1pf 0V
tLH=?
VDD=5V
F F(1-1/e) I tLH
tHL as defined has proved useful at analytically predicting response time of circuits I=0V, F=5V
R C
SWp
L
t
V (t) F I F e
OUT
t
1 F 1 F I F e e
tLH
Example (cont)
With improved model
VOUT
5V
tLH=?
V (t) F I F e
OUT t
RSWp=6K CGSp VDD CGSn
1pf 0V
VDD=5V
R C
SWp
L
F
I t tLH=? tLH=?
Example (cont)
With improved model
tLH=?
tLH
F F(1-1/e) I
I=0V, F=5V
R C
SWp
L
1 F 1 F I F e e 1 F 1 F F e e 1 1 1 e e
tLH
tLH
t tLH
t
LH
t =R C
LH SWp
L
VOUT
Example (cont)
With improved model
5V
RSW CGSp VDD CGSn
1pf
VOUT
5V
RSWp=6K CGSp VDD CGSn
1pf 0V
VDD=5V
t R C t R C
HL SWn
LH SWp
L
2K 1 pF 2n sec
L
6K 1 pF 6n sec
Note this circuit is quite fast !
Note that tHL is much shorter than tlH Often CL will be even smaller and the circuit will be much faster !!
End of Lecture 6