330 EE Lecture 7
Delay Calculations Stick Diagrams Technology Files - Design Rules
Review from Last Time
MOS Transistor
Qualitative Discussion of n-channel Operation
Source Bulk Insulator Gate Drain
Drain
For VGS small
n-channel MOSFET
Gate
Bulk
Source
Source Bulk
Gate
Drain Insulator
Source Bulk Gate Drain Insulator
Resistor
n-channel MOSFET
For VGS large
Review from Last Time
Improved Switch-Level Model
G D RSW CGS VGS
Drain
Gate
Source
Switch closed for VGS="1"
S
Switch-level model including gate capacitance and drain resistance
CGS and RSW dependent upon device sizes and process For minimum-sized devices in a 0.5u process
CGS
1.5fF
R sw
2K n channel 6K p channel
Considerable emphasis will be placed upon device sizing to manage CGS and RSW
Review from Last Time
Drain
Model Summary
1, Switch-Level model
D D G=1 G=0
Gate
Source
S
S
2,
Improves switch-level model
G RSW CGS VG S S D
Switch closed for VGS= large Switch open for VGS= small
Other models will be developed later
Review from Last Time Response time of logic gates (inverter)
A
With improved model
Y CL
t
HL
R C
SWn
SWp
L
t
LH
R C
L
- Logic Circuits can operate very fast - Extremely small parasitic capacitances play key role in speed of a circuit
Review from Last Time Summary: What is the delay of a minimum-sized inverter driving a 1pF load?
X Y
X 1pF
Y
t
t
HL
R C
SWn
L
2K 1 pF 6K 1 pF
2n sec 6n sec
LH
R C
SWp
L
Drain
Improved switch-level model
G RSW CGS VG S S D
Gate
Source
Switch closed for VGS= large Switch open for VGS= small
Previous example showed why RSW in the model was important But of what use is the CGS which did not enter the previous calculations?
For minimum-sized devices in a 0.5u process
CGS
1.5fF
R sw
2K n channel 6K p channel
One gate often drives one or more other gates !
A
Y
What are tHL and tLH?
Example: What is the delay of a minimum-sized inverter driving another identical device?
X Y
G
p-channel Model
D RSWp
?
Load on first inverter
CGSp
Y
G VDD
n-channel Model
Y
S D RSWn CGSn
CGSn
S
CGSn
1.5fF
Y
Loading effects same whether CGSp connected to VDD or GND
Y CGSp+CGSn
For convenience, will reference both to ground
Y 3fF
Example: What is the delay of a minimum-sized inverter driving another identical device? Assume VDD=5V
X Y
X 3fF
Y
Example: What is the delay of a minimum-sized inverter driving another identical device?
X Y
X 3fF
Y
t
t
HL
R C
SWn
L
2K 3 fF 6K 3 fF
6 p sec 18 p sec
LH
R C
SWp
L
Note this is very fast but even the small 1.5fF capacitors are not negligable !
Stick Diagrams
It is often necessary to obtain information about placement, interconnect and physical-layer structure Stick diagrams are often used for small component-count blocks Approximate placement, routing, and area information can be obtained rather quickly with the use of stick diagrams
Stick Diagrams
Metal 1 poly n-diffusion p-diffusion
Metal 2
Contact
Additional layers can be added and color conventions are peronal
Stick Diagram
A B
A
VDD
B
A
B
A stick diagram is not a layout but gives the basic structure (including location,, orientation and interconnects) that will be instantiated in the actual layout itself Modifications can be made much more quickly on a stick diagram than on a layout Iteration may be needed to come up with a good layout structure
Stick Diagram
A B
Alternate Representation
A
B A B
Technology Files
Provide Information About Process
Process Flow (Fabrication Technology) Model Parameters Design Rules
Serve as Interface Between Design Engineer and Process Engineer Insist on getting information that is deemed important for a design
Limited information available in academia Foundries often sensitive to who gets access to information Customer success and satisfaction is critical to foundries
Technology Files
Design Rules Process Flow (Fabrication Technology) next (will
discuss )
Model Parameters (will discuss in substantially more
detail after device operation and more advanced models are introduced)
Typical Design Rules
Typical Design Rules (cont)
Typical Design Rules (cont)
Typical Process Description
Typical Process Description (cont)
Typical Process Description (cont)
Typical Model Parameters
Typical Model Parameters (cont)
Typical Model Parameters (cont)
Typical Model Parameters (cont)
Typical Model Parameters (cont)
Typical Model Parameters (cont)
Typical Model Parameters (cont)
Typical Design Rules (cont)
Technology Files
Design Rules Process Flow (Fabrication Technology) (will
discuss next )
Model Parameters (will discuss in substantially more
detail after device operation and more advanced models are introduced)
Design Rules
Give minimum feature sizes, spacing, and other constraints that are acceptable in a process
Very large number of devices can be reliably made with the design rules of a process Yield and performance unpredictable and often low if rules are violated Compatible with design rule checker in integrated toolsets
Design Rules and Layout
Drain
consider transistors
Layer Map
Drain
p-active n-active
Gate
Gate
Poly 1 Metal 1
Source
Source
n-well contact
L
W
L
W
D
G
Layout
S
D
G
Layout
S
Layout always represented in a top view in two dimensions
Design Rules and Layout
Drain
consider transistors
Layer Map
Drain
p-active n-active
Gate
Gate
Poly 1 Metal 1
Source
Source
n-well contact
L
W
L
W
D
G
Layout
S
D
G
Layout
S
Everything useful in channel region. All other features just overhead that degrades performance
Design Rules
L W
D
G
S
Design rules give minimum feature sizes and spacings Designers generally do layouts to minimize size of circuit subject to design rule constraints (because yield, cost, and performance usually improve)
Design Rules and Layout
Drain
consider transistors
Layer Map
Drain
p-active n-active
Gate
Gate Bulk
Poly 1 Metal 1
Source
Source
n-well contact
L
W
D
G
S
B
D
G
S
Bulk connection needed Single bulk connection can often be used for several (many) transistors
Design Rules and Layout
Drain
consider transistors
Layer Map
p-active n-active
Drain
Gate
Gate
Bulk
Poly 1 Metal 1
Source
Source
n-well contact
D
G
S
B
D
G
S
Bulk connection needed Single bulk connection can often be used for several (many) transistors is they share the same well
Design Rules and Layout
A
Logic Circuit
VDD M2 A M1 M3 M4 Y
(example)
Y
W=0.9u L=0.6u
Circuit Schematic (Including Device Sizing)
A
Y
Stick Diagram
Design Rules (example)
A Y
Layer Map
p-active n-active Poly 1 Metal 1 n-well contact
Layout
Design Rules (example)
Polygons merged in Geometric Description File (GDF) Separate rectangles generally more convenient to represent
Design Rules (example)
Design rules must be satisfied throughout the design DRC runs incrementally during layout in most existing tools to flag most problems DRC can catch layout errors but not circuit design errors
Design Rules (example)
What is wrong with this layout ? Bulk connections missing!
Design Rules (example)
Note diffusions needed for bulk connections Note p-well connections increase area a significant amount Note p-wells are both connected to VDD in this circuit
Design Rules (example)
Layout with shared p-well reduces area
Design Rules (example)
Shared p-active can be combined to reduce area
Shared n-active can be combined to reduce area
Design Rules
Design rules can be given in absolute dimensions for every rule Design rules can be parameterized and given relative to a parameter
Makes movement from one process to another more convenient Easier for designer to remember Some penalty in area efficiency Often termed -based design rules Typically is the minimum feature size in a process
End of Lecture 7