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Peculiarities: There are tests for the conditions < and but not for nor >. It may be possible to choose the source and destination in a comparison to avoid this problem. Unfortunately the asymmetric addressing modes often prevent this, particularly if one value is immediate. Two tests may then be necessary.
5.4.5
Instruction Timing
The number of MCLK cycles required for most instructions is limited by access to memory. This is a typical feature of a RISC-like CPU with a von Neumann architecture and also applies to the ARM7, for instance. Values for typical instructions are listed in Table 5.1 but there are several exceptions, including instructions that change the flow of control and those where the destination is PC. The general principle for Format I instructions (two operands) is as follows. Most of these must read the instruction and two operands from memory and write the result back. The duration is set by the modes used to address memory for the operands. It takes one cycle to fetch the instruction word itself. This is all if both source and destination are in CPU registers. Values from the constant generators are effectively in registers. One more cycle is needed to fetch the source if it is given indirectly as @Rn or @Rn+, in which case the address is already in the CPU. This includes immediate data.
Alternatively, two more cycles are needed if one of the indexed modes is used. The first is to fetch the base address, which is added to the value in a CPU register to get the address of the source. A second cycle is necessary to fetch the operand itself. This includes absolute and symbolic modes.
Table 5.1: Number of MCLK cycles required for typical instructions. It applies only to logical and arithmetic instructions and when the destination is not PC.
Format destination I Rd D(Rd) Format II Rs 1 4 1 Source @Rs, @Rs+ 2 5 3 S(Rs) 3 6 4
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Two more cycles are needed to fetch the destination in the same way if it is indexed. A final cycle is needed to write the destination back to memory if required; no allowance is needed for a register in the CPU. These are illustrated in Figure 5.5. It is amusing that no dedicated cycles are needed for the computation itself. A similar principle applies to the arithmetic operations with a single operand but most instructions with Format II change the flow of control and have individual timings. Jumps always use two cycles, whether conditional jumps are taken or not. There is no difference in the timing between bytes and words so it is pointless to squeeze variables into bytes in the hope of gaining speed. Of course it is an equally bad idea to waste memory by storing large tables as words when the elements would fit into bytes.
(a) Two operands (Format I), destination is register.
add.w Rs, Rd add.w @Rs, Rd add.w S(Rs), Rd
fetch instruction
fetch instruction fetch source @Rs
fetch instruction fetch S fetch source S(Rs)
(b) Two operands (Format I), destination is indexed.
add.w Rs, D(Rd) add.w @Rs, D(Rd) add.w S(Rs), D(Rd)
fetch instruction fetch D fetch destination D(Rd) write destination D(Rd)
fetch instruction fetch source @Rs fetch D fetch destination D(Rd) write destination D(Rd)
fetch instruction fetch S fetch source S(Rs) fetch D fetch destination D(Rd) write destination D(Rd)
(c) One operand (Format II)
rra.w Rs rra.w @Rs rra.w S(Rs)
fetch instruction
fetch instruction fetch source @Rs write source @Rs
fetch instruction fetch S fetch source S(Rs) write source S(Rs)
Figure 5.5: Cycle-by-cycle operation of typical instructions, showing the traffic with memory.
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