270 ECE Module 5 Practice Homework -1Solution 2009 by D. G. Meyer ______________________________________________________________________________ 1. As the competition on American Idol heats up, the judges have become aware of the need for an "improved" scoring circuit. Now that you know something about arithmetic logic circuit design, you can help! Before the next round, RPS (short for Randy, Paula, and Simon) have asked for a circuit that will allow each of them to award a score ranging from zero to five for each contestant; each judge, therefore, will have six pushbuttons to register their result, labeled "0" through "5". The sum of the three judges' scores is to be displayed on an LED "bar-graph", which should only illuminate when all three judges press their chosen button simultaneously. Further, your design should correctly handle multiple (simultaneous) button presses by any individual judge, registering only the highest numbered button pressed (HINT: sounds like a priority encoder). Note that the three-judge vote total has the potential to range from 0 to 15, requiring 16 LEDs in the bar-graph display. To help the bewildered contestants quickly ascertain their status, your design should utilize the following LED color-coding scheme: green for scores in the range of 1215 ("clear winner even Simon kind of liked you"), yellow for scores in the range of 8-11 ("split decision"), red in the range of 1-7 ("the competition is over for you"), and blue for zero ("signed Love is Like a Flower worse than Napoleon Dynamite"). For this problem, you need to complete the following steps: (a) Draw a block diagram of your design. Note that the main "building blocks" you need include 6:3 priority encoders, 4-bit binary adders, and a 4:16 binary decoder.
6:3 Encoder I0 D0 I1 D1 I2 D2 I3 I4 GS I5 6:3 Encoder I0 D0 I1 D1 I2 D2 I3 I4 GS I5 6:3 Encoder I0 D0 I1 D1 I2 D2 I3 I4 GS I5 PUSHBUTTONS PUSHBUTTONS
0
0
VCC
4-bit adder PUSHBUTTONS
0
4-bit adder
4:16 Decoder A B C D
2 3 4
1
Enable
ECE 270 Module 5 Practice Homework -2Solution 2009 by D. G. Meyer ______________________________________________________________________________ (b) Create an ABEL source file for your complete solution, noting that nominally 18 inputs (six buttons for each of the three judges) and 16 outputs (all active low, for sinking current through the bar-graph LEDs) are required.
MODULE idolbar TITLE 'RPS Idol Bar' DECLARATIONS " Pushbutton inputs (contact closure to ground " when pressed, therefore active low -- assume " pulled up to high state when button not pressed !RB0..!RB5 pin; " Randy's pushbuttons !PB0..!PB5 pin; " Paula's pushbuttons !SB0..!SB5 pin; " Simon's pushbuttons RV0..RV2 node istype 'com'; " Randy's encoded vote RV = [0,RV2,RV1,RV0]; RG node istype 'com'; " Randy's vote strobe PV0..PV2 node istype 'com'; " Paula's encoded vote PV = [0,PV2,PV1,PV0]; PG node istype 'com'; " Paula's vote strobe SV0..SV2 node istype 'com'; " Simon's encoded vote SV = [0,SV2,SV1,SV0]; SG node istype 'com'; " Simon's vote strobe " Split into intermediate sum to make it easier for fitter " to find smaller part that works ISUM0..ISUM3 node istype 'com'; " intermediate vote sum ISUM = [ISUM3,ISUM2,ISUM1,ISUM0]; VSUM0..VSUM3 node istype 'com'; " vote sum VSUM = [VSUM3,VSUM2,VSUM1,VSUM0]; !L0..!L15 pin istype 'com'; " LED outputs (active low) LEN node istype 'com'; " LED display enable X = .X.; TRUTH_TABLE ([RB5, RB4, RB3, RB2, RB1, RB0] -> [RV2, RV1, RV0, RG]) [ 0, 0, 0, 0, 0, 0] -> [ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 1] -> [ 0, 0, 0, 1]; [ 0, 0, 0, 0, 1, X] -> [ 0, 0, 1, 1]; [ 0, 0, 0, 1, X, X] -> [ 0, 1, 0, 1]; [ 0, 0, 1, X, X, X] -> [ 0, 1, 1, 1]; [ 0, 1, X, X, X, X] -> [ 1, 0, 0, 1]; [ 1, X, X, X, X, X] -> [ 1, 0, 1, 1];
EQUATIONS LEN = RG & PG & SG; ISUM = RV + PV; VSUM = SV + ISUM; L0 L1 L2 L3 L4 L5 L6 L7 = = = = = = = = LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN LEN & & & & & & & & & & & & & & & & !VSUM3 !VSUM3 !VSUM3 !VSUM3 !VSUM3 !VSUM3 !VSUM3 !VSUM3 VSUM3 VSUM3 VSUM3 VSUM3 VSUM3 VSUM3 VSUM3 VSUM3 & & & & & & & & & & & & & & & & !VSUM2 !VSUM2 !VSUM2 !VSUM2 VSUM2 VSUM2 VSUM2 VSUM2 !VSUM2 !VSUM2 !VSUM2 !VSUM2 VSUM2 VSUM2 VSUM2 VSUM2 & & & & & & & & & & & & & & & &
This could have been done on a single line, but splitting it up like this makes it easier for the fitter to realize the design using a smaller PLD.
!VSUM1 !VSUM1 VSUM1 VSUM1 !VSUM1 !VSUM1 VSUM1 VSUM1 !VSUM1 !VSUM1 VSUM1 VSUM1 !VSUM1 !VSUM1 VSUM1 VSUM1
& & & & & & & & & & & & & & & &
!VSUM0; VSUM0; !VSUM0; VSUM0; !VSUM0; VSUM0; !VSUM0; VSUM0; !VSUM0; VSUM0; !VSUM0; VSUM0; !VSUM0; VSUM0; !VSUM0; VSUM0;
L8 = L9 = L10= L11= L12= L13= L14= L15= END
TRUTH_TABLE ([PB5, PB4, PB3, PB2, PB1, PB0] -> [PV2, PV1, PV0, PG]) [ 0, 0, 0, 0, 0, 0] -> [ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 1] -> [ 0, 0, 0, 1]; [ 0, 0, 0, 0, 1, X] -> [ 0, 0, 1, 1]; [ 0, 0, 0, 1, X, X] -> [ 0, 1, 0, 1]; [ 0, 0, 1, X, X, X] -> [ 0, 1, 1, 1]; [ 0, 1, X, X, X, X] -> [ 1, 0, 0, 1]; [ 1, X, X, X, X, X] -> [ 1, 0, 1, 1];
TRUTH_TABLE ([SB5, SB4, SB3, SB2, SB1, SB0] -> [SV2, SV1, SV0, SG]) [ 0, 0, 0, 0, 0, 0] -> [ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 1] -> [ 0, 0, 0, 1]; [ 0, 0, 0, 0, 1, X] -> [ 0, 0, 1, 1]; [ 0, 0, 0, 1, X, X] -> [ 0, 1, 0, 1]; [ 0, 0, 1, X, X, X] -> [ 0, 1, 1, 1]; [ 0, 1, X, X, X, X] -> [ 1, 0, 0, 1]; [ 1, X, X, X, X, X] -> [ 1, 0, 1, 1];
ECE 270 Module 5 Practice Homework -3Solution 2009 by D. G. Meyer ______________________________________________________________________________ (c) Compile your ABEL source file and fit it into an appropriate sized PLD (note that there are many possible choices in ispLEVER pick the smallest one that works). Include a copy of your "fitter" report to document that your design indeed compiles and fits into an available PLD.
ECE 270 Module 5 Practice Homework -4Solution 2009 by D. G. Meyer ______________________________________________________________________________ 2. After using your "Problem 1" circuit for a week, the judges (RPS) quickly grew tired of "counting LEDS" to compare the contestants' scores. Having just learned about BCD adder circuits, you know how the circuit could be modified to produce a total score that could be displayed on a pair of 7-segment LEDs. In fact, by simply replacing the 4-bit binary adders (used in Problem 1) with BCD adders, and coupling that with a 74x47 BCD decoder/driver (from your DK-1 parts kit), you could meet the judges' needs! (Note that the most significant digit is either BLANK or "1", i.e., either no segments driven or only segments "b" and "c" driven, depending on the state of the "ten's position" output signal.) For this problem, you need to complete the following steps: (a) [5 points] Draw a block diagram of your design. Note that the main "building blocks" you need include 6:3 priority encoders, 4-bit BCD adders, and a 74x74 decoder/driver.
6:3 Encoder I0 D0 I1 D1 I2 D2 I3 I4 GS I5 6:3 Encoder I0 D0 I1 D1 I2 D2 I3 I4 GS I5 6:3 Encoder I0 D0 I1 D1 I2 D2 I3 I4 GS I5
PUSHBUTTONS
PUSHBUTTONS
0
0
4-bit binary adder PUSHBUTTONS
0
VCC
Cout 4-bit BCD adder
Cin
0 A B C 74x47 D
One's Digit
2 3 4
1
BI' Ten's Digit
1 2
ECE 270 Module 5 Practice Homework -5Solution 2009 by D. G. Meyer ______________________________________________________________________________ (b) Create an ABEL source file for your complete solution, noting that nominally 18 inputs (six buttons for each of the three judges) and 5 outputs (single bit for ten's position, 4bit BCD number for one's position note that the values displayed will range from "_0" to "15").
MODULE bcdidol 'RPS TITLE BCD Idol' DECLARATIONS " Pushbutton inputs (contact closure to ground " when pressed, therefore active low -- assume " pulled up to high state when button not pressed)
!RB0..!RB5 pin; " Randy's pushbuttons !PB0..!PB5 pin; " Paula's pushbuttons !SB0..!SB5 pin; " Simon's pushbuttons RV0..RV2 node istype 'com'; " Randy's encoded vote RV = [0,RV2,RV1,RV0]; RG node istype 'com'; " Randy's vote strobe PV0..PV2 node istype 'com'; " Paula's encoded vote PV = [0,PV2,PV1,PV0]; PG node istype 'com'; " Paula's vote strobe SV0..SV2 node istype 'com'; " Simon's encoded vote SV = [0,SV2,SV1,SV0]; SG node istype 'com'; " Simon's vote strobe VSUM0..VSUM3 node istype 'com'; " vote sum VSUM = [VSUM3,VSUM2,VSUM1,VSUM0]; !TENS pin istype 'com'; " BCD Ten's position (active low, direct segment drive) ONES0..ONES3 pin istype 'com'; " BCD One's position (output to 74x47) LEN node istype 'com'; " LED display enable !BI pin istype 'com'; " 74x47 blanking input (active low)
X = .X.; TRUTH_TABLE ([RB5, RB4, RB3, RB2, RB1, RB0] -> [RV2, RV1, RV0, RG]) [ 0, 0, 0, 0, 0, 0] -> [ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 1] -> [ 0, 0, 0, 1]; [ 0, 0, 0, 0, 1, X] -> [ 0, 0, 1, 1]; [ 0, 0, 0, 1, X, X] -> [ 0, 1, 0, 1]; [ 0, 0, 1, X, X, X] -> [ 0, 1, 1, 1]; [ 0, 1, X, X, X, X] -> [ 1, 0, 0, 1]; [ 1, X, X, X, X, X] -> [ 1, 0, 1, 1]; TRUTH_TABLE ([PB5, PB4, PB3, PB2, PB1, PB0] -> [PV2, PV1, PV0, PG]) [ 0, 0, 0, 0, 0, 0] -> [ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 1] -> [ 0, 0, 0, 1]; [ 0, 0, 0, 0, 1, X] -> [ 0, 0, 1, 1]; [ 0, 0, 0, 1, X, X] -> [ 0, 1, 0, 1]; [ 0, 0, 1, X, X, X] -> [ 0, 1, 1, 1]; [ 0, 1, X, X, X, X] -> [ 1, 0, 0, 1]; [ 1, X, X, X, X, X] -> [ 1, 0, 1, 1]; TRUTH_TABLE ([SB5, SB4, SB3, SB2, SB1, SB0] -> [SV2, SV1, SV0, SG]) [ 0, 0, 0, 0, 0, 0] -> [ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 1] -> [ 0, 0, 0, 1]; [ 0, 0, 0, 0, 1, X] -> [ 0, 0, 1, 1]; [ 0, 0, 0, 1, X, X] -> [ 0, 1, 0, 1]; [ 0, 0, 1, X, X, X] -> [ 0, 1, 1, 1]; [ 0, 1, X, X, X, X] -> [ 1, 0, 0, 1]; [ 1, X, X, X, X, X] -> [ 1, 0, 1, 1];
ECE 270 Module 5 Practice Homework -6Solution 2009 by D. G. Meyer ______________________________________________________________________________
TRUTH_TABLE ([LEN, VSUM3, VSUM2, VSUM1, VSUM0] -> [TENS, ONES3, ONES2, ONES1, ONES0]) [ 0, X, X, X, X] -> [ 0, 0, 0, 0, 0]; [ 1, 0, 0, 0, 0] -> [ 0, 0, 0, 0, 0]; [ 1, 0, 0, 0, 1] -> [ 0, 0, 0, 0, 1]; [ 1, 0, 0, 1, 0] -> [ 0, 0, 0, 1, 0]; [ 1, 0, 0, 1, 1] -> [ 0, 0, 0, 1, 1]; [ 1, 0, 1, 0, 0] -> [ 0, 0, 1, 0, 0]; [ 1, 0, 1, 0, 1] -> [ 0, 0, 1, 0, 1]; [ 1, 0, 1, 1, 0] -> [ 0, 0, 1, 1, 0]; [ 1, 0, 1, 1, 1] -> [ 0, 0, 1, 1, 1]; [ 1, 1, 0, 0, 0] -> [ 0, 1, 0, 0, 0]; [ 1, 1, 0, 0, 1] -> [ 0, 1, 0, 0, 1]; [ 1, 1, 0, 1, 0] -> [ 1, 0, 0, 0, 0]; [ 1, 1, 0, 1, 1] -> [ 1, 0, 0, 0, 1]; [ 1, 1, 1, 0, 0] -> [ 1, 0, 0, 1, 0]; [ 1, 1, 1, 0, 1] -> [ 1, 0, 0, 1, 1]; [ 1, 1, 1, 1, 0] -> [ 1, 0, 1, 0, 0]; [ 1, 1, 1, 1, 1] -> [ 1, 0, 1, 0, 1]; EQUATIONS LEN = (RG & PG & SG); " only enable display when all 3 judges vote BI = !LEN; " assert 74x47 blanking input if no vote is taking place VSUM = RV + PV + SV; END
(c) Compile your ABEL source file and fit it into an appropriate sized PLD (note that there are many possible choices in ispLEVER pick the smallest one that works). Include a copy of your "fitter" report to document that your design indeed compiles and fits into an available PLD.
ECE 270 Module 5 Practice Homework -7Solution 2009 by D. G. Meyer ______________________________________________________________________________ 3. Design a 4-bit CLA block (with two 4-bit operand inputs, a 4-bit result output, and a carryin and carry-out), such that all outputs are produced in a single pass (i.e., one unit of propagation delay). Complete the following steps: (a) Create an ABEL source file for your 4-bit CLA block. (b) Compile your ABEL source file and fit it into a Mach M4A3-32/32-5JC. Using the ispLEVER Timing Analysis tool, run a propagation delay (tPD) analysis and print the results obtained. (c) Answer the following questions: Even though your source file (and originally compiled equations) should have yielded a single-pass (here, 5 ns) propagation delay for all outputs, the Timing Analyzer indicates otherwise. What happened, and why? In this design, does it matter which definition of the propagate function (Pi) you used (i.e., Xi+Yi or XiYi? Why or why not?
MODULE f4cla TITLE 'Fast 4-bit CLA Block' DECLARATIONS X0..X3, Y0..Y3 pin; " operands CIN pin; " carry in COUT pin istype 'com'; " carry out S0..S3 pin istype 'com'; " sum outputs G0 G1 G2 G3 P0 P1 P2 P3 = = = = = = = = X0&Y0; X1&Y1; X2&Y2; X3&Y3; X0#Y0; X1#Y1; X2#Y2; X3#Y3; " generate functions
C0 = G0 # CIN&P0; C1 = G1 # G0&P1 # CIN&P0&P1; C2 = G2 # G1&P2 # G0&P1&P2 # CIN&P0&P1&P2; EQUATIONS COUT = G3 # G2&P3 # G1&P2&P3 # G0&P1&P2&P3 # CIN&P0&P1&P2&P3; S0 = CIN$P0; S1 = C0$P1; S2 = C1$P2; S3 = C2$P3;
END
Question 1: The outputs do not all incur a single unit (5 ns) of propagation delay because the fitter "breaks" some of the equations into smaller ones and inserts some nodes to compute intermediate results (this can be seen by comparing the "compiled" equations with the "fit" equations. Note, however, that going through a node (a macrocell that does not have a pin associated with it) is faster than going through a pin, hence the propagation delay penalty is a bit less than two times a single unit of delay.
Question 2: It really does not matter (much) which definition of Pi is used for this realization both designs fit in the same size PLD, and any propagation delay differences are just an artifact of how the splitter broke down the larger equations (although the "OR" is probably easier for the fitter to break down than the "XOR"). The maximum delay path for both cases remains 8.5 ns.
ECE 270 Module 5 Practice Homework -8Solution 2009 by D. G. Meyer ______________________________________________________________________________ 4. Design a 6x4 unsigned binary multiplier, completing the following steps: (a) Create an ABEL source file for your 6x4 multiplier. (b) Compile your ABEL source file and fit it into a MACH M4A3-128/64-55VC. Using the ispLEVER Timing Analysis tool, run a propagation delay (tPD) analysis and print the results obtained. (c) Answer the following questions: Based on the analysis done on multiplier arrays in the text and in the class notes, which multiplier output(s) would you predict to have the largest propagation delay? How do the propagation delays obtained using the Timing Analysis tool differ from the values you predicted? What do you think accounts for the differences?
MODULE mult64 TITLE '6x4 Binary Multiplier' DECLARATIONS X5..X0, Y3..Y0 pin; multiplier P9..P0 pin;
" multiplicand, " product
P = [P9..P0]; " Definition of product components PC1 = Y0 & [ 0, 0, 0, 0,X5,X4,X3,X2,X1,X0]; PC2 = Y1 & [ 0, 0, 0,X5,X4,X3,X2,X1,X0, 0]; PC3 = Y2 & [ 0, 0,X5,X4,X3,X2,X1,X0, 0, 0]; PC4 = Y3 & [ 0,X5,X4,X3,X2,X1,X0, 0, 0, 0]; EQUATIONS " Form unsigned sum of product components P = PC1 + PC2 + PC3 + PC4; END
Question 1: Based on the analysis in the text (and class notes), one would expect the two most significant bits (here, P8 and P9) to incur the largest propagation delay.
Question 2: Curiously, in the design realized here, the outputs expected to incur the largest propagation delay (P8 and P9) exhibit the smallest amount of delay. This has happened because the compiler generates all the equations that produce all the outputs in parallel (i.e., it is not artificially broken down into FA cells, as assumed in the text/notes). The fitter program then breaks the largest equations (here, for P5) into several parts, and uses an intermediate node to accomplish this. This is how the "middle" bit of the result takes the longest to compute.