Questions Similar and Answers
Solutions are based on the fourth edition of the book
1. You are the product manager for Intel core i5-650 processor. The chip has an area of 81 mm2, with a defect
rate of 0.67 defects per cm2 and =4. The die of each chip is occupied by two identical cores (70% total
area) and a shared L3 cache (30% total area). For simplicity, we assumed here that each chip has only two
cores and an L3 cache (no other components).
a. [2 Points] What is the yield of the die?
b. [5 Points] Some researchers proposed that the number of defects in a die can be modeled by Poisson
distribution. Suppose we can use the yield as the probability that there is no defect on a die, what is
the value of parameter in Poisson distribution here?
Note: Poisson distribution means the probability that there are exactly k defects (k being a non-negative
integer, k = 0, 1, 2, ...) is equal to
where,
e is the base of the natural logarithm (e = 2.71828...)
k is the number of occurrences of an event - the probability of which is given by the function
k! is the factorial of k
is a positive real number,
c. [5 Points] In a defected chip, assume defects are independent and uniformly distributed within the
die area. What is the probability that a DEFECTED chip has no defected cores?
d. [3 Points] If there is no defected core in a chip, but L3 is defective, we can still sell it by shutting
down the defected L3 cache. Suppose you can sell the perfectly working (defect-free) chip for
$289.99 each, you need $180 to manufacture and test each chip, what is the minimum sale price for
your chips without L3 cache (defective L3 cache is shutdown) to make any profit?
Solution
a)
The equation used here is from the fourth edition of the book.
Yield of a single die = (1 + (0.670.81)/4 ) -4= 0.601
b)
The probability that there is no defect on the die is
f(0;) = e- =0.601
Therefore = 0.509
c) Suppose there are k defects on the die, the probability that all of them are in the cache area is
(0.3)^k
We also have to compute the probability that there are k defects on the die is f(k;)
Therefore the probability that a DEFECTED chip has no defected cores is
((0.3)*f(1;) + (0.3)^2*f(2;) + + (0.3)^k*f(k;) + ) / (1-f(0;))
The nominator can be computed as
Sum_(k=1)^(inf) (0.3^k* ^k * e^(-) / k! )
= e^(-0.7) Sum_(k=1)^(inf) ((0.3)^k * e^(-0.3) / k! )
= e^(-0.7) (1-f(0;0.3))
The final result is
e^(-0.7) (1-f(0;0.3))/ (1-f(0;)) = 0.248
It is okay to compute above summation by keeping only several large terms.
d)
(180-(289.99*0.601))/ (0.248*(1-0.601)) =57.8 (dollars)
2. One day you got tired with architecture division. So you accepted an offer from a software division. Your job
is to develop a numerical simulation program. The software will be used on a workstation with a single CPU and
Nvidia Tesla C1060 GPU with 240 streaming processors. The CPU can achieve 1GFlops, while each streaming
processors in the GPU can deliver 3.9GFlops (peak). For simplicity, we only consider floating- point operations in
this problem. The CPU and all the streaming processors in GPU can perform calculation simultaneously.
a. [5 Points] If all of the dynamic instructions in your main application are parallelizable, what is the maximum
performance (Flops) you can get from your hardware in the optimal situation? What is the speedup compared
with CPU only execution? State your assumptions, if any.
b.
[5 Points] In reality, the computation cannot be performed without data. Suppose all input data is stored within
the memory prior to execution. Before each round of computation, you have to load the required input data into
the cache within CPU or GPU. Similarly, the computation results, i.e., output data, will be stored in the
corresponding cache immediately after the computation. The output data must be written back to the memory
before next round of computation. Assume that the memory and caches in both CPU and GPU have infinite
capacity, and there is no overlap between data transfer and computation. The bandwidth between CPU and
memory is 5GB/s, while the bandwidth between GPU and is memory 20GB/s. Each byte input data requires 3
Flops to produce 0.5 byte output data on average. There is no dependency among different parts of data. What is
the maximum performance (Flops) you can get from your hardware in the optimal situation if we take the data
transfer time into consideration? What is the speedup in this case compared to CPU-only execution? What
happens to Flops and speedup computation if every input byte requires 30000 Flops to produce 0.5 byte output
data?
CPU
Memory
GPU
c. [5 Points] What conclusions can we make based on our results in b)? Even if the program can be completely
parallelized, can we have linear performance improvement with the number of processing units i.e., if we double
the number of processing units, can we expect two-times performance?
Solution
a)
If all dynamic instructions can be executed on 240 cores simultaneously, the maximum average performance is
around
3.9 * 240 = 936GFlops
The speedup is 936/1 = 936
This an incredibly large number.
b)
If each byte input data requires 3 Flops to produce 0.5 byte output data on average, in order to process 100 GB data,
GPU needs
5+300/936 + 2.5 = 1.82 (s). Its actual performance is 300GFlops/1.82 = 38GFlops
CPU needs
20+ 300/1 +10 = 330 (s). Its actual performance is 300GFlops/330 = 0.91GFlops
The speed up is only 42
If each byte input data requires 30000 Flops to produce 0.5 byte output data on average, the computation time will be much
more than the data transmission time. Therefore, the speed up around 936 as in a)
It is OK if your computation is based on the fact that we can use CPU and GPU simultaneously. We consider GPU only
because the results are close..
c) No. For memory bound programs, improvement in bandwidth may be more important than more number of cores.
3.
[10 points] Assume that values of variables A, B, C and D reside in memory. Write the code sequence for
D = A*B + C * (A B)
for four instruction-set architectures: i) Stack, ii) Accumulator, iii) Register-memory and iv) Register-register
(Load-Store). (These four architectures are shown in Figure B.1 on page B -4 of the Appendix B). Do not
perform any scheduling or other optimizations!
Solution
i)
Stack
Push A
Push B
Sub
Push C
Mul
Push A
Push B
Mul
Add
Pop D
ii)
Accumulator
Load A
Mul B
Store A*B
Load A
Sub B
Mul C
Add A*B
Store D
iii)
Register-memory
Load R1 A
Mul R2,R1,B
Sub R4,R1,B
Mul R1,R1,C
Add R1,R1,R2
Store D,R1
iv)
Register-register
Load R1,A
Load R2,B
Load R3,C
Mul R4,R1,R2
Sub R5,R1,R2
Mul R1,R3,R5
Add R1,R1,R4
Store R1,D
4. There are some addressing modes that are not supported in MIPS. For example,
LDMIA R1,{R2,R3,R4} will perform the following three operations:
R2 = memory[R1], R3 = memory[R1+4]; R4 = memory[R1+8]
In other words, we can replace
LOAD
R2,0(R1)
LOAD
R3,4(R1)
LOAD
R4,8(R1)
ADD R5, R3, R2
ADD R5, R4, R5
STORE
R5, 4(R6)
by
LDMIA R1,{R2,R3,R4}
ADD R5, R3, R2
ADD R5, R4, R5
STORE
R5, 4(R6)
a. [5 Points] Suppose all instructions are still 32 bits. Since this is a R-Type instruction, there are 6 bits reserved for
opcode. Can you design one possible binary format (encoding) for this LDMIA instruction if we want to add it to
MIPS? Why the increment is a multiple of 4?
b. [5 Points] Assume that the new instruction will cause the clock cycle to increase by 2%. Assume that
25% of dynamic instructions are loads. The new instruction affects only the clock speed and not the CPI.
If only 30% of load instruction can be eliminated by the new instructions, will the overall performance
improve?
Solution
a)
There are many possible binary formats for this instruction. For example, we can use 20 bits to address
four registers (5 for each). The increment is 4 indicates that this instruction operates on 32 bits arrays.
Each instruction will load 3 32-bits values into 3 registers.
b)
In the optimal situation, we will remove
25%*30% = 7.5%
The overall execution time becomes
(1-7.5%)*1.02 = 0.94
Therefore, the performance does increase.
It is also fine if you interpret the question as 30% of load instructions can be REPLACE by the new instruction.