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Course: EEC 180A, Spring 2012
School: UC Davis
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OF UNIVERSITY CALIFORNIA--DAVIS DEPARTMENT OF ELECTRICAL &amp; COMPUTER ENGINEERING EEC180A -- DIGITAL SYSTEMS I Winter 2012 PRACTICE PROBLEMS -- SET 2 1. Number Representation: Design a combinational circuit that converts a 4-bit one's complement number X to its corresponding two's complement number Y. 2. ALU Design: Design a bit slice of the ALU shown below. The ALU performs one of the eight operations...

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OF UNIVERSITY CALIFORNIA--DAVIS DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING EEC180A -- DIGITAL SYSTEMS I Winter 2012 PRACTICE PROBLEMS -- SET 2 1. Number Representation: Design a combinational circuit that converts a 4-bit one's complement number X to its corresponding two's complement number Y. 2. ALU Design: Design a bit slice of the ALU shown below. The ALU performs one of the eight operations (summarized in the table below) on the two data inputs A = An 1...A0 and B = Bn 1...B0 according to the values of the selection input S = S2S1S0. An 1 Bn 1 S2 S1 S0 Cn Fn 1 S2 0 0 0 0 1 1 1 1 Slice n 1 A1 M S Cn1 B1 Slice 1 A0 S2 S1 S0 C1 B0 Slice 0 .... S2 S1 S0 C2 C0 F0 F1 ALU Operation F = 0...0 F = B minus A F = A minus B F = A plus B F = A XOR B F = A OR B F = A AND B F = 1...1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Ai S2 S1 S0 Ci + 1 Bi Slice i Ci Fi 3. Waveforms: Complete the output waveforms of the diagram shown below for the following fliplflops: (a) positive-edge triggered JK flipflop, and (b) negative-edge triggered JK flipflop. UC Davis 1 Hussain Al-Asaad Clk J K (a) (b) 4. Waveforms: Complete the timing diagram for the circuit below. Assume that the initial values of the flip-flops is 0. Moreover, assume that the delay of flip-flops and gates is negligible. X D Flip-flop A Z D Flip-flop B Clk Clk X A B Z UC Davis 2 Hussain Al-Asaad 5. Flip-Flop Design: Design a D flip-flop that operates on both the positive and negative edges of the clock. Hint: Use a positive edge D flip-flop, edge negative D flip-flop, and a 2-to-1 multiplexer. 6. Single-Sequence Counter Design: Design a counter that count in the following sequence: 0, 2, 7, 4, 6, 3, 1, 0, ..... Design the counter using T-flipflops. Verify that your implementation is self-starting. 7. Multi-Sequence Counter Design: A particular 2-bit counter counts in binary (00, 01, 10, 11, 00, ...) if the input M = 0 and counts in gray code (00, 01, 11, 10, 00, ...) if the input M = 1. In addition to the state outputs, the counter has an output Z which is set to 1 if the counter is in state 11. Design the counter using JK-flipflops. 8. Counter Analysis: Consider a counter implemented using three T-flipflops, labeled C, B, A from the highest -order bit to lowest. The next state function is implemented by the logic shown below. Assuming that the counter can be reset to state 000, what is the state diagram of the counter? A TA TB B C TC 9. Johnson Counter: The 4-bit Johnson counter advances through the sequence 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, and repeats. Using the standard counter design procedure, implement the 4-bit Johnson counter using (a) D-flipflops and (b) T-flipflops. 10.Counter Design: Using JK flip-flops, design a counter that counts in the following sequence: 000, 111, 001, 110, 010, 101, and repeat. Draw the schematic of your final design. Check whether your counter is self-starting or not. 11.Counter Analysis: Draw the state diagram of the counter shown below. J1 K1 Q1 Q1 S0 R0 Clock Q0 Q0 UC Davis 3 Hussain Al-Asaad
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