Integrated Digital Circuits
YuZhuo Fu
contact:[e-mail]
Office location417 room
WeiDianZi building,No 800 DongChuan road,MinHang
Campus
1.Introduction
If the automobile had followed the same
development cycle as the computer, a RollsRoyce would today cost $100, get one
million miles to the gallon and explode once
a year
outline
Course Introduction
A brief history
Design Metrics
MOS transistor
CMOS logic
Semiconductor processing
DIC characteristics
Design partitioning
Example: a simple MIPS microprocessor
1. Introduction
3
course instruction
Course namedDigital Integrated Circuit
Course codeSOME-021
Course typefundamental
credit68 hours4 credits
2011/2/24
4
Textbook
Digital integrated circuit Jan M.Rabaey
CMOS VLSI design- a circuits and systems
perspective Meil H.E.Weste, addison wesley press
Reference
Computer organization and design, john.l.hennessy
CMOS IC layout, dan clein
Reuse Methodology manual for system-on-chip
designs, Michael Keating
2011/2/24
5
Method of course
Time, location
120 weeks
Wed.1-2[8:00AM-9:40AM], Room 409
Fri.3-8[10:00AM-11:40], Room409
materials
slides
Please pre-read the slides before the lessons
Do not note the materials which slides have
Download address
Ic.sjtu.edu.cn/
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exam
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Office Hours
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6*3=18 4*3=12
3*3=9
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3*3=12
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18
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Lab assistant
teacherprof. yuzhuo fu
contact:[e-mail]
Office location417 room
Office hours:Weds 15:30PM-16:30PM, Fri. 15:30PM16:30PM
microelectronic building,No 800 DongChuan
road,MinHang Campus
predigital logic, circuit basic
Lab assistant:
[e-mail]
weidianzi blds 2th floor
Office hours:
8
target
Understanding the basic principle of Digital IC
Inverter analysis
Combinational logic
Sequential logic
Clocking issues
Wire and interconnection issues
Datapath design
Skills
SPICE
layout
2011/2/24
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what is this book all about?
Introduction to digital integrated circuits.
CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design methodologies.
What will you learn?
Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability
10
Why digital circuits ?
Design and implement the module libraries
Critical timing path still need circuit design
Some technologies tend to be pushed to its limit need
circuit design
Abstraction-based approach is only correct to a certain
degree, such as interconnect parasitics, etc
Scaling tends to emphasize some other deficiencies of
the abstraction-based model
New design issues and constraints tend to emerge over
time
Model not always show the truth
11
Some references
http://www.itrs.net/
http://www.lib.sjtu.edu.cn(IEEE conferences
and journals)
IEEE Journal of Solid-State Circuits (JSSC)
IEEE International Solid-State Circuits
Conference(ISSCC)
Symposium on VLSI Circuits (VLSI)
12
outline
Course Introduction
a brief history
Design Metrics
MOS transistor
Semiconductor processing
DIC characteristics
Design partitioning/CMOS logic
Example: a simple MIPS microprocessor
0: Introduction
Slide 13
The First Computer
The babbage difference engine(1832)
25,000 parts cost: 17,470
[1] The Babbage Pages http://www.ex.ac.uk/BABBAGE/
[2] J. A. N. Lee http://ei.cs.vt.edu/~history/Babbage.html
[3] Charles Babbage Institute http://www.cbi.umn.edu/charles.htm
[4] Howard Rheingold Tools For Thought http://www.rheingold.com/texts/tft/index.html
[5] Ada http://www.cs.yale.edu/homes/tap/Files/ada-lovelace-notes.html
[6] Dr. Betty Toole Ada http://www.cs.yale.edu/homes/tap/Files/ada-bio.html
[7]
[9]
2011/2/24
14
ENIAC
- The first electronic computer (1946)
http://www.seas.upenn.edu/~museum/
John Mauchly and J. Presper Eckert
15
Current fastest computer in the world
2011/2/24
16
The Transistor Revolution
William Shockley
John Bardeen
T-R-A-N-S-I-S-T-O-R
Resistor which can amplify electrical
signals as they are transferred
2011/2/24
Walter Brattain
First transistor
Bell Labs, 1948
17
The First Integrated Circuits
No vacuum, no filament, no glass tube but cold
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18
Greatest persons
Jack S.Kilby(1923-2005) William Shockley(1910-1989)
Robert Noyce1927-1990
Greatest persons
09IC11243.7%
0.3%[Gartner]
200941.59
200834.1121.93%
10%
21
$24M
$0.3
80M
23
$40
$15
Shopkeeper
$8
Logitech
$14
Device Vendors
$3
Total Manufacturing
24
Moores Law
In 1965, Gordon Moore noted that the number of
transistors on a chip doubled every 18 to 24
months.
He made a prediction that semiconductor
technology will double its effectiveness every 18
months
25
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moores Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
2011/2/24
26
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium III
Pentium II
Pentium Pro
Pentium
8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Courtesy, Intel
2011/2/24
Projected
27
Moores law in Microprocessors
Transistors (MT)
1000
2X growth in 26 months)!
100
10
486
1
386
286
0.1
0.01
P6
Pentium proc
8086
8080
8008
4004
8085
0.001
1970
1980
1990
Year
2000
2010
Courtesy, Intel
Transistors on Lead Microprocessors double every 2 years
2011/2/24
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Die Size Growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
386
286
P6
Pentium proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Courtesy, Intel
Die size grows by 14% to satisfy Moores Law
2011/2/24
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Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium proc
386
8080
8008
4004
1980
Courtesy, Intel
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
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Power Dissipation
Power (Watts)
100
P6
Pentium proc
10
8086 286
1
8008
4004
486
386
8085
8080
Courtesy, Intel
0.1
1971
1974
1978
1985
Year
1992
2000
Lead Microprocessors power continues to increase
2011/2/24
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Power will be a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
100
Pentium proc
286
8086 386486
10
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Courtesy, Intel
Year
Power delivery and dissipation will be prohibitive
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Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium Intel
Power proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Courtesy, density too high to keep junctions at low temp
2011/2/24
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Not Only Microprocessors
Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
Power
RF
Power
Management
1996 1997 1998 1999 2000
Units
48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)
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10,000
10,000,000
1 00,000,000
100,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
1 0,000,000
10,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1 ,000,000
1,000
58%/Yr. compounded
Complexity growth rate
1
10,0000
1 00,000
100
1
1,000
1 0,000
10
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0 00
1.1
00
1.01
Courtesy, ITRS Roadmap
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
2011/2/24
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Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
Cost of a function decreases by 2x
But
How to design chips with more and more functions?
Design engineering population does not double every
two years
Hence, a need for more efficient design methods
Exploit different levels of abstraction
2011/2/24
36
Technology Strategy / Roadmap
37
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
2011/2/24
D
n+
38
outline
Course Introduction
a brief history
Design Metrics
MOS transistor
Semiconductor processing
DIC characteristics
Design partitioning/CMOS logic
Example: a simple MIPS microprocessor
0: Introduction
Slide 39
Design Metrics
How to evaluate performance of a digital
circuit (gate, block, )?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
2011/2/24
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Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area
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NRE Cost is Increasing
2011/2/24
42
Die Cost
Single die
Wafer
Going up to 12 (30cm)
From http://www.amd.com
2011/2/24
43
Design Economics
Non-recurring engineering costs(NREs)
Recurring costs
Fixed costs
Ctotal
Stotal =
(1-m)
Ctotal is the manufacturing cost of a single IC to the vendor
M is the desired profit margin
44
Non-recurring engineering costs
Spent once during the design of integrated
circuit Ftotal
Engineering design cost Etotal
Prototype manufacturing cost Ptotal
The NRE costs can be amortized over the
lifetime volume of the chips
45
Non-recurring engineering costs
Spent once during the design of integrated
circuit Ftotal
Ftotal= Etotal + Ptotal
Engineering design cost Etotal
Prototype manufacturing cost Ptotal
The NRE costs can be amortized over the
lifetime volume of the chips
46
Non-recurring engineering costs
Spent once during the design of integrated circuit Ftotal
Engineering design cost Etotal
The cost of designing the IC Etotal hopefully will happen
once during the chip design process
Personnel cost
Architectural design
Logic capture
Simulation for functionality
Layout of modules and chip
Timing verification
DRC and tapout procedures
Test generation
47
Non-recurring engineering costs
Spent once during the design of integrated
circuit Ftotal
Engineering design cost Etotal
The cost of designing the IC Etotal hopefully will
happen once during the chip design process
Support costs
Computer costs
CAD software costs
Education or re-education costs
48
Non-recurring engineering costs
Spent once during the design of integrated circuit Ftotal
Engineering design cost Etotal
The cost of designing the IC Etotal hopefully will happen
once during the chip design process
Costs reference(2010)
Salary $50-$100K
Overhead $10-$30K
Computer costs $2K
CAD software costs
Digital $10K
Analog $100K
Back end $1M
49
Non-recurring engineering costs
Spent once during the design of integrated
circuit Ftotal
Ftotal= Etotal + Ptotal
Engineering design cost Etotal
Prototype manufacturing cost Ptotal
The mask costs($500K-$1M for 130nm process)
Test fixture costs($1K-$50K)
Package tooling
MPW is an economical way of prototype(MOSIS)
50
An example of NRE
You are starting a company to commercialize your
brilliant research idea. Estimate the cost to prototype a
mixed-signal chip. Assume you have 7 digital designers.
3 analog designers and 5 support personnel and that
the prototype takes 2 fabrication runs and 2 years
Digital designers:7*($70K+$30K+$10K+$10K)=$840K
Analog designers:3*($100K+$30K+$10K+$100K)=$720K
Support personnel:5*($40K+$20K+$10K)=$350K
2 fabrication:$2M
Total:$4*2M=$8M
51
Design Economics
Non-recurring engineering costs(NREs)
Recurring costs
Fixed costs
C total
Stotal
(1 m)
Ctotal is the manufacturing cost of a single IC to the vendor
M is the desired profit margin
52
Recurring costs
Rtotal=Rprocess+Rpackage+Rtest
Rprocess process cost
Rprocess=W/(N.Yw.Ypa)
W=wafer cost($500-$3000) depending on process
and wafer size
N= gross die per wafer
Yw=die yield wafer(should be 70%-90% for
moderate sized dice in a mature process)
Ypa=packaging yield (should be 95%-99%)
53
Yield
No. of good chips per wafer
Y
100%
T otal number of chips per wafer
Wafer cost
Die cost
Dies per wafer Die yield
Wasted area around
the edges of a
circular wafer
wafer diameter/2 2 wafer diameter
Dies p er wafer
die area
2 die area
54
Design Economics
Non-recurring engineering costs(NREs)
Recurring costs
Fixed costs
Once a chip has been designed and put into
manufacture, the cost to support that chip from
an engineering viewpoint may face a few sources
Data sheets___characteristics
Application notes
55
An example of NRE
Suppose your startup seeks a return on investment of 5,
the wafers cost $2000 and hold 400 gross die with a
yield of 70%. If packaging, test and fixed costs are
negligible.
How much do you need to charge per chip to have a 60%
profit margin?
How many chips do you need to sell to obtain a 5-fold
return on your $8M investment
Rtotal=Rprocess=2000/(400*0.7)=$7.14
Chip are sold at $7.14/(1-0.6)=$17.86
Profit per unit is $17.86-$7.14=$10.72
8M*5/10.72=3.73M(assuming 1.5 year lifetime,
3.73/1.5*12=207K/month)
56
We were strong
300mm wafer and Pentium 4 IC.
0: Introduction
57
Photos courtesy of Intel.
We were strong
58
What should we know
Reading some history
Moores Law
NRE Cost
59
What should we know
Reading some history
Moores Law
NRE Cost
60