VLSI CMOS Design
2.CMOS Transistor Theory
Fu yuzhuo
School of microelectronics,SJTU
Introduction
Digital IC
2: Device
omar fadhil,Baghdad
outline
PN junction principle
CMOS transistor introduction
Ideal I-V characteristics under static
conditions
Dynamic Characteristics
Non-ideal I-V effects
Digital IC
2: Device
2/74
Diffusion&Drift activity
PN junction diffusion
P-type hole concentration>>N-type hole concentration
N-type electron concentration>>P-type electron
concentration
Diffusion result
Build up space-charge region(depletion)
Stronger diffusion current, wider space-charge region
Drift result
Opposite to the diffusion current
Resulting in a zero net flow
Digital IC
2: Device
3/74
Depletion Region
hole diffusion
electron diffusion
p
B
p
hole drift
electron drift
n
r
+
x
Distance
-
(b) Charge density.
Cross-section of pn-junction in an IC process
A
Electrical
Field
SiO
2
(a) Current flow.
n
Charge
Density
A
Al
x
x
(c) Electric field.
Al
p
A
n
B
V
Potential
-W 1
y0
x
W2
Digital IC
(d) Electrostatic
potential.
2: Device
One-dimensional
representation
B
diode symbol
4/74
PN junction energy band
Example an abrupt junction has doping densities of NA=1015 atoms/cm3,
and ND=1016 atoms/cm3, calculate the built-in potential at 300K, ni is the
intrinsic carrier concentration in a pure sample of semi and equals
approximately 1.5X1010 atoms/cm3
0 =
Digital IC
kT N D N A
NN
ln(
) = 0.026 ln( D 2 A ) 600 mV
q
n i2
ni
2: Device
5/74
Forward-bias Mode
Applied potential lowers the potential barrier
Diffusion current dominates the drift
component
Digital IC
2: Device
6
Reverse-bias mode
Potential barrier is raised
Drift current becomes dominant
The number of minority carriers in the
neutral regions is very small, so drift
current component can almost be ignored
Digital IC
2: Device
7/74
Pn-juntion outline
PN junction analysis
PN junction current
PN junction capacitance
Digital IC
2: Device
8/74
Diode static behavior
Minority carrier concentration in the neutral
regions near the pn-junction under forward-bias
Minority carrier concentration
conditions
is supported by p-zone
majority carrier concentration
Digital IC
2: Device
9
How to calculate diffusion current?
N-region diffusion
computingp/nare
mobility of hole/electron
Diffusion coefficiency
Dn 34cm 2 / s, Dp 13cm 2 / s
dp n
dp
= qA D D p n
dx
dx
p n (W2 ) - p n 0
p (W ) W - p W
p n (x) =
x+ n 2 n n 0 2
Wn - W2
Wn - W2
I D,p T
pn0 N D n p 0 N A ni2
pn ( W2 ) pn0eVD / T N A
Digital IC
2: Device
10
How to calculate diffusion
current?
I D p qAD D p
pn0
Wn W2
(e VD /T 1)
I Dn qAD Dn
n p0
W p W1
(e
VD /T
1)
V /
n p0
pn0
I D I D p I Dn qAD ( Dn
Dp
) (e D T 1)
W p W1
Wn W2
VD /T
I S (e
1)
Digital IC
2: Device
11/74
Diode static behavior
Minority carrier concentration in the neutral regions
near the pn-junction under reverse-bias conditions
Digital IC
2: Device
12/74
Diode Current
T = kT/q = 26mV at 300K
IS is the saturation current of the diode
Digital IC
2: Device
13/74
Models for Manual Analysis
+
ID = IS(eV D/T 1)
ID
+
VD
+
VD
VDon
(a) Ideal diode model
(b) First-order diode model
Example 3.2
Digital IC
2: Device
14/74
PN junction outline
PN junction analysis
PN junction current
PN junction capacitance
Digital IC
2: Device
15/74
Dynamic behavior of pn-junction
Junction capacitance/depletion
capacitance -Cj
Diffusion capacitance/dope
capacitance -Cd
dQ
C
dV
Digital IC
2: Device
16/74
Junction capacitance
P
+N
+
The boundary of PN-junction could accumulate
charge when bias voltage was changed, which
show capacitance characteristic
When forward voltage improvedmore charges
pass,just like these charges are saved
When forward voltage decreased, less charges
pass, just like these charges are leaved
2011/3/15
Digital IC
2: Device
17
Junction capacitance
Depletion-region width
2 si N A N D
W j W2 W1
q N N 0 VD
AD
Maximum electric field
2q N A N D
Ej
N N 0 VD
D
si A
Depletion-region charge
Cj
dQ j
dVD
AD
Q j AD
N AND
2 si q
0 VD
N A ND
C j0
C j0
si q N A N D
0 VD 1
0.5
2 N N
1 VD 0 1 VD 0
A
D
Zero-bias conditions
C j0 AD
Digital IC
si q N A N D
20 N A N D
2: Device
18/74
Junction Capacitance
Digital IC
2: Device
19/74
Diffusion capacitance
Diffusion capacitance is dominant when PN-juntion works under forwardbias mode, because its current is supported by minority carrier
Charge of diffusion region
p n (x) =
Q p qAD
Wn
p ( x ) p dx
n
n0
Wn W2 pn 0 e
W2
qAD
Wn W2 2 I
2Dp
VD T
2
Dp
p n (W2 ) - p n 0
p (W ) W - p W
x+ n 2 n n 0 2
Wn - W2
Wn - W2
1
Qn
Wp
2
2 Dn
I Dn
2
Wn
I Dp
2Dp
Digital IC
I D p qAD D p
2: Device
pn0
Wn W2
(e VD /T 1)
20/74
Diffusion capacitance cont.
Transmit time
Tn
Wn2
Tp
2Dp
Diffusion current
Qn QD
ID
Tp Tn T
ID IS ( e
Digital IC
2: Device
2 Dn
Qn
dQD
dI
I
Cd
T D T D
dVD
dVD
T
Qp
W p2
VD
T
Wp
2
2 Dn
1 )
21
I Dn
Junction and diffusion
capacitance
Forward-bias mode
Diffusion cap. Is dominant
small RC effect for ignoring Junction cap.
Reverse-bias mode
Minority carrier concentration is very small,
so its diffusion cap. Can be ignored
Junction cap. Is dominant
large RC effect
Digital IC
2: Device
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PN junction switch model
Digital IC
2: Device
23
PN junction switching model
Rsrc
VD
V1
ID
Vsrc
V2
t=0
t=T
VD
Excess charge
Space charge
OFF
ON
Digital IC
Time
2: Device
ON
24
Diode Model
Cd
dQD
dI
I
T D T D
dVD
dVD
T
RS
+
VD
ID
CD
-
Cdiode
T ID
T
Digital IC
C j0
1 VD
2: Device
0
m
25/74
outline
PN junction principle
CMOS transistor introduction
Ideal I-V characteristics under static conditions
Dynamic Characteristics
Nonideal I-V effects
Digital IC
2: Device
26/74
What is a Transistor?
A Switch!
An MOS Transistor
VGS V T
|V GS|
Ron
S
D
Digital IC
2: Device
27/74
Why MOS transistor?
MOSMetal Oxide Semiconductor type
Field Effective Transistor-MOSTFET)
Merits
Simple manufacturing process
yield
Low power, high density
High input resistor
Digital IC
2: Device
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Terminal Voltages
Mode of operation depends on Vgs, Vgd, Vds
Vds = Vd Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Vg
Cutoff
+
Vgd
-
+
Vgs
-
Linear
Saturation
Vs
Digital IC
2: Device
-
Vds
+
Vd
29/74
nMOS Cutoff
No channel
Ids = 0
Vgs = 0
+
-
g
+
-
s
d
n+
Vgd
n+
p-type body
b
Digital IC
2: Device
30/74
nMOS threshold voltage
Vt>Vgs>0
depletion region(inversion) is formed below
the gate
Vgs=Vt
A strong inversion is built up, the potential at
the silicon surface reaches a critical value
Further increases the gate voltage produce
no further changes in the depletion layer
width
Digital IC
2: Device
31/74
Threshold Voltage
+
S
VGS
-
D
G
n+
n+
n-channel
Depletion
Region
p-substrate
B
VT is a function of several components
Digital IC
2: Device
32
outline
PN junction principle
CMOS transistor introduction
Ideal I-V characteristics under static conditions
Velocity Saturation
Dynamic Characteristics
Nonideal I-V effects
Digital IC
2: Device
33/74
nMOS Linear
Channel forms
V
Current flows from d to s
e- from s to d
Ids increases with Vds
Similar to linear resistor V
gs
> Vt
+
-
g
+
-
s
d
n+
Vgd = Vgs
n+
Vds = 0
p-type body
b
gs
> Vt
+
-
g
s
+
d
n+
n+
Vgs > Vgd > Vt
Ids
0 < Vds < Vgs-Vt
p-type body
b
Digital IC
2: Device
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nMOS in linear area
n = 3800 cm 2 /v . s, p = 1800 cm 2 /v . s
Charge per unit area: Qi ( x) Co x [Vgs V ( x) VT ]
dV
vn ( x) n E ( x) n
I D vn ( x)Qi ( x)W
dx
dV
I D n
Co x [Vgs V ( x ) VT ]W
dx
L
I
0
D
dx
VDS
C
n
ox
[Vgs V ( x ) VT ]WdV
0
2
2
VDS
VDS
W
W
'
I D=nCo x [(V gs-VT )VDS ]=kn [(V gs-VT )VDS ]
L
2
L
2
Digital IC
2: Device
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The Threshold Voltage
where
VT = VT0 + (|-2F + VSB| - |-2F|)
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process
Difference in work-function between gate and substrate material, oxide
thickness, Fermi voltage, charge of impurities trapped at the surface, dosage
of implanted ions, etc.
VSB is the source-bulk voltage
F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the
thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K
is the intrinsic carrier concentration in pure silicon)
(2qsiNA)/Cox = is the body-effect coefficient (impact of changes in
VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate
oxide capacitance with ox=3.5x10-11F/m)
Digital IC
2: Device
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I-V character in resistive or linear region
Page 92
'W
I D kn
L
2
2
VDS
VDS
(VGS VT )VDS
k n (VGS VT )VDS
2
2
'
k n nCox n
kn = k'
n
ox
tox
W
W
W
= nC ox
= n ox
L
L
tox L
Linear dependence between Vds and ID
Digital IC
2: Device
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nMOS Saturation
Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt
g
+
-
+
-
Vgd < Vt
d Ids
s
n+
n+
Vds > Vgs-Vt
p-type body
b
Digital IC
2: Device
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I-V relation under Saturation
condition
VdsVgs-VT
2
2
VDS
(VGS VT )
I D kn (VGS VT )VDS
Vds Vgs VT kn
2
2
ox
k = unCox = un
to x
'
n
Digital IC
2: Device
39
I-V characteristic of saturation
Charge per unit area:
Qi ( x) Co x [Vgs V ( x) VT ]
dV
vn ( x ) n E ( x ) n
I D vn ( x)Qi ( x)W
dx
dV
I D n
Co x [Vgs V ( x ) VT ]W
dx
L
I
D
dx
VGS VT
C
n
0
ox
[Vgs V ( x ) VT ]WdV
0
I Dsat
k 'n W
2
VGS - VT
=
2L
Digital IC
2: Device
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Current-Voltage Relations
Long-Channel Device
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VDS = VGS - VT
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
Digital IC
2: Device
41/74
Another method for giving I-V
Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?
Digital IC
2: Device
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Another method for giving I-V
Characteristics
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Qchannel =
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
p-type body
Digital IC
2: Device
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+
Vds
p-type body
43
Channel Charge
MOS structure looks like parallel plate capacitor while operating in
inversion
Gate oxide channel
Qchannel = CV
C=
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
p-type body
Digital IC
2: Device
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+
Vds
p-type body
44
Channel Charge
MOS structure looks like parallel plate capacitor while operating in
inversion
Gate oxide channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V=
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
p-type body
Digital IC
2: Device
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+
Vds
p-type body
45
Channel Charge
MOS structure looks like parallel plate capacitor while operating in
inversion
Gate oxide channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL
Cox = ox / tox
V = Vgc Vt = (Vgs Vds/2) Vt
gate
Vg
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, ox = 3.9)
p-type body
Digital IC
2: Device
+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+ n+
n+
Vds
p-type body
46
Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between
source and drain
v=
Digital IC
2: Device
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Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between
source and drain
v = E
called mobility
E=
Digital IC
2: Device
48/74
Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between
source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=
Digital IC
2: Device
49/74
Carrier velocity
Charge is carried by eCarrier velocity v proportional to lateral E-field between
source and drain
v = E
called mobility
E = Vds/L
Time for carrier to cross channel:
t=L/v
Digital IC
2: Device
50/74
nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
I ds
Digital IC
2: Device
51/74
nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qchannel
I ds
t
Digital IC
2: Device
52/74
nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qc
VDS
W
I ds =
= Cox (VGS - VT )VDS
t
L
2
VDS
= k(VGS - VT )VDS
2
ox w
w
w
kn = k
= unCox = un
L
L
tox L
'
n
Digital IC
2: Device
53/74
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
Ids=
Digital IC
2: Device
54/74
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
Ids=k(Vgs-Vt-Vdsat/2)Vdsat
Digital IC
2: Device
55/74
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
Ids=k(Vgs-Vt-Vdsat/2)Vdsat=k(Vgs-Vt)2/2
Digital IC
2: Device
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summary
Shockley 1st order transistor models
0
Ids=
Vgs<Vt
cutoff
k(Vgs-Vt-Vdsat/2)Vdsat Vds<Vdsat
linear
k(Vgs-Vt)2/2
saturation
Digital IC
Vds>Vdsat
2: Device
57/74
outline
PN junction principle
CMOS transistor introduction
Ideal I-V characteristics under static conditions
Velocity Saturation
Dynamic Characteristics
Nonideal I-V effects
Digital IC
2: Device
58/74
Current-Voltage Relations
The Deep-Submicron Era
2.5
x 10
-4
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
ID (A)
1.5
1
0.5
0
Linear
Relationship
VGS= 1.5 V
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
Digital IC
2: Device
59/74
Attention : velocity position
n = 3800 cm 2 /v . s, p = 1800 cm 2 /v . s
Qi ( x) Co x [Vgs V ( x) VT ]
Charge per unit area:
dV
I D vn ( x)Qi ( x)W
vn ( x) n E ( x) n
dx
dV
I D n
Co x [Vgs V ( x ) VT ]W
dx
L
I
0
I D satCoxW (VGT
D
dx
VDS
C
n
ox
[Vgs V ( x ) VT ]WdV
0
W
VDSAT ) nCox
L
Digital IC
2
VDSAT
(VGS VT )VDSAT
(VDSAT )
2
2: Device
60/74
un ( m /s)
Velocity Saturation
u
= 10 5
sat
nz
v
for z z c
1 z
zc
vsat
for z z c
Constant velocity
Constant mobility (slope = )
x = 1.5
x (V/m)
c
The critical field depends upon the doping levels and
the vertical electrical field applied(1-5V/um)
Digital IC
2: Device
61/74
Velocity Saturation
ID
nCox
V
1 ( DS
W
nCox
L
Lx c
W
)L
2
VDS
(VGS VT )VDS
2
2
VDS
(VGS VT )VDS
(VDS )
2
1
(V) =
1+ V
L c
Digital IC
2: Device
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Velocity Saturation
I D satCoxW (VGT
W
VDSAT ) nCox
L
2
VDSAT
(VGS VT )VDSAT
(VDSAT )
2
VDSAT (VGT )VGT
Digital IC
2: Device
63/74
Perspective
ID
Long-channel device
VGS = VDD
Short-channel device
V DSAT
VGS - V T
Digital IC
2: Device
VDS
64/74
ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
2
2.5
0
0
0.5
1
1.5
2
2.5
VGS(V)
VGS(V)
Long Channel
Short Channel
Digital IC
2: Device
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Another two assumptions
nz
v
for z z c
1 z
zc
vsat
for z z c
v nz
for z z c
vsat
for z z c
VDSAT (VGT )VGT
VDSAT
VGT
VGT
1
xc L
Digital IC
2: Device
VGT
xc L
LvSAT
n
66/74
Modify the velocity formula to be coherent with the
familiar long-channel equations
v nz
for z z c
vsat
for z z c
VDSAT x c L
W
I D nCox
L
ID
VDS VDSAT
n
2
VDSAT
(VGS VT )VDSAT
2
W
nCox
L
vsatCoxW (VGT
LvSAT
2
VDSAT
(VGS VT )VDSAT
2
VDSAT
)
2
Digital IC
2: Device
67/74
ID versus VDS
6
x 104
2.5
VGS= 2.5 V
x 10-4
VGS= 2.5 V
5
3
VDS = VGS - VT
2
VGS= 1.5 V
1
VGS= 1.0 V
0
0
0.5
1
VDSV)
(
1.5
2
2.5
VGS= 2.0 V
Linear dependence
ID(A)
VGS= 2.0 V
1.5
ID (A)
4
2
Saturation
Quadratic dependence
Resistive
VGS= 1.5 V
1
0.5
0
0
VGS= 1.0 V
0.5
1
1.5
2
2.5
VDS(V)
Long Channel
Short Channel
Digital IC
2: Device
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A unified model for manual analysis
G
S
D
B
Digital IC
2: Device
69
Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
I (A)
1.5
D
Linear
1
VDSAT=VGT
0.5
VDS=VGT
Saturated
0
0
0.5
1
1.5
2
2.5
V DS (V)
Digital IC
2: Device
70/74
A pMOS Transistor
-4
0
x 10
-0.2
VGS = -1.5V
Assume all variables
negative!
ID (A)
-0.4
VGS = -1.0V
-0.6
VGS = -2.0V
-0.8
-1
-2.5
VGS = -2.5V
-2
-1.5
-1
-0.5
0
VDS (V)
Digital IC
2: Device
71/74
Summary
Strong Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS VDSAT
Weak Inversion (Sub-Threshold) VGS VT
Exponential in VGS with linear VDS
dependence
Digital IC
2: Device
72/74